1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
6 * @file Header file containing DPDK compilation parameters
8 * Header file containing DPDK compilation parameters. Also include the
9 * meson-generated header file containing the detected parameters that
10 * are variable across builds or build environments.
12 * NOTE: This file is only used for meson+ninja builds. For builds done
13 * using make/gmake, the rte_config.h file is autogenerated from the
14 * defconfig_* files in the config directory.
16 #ifndef _RTE_CONFIG_H_
17 #define _RTE_CONFIG_H_
19 #include <rte_build_config.h>
22 #ifdef RTE_EXEC_ENV_LINUX
23 #define RTE_EXEC_ENV_LINUXAPP 1
25 #ifdef RTE_EXEC_ENV_FREEBSD
26 #define RTE_EXEC_ENV_BSDAPP 1
29 /* String that appears before the version number */
30 #define RTE_VER_PREFIX "DPDK"
32 /****** library defines ********/
35 #define RTE_MAX_HEAPS 32
36 #define RTE_MAX_MEMSEG_LISTS 128
37 #define RTE_MAX_MEMSEG_PER_LIST 8192
38 #define RTE_MAX_MEM_MB_PER_LIST 32768
39 #define RTE_MAX_MEMSEG_PER_TYPE 32768
40 #define RTE_MAX_MEM_MB_PER_TYPE 65536
41 #define RTE_MAX_MEMZONE 2560
42 #define RTE_MAX_TAILQ 32
43 #define RTE_LOG_DP_LEVEL RTE_LOG_INFO
44 #define RTE_BACKTRACE 1
45 #define RTE_MAX_VFIO_CONTAINERS 64
47 /* bsd module defines */
48 #define RTE_CONTIGMEM_MAX_NUM_BUFS 64
49 #define RTE_CONTIGMEM_DEFAULT_NUM_BUFS 1
50 #define RTE_CONTIGMEM_DEFAULT_BUF_SIZE (512*1024*1024)
53 #define RTE_MEMPOOL_CACHE_MAX_SIZE 512
56 #define RTE_MBUF_DEFAULT_MEMPOOL_OPS "ring_mp_mc"
57 #define RTE_MBUF_REFCNT_ATOMIC 1
58 #define RTE_PKTMBUF_HEADROOM 128
61 #define RTE_MAX_QUEUES_PER_PORT 1024
62 #define RTE_ETHDEV_QUEUE_STAT_CNTRS 16
63 #define RTE_ETHDEV_RXTX_CALLBACKS 1
65 /* cryptodev defines */
66 #define RTE_CRYPTO_MAX_DEVS 64
67 #define RTE_CRYPTODEV_NAME_LEN 64
69 /* compressdev defines */
70 #define RTE_COMPRESS_MAX_DEVS 64
72 /* regexdev defines */
73 #define RTE_MAX_REGEXDEV_DEVS 32
75 /* eventdev defines */
76 #define RTE_EVENT_MAX_DEVS 16
77 #define RTE_EVENT_MAX_QUEUES_PER_DEV 64
78 #define RTE_EVENT_TIMER_ADAPTER_NUM_MAX 32
79 #define RTE_EVENT_ETH_INTR_RING_SIZE 1024
80 #define RTE_EVENT_CRYPTO_ADAPTER_MAX_INSTANCE 32
81 #define RTE_EVENT_ETH_TX_ADAPTER_MAX_INSTANCE 32
84 #define RTE_RAWDEV_MAX_DEVS 64
86 /* ip_fragmentation defines */
87 #define RTE_LIBRTE_IP_FRAG_MAX_FRAG 4
88 #undef RTE_LIBRTE_IP_FRAG_TBL_STAT
90 /* rte_power defines */
91 #define RTE_MAX_LCORE_FREQS 64
93 /* rte_sched defines */
95 #undef RTE_SCHED_COLLECT_STATS
96 #undef RTE_SCHED_SUBPORT_TC_OV
97 #define RTE_SCHED_PORT_N_GRINDERS 8
98 #undef RTE_SCHED_VECTOR
101 #define RTE_KNI_PREEMPT_DEFAULT 1
103 /* rte_graph defines */
104 #define RTE_GRAPH_BURST_SIZE 256
105 #define RTE_LIBRTE_GRAPH_STATS 1
107 /****** driver defines ********/
109 /* QuickAssist device */
110 /* Max. number of QuickAssist devices which can be attached */
111 #define RTE_PMD_QAT_MAX_PCI_DEVICES 48
112 #define RTE_PMD_QAT_COMP_SGL_MAX_SEGMENTS 16
113 #define RTE_PMD_QAT_COMP_IM_BUFFER_SIZE 65536
115 /* virtio crypto defines */
116 #define RTE_MAX_VIRTIO_CRYPTO 32
118 /* DPAA SEC max cryptodev devices*/
119 #define RTE_LIBRTE_DPAA_MAX_CRYPTODEV 4
122 #define RTE_LIBRTE_FM10K_RX_OLFLAGS_ENABLE 1
125 #define RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC 1
126 #undef RTE_LIBRTE_I40E_16BYTE_RX_DESC
127 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF 64
128 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF 4
129 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM 4
131 /* Ring net PMD settings */
132 #define RTE_PMD_RING_MAX_RX_RINGS 16
133 #define RTE_PMD_RING_MAX_TX_RINGS 16
135 /* QEDE PMD defines */
136 #define RTE_LIBRTE_QEDE_FW ""
138 #endif /* _RTE_CONFIG_H_ */