drivers/bus/dpaa/base/qbman/qman.c

   1 /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)
   2  *
   3  * Copyright 2008-2016 Freescale Semiconductor Inc.
   4  * Copyright 2017 NXP
   5  *
   6  */
   7
   8 #include "qman.h"
   9 #include <rte_branch_prediction.h>
  10 #include <rte_dpaa_bus.h>
  11
  12 /* Compilation constants */
  13 #define DQRR_MAXFILL    15
  14 #define EQCR_ITHRESH    4       /* if EQCR congests, interrupt threshold */
  15 #define IRQNAME         "QMan portal %d"
  16 #define MAX_IRQNAME     16      /* big enough for "QMan portal %d" */
  17 /* maximum number of DQRR entries to process in qman_poll() */
  18 #define FSL_QMAN_POLL_LIMIT 8
  19
  20 /* Lock/unlock frame queues, subject to the "LOCKED" flag. This is about
  21  * inter-processor locking only. Note, FQLOCK() is always called either under a
  22  * local_irq_save() or from interrupt context - hence there's no need for irq
  23  * protection (and indeed, attempting to nest irq-protection doesn't work, as
  24  * the "irq en/disable" machinery isn't recursive...).
  25  */
  26 #define FQLOCK(fq) \
  27         do { \
  28                 struct qman_fq *__fq478 = (fq); \
  29                 if (fq_isset(__fq478, QMAN_FQ_FLAG_LOCKED)) \
  30                         spin_lock(&__fq478->fqlock); \
  31         } while (0)
  32 #define FQUNLOCK(fq) \
  33         do { \
  34                 struct qman_fq *__fq478 = (fq); \
  35                 if (fq_isset(__fq478, QMAN_FQ_FLAG_LOCKED)) \
  36                         spin_unlock(&__fq478->fqlock); \
  37         } while (0)
  38
  39 static inline void fq_set(struct qman_fq *fq, u32 mask)
  40 {
  41         dpaa_set_bits(mask, &fq->flags);
  42 }
  43
  44 static inline void fq_clear(struct qman_fq *fq, u32 mask)
  45 {
  46         dpaa_clear_bits(mask, &fq->flags);
  47 }
  48
  49 static inline int fq_isset(struct qman_fq *fq, u32 mask)
  50 {
  51         return fq->flags & mask;
  52 }
  53
  54 static inline int fq_isclear(struct qman_fq *fq, u32 mask)
  55 {
  56         return !(fq->flags & mask);
  57 }
  58
  59 struct qman_portal {
  60         struct qm_portal p;
  61         /* PORTAL_BITS_*** - dynamic, strictly internal */
  62         unsigned long bits;
  63         /* interrupt sources processed by portal_isr(), configurable */
  64         unsigned long irq_sources;
  65         u32 use_eqcr_ci_stashing;
  66         u32 slowpoll;   /* only used when interrupts are off */
  67         /* only 1 volatile dequeue at a time */
  68         struct qman_fq *vdqcr_owned;
  69         u32 sdqcr;
  70         int dqrr_disable_ref;
  71         /* A portal-specific handler for DCP ERNs. If this is NULL, the global
  72          * handler is called instead.
  73          */
  74         qman_cb_dc_ern cb_dc_ern;
  75         /* When the cpu-affine portal is activated, this is non-NULL */
  76         const struct qm_portal_config *config;
  77         struct dpa_rbtree retire_table;
  78         char irqname[MAX_IRQNAME];
  79         /* 2-element array. cgrs[0] is mask, cgrs[1] is snapshot. */
  80         struct qman_cgrs *cgrs;
  81         /* linked-list of CSCN handlers. */
  82         struct list_head cgr_cbs;
  83         /* list lock */
  84         spinlock_t cgr_lock;
  85         /* track if memory was allocated by the driver */
  86 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
  87         /* Keep a shadow copy of the DQRR on LE systems as the SW needs to
  88          * do byte swaps of DQRR read only memory.  First entry must be aligned
  89          * to 2 ** 10 to ensure DQRR index calculations based shadow copy
  90          * address (6 bits for address shift + 4 bits for the DQRR size).
  91          */
  92         struct qm_dqrr_entry shadow_dqrr[QM_DQRR_SIZE]
  93                     __attribute__((aligned(1024)));
  94 #endif
  95 };
  96
  97 /* Global handler for DCP ERNs. Used when the portal receiving the message does
  98  * not have a portal-specific handler.
  99  */
 100 static qman_cb_dc_ern cb_dc_ern;
 101
 102 static cpumask_t affine_mask;
 103 static DEFINE_SPINLOCK(affine_mask_lock);
 104 static u16 affine_channels[NR_CPUS];
 105 static RTE_DEFINE_PER_LCORE(struct qman_portal, qman_affine_portal);
 106
 107 static inline struct qman_portal *get_affine_portal(void)
 108 {
 109         return &RTE_PER_LCORE(qman_affine_portal);
 110 }
 111
 112 /* This gives a FQID->FQ lookup to cover the fact that we can't directly demux
 113  * retirement notifications (the fact they are sometimes h/w-consumed means that
 114  * contextB isn't always a s/w demux - and as we can't know which case it is
 115  * when looking at the notification, we have to use the slow lookup for all of
 116  * them). NB, it's possible to have multiple FQ objects refer to the same FQID
 117  * (though at most one of them should be the consumer), so this table isn't for
 118  * all FQs - FQs are added when retirement commands are issued, and removed when
 119  * they complete, which also massively reduces the size of this table.
 120  */
 121 IMPLEMENT_DPAA_RBTREE(fqtree, struct qman_fq, node, fqid);
 122 /*
 123  * This is what everything can wait on, even if it migrates to a different cpu
 124  * to the one whose affine portal it is waiting on.
 125  */
 126 static DECLARE_WAIT_QUEUE_HEAD(affine_queue);
 127
 128 static inline int table_push_fq(struct qman_portal *p, struct qman_fq *fq)
 129 {
 130         int ret = fqtree_push(&p->retire_table, fq);
 131
 132         if (ret)
 133                 pr_err("ERROR: double FQ-retirement %d\n", fq->fqid);
 134         return ret;
 135 }
 136
 137 static inline void table_del_fq(struct qman_portal *p, struct qman_fq *fq)
 138 {
 139         fqtree_del(&p->retire_table, fq);
 140 }
 141
 142 static inline struct qman_fq *table_find_fq(struct qman_portal *p, u32 fqid)
 143 {
 144         return fqtree_find(&p->retire_table, fqid);
 145 }
 146
 147 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
 148 static void **qman_fq_lookup_table;
 149 static size_t qman_fq_lookup_table_size;
 150
 151 int qman_setup_fq_lookup_table(size_t num_entries)
 152 {
 153         num_entries++;
 154         /* Allocate 1 more entry since the first entry is not used */
 155         qman_fq_lookup_table = vmalloc((num_entries * sizeof(void *)));
 156         if (!qman_fq_lookup_table) {
 157                 pr_err("QMan: Could not allocate fq lookup table\n");
 158                 return -ENOMEM;
 159         }
 160         memset(qman_fq_lookup_table, 0, num_entries * sizeof(void *));
 161         qman_fq_lookup_table_size = num_entries;
 162         pr_debug("QMan: Allocated lookup table at %p, entry count %lu\n",
 163                 qman_fq_lookup_table,
 164                         (unsigned long)qman_fq_lookup_table_size);
 165         return 0;
 166 }
 167
 168 /* global structure that maintains fq object mapping */
 169 static DEFINE_SPINLOCK(fq_hash_table_lock);
 170
 171 static int find_empty_fq_table_entry(u32 *entry, struct qman_fq *fq)
 172 {
 173         u32 i;
 174
 175         spin_lock(&fq_hash_table_lock);
 176         /* Can't use index zero because this has special meaning
 177          * in context_b field.
 178          */
 179         for (i = 1; i < qman_fq_lookup_table_size; i++) {
 180                 if (qman_fq_lookup_table[i] == NULL) {
 181                         *entry = i;
 182                         qman_fq_lookup_table[i] = fq;
 183                         spin_unlock(&fq_hash_table_lock);
 184                         return 0;
 185                 }
 186         }
 187         spin_unlock(&fq_hash_table_lock);
 188         return -ENOMEM;
 189 }
 190
 191 static void clear_fq_table_entry(u32 entry)
 192 {
 193         spin_lock(&fq_hash_table_lock);
 194         DPAA_BUG_ON(entry >= qman_fq_lookup_table_size);
 195         qman_fq_lookup_table[entry] = NULL;
 196         spin_unlock(&fq_hash_table_lock);
 197 }
 198
 199 static inline struct qman_fq *get_fq_table_entry(u32 entry)
 200 {
 201         DPAA_BUG_ON(entry >= qman_fq_lookup_table_size);
 202         return qman_fq_lookup_table[entry];
 203 }
 204 #endif
 205
 206 static inline void cpu_to_hw_fqd(struct qm_fqd *fqd)
 207 {
 208         /* Byteswap the FQD to HW format */
 209         fqd->fq_ctrl = cpu_to_be16(fqd->fq_ctrl);
 210         fqd->dest_wq = cpu_to_be16(fqd->dest_wq);
 211         fqd->ics_cred = cpu_to_be16(fqd->ics_cred);
 212         fqd->context_b = cpu_to_be32(fqd->context_b);
 213         fqd->context_a.opaque = cpu_to_be64(fqd->context_a.opaque);
 214         fqd->opaque_td = cpu_to_be16(fqd->opaque_td);
 215 }
 216
 217 static inline void hw_fqd_to_cpu(struct qm_fqd *fqd)
 218 {
 219         /* Byteswap the FQD to CPU format */
 220         fqd->fq_ctrl = be16_to_cpu(fqd->fq_ctrl);
 221         fqd->dest_wq = be16_to_cpu(fqd->dest_wq);
 222         fqd->ics_cred = be16_to_cpu(fqd->ics_cred);
 223         fqd->context_b = be32_to_cpu(fqd->context_b);
 224         fqd->context_a.opaque = be64_to_cpu(fqd->context_a.opaque);
 225 }
 226
 227 static inline void cpu_to_hw_fd(struct qm_fd *fd)
 228 {
 229         fd->addr = cpu_to_be40(fd->addr);
 230         fd->status = cpu_to_be32(fd->status);
 231         fd->opaque = cpu_to_be32(fd->opaque);
 232 }
 233
 234 static inline void hw_fd_to_cpu(struct qm_fd *fd)
 235 {
 236         fd->addr = be40_to_cpu(fd->addr);
 237         fd->status = be32_to_cpu(fd->status);
 238         fd->opaque = be32_to_cpu(fd->opaque);
 239 }
 240
 241 /* In the case that slow- and fast-path handling are both done by qman_poll()
 242  * (ie. because there is no interrupt handling), we ought to balance how often
 243  * we do the fast-path poll versus the slow-path poll. We'll use two decrementer
 244  * sources, so we call the fast poll 'n' times before calling the slow poll
 245  * once. The idle decrementer constant is used when the last slow-poll detected
 246  * no work to do, and the busy decrementer constant when the last slow-poll had
 247  * work to do.
 248  */
 249 #define SLOW_POLL_IDLE   1000
 250 #define SLOW_POLL_BUSY   10
 251 static u32 __poll_portal_slow(struct qman_portal *p, u32 is);
 252 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
 253                                               unsigned int poll_limit);
 254
 255 /* Portal interrupt handler */
 256 static irqreturn_t portal_isr(__always_unused int irq, void *ptr)
 257 {
 258         struct qman_portal *p = ptr;
 259         /*
 260          * The CSCI/CCSCI source is cleared inside __poll_portal_slow(), because
 261          * it could race against a Query Congestion State command also given
 262          * as part of the handling of this interrupt source. We mustn't
 263          * clear it a second time in this top-level function.
 264          */
 265         u32 clear = QM_DQAVAIL_MASK | (p->irq_sources &
 266                 ~(QM_PIRQ_CSCI | QM_PIRQ_CCSCI));
 267         u32 is = qm_isr_status_read(&p->p) & p->irq_sources;
 268         /* DQRR-handling if it's interrupt-driven */
 269         if (is & QM_PIRQ_DQRI)
 270                 __poll_portal_fast(p, FSL_QMAN_POLL_LIMIT);
 271         /* Handling of anything else that's interrupt-driven */
 272         clear |= __poll_portal_slow(p, is);
 273         qm_isr_status_clear(&p->p, clear);
 274         return IRQ_HANDLED;
 275 }
 276
 277 /* This inner version is used privately by qman_create_affine_portal(), as well
 278  * as by the exported qman_stop_dequeues().
 279  */
 280 static inline void qman_stop_dequeues_ex(struct qman_portal *p)
 281 {
 282         if (!(p->dqrr_disable_ref++))
 283                 qm_dqrr_set_maxfill(&p->p, 0);
 284 }
 285
 286 static int drain_mr_fqrni(struct qm_portal *p)
 287 {
 288         const struct qm_mr_entry *msg;
 289 loop:
 290         msg = qm_mr_current(p);
 291         if (!msg) {
 292                 /*
 293                  * if MR was full and h/w had other FQRNI entries to produce, we
 294                  * need to allow it time to produce those entries once the
 295                  * existing entries are consumed. A worst-case situation
 296                  * (fully-loaded system) means h/w sequencers may have to do 3-4
 297                  * other things before servicing the portal's MR pump, each of
 298                  * which (if slow) may take ~50 qman cycles (which is ~200
 299                  * processor cycles). So rounding up and then multiplying this
 300                  * worst-case estimate by a factor of 10, just to be
 301                  * ultra-paranoid, goes as high as 10,000 cycles. NB, we consume
 302                  * one entry at a time, so h/w has an opportunity to produce new
 303                  * entries well before the ring has been fully consumed, so
 304                  * we're being *really* paranoid here.
 305                  */
 306                 u64 now, then = mfatb();
 307
 308                 do {
 309                         now = mfatb();
 310                 } while ((then + 10000) > now);
 311                 msg = qm_mr_current(p);
 312                 if (!msg)
 313                         return 0;
 314         }
 315         if ((msg->verb & QM_MR_VERB_TYPE_MASK) != QM_MR_VERB_FQRNI) {
 316                 /* We aren't draining anything but FQRNIs */
 317                 pr_err("Found verb 0x%x in MR\n", msg->verb);
 318                 return -1;
 319         }
 320         qm_mr_next(p);
 321         qm_mr_cci_consume(p, 1);
 322         goto loop;
 323 }
 324
 325 static inline int qm_eqcr_init(struct qm_portal *portal,
 326                                enum qm_eqcr_pmode pmode,
 327                                unsigned int eq_stash_thresh,
 328                                int eq_stash_prio)
 329 {
 330         /* This use of 'register', as well as all other occurrences, is because
 331          * it has been observed to generate much faster code with gcc than is
 332          * otherwise the case.
 333          */
 334         register struct qm_eqcr *eqcr = &portal->eqcr;
 335         u32 cfg;
 336         u8 pi;
 337
 338         eqcr->ring = portal->addr.ce + QM_CL_EQCR;
 339         eqcr->ci = qm_in(EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
 340         qm_cl_invalidate(EQCR_CI);
 341         pi = qm_in(EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
 342         eqcr->cursor = eqcr->ring + pi;
 343         eqcr->vbit = (qm_in(EQCR_PI_CINH) & QM_EQCR_SIZE) ?
 344                         QM_EQCR_VERB_VBIT : 0;
 345         eqcr->available = QM_EQCR_SIZE - 1 -
 346                         qm_cyc_diff(QM_EQCR_SIZE, eqcr->ci, pi);
 347         eqcr->ithresh = qm_in(EQCR_ITR);
 348 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 349         eqcr->busy = 0;
 350         eqcr->pmode = pmode;
 351 #endif
 352         cfg = (qm_in(CFG) & 0x00ffffff) |
 353                 (eq_stash_thresh << 28) | /* QCSP_CFG: EST */
 354                 (eq_stash_prio << 26)   | /* QCSP_CFG: EP */
 355                 ((pmode & 0x3) << 24);  /* QCSP_CFG::EPM */
 356         qm_out(CFG, cfg);
 357         return 0;
 358 }
 359
 360 static inline void qm_eqcr_finish(struct qm_portal *portal)
 361 {
 362         register struct qm_eqcr *eqcr = &portal->eqcr;
 363         u8 pi, ci;
 364         u32 cfg;
 365
 366         /*
 367          * Disable EQCI stashing because the QMan only
 368          * presents the value it previously stashed to
 369          * maintain coherency.  Setting the stash threshold
 370          * to 1 then 0 ensures that QMan has resyncronized
 371          * its internal copy so that the portal is clean
 372          * when it is reinitialized in the future
 373          */
 374         cfg = (qm_in(CFG) & 0x0fffffff) |
 375                 (1 << 28); /* QCSP_CFG: EST */
 376         qm_out(CFG, cfg);
 377         cfg &= 0x0fffffff; /* stash threshold = 0 */
 378         qm_out(CFG, cfg);
 379
 380         pi = qm_in(EQCR_PI_CINH) & (QM_EQCR_SIZE - 1);
 381         ci = qm_in(EQCR_CI_CINH) & (QM_EQCR_SIZE - 1);
 382
 383         /* Refresh EQCR CI cache value */
 384         qm_cl_invalidate(EQCR_CI);
 385         eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
 386
 387 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 388         DPAA_ASSERT(!eqcr->busy);
 389 #endif
 390         if (pi != EQCR_PTR2IDX(eqcr->cursor))
 391                 pr_crit("losing uncommitted EQCR entries\n");
 392         if (ci != eqcr->ci)
 393                 pr_crit("missing existing EQCR completions\n");
 394         if (eqcr->ci != EQCR_PTR2IDX(eqcr->cursor))
 395                 pr_crit("EQCR destroyed unquiesced\n");
 396 }
 397
 398 static inline int qm_dqrr_init(struct qm_portal *portal,
 399                         __maybe_unused const struct qm_portal_config *config,
 400                         enum qm_dqrr_dmode dmode,
 401                         __maybe_unused enum qm_dqrr_pmode pmode,
 402                         enum qm_dqrr_cmode cmode, u8 max_fill)
 403 {
 404         register struct qm_dqrr *dqrr = &portal->dqrr;
 405         u32 cfg;
 406
 407         /* Make sure the DQRR will be idle when we enable */
 408         qm_out(DQRR_SDQCR, 0);
 409         qm_out(DQRR_VDQCR, 0);
 410         qm_out(DQRR_PDQCR, 0);
 411         dqrr->ring = portal->addr.ce + QM_CL_DQRR;
 412         dqrr->pi = qm_in(DQRR_PI_CINH) & (QM_DQRR_SIZE - 1);
 413         dqrr->ci = qm_in(DQRR_CI_CINH) & (QM_DQRR_SIZE - 1);
 414         dqrr->cursor = dqrr->ring + dqrr->ci;
 415         dqrr->fill = qm_cyc_diff(QM_DQRR_SIZE, dqrr->ci, dqrr->pi);
 416         dqrr->vbit = (qm_in(DQRR_PI_CINH) & QM_DQRR_SIZE) ?
 417                         QM_DQRR_VERB_VBIT : 0;
 418         dqrr->ithresh = qm_in(DQRR_ITR);
 419 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 420         dqrr->dmode = dmode;
 421         dqrr->pmode = pmode;
 422         dqrr->cmode = cmode;
 423 #endif
 424         /* Invalidate every ring entry before beginning */
 425         for (cfg = 0; cfg < QM_DQRR_SIZE; cfg++)
 426                 dccivac(qm_cl(dqrr->ring, cfg));
 427         cfg = (qm_in(CFG) & 0xff000f00) |
 428                 ((max_fill & (QM_DQRR_SIZE - 1)) << 20) | /* DQRR_MF */
 429                 ((dmode & 1) << 18) |                   /* DP */
 430                 ((cmode & 3) << 16) |                   /* DCM */
 431                 0xa0 |                                  /* RE+SE */
 432                 (0 ? 0x40 : 0) |                        /* Ignore RP */
 433                 (0 ? 0x10 : 0);                         /* Ignore SP */
 434         qm_out(CFG, cfg);
 435         qm_dqrr_set_maxfill(portal, max_fill);
 436         return 0;
 437 }
 438
 439 static inline void qm_dqrr_finish(struct qm_portal *portal)
 440 {
 441         __maybe_unused register struct qm_dqrr *dqrr = &portal->dqrr;
 442 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 443         if ((dqrr->cmode != qm_dqrr_cdc) &&
 444             (dqrr->ci != DQRR_PTR2IDX(dqrr->cursor)))
 445                 pr_crit("Ignoring completed DQRR entries\n");
 446 #endif
 447 }
 448
 449 static inline int qm_mr_init(struct qm_portal *portal,
 450                              __maybe_unused enum qm_mr_pmode pmode,
 451                              enum qm_mr_cmode cmode)
 452 {
 453         register struct qm_mr *mr = &portal->mr;
 454         u32 cfg;
 455
 456         mr->ring = portal->addr.ce + QM_CL_MR;
 457         mr->pi = qm_in(MR_PI_CINH) & (QM_MR_SIZE - 1);
 458         mr->ci = qm_in(MR_CI_CINH) & (QM_MR_SIZE - 1);
 459         mr->cursor = mr->ring + mr->ci;
 460         mr->fill = qm_cyc_diff(QM_MR_SIZE, mr->ci, mr->pi);
 461         mr->vbit = (qm_in(MR_PI_CINH) & QM_MR_SIZE) ? QM_MR_VERB_VBIT : 0;
 462         mr->ithresh = qm_in(MR_ITR);
 463 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 464         mr->pmode = pmode;
 465         mr->cmode = cmode;
 466 #endif
 467         cfg = (qm_in(CFG) & 0xfffff0ff) |
 468                 ((cmode & 1) << 8);             /* QCSP_CFG:MM */
 469         qm_out(CFG, cfg);
 470         return 0;
 471 }
 472
 473 static inline void qm_mr_pvb_update(struct qm_portal *portal)
 474 {
 475         register struct qm_mr *mr = &portal->mr;
 476         const struct qm_mr_entry *res = qm_cl(mr->ring, mr->pi);
 477
 478 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
 479         DPAA_ASSERT(mr->pmode == qm_mr_pvb);
 480 #endif
 481         /* when accessing 'verb', use __raw_readb() to ensure that compiler
 482          * inlining doesn't try to optimise out "excess reads".
 483          */
 484         if ((__raw_readb(&res->verb) & QM_MR_VERB_VBIT) == mr->vbit) {
 485                 mr->pi = (mr->pi + 1) & (QM_MR_SIZE - 1);
 486                 if (!mr->pi)
 487                         mr->vbit ^= QM_MR_VERB_VBIT;
 488                 mr->fill++;
 489                 res = MR_INC(res);
 490         }
 491         dcbit_ro(res);
 492 }
 493
 494 static inline
 495 struct qman_portal *qman_create_portal(
 496                         struct qman_portal *portal,
 497                               const struct qm_portal_config *c,
 498                               const struct qman_cgrs *cgrs)
 499 {
 500         struct qm_portal *p;
 501         char buf[16];
 502         int ret;
 503         u32 isdr;
 504
 505         p = &portal->p;
 506
 507         if (dpaa_svr_family == SVR_LS1043A_FAMILY)
 508                 portal->use_eqcr_ci_stashing = 3;
 509         else
 510                 portal->use_eqcr_ci_stashing =
 511                                         ((qman_ip_rev >= QMAN_REV30) ? 1 : 0);
 512
 513         /*
 514          * prep the low-level portal struct with the mapped addresses from the
 515          * config, everything that follows depends on it and "config" is more
 516          * for (de)reference
 517          */
 518         p->addr.ce = c->addr_virt[DPAA_PORTAL_CE];
 519         p->addr.ci = c->addr_virt[DPAA_PORTAL_CI];
 520         /*
 521          * If CI-stashing is used, the current defaults use a threshold of 3,
 522          * and stash with high-than-DQRR priority.
 523          */
 524         if (qm_eqcr_init(p, qm_eqcr_pvb,
 525                          portal->use_eqcr_ci_stashing, 1)) {
 526                 pr_err("Qman EQCR initialisation failed\n");
 527                 goto fail_eqcr;
 528         }
 529         if (qm_dqrr_init(p, c, qm_dqrr_dpush, qm_dqrr_pvb,
 530                          qm_dqrr_cdc, DQRR_MAXFILL)) {
 531                 pr_err("Qman DQRR initialisation failed\n");
 532                 goto fail_dqrr;
 533         }
 534         if (qm_mr_init(p, qm_mr_pvb, qm_mr_cci)) {
 535                 pr_err("Qman MR initialisation failed\n");
 536                 goto fail_mr;
 537         }
 538         if (qm_mc_init(p)) {
 539                 pr_err("Qman MC initialisation failed\n");
 540                 goto fail_mc;
 541         }
 542
 543         /* static interrupt-gating controls */
 544         qm_dqrr_set_ithresh(p, 0);
 545         qm_mr_set_ithresh(p, 0);
 546         qm_isr_set_iperiod(p, 0);
 547         portal->cgrs = kmalloc(2 * sizeof(*cgrs), GFP_KERNEL);
 548         if (!portal->cgrs)
 549                 goto fail_cgrs;
 550         /* initial snapshot is no-depletion */
 551         qman_cgrs_init(&portal->cgrs[1]);
 552         if (cgrs)
 553                 portal->cgrs[0] = *cgrs;
 554         else
 555                 /* if the given mask is NULL, assume all CGRs can be seen */
 556                 qman_cgrs_fill(&portal->cgrs[0]);
 557         INIT_LIST_HEAD(&portal->cgr_cbs);
 558         spin_lock_init(&portal->cgr_lock);
 559         portal->bits = 0;
 560         portal->slowpoll = 0;
 561         portal->sdqcr = QM_SDQCR_SOURCE_CHANNELS | QM_SDQCR_COUNT_UPTO3 |
 562                         QM_SDQCR_DEDICATED_PRECEDENCE | QM_SDQCR_TYPE_PRIO_QOS |
 563                         QM_SDQCR_TOKEN_SET(0xab) | QM_SDQCR_CHANNELS_DEDICATED;
 564         portal->dqrr_disable_ref = 0;
 565         portal->cb_dc_ern = NULL;
 566         sprintf(buf, "qportal-%d", c->channel);
 567         dpa_rbtree_init(&portal->retire_table);
 568         isdr = 0xffffffff;
 569         qm_isr_disable_write(p, isdr);
 570         portal->irq_sources = 0;
 571         qm_isr_enable_write(p, portal->irq_sources);
 572         qm_isr_status_clear(p, 0xffffffff);
 573         snprintf(portal->irqname, MAX_IRQNAME, IRQNAME, c->cpu);
 574         if (request_irq(c->irq, portal_isr, 0, portal->irqname,
 575                         portal)) {
 576                 pr_err("request_irq() failed\n");
 577                 goto fail_irq;
 578         }
 579
 580         /* Need EQCR to be empty before continuing */
 581         isdr &= ~QM_PIRQ_EQCI;
 582         qm_isr_disable_write(p, isdr);
 583         ret = qm_eqcr_get_fill(p);
 584         if (ret) {
 585                 pr_err("Qman EQCR unclean\n");
 586                 goto fail_eqcr_empty;
 587         }
 588         isdr &= ~(QM_PIRQ_DQRI | QM_PIRQ_MRI);
 589         qm_isr_disable_write(p, isdr);
 590         if (qm_dqrr_current(p)) {
 591                 pr_err("Qman DQRR unclean\n");
 592                 qm_dqrr_cdc_consume_n(p, 0xffff);
 593         }
 594         if (qm_mr_current(p) && drain_mr_fqrni(p)) {
 595                 /* special handling, drain just in case it's a few FQRNIs */
 596                 if (drain_mr_fqrni(p))
 597                         goto fail_dqrr_mr_empty;
 598         }
 599         /* Success */
 600         portal->config = c;
 601         qm_isr_disable_write(p, 0);
 602         qm_isr_uninhibit(p);
 603         /* Write a sane SDQCR */
 604         qm_dqrr_sdqcr_set(p, portal->sdqcr);
 605         return portal;
 606 fail_dqrr_mr_empty:
 607 fail_eqcr_empty:
 608         free_irq(c->irq, portal);
 609 fail_irq:
 610         kfree(portal->cgrs);
 611         spin_lock_destroy(&portal->cgr_lock);
 612 fail_cgrs:
 613         qm_mc_finish(p);
 614 fail_mc:
 615         qm_mr_finish(p);
 616 fail_mr:
 617         qm_dqrr_finish(p);
 618 fail_dqrr:
 619         qm_eqcr_finish(p);
 620 fail_eqcr:
 621         return NULL;
 622 }
 623
 624 #define MAX_GLOBAL_PORTALS 8
 625 static struct qman_portal global_portals[MAX_GLOBAL_PORTALS];
 626 static int global_portals_used[MAX_GLOBAL_PORTALS];
 627
 628 static struct qman_portal *
 629 qman_alloc_global_portal(void)
 630 {
 631         unsigned int i;
 632
 633         for (i = 0; i < MAX_GLOBAL_PORTALS; i++) {
 634                 if (global_portals_used[i] == 0) {
 635                         global_portals_used[i] = 1;
 636                         return &global_portals[i];
 637                 }
 638         }
 639         pr_err("No portal available (%x)\n", MAX_GLOBAL_PORTALS);
 640
 641         return NULL;
 642 }
 643
 644 static int
 645 qman_free_global_portal(struct qman_portal *portal)
 646 {
 647         unsigned int i;
 648
 649         for (i = 0; i < MAX_GLOBAL_PORTALS; i++) {
 650                 if (&global_portals[i] == portal) {
 651                         global_portals_used[i] = 0;
 652                         return 0;
 653                 }
 654         }
 655         return -1;
 656 }
 657
 658 struct qman_portal *qman_create_affine_portal(const struct qm_portal_config *c,
 659                                               const struct qman_cgrs *cgrs,
 660                                               int alloc)
 661 {
 662         struct qman_portal *res;
 663         struct qman_portal *portal;
 664
 665         if (alloc)
 666                 portal = qman_alloc_global_portal();
 667         else
 668                 portal = get_affine_portal();
 669
 670         /* A criteria for calling this function (from qman_driver.c) is that
 671          * we're already affine to the cpu and won't schedule onto another cpu.
 672          */
 673
 674         res = qman_create_portal(portal, c, cgrs);
 675         if (res) {
 676                 spin_lock(&affine_mask_lock);
 677                 CPU_SET(c->cpu, &affine_mask);
 678                 affine_channels[c->cpu] =
 679                         c->channel;
 680                 spin_unlock(&affine_mask_lock);
 681         }
 682         return res;
 683 }
 684
 685 static inline
 686 void qman_destroy_portal(struct qman_portal *qm)
 687 {
 688         const struct qm_portal_config *pcfg;
 689
 690         /* Stop dequeues on the portal */
 691         qm_dqrr_sdqcr_set(&qm->p, 0);
 692
 693         /*
 694          * NB we do this to "quiesce" EQCR. If we add enqueue-completions or
 695          * something related to QM_PIRQ_EQCI, this may need fixing.
 696          * Also, due to the prefetching model used for CI updates in the enqueue
 697          * path, this update will only invalidate the CI cacheline *after*
 698          * working on it, so we need to call this twice to ensure a full update
 699          * irrespective of where the enqueue processing was at when the teardown
 700          * began.
 701          */
 702         qm_eqcr_cce_update(&qm->p);
 703         qm_eqcr_cce_update(&qm->p);
 704         pcfg = qm->config;
 705
 706         free_irq(pcfg->irq, qm);
 707
 708         kfree(qm->cgrs);
 709         qm_mc_finish(&qm->p);
 710         qm_mr_finish(&qm->p);
 711         qm_dqrr_finish(&qm->p);
 712         qm_eqcr_finish(&qm->p);
 713
 714         qm->config = NULL;
 715
 716         spin_lock_destroy(&qm->cgr_lock);
 717 }
 718
 719 const struct qm_portal_config *
 720 qman_destroy_affine_portal(struct qman_portal *qp)
 721 {
 722         /* We don't want to redirect if we're a slave, use "raw" */
 723         struct qman_portal *qm;
 724         const struct qm_portal_config *pcfg;
 725         int cpu;
 726
 727         if (qp == NULL)
 728                 qm = get_affine_portal();
 729         else
 730                 qm = qp;
 731         pcfg = qm->config;
 732         cpu = pcfg->cpu;
 733
 734         qman_destroy_portal(qm);
 735
 736         spin_lock(&affine_mask_lock);
 737         CPU_CLR(cpu, &affine_mask);
 738         spin_unlock(&affine_mask_lock);
 739
 740         qman_free_global_portal(qm);
 741
 742         return pcfg;
 743 }
 744
 745 int qman_get_portal_index(void)
 746 {
 747         struct qman_portal *p = get_affine_portal();
 748         return p->config->index;
 749 }
 750
 751 /* Inline helper to reduce nesting in __poll_portal_slow() */
 752 static inline void fq_state_change(struct qman_portal *p, struct qman_fq *fq,
 753                                    const struct qm_mr_entry *msg, u8 verb)
 754 {
 755         FQLOCK(fq);
 756         switch (verb) {
 757         case QM_MR_VERB_FQRL:
 758                 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_ORL));
 759                 fq_clear(fq, QMAN_FQ_STATE_ORL);
 760                 table_del_fq(p, fq);
 761                 break;
 762         case QM_MR_VERB_FQRN:
 763                 DPAA_ASSERT((fq->state == qman_fq_state_parked) ||
 764                             (fq->state == qman_fq_state_sched));
 765                 DPAA_ASSERT(fq_isset(fq, QMAN_FQ_STATE_CHANGING));
 766                 fq_clear(fq, QMAN_FQ_STATE_CHANGING);
 767                 if (msg->fq.fqs & QM_MR_FQS_NOTEMPTY)
 768                         fq_set(fq, QMAN_FQ_STATE_NE);
 769                 if (msg->fq.fqs & QM_MR_FQS_ORLPRESENT)
 770                         fq_set(fq, QMAN_FQ_STATE_ORL);
 771                 else
 772                         table_del_fq(p, fq);
 773                 fq->state = qman_fq_state_retired;
 774                 break;
 775         case QM_MR_VERB_FQPN:
 776                 DPAA_ASSERT(fq->state == qman_fq_state_sched);
 777                 DPAA_ASSERT(fq_isclear(fq, QMAN_FQ_STATE_CHANGING));
 778                 fq->state = qman_fq_state_parked;
 779         }
 780         FQUNLOCK(fq);
 781 }
 782
 783 static u32 __poll_portal_slow(struct qman_portal *p, u32 is)
 784 {
 785         const struct qm_mr_entry *msg;
 786         struct qm_mr_entry swapped_msg;
 787
 788         if (is & QM_PIRQ_CSCI) {
 789                 struct qman_cgrs rr, c;
 790                 struct qm_mc_result *mcr;
 791                 struct qman_cgr *cgr;
 792
 793                 spin_lock(&p->cgr_lock);
 794                 /*
 795                  * The CSCI bit must be cleared _before_ issuing the
 796                  * Query Congestion State command, to ensure that a long
 797                  * CGR State Change callback cannot miss an intervening
 798                  * state change.
 799                  */
 800                 qm_isr_status_clear(&p->p, QM_PIRQ_CSCI);
 801                 qm_mc_start(&p->p);
 802                 qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
 803                 while (!(mcr = qm_mc_result(&p->p)))
 804                         cpu_relax();
 805                 /* mask out the ones I'm not interested in */
 806                 qman_cgrs_and(&rr, (const struct qman_cgrs *)
 807                         &mcr->querycongestion.state, &p->cgrs[0]);
 808                 /* check previous snapshot for delta, enter/exit congestion */
 809                 qman_cgrs_xor(&c, &rr, &p->cgrs[1]);
 810                 /* update snapshot */
 811                 qman_cgrs_cp(&p->cgrs[1], &rr);
 812                 /* Invoke callback */
 813                 list_for_each_entry(cgr, &p->cgr_cbs, node)
 814                         if (cgr->cb && qman_cgrs_get(&c, cgr->cgrid))
 815                                 cgr->cb(p, cgr, qman_cgrs_get(&rr, cgr->cgrid));
 816                 spin_unlock(&p->cgr_lock);
 817         }
 818
 819         if (is & QM_PIRQ_EQRI) {
 820                 qm_eqcr_cce_update(&p->p);
 821                 qm_eqcr_set_ithresh(&p->p, 0);
 822                 wake_up(&affine_queue);
 823         }
 824
 825         if (is & QM_PIRQ_MRI) {
 826                 struct qman_fq *fq;
 827                 u8 verb, num = 0;
 828 mr_loop:
 829                 qm_mr_pvb_update(&p->p);
 830                 msg = qm_mr_current(&p->p);
 831                 if (!msg)
 832                         goto mr_done;
 833                 swapped_msg = *msg;
 834                 hw_fd_to_cpu(&swapped_msg.ern.fd);
 835                 verb = msg->verb & QM_MR_VERB_TYPE_MASK;
 836                 /* The message is a software ERN iff the 0x20 bit is set */
 837                 if (verb & 0x20) {
 838                         switch (verb) {
 839                         case QM_MR_VERB_FQRNI:
 840                                 /* nada, we drop FQRNIs on the floor */
 841                                 break;
 842                         case QM_MR_VERB_FQRN:
 843                         case QM_MR_VERB_FQRL:
 844                                 /* Lookup in the retirement table */
 845                                 fq = table_find_fq(p,
 846                                                    be32_to_cpu(msg->fq.fqid));
 847                                 DPAA_BUG_ON(!fq);
 848                                 fq_state_change(p, fq, &swapped_msg, verb);
 849                                 if (fq->cb.fqs)
 850                                         fq->cb.fqs(p, fq, &swapped_msg);
 851                                 break;
 852                         case QM_MR_VERB_FQPN:
 853                                 /* Parked */
 854 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
 855                                 fq = get_fq_table_entry(
 856                                         be32_to_cpu(msg->fq.contextB));
 857 #else
 858                                 fq = (void *)(uintptr_t)
 859                                         be32_to_cpu(msg->fq.contextB);
 860 #endif
 861                                 fq_state_change(p, fq, msg, verb);
 862                                 if (fq->cb.fqs)
 863                                         fq->cb.fqs(p, fq, &swapped_msg);
 864                                 break;
 865                         case QM_MR_VERB_DC_ERN:
 866                                 /* DCP ERN */
 867                                 if (p->cb_dc_ern)
 868                                         p->cb_dc_ern(p, msg);
 869                                 else if (cb_dc_ern)
 870                                         cb_dc_ern(p, msg);
 871                                 else {
 872                                         static int warn_once;
 873
 874                                         if (!warn_once) {
 875                                                 pr_crit("Leaking DCP ERNs!\n");
 876                                                 warn_once = 1;
 877                                         }
 878                                 }
 879                                 break;
 880                         default:
 881                                 pr_crit("Invalid MR verb 0x%02x\n", verb);
 882                         }
 883                 } else {
 884                         /* Its a software ERN */
 885 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
 886                         fq = get_fq_table_entry(be32_to_cpu(msg->ern.tag));
 887 #else
 888                         fq = (void *)(uintptr_t)be32_to_cpu(msg->ern.tag);
 889 #endif
 890                         fq->cb.ern(p, fq, &swapped_msg);
 891                 }
 892                 num++;
 893                 qm_mr_next(&p->p);
 894                 goto mr_loop;
 895 mr_done:
 896                 qm_mr_cci_consume(&p->p, num);
 897         }
 898         /*
 899          * QM_PIRQ_CSCI/CCSCI has already been cleared, as part of its specific
 900          * processing. If that interrupt source has meanwhile been re-asserted,
 901          * we mustn't clear it here (or in the top-level interrupt handler).
 902          */
 903         return is & (QM_PIRQ_EQCI | QM_PIRQ_EQRI | QM_PIRQ_MRI);
 904 }
 905
 906 /*
 907  * remove some slowish-path stuff from the "fast path" and make sure it isn't
 908  * inlined.
 909  */
 910 static noinline void clear_vdqcr(struct qman_portal *p, struct qman_fq *fq)
 911 {
 912         p->vdqcr_owned = NULL;
 913         FQLOCK(fq);
 914         fq_clear(fq, QMAN_FQ_STATE_VDQCR);
 915         FQUNLOCK(fq);
 916         wake_up(&affine_queue);
 917 }
 918
 919 /*
 920  * The only states that would conflict with other things if they ran at the
 921  * same time on the same cpu are:
 922  *
 923  *   (i) setting/clearing vdqcr_owned, and
 924  *  (ii) clearing the NE (Not Empty) flag.
 925  *
 926  * Both are safe. Because;
 927  *
 928  *   (i) this clearing can only occur after qman_set_vdq() has set the
 929  *       vdqcr_owned field (which it does before setting VDQCR), and
 930  *       qman_volatile_dequeue() blocks interrupts and preemption while this is
 931  *       done so that we can't interfere.
 932  *  (ii) the NE flag is only cleared after qman_retire_fq() has set it, and as
 933  *       with (i) that API prevents us from interfering until it's safe.
 934  *
 935  * The good thing is that qman_set_vdq() and qman_retire_fq() run far
 936  * less frequently (ie. per-FQ) than __poll_portal_fast() does, so the nett
 937  * advantage comes from this function not having to "lock" anything at all.
 938  *
 939  * Note also that the callbacks are invoked at points which are safe against the
 940  * above potential conflicts, but that this function itself is not re-entrant
 941  * (this is because the function tracks one end of each FIFO in the portal and
 942  * we do *not* want to lock that). So the consequence is that it is safe for
 943  * user callbacks to call into any QMan API.
 944  */
 945 static inline unsigned int __poll_portal_fast(struct qman_portal *p,
 946                                               unsigned int poll_limit)
 947 {
 948         const struct qm_dqrr_entry *dq;
 949         struct qman_fq *fq;
 950         enum qman_cb_dqrr_result res;
 951         unsigned int limit = 0;
 952 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
 953         struct qm_dqrr_entry *shadow;
 954 #endif
 955         do {
 956                 qm_dqrr_pvb_update(&p->p);
 957                 dq = qm_dqrr_current(&p->p);
 958                 if (unlikely(!dq))
 959                         break;
 960 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
 961         /* If running on an LE system the fields of the
 962          * dequeue entry must be swapper.  Because the
 963          * QMan HW will ignore writes the DQRR entry is
 964          * copied and the index stored within the copy
 965          */
 966                 shadow = &p->shadow_dqrr[DQRR_PTR2IDX(dq)];
 967                 *shadow = *dq;
 968                 dq = shadow;
 969                 shadow->fqid = be32_to_cpu(shadow->fqid);
 970                 shadow->contextB = be32_to_cpu(shadow->contextB);
 971                 shadow->seqnum = be16_to_cpu(shadow->seqnum);
 972                 hw_fd_to_cpu(&shadow->fd);
 973 #endif
 974
 975                 if (dq->stat & QM_DQRR_STAT_UNSCHEDULED) {
 976                         /*
 977                          * VDQCR: don't trust context_b as the FQ may have
 978                          * been configured for h/w consumption and we're
 979                          * draining it post-retirement.
 980                          */
 981                         fq = p->vdqcr_owned;
 982                         /*
 983                          * We only set QMAN_FQ_STATE_NE when retiring, so we
 984                          * only need to check for clearing it when doing
 985                          * volatile dequeues.  It's one less thing to check
 986                          * in the critical path (SDQCR).
 987                          */
 988                         if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
 989                                 fq_clear(fq, QMAN_FQ_STATE_NE);
 990                         /*
 991                          * This is duplicated from the SDQCR code, but we
 992                          * have stuff to do before *and* after this callback,
 993                          * and we don't want multiple if()s in the critical
 994                          * path (SDQCR).
 995                          */
 996                         res = fq->cb.dqrr(p, fq, dq);
 997                         if (res == qman_cb_dqrr_stop)
 998                                 break;
 999                         /* Check for VDQCR completion */
1000                         if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1001                                 clear_vdqcr(p, fq);
1002                 } else {
1003                         /* SDQCR: context_b points to the FQ */
1004 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1005                         fq = get_fq_table_entry(dq->contextB);
1006 #else
1007                         fq = (void *)(uintptr_t)dq->contextB;
1008 #endif
1009                         /* Now let the callback do its stuff */
1010                         res = fq->cb.dqrr(p, fq, dq);
1011                         /*
1012                          * The callback can request that we exit without
1013                          * consuming this entry nor advancing;
1014                          */
1015                         if (res == qman_cb_dqrr_stop)
1016                                 break;
1017                 }
1018                 /* Interpret 'dq' from a driver perspective. */
1019                 /*
1020                  * Parking isn't possible unless HELDACTIVE was set. NB,
1021                  * FORCEELIGIBLE implies HELDACTIVE, so we only need to
1022                  * check for HELDACTIVE to cover both.
1023                  */
1024                 DPAA_ASSERT((dq->stat & QM_DQRR_STAT_FQ_HELDACTIVE) ||
1025                             (res != qman_cb_dqrr_park));
1026                 /* just means "skip it, I'll consume it myself later on" */
1027                 if (res != qman_cb_dqrr_defer)
1028                         qm_dqrr_cdc_consume_1ptr(&p->p, dq,
1029                                                  res == qman_cb_dqrr_park);
1030                 /* Move forward */
1031                 qm_dqrr_next(&p->p);
1032                 /*
1033                  * Entry processed and consumed, increment our counter.  The
1034                  * callback can request that we exit after consuming the
1035                  * entry, and we also exit if we reach our processing limit,
1036                  * so loop back only if neither of these conditions is met.
1037                  */
1038         } while (++limit < poll_limit && res != qman_cb_dqrr_consume_stop);
1039
1040         return limit;
1041 }
1042
1043 u16 qman_affine_channel(int cpu)
1044 {
1045         if (cpu < 0) {
1046                 struct qman_portal *portal = get_affine_portal();
1047
1048                 cpu = portal->config->cpu;
1049         }
1050         DPAA_BUG_ON(!CPU_ISSET(cpu, &affine_mask));
1051         return affine_channels[cpu];
1052 }
1053
1054 struct qm_dqrr_entry *qman_dequeue(struct qman_fq *fq)
1055 {
1056         struct qman_portal *p = get_affine_portal();
1057         const struct qm_dqrr_entry *dq;
1058 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
1059         struct qm_dqrr_entry *shadow;
1060 #endif
1061
1062         qm_dqrr_pvb_update(&p->p);
1063         dq = qm_dqrr_current(&p->p);
1064         if (!dq)
1065                 return NULL;
1066
1067         if (!(dq->stat & QM_DQRR_STAT_FD_VALID)) {
1068                 /* Invalid DQRR - put the portal and consume the DQRR.
1069                  * Return NULL to user as no packet is seen.
1070                  */
1071                 qman_dqrr_consume(fq, (struct qm_dqrr_entry *)dq);
1072                 return NULL;
1073         }
1074
1075 #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
1076         shadow = &p->shadow_dqrr[DQRR_PTR2IDX(dq)];
1077         *shadow = *dq;
1078         dq = shadow;
1079         shadow->fqid = be32_to_cpu(shadow->fqid);
1080         shadow->contextB = be32_to_cpu(shadow->contextB);
1081         shadow->seqnum = be16_to_cpu(shadow->seqnum);
1082         hw_fd_to_cpu(&shadow->fd);
1083 #endif
1084
1085         if (dq->stat & QM_DQRR_STAT_FQ_EMPTY)
1086                 fq_clear(fq, QMAN_FQ_STATE_NE);
1087
1088         return (struct qm_dqrr_entry *)dq;
1089 }
1090
1091 void qman_dqrr_consume(struct qman_fq *fq,
1092                        struct qm_dqrr_entry *dq)
1093 {
1094         struct qman_portal *p = get_affine_portal();
1095
1096         if (dq->stat & QM_DQRR_STAT_DQCR_EXPIRED)
1097                 clear_vdqcr(p, fq);
1098
1099         qm_dqrr_cdc_consume_1ptr(&p->p, dq, 0);
1100         qm_dqrr_next(&p->p);
1101 }
1102
1103 int qman_poll_dqrr(unsigned int limit)
1104 {
1105         struct qman_portal *p = get_affine_portal();
1106         int ret;
1107
1108         ret = __poll_portal_fast(p, limit);
1109         return ret;
1110 }
1111
1112 void qman_poll(void)
1113 {
1114         struct qman_portal *p = get_affine_portal();
1115
1116         if ((~p->irq_sources) & QM_PIRQ_SLOW) {
1117                 if (!(p->slowpoll--)) {
1118                         u32 is = qm_isr_status_read(&p->p) & ~p->irq_sources;
1119                         u32 active = __poll_portal_slow(p, is);
1120
1121                         if (active) {
1122                                 qm_isr_status_clear(&p->p, active);
1123                                 p->slowpoll = SLOW_POLL_BUSY;
1124                         } else
1125                                 p->slowpoll = SLOW_POLL_IDLE;
1126                 }
1127         }
1128         if ((~p->irq_sources) & QM_PIRQ_DQRI)
1129                 __poll_portal_fast(p, FSL_QMAN_POLL_LIMIT);
1130 }
1131
1132 void qman_stop_dequeues(void)
1133 {
1134         struct qman_portal *p = get_affine_portal();
1135
1136         qman_stop_dequeues_ex(p);
1137 }
1138
1139 void qman_start_dequeues(void)
1140 {
1141         struct qman_portal *p = get_affine_portal();
1142
1143         DPAA_ASSERT(p->dqrr_disable_ref > 0);
1144         if (!(--p->dqrr_disable_ref))
1145                 qm_dqrr_set_maxfill(&p->p, DQRR_MAXFILL);
1146 }
1147
1148 void qman_static_dequeue_add(u32 pools, struct qman_portal *qp)
1149 {
1150         struct qman_portal *p = qp ? qp : get_affine_portal();
1151
1152         pools &= p->config->pools;
1153         p->sdqcr |= pools;
1154         qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1155 }
1156
1157 void qman_static_dequeue_del(u32 pools, struct qman_portal *qp)
1158 {
1159         struct qman_portal *p = qp ? qp : get_affine_portal();
1160
1161         pools &= p->config->pools;
1162         p->sdqcr &= ~pools;
1163         qm_dqrr_sdqcr_set(&p->p, p->sdqcr);
1164 }
1165
1166 u32 qman_static_dequeue_get(struct qman_portal *qp)
1167 {
1168         struct qman_portal *p = qp ? qp : get_affine_portal();
1169         return p->sdqcr;
1170 }
1171
1172 void qman_dca(struct qm_dqrr_entry *dq, int park_request)
1173 {
1174         struct qman_portal *p = get_affine_portal();
1175
1176         qm_dqrr_cdc_consume_1ptr(&p->p, dq, park_request);
1177 }
1178
1179 /* Frame queue API */
1180 static const char *mcr_result_str(u8 result)
1181 {
1182         switch (result) {
1183         case QM_MCR_RESULT_NULL:
1184                 return "QM_MCR_RESULT_NULL";
1185         case QM_MCR_RESULT_OK:
1186                 return "QM_MCR_RESULT_OK";
1187         case QM_MCR_RESULT_ERR_FQID:
1188                 return "QM_MCR_RESULT_ERR_FQID";
1189         case QM_MCR_RESULT_ERR_FQSTATE:
1190                 return "QM_MCR_RESULT_ERR_FQSTATE";
1191         case QM_MCR_RESULT_ERR_NOTEMPTY:
1192                 return "QM_MCR_RESULT_ERR_NOTEMPTY";
1193         case QM_MCR_RESULT_PENDING:
1194                 return "QM_MCR_RESULT_PENDING";
1195         case QM_MCR_RESULT_ERR_BADCOMMAND:
1196                 return "QM_MCR_RESULT_ERR_BADCOMMAND";
1197         }
1198         return "<unknown MCR result>";
1199 }
1200
1201 int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq)
1202 {
1203         struct qm_fqd fqd;
1204         struct qm_mcr_queryfq_np np;
1205         struct qm_mc_command *mcc;
1206         struct qm_mc_result *mcr;
1207         struct qman_portal *p;
1208
1209         if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID) {
1210                 int ret = qman_alloc_fqid(&fqid);
1211
1212                 if (ret)
1213                         return ret;
1214         }
1215         spin_lock_init(&fq->fqlock);
1216         fq->fqid = fqid;
1217         fq->fqid_le = cpu_to_be32(fqid);
1218         fq->flags = flags;
1219         fq->state = qman_fq_state_oos;
1220         fq->cgr_groupid = 0;
1221 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1222         if (unlikely(find_empty_fq_table_entry(&fq->key, fq))) {
1223                 pr_info("Find empty table entry failed\n");
1224                 return -ENOMEM;
1225         }
1226 #endif
1227         if (!(flags & QMAN_FQ_FLAG_AS_IS) || (flags & QMAN_FQ_FLAG_NO_MODIFY))
1228                 return 0;
1229         /* Everything else is AS_IS support */
1230         p = get_affine_portal();
1231         mcc = qm_mc_start(&p->p);
1232         mcc->queryfq.fqid = cpu_to_be32(fqid);
1233         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
1234         while (!(mcr = qm_mc_result(&p->p)))
1235                 cpu_relax();
1236         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ);
1237         if (mcr->result != QM_MCR_RESULT_OK) {
1238                 pr_err("QUERYFQ failed: %s\n", mcr_result_str(mcr->result));
1239                 goto err;
1240         }
1241         fqd = mcr->queryfq.fqd;
1242         hw_fqd_to_cpu(&fqd);
1243         mcc = qm_mc_start(&p->p);
1244         mcc->queryfq_np.fqid = cpu_to_be32(fqid);
1245         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
1246         while (!(mcr = qm_mc_result(&p->p)))
1247                 cpu_relax();
1248         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYFQ_NP);
1249         if (mcr->result != QM_MCR_RESULT_OK) {
1250                 pr_err("QUERYFQ_NP failed: %s\n", mcr_result_str(mcr->result));
1251                 goto err;
1252         }
1253         np = mcr->queryfq_np;
1254         /* Phew, have queryfq and queryfq_np results, stitch together
1255          * the FQ object from those.
1256          */
1257         fq->cgr_groupid = fqd.cgid;
1258         switch (np.state & QM_MCR_NP_STATE_MASK) {
1259         case QM_MCR_NP_STATE_OOS:
1260                 break;
1261         case QM_MCR_NP_STATE_RETIRED:
1262                 fq->state = qman_fq_state_retired;
1263                 if (np.frm_cnt)
1264                         fq_set(fq, QMAN_FQ_STATE_NE);
1265                 break;
1266         case QM_MCR_NP_STATE_TEN_SCHED:
1267         case QM_MCR_NP_STATE_TRU_SCHED:
1268         case QM_MCR_NP_STATE_ACTIVE:
1269                 fq->state = qman_fq_state_sched;
1270                 if (np.state & QM_MCR_NP_STATE_R)
1271                         fq_set(fq, QMAN_FQ_STATE_CHANGING);
1272                 break;
1273         case QM_MCR_NP_STATE_PARKED:
1274                 fq->state = qman_fq_state_parked;
1275                 break;
1276         default:
1277                 DPAA_ASSERT(NULL == "invalid FQ state");
1278         }
1279         if (fqd.fq_ctrl & QM_FQCTRL_CGE)
1280                 fq->state |= QMAN_FQ_STATE_CGR_EN;
1281         return 0;
1282 err:
1283         if (flags & QMAN_FQ_FLAG_DYNAMIC_FQID)
1284                 qman_release_fqid(fqid);
1285         return -EIO;
1286 }
1287
1288 void qman_destroy_fq(struct qman_fq *fq, u32 flags __maybe_unused)
1289 {
1290         /*
1291          * We don't need to lock the FQ as it is a pre-condition that the FQ be
1292          * quiesced. Instead, run some checks.
1293          */
1294         switch (fq->state) {
1295         case qman_fq_state_parked:
1296                 DPAA_ASSERT(flags & QMAN_FQ_DESTROY_PARKED);
1297                 /* Fallthrough */
1298         case qman_fq_state_oos:
1299                 if (fq_isset(fq, QMAN_FQ_FLAG_DYNAMIC_FQID))
1300                         qman_release_fqid(fq->fqid);
1301 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1302                 clear_fq_table_entry(fq->key);
1303 #endif
1304                 return;
1305         default:
1306                 break;
1307         }
1308         DPAA_ASSERT(NULL == "qman_free_fq() on unquiesced FQ!");
1309 }
1310
1311 u32 qman_fq_fqid(struct qman_fq *fq)
1312 {
1313         return fq->fqid;
1314 }
1315
1316 void qman_fq_state(struct qman_fq *fq, enum qman_fq_state *state, u32 *flags)
1317 {
1318         if (state)
1319                 *state = fq->state;
1320         if (flags)
1321                 *flags = fq->flags;
1322 }
1323
1324 int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
1325 {
1326         struct qm_mc_command *mcc;
1327         struct qm_mc_result *mcr;
1328         struct qman_portal *p;
1329
1330         u8 res, myverb = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1331                 QM_MCC_VERB_INITFQ_SCHED : QM_MCC_VERB_INITFQ_PARKED;
1332
1333         if ((fq->state != qman_fq_state_oos) &&
1334             (fq->state != qman_fq_state_parked))
1335                 return -EINVAL;
1336 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1337         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1338                 return -EINVAL;
1339 #endif
1340         if (opts && (opts->we_mask & QM_INITFQ_WE_OAC)) {
1341                 /* And can't be set at the same time as TDTHRESH */
1342                 if (opts->we_mask & QM_INITFQ_WE_TDTHRESH)
1343                         return -EINVAL;
1344         }
1345         /* Issue an INITFQ_[PARKED|SCHED] management command */
1346         p = get_affine_portal();
1347         FQLOCK(fq);
1348         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) ||
1349                      ((fq->state != qman_fq_state_oos) &&
1350                                 (fq->state != qman_fq_state_parked)))) {
1351                 FQUNLOCK(fq);
1352                 return -EBUSY;
1353         }
1354         mcc = qm_mc_start(&p->p);
1355         if (opts)
1356                 mcc->initfq = *opts;
1357         mcc->initfq.fqid = cpu_to_be32(fq->fqid);
1358         mcc->initfq.count = 0;
1359         /*
1360          * If the FQ does *not* have the TO_DCPORTAL flag, context_b is set as a
1361          * demux pointer. Otherwise, the caller-provided value is allowed to
1362          * stand, don't overwrite it.
1363          */
1364         if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
1365                 dma_addr_t phys_fq;
1366
1367                 mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTB;
1368 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1369                 mcc->initfq.fqd.context_b = fq->key;
1370 #else
1371                 mcc->initfq.fqd.context_b = (u32)(uintptr_t)fq;
1372 #endif
1373                 /*
1374                  *  and the physical address - NB, if the user wasn't trying to
1375                  * set CONTEXTA, clear the stashing settings.
1376                  */
1377                 if (!(mcc->initfq.we_mask & QM_INITFQ_WE_CONTEXTA)) {
1378                         mcc->initfq.we_mask |= QM_INITFQ_WE_CONTEXTA;
1379                         memset(&mcc->initfq.fqd.context_a, 0,
1380                                sizeof(mcc->initfq.fqd.context_a));
1381                 } else {
1382                         phys_fq = rte_mem_virt2iova(fq);
1383                         qm_fqd_stashing_set64(&mcc->initfq.fqd, phys_fq);
1384                 }
1385         }
1386         if (flags & QMAN_INITFQ_FLAG_LOCAL) {
1387                 mcc->initfq.fqd.dest.channel = p->config->channel;
1388                 if (!(mcc->initfq.we_mask & QM_INITFQ_WE_DESTWQ)) {
1389                         mcc->initfq.we_mask |= QM_INITFQ_WE_DESTWQ;
1390                         mcc->initfq.fqd.dest.wq = 4;
1391                 }
1392         }
1393         mcc->initfq.we_mask = cpu_to_be16(mcc->initfq.we_mask);
1394         cpu_to_hw_fqd(&mcc->initfq.fqd);
1395         qm_mc_commit(&p->p, myverb);
1396         while (!(mcr = qm_mc_result(&p->p)))
1397                 cpu_relax();
1398         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1399         res = mcr->result;
1400         if (res != QM_MCR_RESULT_OK) {
1401                 FQUNLOCK(fq);
1402                 return -EIO;
1403         }
1404         if (opts) {
1405                 if (opts->we_mask & QM_INITFQ_WE_FQCTRL) {
1406                         if (opts->fqd.fq_ctrl & QM_FQCTRL_CGE)
1407                                 fq_set(fq, QMAN_FQ_STATE_CGR_EN);
1408                         else
1409                                 fq_clear(fq, QMAN_FQ_STATE_CGR_EN);
1410                 }
1411                 if (opts->we_mask & QM_INITFQ_WE_CGID)
1412                         fq->cgr_groupid = opts->fqd.cgid;
1413         }
1414         fq->state = (flags & QMAN_INITFQ_FLAG_SCHED) ?
1415                 qman_fq_state_sched : qman_fq_state_parked;
1416         FQUNLOCK(fq);
1417         return 0;
1418 }
1419
1420 int qman_schedule_fq(struct qman_fq *fq)
1421 {
1422         struct qm_mc_command *mcc;
1423         struct qm_mc_result *mcr;
1424         struct qman_portal *p;
1425
1426         int ret = 0;
1427         u8 res;
1428
1429         if (fq->state != qman_fq_state_parked)
1430                 return -EINVAL;
1431 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1432         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1433                 return -EINVAL;
1434 #endif
1435         /* Issue a ALTERFQ_SCHED management command */
1436         p = get_affine_portal();
1437
1438         FQLOCK(fq);
1439         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) ||
1440                      (fq->state != qman_fq_state_parked))) {
1441                 ret = -EBUSY;
1442                 goto out;
1443         }
1444         mcc = qm_mc_start(&p->p);
1445         mcc->alterfq.fqid = cpu_to_be32(fq->fqid);
1446         qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_SCHED);
1447         while (!(mcr = qm_mc_result(&p->p)))
1448                 cpu_relax();
1449         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_SCHED);
1450         res = mcr->result;
1451         if (res != QM_MCR_RESULT_OK) {
1452                 ret = -EIO;
1453                 goto out;
1454         }
1455         fq->state = qman_fq_state_sched;
1456 out:
1457         FQUNLOCK(fq);
1458
1459         return ret;
1460 }
1461
1462 int qman_retire_fq(struct qman_fq *fq, u32 *flags)
1463 {
1464         struct qm_mc_command *mcc;
1465         struct qm_mc_result *mcr;
1466         struct qman_portal *p;
1467
1468         int rval;
1469         u8 res;
1470
1471         if ((fq->state != qman_fq_state_parked) &&
1472             (fq->state != qman_fq_state_sched))
1473                 return -EINVAL;
1474 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1475         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1476                 return -EINVAL;
1477 #endif
1478         p = get_affine_portal();
1479
1480         FQLOCK(fq);
1481         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) ||
1482                      (fq->state == qman_fq_state_retired) ||
1483                                 (fq->state == qman_fq_state_oos))) {
1484                 rval = -EBUSY;
1485                 goto out;
1486         }
1487         rval = table_push_fq(p, fq);
1488         if (rval)
1489                 goto out;
1490         mcc = qm_mc_start(&p->p);
1491         mcc->alterfq.fqid = cpu_to_be32(fq->fqid);
1492         qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_RETIRE);
1493         while (!(mcr = qm_mc_result(&p->p)))
1494                 cpu_relax();
1495         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_RETIRE);
1496         res = mcr->result;
1497         /*
1498          * "Elegant" would be to treat OK/PENDING the same way; set CHANGING,
1499          * and defer the flags until FQRNI or FQRN (respectively) show up. But
1500          * "Friendly" is to process OK immediately, and not set CHANGING. We do
1501          * friendly, otherwise the caller doesn't necessarily have a fully
1502          * "retired" FQ on return even if the retirement was immediate. However
1503          * this does mean some code duplication between here and
1504          * fq_state_change().
1505          */
1506         if (likely(res == QM_MCR_RESULT_OK)) {
1507                 rval = 0;
1508                 /* Process 'fq' right away, we'll ignore FQRNI */
1509                 if (mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY)
1510                         fq_set(fq, QMAN_FQ_STATE_NE);
1511                 if (mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)
1512                         fq_set(fq, QMAN_FQ_STATE_ORL);
1513                 else
1514                         table_del_fq(p, fq);
1515                 if (flags)
1516                         *flags = fq->flags;
1517                 fq->state = qman_fq_state_retired;
1518                 if (fq->cb.fqs) {
1519                         /*
1520                          * Another issue with supporting "immediate" retirement
1521                          * is that we're forced to drop FQRNIs, because by the
1522                          * time they're seen it may already be "too late" (the
1523                          * fq may have been OOS'd and free()'d already). But if
1524                          * the upper layer wants a callback whether it's
1525                          * immediate or not, we have to fake a "MR" entry to
1526                          * look like an FQRNI...
1527                          */
1528                         struct qm_mr_entry msg;
1529
1530                         msg.verb = QM_MR_VERB_FQRNI;
1531                         msg.fq.fqs = mcr->alterfq.fqs;
1532                         msg.fq.fqid = fq->fqid;
1533 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1534                         msg.fq.contextB = fq->key;
1535 #else
1536                         msg.fq.contextB = (u32)(uintptr_t)fq;
1537 #endif
1538                         fq->cb.fqs(p, fq, &msg);
1539                 }
1540         } else if (res == QM_MCR_RESULT_PENDING) {
1541                 rval = 1;
1542                 fq_set(fq, QMAN_FQ_STATE_CHANGING);
1543         } else {
1544                 rval = -EIO;
1545                 table_del_fq(p, fq);
1546         }
1547 out:
1548         FQUNLOCK(fq);
1549         return rval;
1550 }
1551
1552 int qman_oos_fq(struct qman_fq *fq)
1553 {
1554         struct qm_mc_command *mcc;
1555         struct qm_mc_result *mcr;
1556         struct qman_portal *p;
1557
1558         int ret = 0;
1559         u8 res;
1560
1561         if (fq->state != qman_fq_state_retired)
1562                 return -EINVAL;
1563 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1564         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1565                 return -EINVAL;
1566 #endif
1567         p = get_affine_portal();
1568         FQLOCK(fq);
1569         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_BLOCKOOS)) ||
1570                      (fq->state != qman_fq_state_retired))) {
1571                 ret = -EBUSY;
1572                 goto out;
1573         }
1574         mcc = qm_mc_start(&p->p);
1575         mcc->alterfq.fqid = cpu_to_be32(fq->fqid);
1576         qm_mc_commit(&p->p, QM_MCC_VERB_ALTER_OOS);
1577         while (!(mcr = qm_mc_result(&p->p)))
1578                 cpu_relax();
1579         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_ALTER_OOS);
1580         res = mcr->result;
1581         if (res != QM_MCR_RESULT_OK) {
1582                 ret = -EIO;
1583                 goto out;
1584         }
1585         fq->state = qman_fq_state_oos;
1586 out:
1587         FQUNLOCK(fq);
1588         return ret;
1589 }
1590
1591 int qman_fq_flow_control(struct qman_fq *fq, int xon)
1592 {
1593         struct qm_mc_command *mcc;
1594         struct qm_mc_result *mcr;
1595         struct qman_portal *p;
1596
1597         int ret = 0;
1598         u8 res;
1599         u8 myverb;
1600
1601         if ((fq->state == qman_fq_state_oos) ||
1602             (fq->state == qman_fq_state_retired) ||
1603                 (fq->state == qman_fq_state_parked))
1604                 return -EINVAL;
1605
1606 #ifdef RTE_LIBRTE_DPAA_HWDEBUG
1607         if (unlikely(fq_isset(fq, QMAN_FQ_FLAG_NO_MODIFY)))
1608                 return -EINVAL;
1609 #endif
1610         /* Issue a ALTER_FQXON or ALTER_FQXOFF management command */
1611         p = get_affine_portal();
1612         FQLOCK(fq);
1613         if (unlikely((fq_isset(fq, QMAN_FQ_STATE_CHANGING)) ||
1614                      (fq->state == qman_fq_state_parked) ||
1615                         (fq->state == qman_fq_state_oos) ||
1616                         (fq->state == qman_fq_state_retired))) {
1617                 ret = -EBUSY;
1618                 goto out;
1619         }
1620         mcc = qm_mc_start(&p->p);
1621         mcc->alterfq.fqid = fq->fqid;
1622         mcc->alterfq.count = 0;
1623         myverb = xon ? QM_MCC_VERB_ALTER_FQXON : QM_MCC_VERB_ALTER_FQXOFF;
1624
1625         qm_mc_commit(&p->p, myverb);
1626         while (!(mcr = qm_mc_result(&p->p)))
1627                 cpu_relax();
1628         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1629
1630         res = mcr->result;
1631         if (res != QM_MCR_RESULT_OK) {
1632                 ret = -EIO;
1633                 goto out;
1634         }
1635 out:
1636         FQUNLOCK(fq);
1637         return ret;
1638 }
1639
1640 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
1641 {
1642         struct qm_mc_command *mcc;
1643         struct qm_mc_result *mcr;
1644         struct qman_portal *p = get_affine_portal();
1645
1646         u8 res;
1647
1648         mcc = qm_mc_start(&p->p);
1649         mcc->queryfq.fqid = cpu_to_be32(fq->fqid);
1650         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ);
1651         while (!(mcr = qm_mc_result(&p->p)))
1652                 cpu_relax();
1653         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
1654         res = mcr->result;
1655         if (res == QM_MCR_RESULT_OK)
1656                 *fqd = mcr->queryfq.fqd;
1657         hw_fqd_to_cpu(fqd);
1658         if (res != QM_MCR_RESULT_OK)
1659                 return -EIO;
1660         return 0;
1661 }
1662
1663 int qman_query_fq_has_pkts(struct qman_fq *fq)
1664 {
1665         struct qm_mc_command *mcc;
1666         struct qm_mc_result *mcr;
1667         struct qman_portal *p = get_affine_portal();
1668
1669         int ret = 0;
1670         u8 res;
1671
1672         mcc = qm_mc_start(&p->p);
1673         mcc->queryfq.fqid = cpu_to_be32(fq->fqid);
1674         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
1675         while (!(mcr = qm_mc_result(&p->p)))
1676                 cpu_relax();
1677         res = mcr->result;
1678         if (res == QM_MCR_RESULT_OK)
1679                 ret = !!mcr->queryfq_np.frm_cnt;
1680         return ret;
1681 }
1682
1683 int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
1684 {
1685         struct qm_mc_command *mcc;
1686         struct qm_mc_result *mcr;
1687         struct qman_portal *p = get_affine_portal();
1688
1689         u8 res;
1690
1691         mcc = qm_mc_start(&p->p);
1692         mcc->queryfq.fqid = cpu_to_be32(fq->fqid);
1693         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYFQ_NP);
1694         while (!(mcr = qm_mc_result(&p->p)))
1695                 cpu_relax();
1696         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
1697         res = mcr->result;
1698         if (res == QM_MCR_RESULT_OK) {
1699                 *np = mcr->queryfq_np;
1700                 np->fqd_link = be24_to_cpu(np->fqd_link);
1701                 np->odp_seq = be16_to_cpu(np->odp_seq);
1702                 np->orp_nesn = be16_to_cpu(np->orp_nesn);
1703                 np->orp_ea_hseq  = be16_to_cpu(np->orp_ea_hseq);
1704                 np->orp_ea_tseq  = be16_to_cpu(np->orp_ea_tseq);
1705                 np->orp_ea_hptr = be24_to_cpu(np->orp_ea_hptr);
1706                 np->orp_ea_tptr = be24_to_cpu(np->orp_ea_tptr);
1707                 np->pfdr_hptr = be24_to_cpu(np->pfdr_hptr);
1708                 np->pfdr_tptr = be24_to_cpu(np->pfdr_tptr);
1709                 np->ics_surp = be16_to_cpu(np->ics_surp);
1710                 np->byte_cnt = be32_to_cpu(np->byte_cnt);
1711                 np->frm_cnt = be24_to_cpu(np->frm_cnt);
1712                 np->ra1_sfdr = be16_to_cpu(np->ra1_sfdr);
1713                 np->ra2_sfdr = be16_to_cpu(np->ra2_sfdr);
1714                 np->od1_sfdr = be16_to_cpu(np->od1_sfdr);
1715                 np->od2_sfdr = be16_to_cpu(np->od2_sfdr);
1716                 np->od3_sfdr = be16_to_cpu(np->od3_sfdr);
1717         }
1718         if (res == QM_MCR_RESULT_ERR_FQID)
1719                 return -ERANGE;
1720         else if (res != QM_MCR_RESULT_OK)
1721                 return -EIO;
1722         return 0;
1723 }
1724
1725 int qman_query_wq(u8 query_dedicated, struct qm_mcr_querywq *wq)
1726 {
1727         struct qm_mc_command *mcc;
1728         struct qm_mc_result *mcr;
1729         struct qman_portal *p = get_affine_portal();
1730
1731         u8 res, myverb;
1732
1733         myverb = (query_dedicated) ? QM_MCR_VERB_QUERYWQ_DEDICATED :
1734                                  QM_MCR_VERB_QUERYWQ;
1735         mcc = qm_mc_start(&p->p);
1736         mcc->querywq.channel.id = cpu_to_be16(wq->channel.id);
1737         qm_mc_commit(&p->p, myverb);
1738         while (!(mcr = qm_mc_result(&p->p)))
1739                 cpu_relax();
1740         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == myverb);
1741         res = mcr->result;
1742         if (res == QM_MCR_RESULT_OK) {
1743                 int i, array_len;
1744
1745                 wq->channel.id = be16_to_cpu(mcr->querywq.channel.id);
1746                 array_len = ARRAY_SIZE(mcr->querywq.wq_len);
1747                 for (i = 0; i < array_len; i++)
1748                         wq->wq_len[i] = be32_to_cpu(mcr->querywq.wq_len[i]);
1749         }
1750         if (res != QM_MCR_RESULT_OK) {
1751                 pr_err("QUERYWQ failed: %s\n", mcr_result_str(res));
1752                 return -EIO;
1753         }
1754         return 0;
1755 }
1756
1757 int qman_testwrite_cgr(struct qman_cgr *cgr, u64 i_bcnt,
1758                        struct qm_mcr_cgrtestwrite *result)
1759 {
1760         struct qm_mc_command *mcc;
1761         struct qm_mc_result *mcr;
1762         struct qman_portal *p = get_affine_portal();
1763
1764         u8 res;
1765
1766         mcc = qm_mc_start(&p->p);
1767         mcc->cgrtestwrite.cgid = cgr->cgrid;
1768         mcc->cgrtestwrite.i_bcnt_hi = (u8)(i_bcnt >> 32);
1769         mcc->cgrtestwrite.i_bcnt_lo = (u32)i_bcnt;
1770         qm_mc_commit(&p->p, QM_MCC_VERB_CGRTESTWRITE);
1771         while (!(mcr = qm_mc_result(&p->p)))
1772                 cpu_relax();
1773         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_CGRTESTWRITE);
1774         res = mcr->result;
1775         if (res == QM_MCR_RESULT_OK)
1776                 *result = mcr->cgrtestwrite;
1777         if (res != QM_MCR_RESULT_OK) {
1778                 pr_err("CGR TEST WRITE failed: %s\n", mcr_result_str(res));
1779                 return -EIO;
1780         }
1781         return 0;
1782 }
1783
1784 int qman_query_cgr(struct qman_cgr *cgr, struct qm_mcr_querycgr *cgrd)
1785 {
1786         struct qm_mc_command *mcc;
1787         struct qm_mc_result *mcr;
1788         struct qman_portal *p = get_affine_portal();
1789         u8 res;
1790         unsigned int i;
1791
1792         mcc = qm_mc_start(&p->p);
1793         mcc->querycgr.cgid = cgr->cgrid;
1794         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCGR);
1795         while (!(mcr = qm_mc_result(&p->p)))
1796                 cpu_relax();
1797         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCC_VERB_QUERYCGR);
1798         res = mcr->result;
1799         if (res == QM_MCR_RESULT_OK)
1800                 *cgrd = mcr->querycgr;
1801         if (res != QM_MCR_RESULT_OK) {
1802                 pr_err("QUERY_CGR failed: %s\n", mcr_result_str(res));
1803                 return -EIO;
1804         }
1805         cgrd->cgr.wr_parm_g.word =
1806                 be32_to_cpu(cgrd->cgr.wr_parm_g.word);
1807         cgrd->cgr.wr_parm_y.word =
1808                 be32_to_cpu(cgrd->cgr.wr_parm_y.word);
1809         cgrd->cgr.wr_parm_r.word =
1810                 be32_to_cpu(cgrd->cgr.wr_parm_r.word);
1811         cgrd->cgr.cscn_targ =  be32_to_cpu(cgrd->cgr.cscn_targ);
1812         cgrd->cgr.__cs_thres = be16_to_cpu(cgrd->cgr.__cs_thres);
1813         for (i = 0; i < ARRAY_SIZE(cgrd->cscn_targ_swp); i++)
1814                 cgrd->cscn_targ_swp[i] =
1815                         be32_to_cpu(cgrd->cscn_targ_swp[i]);
1816         return 0;
1817 }
1818
1819 int qman_query_congestion(struct qm_mcr_querycongestion *congestion)
1820 {
1821         struct qm_mc_result *mcr;
1822         struct qman_portal *p = get_affine_portal();
1823         u8 res;
1824         unsigned int i;
1825
1826         qm_mc_start(&p->p);
1827         qm_mc_commit(&p->p, QM_MCC_VERB_QUERYCONGESTION);
1828         while (!(mcr = qm_mc_result(&p->p)))
1829                 cpu_relax();
1830         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
1831                         QM_MCC_VERB_QUERYCONGESTION);
1832         res = mcr->result;
1833         if (res == QM_MCR_RESULT_OK)
1834                 *congestion = mcr->querycongestion;
1835         if (res != QM_MCR_RESULT_OK) {
1836                 pr_err("QUERY_CONGESTION failed: %s\n", mcr_result_str(res));
1837                 return -EIO;
1838         }
1839         for (i = 0; i < ARRAY_SIZE(congestion->state.state); i++)
1840                 congestion->state.state[i] =
1841                         be32_to_cpu(congestion->state.state[i]);
1842         return 0;
1843 }
1844
1845 int qman_set_vdq(struct qman_fq *fq, u16 num)
1846 {
1847         struct qman_portal *p = get_affine_portal();
1848         uint32_t vdqcr;
1849         int ret = -EBUSY;
1850
1851         vdqcr = QM_VDQCR_EXACT;
1852         vdqcr |= QM_VDQCR_NUMFRAMES_SET(num);
1853
1854         if ((fq->state != qman_fq_state_parked) &&
1855             (fq->state != qman_fq_state_retired)) {
1856                 ret = -EINVAL;
1857                 goto out;
1858         }
1859         if (fq_isset(fq, QMAN_FQ_STATE_VDQCR)) {
1860                 ret = -EBUSY;
1861                 goto out;
1862         }
1863         vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
1864
1865         if (!p->vdqcr_owned) {
1866                 FQLOCK(fq);
1867                 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
1868                         goto escape;
1869                 fq_set(fq, QMAN_FQ_STATE_VDQCR);
1870                 FQUNLOCK(fq);
1871                 p->vdqcr_owned = fq;
1872                 ret = 0;
1873         }
1874 escape:
1875         if (!ret)
1876                 qm_dqrr_vdqcr_set(&p->p, vdqcr);
1877
1878 out:
1879         return ret;
1880 }
1881
1882 int qman_volatile_dequeue(struct qman_fq *fq, u32 flags __maybe_unused,
1883                           u32 vdqcr)
1884 {
1885         struct qman_portal *p;
1886         int ret = -EBUSY;
1887
1888         if ((fq->state != qman_fq_state_parked) &&
1889             (fq->state != qman_fq_state_retired))
1890                 return -EINVAL;
1891         if (vdqcr & QM_VDQCR_FQID_MASK)
1892                 return -EINVAL;
1893         if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
1894                 return -EBUSY;
1895         vdqcr = (vdqcr & ~QM_VDQCR_FQID_MASK) | fq->fqid;
1896
1897         p = get_affine_portal();
1898
1899         if (!p->vdqcr_owned) {
1900                 FQLOCK(fq);
1901                 if (fq_isset(fq, QMAN_FQ_STATE_VDQCR))
1902                         goto escape;
1903                 fq_set(fq, QMAN_FQ_STATE_VDQCR);
1904                 FQUNLOCK(fq);
1905                 p->vdqcr_owned = fq;
1906                 ret = 0;
1907         }
1908 escape:
1909         if (ret)
1910                 return ret;
1911
1912         /* VDQCR is set */
1913         qm_dqrr_vdqcr_set(&p->p, vdqcr);
1914         return 0;
1915 }
1916
1917 static noinline void update_eqcr_ci(struct qman_portal *p, u8 avail)
1918 {
1919         if (avail)
1920                 qm_eqcr_cce_prefetch(&p->p);
1921         else
1922                 qm_eqcr_cce_update(&p->p);
1923 }
1924
1925 int qman_eqcr_is_empty(void)
1926 {
1927         struct qman_portal *p = get_affine_portal();
1928         u8 avail;
1929
1930         update_eqcr_ci(p, 0);
1931         avail = qm_eqcr_get_fill(&p->p);
1932         return (avail == 0);
1933 }
1934
1935 void qman_set_dc_ern(qman_cb_dc_ern handler, int affine)
1936 {
1937         if (affine) {
1938                 struct qman_portal *p = get_affine_portal();
1939
1940                 p->cb_dc_ern = handler;
1941         } else
1942                 cb_dc_ern = handler;
1943 }
1944
1945 static inline struct qm_eqcr_entry *try_p_eq_start(struct qman_portal *p,
1946                                         struct qman_fq *fq,
1947                                         const struct qm_fd *fd,
1948                                         u32 flags)
1949 {
1950         struct qm_eqcr_entry *eq;
1951         u8 avail;
1952
1953         if (p->use_eqcr_ci_stashing) {
1954                 /*
1955                  * The stashing case is easy, only update if we need to in
1956                  * order to try and liberate ring entries.
1957                  */
1958                 eq = qm_eqcr_start_stash(&p->p);
1959         } else {
1960                 /*
1961                  * The non-stashing case is harder, need to prefetch ahead of
1962                  * time.
1963                  */
1964                 avail = qm_eqcr_get_avail(&p->p);
1965                 if (avail < 2)
1966                         update_eqcr_ci(p, avail);
1967                 eq = qm_eqcr_start_no_stash(&p->p);
1968         }
1969
1970         if (unlikely(!eq))
1971                 return NULL;
1972
1973         if (flags & QMAN_ENQUEUE_FLAG_DCA)
1974                 eq->dca = QM_EQCR_DCA_ENABLE |
1975                         ((flags & QMAN_ENQUEUE_FLAG_DCA_PARK) ?
1976                                         QM_EQCR_DCA_PARK : 0) |
1977                         ((flags >> 8) & QM_EQCR_DCA_IDXMASK);
1978         eq->fqid = cpu_to_be32(fq->fqid);
1979 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
1980         eq->tag = cpu_to_be32(fq->key);
1981 #else
1982         eq->tag = cpu_to_be32((u32)(uintptr_t)fq);
1983 #endif
1984         eq->fd = *fd;
1985         cpu_to_hw_fd(&eq->fd);
1986         return eq;
1987 }
1988
1989 int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd, u32 flags)
1990 {
1991         struct qman_portal *p = get_affine_portal();
1992         struct qm_eqcr_entry *eq;
1993
1994         eq = try_p_eq_start(p, fq, fd, flags);
1995         if (!eq)
1996                 return -EBUSY;
1997         /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */
1998         qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_CMD_ENQUEUE |
1999                 (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT)));
2000         /* Factor the below out, it's used from qman_enqueue_orp() too */
2001         return 0;
2002 }
2003
2004 int qman_enqueue_multi(struct qman_fq *fq,
2005                        const struct qm_fd *fd,
2006                        int frames_to_send)
2007 {
2008         struct qman_portal *p = get_affine_portal();
2009         struct qm_portal *portal = &p->p;
2010
2011         register struct qm_eqcr *eqcr = &portal->eqcr;
2012         struct qm_eqcr_entry *eq = eqcr->cursor, *prev_eq;
2013
2014         u8 i, diff, old_ci, sent = 0;
2015
2016         /* Update the available entries if no entry is free */
2017         if (!eqcr->available) {
2018                 old_ci = eqcr->ci;
2019                 eqcr->ci = qm_cl_in(EQCR_CI) & (QM_EQCR_SIZE - 1);
2020                 diff = qm_cyc_diff(QM_EQCR_SIZE, old_ci, eqcr->ci);
2021                 eqcr->available += diff;
2022                 if (!diff)
2023                         return 0;
2024         }
2025
2026         /* try to send as many frames as possible */
2027         while (eqcr->available && frames_to_send--) {
2028                 eq->fqid = fq->fqid_le;
2029 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP
2030                 eq->tag = cpu_to_be32(fq->key);
2031 #else
2032                 eq->tag = cpu_to_be32((u32)(uintptr_t)fq);
2033 #endif
2034                 eq->fd.opaque_addr = fd->opaque_addr;
2035                 eq->fd.addr = cpu_to_be40(fd->addr);
2036                 eq->fd.status = cpu_to_be32(fd->status);
2037                 eq->fd.opaque = cpu_to_be32(fd->opaque);
2038
2039                 eq = (void *)((unsigned long)(eq + 1) &
2040                         (~(unsigned long)(QM_EQCR_SIZE << 6)));
2041                 eqcr->available--;
2042                 sent++;
2043                 fd++;
2044         }
2045         lwsync();
2046
2047         /* In order for flushes to complete faster, all lines are recorded in
2048          * 32 bit word.
2049          */
2050         eq = eqcr->cursor;
2051         for (i = 0; i < sent; i++) {
2052                 eq->__dont_write_directly__verb =
2053                         QM_EQCR_VERB_CMD_ENQUEUE | eqcr->vbit;
2054                 prev_eq = eq;
2055                 eq = (void *)((unsigned long)(eq + 1) &
2056                         (~(unsigned long)(QM_EQCR_SIZE << 6)));
2057                 if (unlikely((prev_eq + 1) != eq))
2058                         eqcr->vbit ^= QM_EQCR_VERB_VBIT;
2059         }
2060
2061         /* We need  to flush all the lines but without load/store operations
2062          * between them
2063          */
2064         eq = eqcr->cursor;
2065         for (i = 0; i < sent; i++) {
2066                 dcbf(eq);
2067                 eq = (void *)((unsigned long)(eq + 1) &
2068                         (~(unsigned long)(QM_EQCR_SIZE << 6)));
2069         }
2070         /* Update cursor for the next call */
2071         eqcr->cursor = eq;
2072         return sent;
2073 }
2074
2075 int qman_enqueue_orp(struct qman_fq *fq, const struct qm_fd *fd, u32 flags,
2076                      struct qman_fq *orp, u16 orp_seqnum)
2077 {
2078         struct qman_portal *p  = get_affine_portal();
2079         struct qm_eqcr_entry *eq;
2080
2081         eq = try_p_eq_start(p, fq, fd, flags);
2082         if (!eq)
2083                 return -EBUSY;
2084         /* Process ORP-specifics here */
2085         if (flags & QMAN_ENQUEUE_FLAG_NLIS)
2086                 orp_seqnum |= QM_EQCR_SEQNUM_NLIS;
2087         else {
2088                 orp_seqnum &= ~QM_EQCR_SEQNUM_NLIS;
2089                 if (flags & QMAN_ENQUEUE_FLAG_NESN)
2090                         orp_seqnum |= QM_EQCR_SEQNUM_NESN;
2091                 else
2092                         /* No need to check 4 QMAN_ENQUEUE_FLAG_HOLE */
2093                         orp_seqnum &= ~QM_EQCR_SEQNUM_NESN;
2094         }
2095         eq->seqnum = cpu_to_be16(orp_seqnum);
2096         eq->orp = cpu_to_be32(orp->fqid);
2097         /* Note: QM_EQCR_VERB_INTERRUPT == QMAN_ENQUEUE_FLAG_WAIT_SYNC */
2098         qm_eqcr_pvb_commit(&p->p, QM_EQCR_VERB_ORP |
2099                 ((flags & (QMAN_ENQUEUE_FLAG_HOLE | QMAN_ENQUEUE_FLAG_NESN)) ?
2100                                 0 : QM_EQCR_VERB_CMD_ENQUEUE) |
2101                 (flags & (QM_EQCR_VERB_COLOUR_MASK | QM_EQCR_VERB_INTERRUPT)));
2102
2103         return 0;
2104 }
2105
2106 int qman_modify_cgr(struct qman_cgr *cgr, u32 flags,
2107                     struct qm_mcc_initcgr *opts)
2108 {
2109         struct qm_mc_command *mcc;
2110         struct qm_mc_result *mcr;
2111         struct qman_portal *p = get_affine_portal();
2112
2113         u8 res;
2114         u8 verb = QM_MCC_VERB_MODIFYCGR;
2115
2116         mcc = qm_mc_start(&p->p);
2117         if (opts)
2118                 mcc->initcgr = *opts;
2119         mcc->initcgr.we_mask = cpu_to_be16(mcc->initcgr.we_mask);
2120         mcc->initcgr.cgr.wr_parm_g.word =
2121                 cpu_to_be32(mcc->initcgr.cgr.wr_parm_g.word);
2122         mcc->initcgr.cgr.wr_parm_y.word =
2123                 cpu_to_be32(mcc->initcgr.cgr.wr_parm_y.word);
2124         mcc->initcgr.cgr.wr_parm_r.word =
2125                 cpu_to_be32(mcc->initcgr.cgr.wr_parm_r.word);
2126         mcc->initcgr.cgr.cscn_targ =  cpu_to_be32(mcc->initcgr.cgr.cscn_targ);
2127         mcc->initcgr.cgr.__cs_thres = cpu_to_be16(mcc->initcgr.cgr.__cs_thres);
2128
2129         mcc->initcgr.cgid = cgr->cgrid;
2130         if (flags & QMAN_CGR_FLAG_USE_INIT)
2131                 verb = QM_MCC_VERB_INITCGR;
2132         qm_mc_commit(&p->p, verb);
2133         while (!(mcr = qm_mc_result(&p->p)))
2134                 cpu_relax();
2135
2136         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == verb);
2137         res = mcr->result;
2138         return (res == QM_MCR_RESULT_OK) ? 0 : -EIO;
2139 }
2140
2141 #define TARG_MASK(n) (0x80000000 >> (n->config->channel - \
2142                                         QM_CHANNEL_SWPORTAL0))
2143 #define TARG_DCP_MASK(n) (0x80000000 >> (10 + n))
2144 #define PORTAL_IDX(n) (n->config->channel - QM_CHANNEL_SWPORTAL0)
2145
2146 int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
2147                     struct qm_mcc_initcgr *opts)
2148 {
2149         struct qm_mcr_querycgr cgr_state;
2150         struct qm_mcc_initcgr local_opts;
2151         int ret;
2152         struct qman_portal *p;
2153
2154         /* We have to check that the provided CGRID is within the limits of the
2155          * data-structures, for obvious reasons. However we'll let h/w take
2156          * care of determining whether it's within the limits of what exists on
2157          * the SoC.
2158          */
2159         if (cgr->cgrid >= __CGR_NUM)
2160                 return -EINVAL;
2161
2162         p = get_affine_portal();
2163
2164         memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2165         cgr->chan = p->config->channel;
2166         spin_lock(&p->cgr_lock);
2167
2168         /* if no opts specified, just add it to the list */
2169         if (!opts)
2170                 goto add_list;
2171
2172         ret = qman_query_cgr(cgr, &cgr_state);
2173         if (ret)
2174                 goto release_lock;
2175         if (opts)
2176                 local_opts = *opts;
2177         if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2178                 local_opts.cgr.cscn_targ_upd_ctrl =
2179                         QM_CGR_TARG_UDP_CTRL_WRITE_BIT | PORTAL_IDX(p);
2180         else
2181                 /* Overwrite TARG */
2182                 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ |
2183                                                         TARG_MASK(p);
2184         local_opts.we_mask |= QM_CGR_WE_CSCN_TARG;
2185
2186         /* send init if flags indicate so */
2187         if (opts && (flags & QMAN_CGR_FLAG_USE_INIT))
2188                 ret = qman_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT, &local_opts);
2189         else
2190                 ret = qman_modify_cgr(cgr, 0, &local_opts);
2191         if (ret)
2192                 goto release_lock;
2193 add_list:
2194         list_add(&cgr->node, &p->cgr_cbs);
2195
2196         /* Determine if newly added object requires its callback to be called */
2197         ret = qman_query_cgr(cgr, &cgr_state);
2198         if (ret) {
2199                 /* we can't go back, so proceed and return success, but screen
2200                  * and wail to the log file.
2201                  */
2202                 pr_crit("CGR HW state partially modified\n");
2203                 ret = 0;
2204                 goto release_lock;
2205         }
2206         if (cgr->cb && cgr_state.cgr.cscn_en && qman_cgrs_get(&p->cgrs[1],
2207                                                               cgr->cgrid))
2208                 cgr->cb(p, cgr, 1);
2209 release_lock:
2210         spin_unlock(&p->cgr_lock);
2211         return ret;
2212 }
2213
2214 int qman_create_cgr_to_dcp(struct qman_cgr *cgr, u32 flags, u16 dcp_portal,
2215                            struct qm_mcc_initcgr *opts)
2216 {
2217         struct qm_mcc_initcgr local_opts;
2218         struct qm_mcr_querycgr cgr_state;
2219         int ret;
2220
2221         if ((qman_ip_rev & 0xFF00) < QMAN_REV30) {
2222                 pr_warn("QMan version doesn't support CSCN => DCP portal\n");
2223                 return -EINVAL;
2224         }
2225         /* We have to check that the provided CGRID is within the limits of the
2226          * data-structures, for obvious reasons. However we'll let h/w take
2227          * care of determining whether it's within the limits of what exists on
2228          * the SoC.
2229          */
2230         if (cgr->cgrid >= __CGR_NUM)
2231                 return -EINVAL;
2232
2233         ret = qman_query_cgr(cgr, &cgr_state);
2234         if (ret)
2235                 return ret;
2236
2237         memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2238         if (opts)
2239                 local_opts = *opts;
2240
2241         if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2242                 local_opts.cgr.cscn_targ_upd_ctrl =
2243                                 QM_CGR_TARG_UDP_CTRL_WRITE_BIT |
2244                                 QM_CGR_TARG_UDP_CTRL_DCP | dcp_portal;
2245         else
2246                 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ |
2247                                         TARG_DCP_MASK(dcp_portal);
2248         local_opts.we_mask |= QM_CGR_WE_CSCN_TARG;
2249
2250         /* send init if flags indicate so */
2251         if (opts && (flags & QMAN_CGR_FLAG_USE_INIT))
2252                 ret = qman_modify_cgr(cgr, QMAN_CGR_FLAG_USE_INIT,
2253                                       &local_opts);
2254         else
2255                 ret = qman_modify_cgr(cgr, 0, &local_opts);
2256
2257         return ret;
2258 }
2259
2260 int qman_delete_cgr(struct qman_cgr *cgr)
2261 {
2262         struct qm_mcr_querycgr cgr_state;
2263         struct qm_mcc_initcgr local_opts;
2264         int ret = 0;
2265         struct qman_cgr *i;
2266         struct qman_portal *p = get_affine_portal();
2267
2268         if (cgr->chan != p->config->channel) {
2269                 pr_crit("Attempting to delete cgr from different portal than"
2270                         " it was create: create 0x%x, delete 0x%x\n",
2271                         cgr->chan, p->config->channel);
2272                 ret = -EINVAL;
2273                 goto put_portal;
2274         }
2275         memset(&local_opts, 0, sizeof(struct qm_mcc_initcgr));
2276         spin_lock(&p->cgr_lock);
2277         list_del(&cgr->node);
2278         /*
2279          * If there are no other CGR objects for this CGRID in the list,
2280          * update CSCN_TARG accordingly
2281          */
2282         list_for_each_entry(i, &p->cgr_cbs, node)
2283                 if ((i->cgrid == cgr->cgrid) && i->cb)
2284                         goto release_lock;
2285         ret = qman_query_cgr(cgr, &cgr_state);
2286         if (ret)  {
2287                 /* add back to the list */
2288                 list_add(&cgr->node, &p->cgr_cbs);
2289                 goto release_lock;
2290         }
2291         /* Overwrite TARG */
2292         local_opts.we_mask = QM_CGR_WE_CSCN_TARG;
2293         if ((qman_ip_rev & 0xFF00) >= QMAN_REV30)
2294                 local_opts.cgr.cscn_targ_upd_ctrl = PORTAL_IDX(p);
2295         else
2296                 local_opts.cgr.cscn_targ = cgr_state.cgr.cscn_targ &
2297                                                          ~(TARG_MASK(p));
2298         ret = qman_modify_cgr(cgr, 0, &local_opts);
2299         if (ret)
2300                 /* add back to the list */
2301                 list_add(&cgr->node, &p->cgr_cbs);
2302 release_lock:
2303         spin_unlock(&p->cgr_lock);
2304 put_portal:
2305         return ret;
2306 }
2307
2308 int qman_shutdown_fq(u32 fqid)
2309 {
2310         struct qman_portal *p;
2311         struct qm_portal *low_p;
2312         struct qm_mc_command *mcc;
2313         struct qm_mc_result *mcr;
2314         u8 state;
2315         int orl_empty, fq_empty, drain = 0;
2316         u32 result;
2317         u32 channel, wq;
2318         u16 dest_wq;
2319
2320         p = get_affine_portal();
2321         low_p = &p->p;
2322
2323         /* Determine the state of the FQID */
2324         mcc = qm_mc_start(low_p);
2325         mcc->queryfq_np.fqid = cpu_to_be32(fqid);
2326         qm_mc_commit(low_p, QM_MCC_VERB_QUERYFQ_NP);
2327         while (!(mcr = qm_mc_result(low_p)))
2328                 cpu_relax();
2329         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ_NP);
2330         state = mcr->queryfq_np.state & QM_MCR_NP_STATE_MASK;
2331         if (state == QM_MCR_NP_STATE_OOS)
2332                 return 0; /* Already OOS, no need to do anymore checks */
2333
2334         /* Query which channel the FQ is using */
2335         mcc = qm_mc_start(low_p);
2336         mcc->queryfq.fqid = cpu_to_be32(fqid);
2337         qm_mc_commit(low_p, QM_MCC_VERB_QUERYFQ);
2338         while (!(mcr = qm_mc_result(low_p)))
2339                 cpu_relax();
2340         DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) == QM_MCR_VERB_QUERYFQ);
2341
2342         /* Need to store these since the MCR gets reused */
2343         dest_wq = be16_to_cpu(mcr->queryfq.fqd.dest_wq);
2344         channel = dest_wq & 0x7;
2345         wq = dest_wq >> 3;
2346
2347         switch (state) {
2348         case QM_MCR_NP_STATE_TEN_SCHED:
2349         case QM_MCR_NP_STATE_TRU_SCHED:
2350         case QM_MCR_NP_STATE_ACTIVE:
2351         case QM_MCR_NP_STATE_PARKED:
2352                 orl_empty = 0;
2353                 mcc = qm_mc_start(low_p);
2354                 mcc->alterfq.fqid = cpu_to_be32(fqid);
2355                 qm_mc_commit(low_p, QM_MCC_VERB_ALTER_RETIRE);
2356                 while (!(mcr = qm_mc_result(low_p)))
2357                         cpu_relax();
2358                 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2359                            QM_MCR_VERB_ALTER_RETIRE);
2360                 result = mcr->result; /* Make a copy as we reuse MCR below */
2361
2362                 if (result == QM_MCR_RESULT_PENDING) {
2363                         /* Need to wait for the FQRN in the message ring, which
2364                          * will only occur once the FQ has been drained.  In
2365                          * order for the FQ to drain the portal needs to be set
2366                          * to dequeue from the channel the FQ is scheduled on
2367                          */
2368                         const struct qm_mr_entry *msg;
2369                         const struct qm_dqrr_entry *dqrr = NULL;
2370                         int found_fqrn = 0;
2371                         __maybe_unused u16 dequeue_wq = 0;
2372
2373                         /* Flag that we need to drain FQ */
2374                         drain = 1;
2375
2376                         if (channel >= qm_channel_pool1 &&
2377                             channel < (u16)(qm_channel_pool1 + 15)) {
2378                                 /* Pool channel, enable the bit in the portal */
2379                                 dequeue_wq = (channel -
2380                                               qm_channel_pool1 + 1) << 4 | wq;
2381                         } else if (channel < qm_channel_pool1) {
2382                                 /* Dedicated channel */
2383                                 dequeue_wq = wq;
2384                         } else {
2385                                 pr_info("Cannot recover FQ 0x%x,"
2386                                         " it is scheduled on channel 0x%x",
2387                                         fqid, channel);
2388                                 return -EBUSY;
2389                         }
2390                         /* Set the sdqcr to drain this channel */
2391                         if (channel < qm_channel_pool1)
2392                                 qm_dqrr_sdqcr_set(low_p,
2393                                                   QM_SDQCR_TYPE_ACTIVE |
2394                                           QM_SDQCR_CHANNELS_DEDICATED);
2395                         else
2396                                 qm_dqrr_sdqcr_set(low_p,
2397                                                   QM_SDQCR_TYPE_ACTIVE |
2398                                                   QM_SDQCR_CHANNELS_POOL_CONV
2399                                                   (channel));
2400                         while (!found_fqrn) {
2401                                 /* Keep draining DQRR while checking the MR*/
2402                                 qm_dqrr_pvb_update(low_p);
2403                                 dqrr = qm_dqrr_current(low_p);
2404                                 while (dqrr) {
2405                                         qm_dqrr_cdc_consume_1ptr(
2406                                                 low_p, dqrr, 0);
2407                                         qm_dqrr_pvb_update(low_p);
2408                                         qm_dqrr_next(low_p);
2409                                         dqrr = qm_dqrr_current(low_p);
2410                                 }
2411                                 /* Process message ring too */
2412                                 qm_mr_pvb_update(low_p);
2413                                 msg = qm_mr_current(low_p);
2414                                 while (msg) {
2415                                         if ((msg->verb &
2416                                              QM_MR_VERB_TYPE_MASK)
2417                                             == QM_MR_VERB_FQRN)
2418                                                 found_fqrn = 1;
2419                                         qm_mr_next(low_p);
2420                                         qm_mr_cci_consume_to_current(low_p);
2421                                         qm_mr_pvb_update(low_p);
2422                                         msg = qm_mr_current(low_p);
2423                                 }
2424                                 cpu_relax();
2425                         }
2426                 }
2427                 if (result != QM_MCR_RESULT_OK &&
2428                     result !=  QM_MCR_RESULT_PENDING) {
2429                         /* error */
2430                         pr_err("qman_retire_fq failed on FQ 0x%x,"
2431                                " result=0x%x\n", fqid, result);
2432                         return -1;
2433                 }
2434                 if (!(mcr->alterfq.fqs & QM_MCR_FQS_ORLPRESENT)) {
2435                         /* ORL had no entries, no need to wait until the
2436                          * ERNs come in.
2437                          */
2438                         orl_empty = 1;
2439                 }
2440                 /* Retirement succeeded, check to see if FQ needs
2441                  * to be drained.
2442                  */
2443                 if (drain || mcr->alterfq.fqs & QM_MCR_FQS_NOTEMPTY) {
2444                         /* FQ is Not Empty, drain using volatile DQ commands */
2445                         fq_empty = 0;
2446                         do {
2447                                 const struct qm_dqrr_entry *dqrr = NULL;
2448                                 u32 vdqcr = fqid | QM_VDQCR_NUMFRAMES_SET(3);
2449
2450                                 qm_dqrr_vdqcr_set(low_p, vdqcr);
2451
2452                                 /* Wait for a dequeue to occur */
2453                                 while (dqrr == NULL) {
2454                                         qm_dqrr_pvb_update(low_p);
2455                                         dqrr = qm_dqrr_current(low_p);
2456                                         if (!dqrr)
2457                                                 cpu_relax();
2458                                 }
2459                                 /* Process the dequeues, making sure to
2460                                  * empty the ring completely.
2461                                  */
2462                                 while (dqrr) {
2463                                         if (dqrr->fqid == fqid &&
2464                                             dqrr->stat & QM_DQRR_STAT_FQ_EMPTY)
2465                                                 fq_empty = 1;
2466                                         qm_dqrr_cdc_consume_1ptr(low_p,
2467                                                                  dqrr, 0);
2468                                         qm_dqrr_pvb_update(low_p);
2469                                         qm_dqrr_next(low_p);
2470                                         dqrr = qm_dqrr_current(low_p);
2471                                 }
2472                         } while (fq_empty == 0);
2473                 }
2474                 qm_dqrr_sdqcr_set(low_p, 0);
2475
2476                 /* Wait for the ORL to have been completely drained */
2477                 while (orl_empty == 0) {
2478                         const struct qm_mr_entry *msg;
2479
2480                         qm_mr_pvb_update(low_p);
2481                         msg = qm_mr_current(low_p);
2482                         while (msg) {
2483                                 if ((msg->verb & QM_MR_VERB_TYPE_MASK) ==
2484                                     QM_MR_VERB_FQRL)
2485                                         orl_empty = 1;
2486                                 qm_mr_next(low_p);
2487                                 qm_mr_cci_consume_to_current(low_p);
2488                                 qm_mr_pvb_update(low_p);
2489                                 msg = qm_mr_current(low_p);
2490                         }
2491                         cpu_relax();
2492                 }
2493                 mcc = qm_mc_start(low_p);
2494                 mcc->alterfq.fqid = cpu_to_be32(fqid);
2495                 qm_mc_commit(low_p, QM_MCC_VERB_ALTER_OOS);
2496                 while (!(mcr = qm_mc_result(low_p)))
2497                         cpu_relax();
2498                 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2499                            QM_MCR_VERB_ALTER_OOS);
2500                 if (mcr->result != QM_MCR_RESULT_OK) {
2501                         pr_err(
2502                         "OOS after drain Failed on FQID 0x%x, result 0x%x\n",
2503                                fqid, mcr->result);
2504                         return -1;
2505                 }
2506                 return 0;
2507
2508         case QM_MCR_NP_STATE_RETIRED:
2509                 /* Send OOS Command */
2510                 mcc = qm_mc_start(low_p);
2511                 mcc->alterfq.fqid = cpu_to_be32(fqid);
2512                 qm_mc_commit(low_p, QM_MCC_VERB_ALTER_OOS);
2513                 while (!(mcr = qm_mc_result(low_p)))
2514                         cpu_relax();
2515                 DPAA_ASSERT((mcr->verb & QM_MCR_VERB_MASK) ==
2516                            QM_MCR_VERB_ALTER_OOS);
2517                 if (mcr->result) {
2518                         pr_err("OOS Failed on FQID 0x%x\n", fqid);
2519                         return -1;
2520                 }
2521                 return 0;
2522
2523         }
2524         return -1;
2525 }