1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
17 #include <sys/types.h>
18 #include <sys/queue.h>
19 #include <sys/ioctl.h>
22 #include <sys/syscall.h>
23 #include <sys/epoll.h>
24 #include<sys/eventfd.h>
27 #include <rte_ethdev.h>
28 #include <rte_malloc.h>
29 #include <rte_memcpy.h>
30 #include <rte_string_fns.h>
31 #include <rte_cycles.h>
32 #include <rte_kvargs.h>
35 #include <fslmc_logs.h>
36 #include <rte_fslmc.h>
37 #include "dpaa2_hw_pvt.h"
38 #include "dpaa2_hw_dpio.h"
39 #include <mc/fsl_dpmng.h>
41 #define NUM_HOST_CPUS RTE_MAX_LCORE
43 struct dpaa2_io_portal_t dpaa2_io_portal[RTE_MAX_LCORE];
44 RTE_DEFINE_PER_LCORE(struct dpaa2_io_portal_t, _dpaa2_io);
46 struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
48 TAILQ_HEAD(dpio_dev_list, dpaa2_dpio_dev);
49 static struct dpio_dev_list dpio_dev_list
50 = TAILQ_HEAD_INITIALIZER(dpio_dev_list); /*!< DPIO device list */
51 static uint32_t io_space_count;
53 /*Stashing Macros default for LS208x*/
54 static int dpaa2_core_cluster_base = 0x04;
55 static int dpaa2_cluster_sz = 2;
57 /* For LS208X platform There are four clusters with following mapping:
58 * Cluster 1 (ID = x04) : CPU0, CPU1;
59 * Cluster 2 (ID = x05) : CPU2, CPU3;
60 * Cluster 3 (ID = x06) : CPU4, CPU5;
61 * Cluster 4 (ID = x07) : CPU6, CPU7;
63 /* For LS108X platform There are two clusters with following mapping:
64 * Cluster 1 (ID = x02) : CPU0, CPU1, CPU2, CPU3;
65 * Cluster 2 (ID = x03) : CPU4, CPU5, CPU6, CPU7;
67 /* For LX2160 platform There are four clusters with following mapping:
68 * Cluster 1 (ID = x00) : CPU0, CPU1;
69 * Cluster 2 (ID = x01) : CPU2, CPU3;
70 * Cluster 3 (ID = x02) : CPU4, CPU5;
71 * Cluster 4 (ID = x03) : CPU6, CPU7;
72 * Cluster 1 (ID = x04) : CPU8, CPU9;
73 * Cluster 2 (ID = x05) : CPU10, CP11;
74 * Cluster 3 (ID = x06) : CPU12, CPU13;
75 * Cluster 4 (ID = x07) : CPU14, CPU15;
79 dpaa2_core_cluster_sdest(int cpu_id)
81 int x = cpu_id / dpaa2_cluster_sz;
83 return dpaa2_core_cluster_base + x;
86 static void dpaa2_affine_dpio_intr_to_respective_core(int32_t dpio_id)
89 #define COMMAND_LEN 50
90 uint32_t cpu_mask = 1;
93 char *temp = NULL, *token = NULL;
94 char string[STRING_LEN], command[COMMAND_LEN];
97 snprintf(string, STRING_LEN, "dpio.%d", dpio_id);
98 file = fopen("/proc/interrupts", "r");
100 PMD_DRV_LOG(WARNING, "Failed to open /proc/interrupts file\n");
103 while (getline(&temp, &len, file) != -1) {
104 if ((strstr(temp, string)) != NULL) {
105 token = strtok(temp, ":");
111 PMD_DRV_LOG(WARNING, "Failed to get interrupt id for dpio.%d\n",
119 cpu_mask = cpu_mask << rte_lcore_id();
120 snprintf(command, COMMAND_LEN, "echo %X > /proc/irq/%s/smp_affinity",
122 ret = system(command);
125 "Failed to affine interrupts on respective core\n");
127 PMD_DRV_LOG(WARNING, " %s command is executed\n", command);
133 static int dpaa2_dpio_intr_init(struct dpaa2_dpio_dev *dpio_dev)
135 struct epoll_event epoll_ev;
136 int eventfd, dpio_epoll_fd, ret;
137 int threshold = 0x3, timeout = 0xFF;
139 dpio_epoll_fd = epoll_create(1);
140 ret = rte_dpaa2_intr_enable(&dpio_dev->intr_handle, 0);
142 PMD_DRV_LOG(ERR, "Interrupt registeration failed\n");
146 if (getenv("DPAA2_PORTAL_INTR_THRESHOLD"))
147 threshold = atoi(getenv("DPAA2_PORTAL_INTR_THRESHOLD"));
149 if (getenv("DPAA2_PORTAL_INTR_TIMEOUT"))
150 sscanf(getenv("DPAA2_PORTAL_INTR_TIMEOUT"), "%x", &timeout);
152 qbman_swp_interrupt_set_trigger(dpio_dev->sw_portal,
153 QBMAN_SWP_INTERRUPT_DQRI);
154 qbman_swp_interrupt_clear_status(dpio_dev->sw_portal, 0xffffffff);
155 qbman_swp_interrupt_set_inhibit(dpio_dev->sw_portal, 0);
156 qbman_swp_dqrr_thrshld_write(dpio_dev->sw_portal, threshold);
157 qbman_swp_intr_timeout_write(dpio_dev->sw_portal, timeout);
159 eventfd = dpio_dev->intr_handle.fd;
160 epoll_ev.events = EPOLLIN | EPOLLPRI | EPOLLET;
161 epoll_ev.data.fd = eventfd;
163 ret = epoll_ctl(dpio_epoll_fd, EPOLL_CTL_ADD, eventfd, &epoll_ev);
165 PMD_DRV_LOG(ERR, "epoll_ctl failed\n");
168 dpio_dev->epoll_fd = dpio_epoll_fd;
170 dpaa2_affine_dpio_intr_to_respective_core(dpio_dev->hw_id);
176 configure_dpio_qbman_swp(struct dpaa2_dpio_dev *dpio_dev)
178 struct qbman_swp_desc p_des;
179 struct dpio_attr attr;
181 dpio_dev->dpio = malloc(sizeof(struct fsl_mc_io));
182 if (!dpio_dev->dpio) {
183 PMD_INIT_LOG(ERR, "Memory allocation failure\n");
187 PMD_DRV_LOG(DEBUG, "Allocated DPIO Portal[%p]", dpio_dev->dpio);
188 dpio_dev->dpio->regs = dpio_dev->mc_portal;
189 if (dpio_open(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->hw_id,
191 PMD_INIT_LOG(ERR, "Failed to allocate IO space\n");
192 free(dpio_dev->dpio);
196 if (dpio_reset(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
197 PMD_INIT_LOG(ERR, "Failed to reset dpio\n");
198 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
199 free(dpio_dev->dpio);
203 if (dpio_enable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token)) {
204 PMD_INIT_LOG(ERR, "Failed to Enable dpio\n");
205 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
206 free(dpio_dev->dpio);
210 if (dpio_get_attributes(dpio_dev->dpio, CMD_PRI_LOW,
211 dpio_dev->token, &attr)) {
212 PMD_INIT_LOG(ERR, "DPIO Get attribute failed\n");
213 dpio_disable(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
214 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
215 free(dpio_dev->dpio);
219 /* Configure & setup SW portal */
221 p_des.idx = attr.qbman_portal_id;
222 p_des.cena_bar = (void *)(dpio_dev->qbman_portal_ce_paddr);
223 p_des.cinh_bar = (void *)(dpio_dev->qbman_portal_ci_paddr);
225 p_des.qman_version = attr.qbman_version;
227 dpio_dev->sw_portal = qbman_swp_init(&p_des);
228 if (dpio_dev->sw_portal == NULL) {
229 PMD_DRV_LOG(ERR, " QBMan SW Portal Init failed\n");
230 dpio_close(dpio_dev->dpio, CMD_PRI_LOW, dpio_dev->token);
231 free(dpio_dev->dpio);
239 dpaa2_configure_stashing(struct dpaa2_dpio_dev *dpio_dev, int cpu_id)
242 static int first_time;
244 /* find the SoC type for the first time */
246 struct mc_soc_version mc_plat_info = {0};
248 if (mc_get_soc_version(dpio_dev->dpio,
249 CMD_PRI_LOW, &mc_plat_info)) {
250 PMD_INIT_LOG(ERR, "\tmc_get_soc_version failed\n");
251 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LS1080A) {
252 dpaa2_core_cluster_base = 0x02;
253 dpaa2_cluster_sz = 4;
254 PMD_INIT_LOG(DEBUG, "\tLS108x (A53) Platform Detected");
255 } else if ((mc_plat_info.svr & 0xffff0000) == SVR_LX2160A) {
256 dpaa2_core_cluster_base = 0x00;
257 dpaa2_cluster_sz = 2;
258 PMD_INIT_LOG(DEBUG, "\tLX2160 Platform Detected");
263 /* Set the Stashing Destination */
265 cpu_id = rte_get_master_lcore();
267 RTE_LOG(ERR, PMD, "\tGetting CPU Index failed\n");
271 /* Set the STASH Destination depending on Current CPU ID.
272 * Valid values of SDEST are 4,5,6,7. Where,
275 sdest = dpaa2_core_cluster_sdest(cpu_id);
276 PMD_DRV_LOG(DEBUG, "Portal= %d CPU= %u SDEST= %d",
277 dpio_dev->index, cpu_id, sdest);
279 ret = dpio_set_stashing_destination(dpio_dev->dpio, CMD_PRI_LOW,
280 dpio_dev->token, sdest);
282 PMD_DRV_LOG(ERR, "%d ERROR in SDEST\n", ret);
286 if (dpaa2_dpio_intr_init(dpio_dev)) {
287 PMD_DRV_LOG(ERR, "Interrupt registration failed for dpio\n");
294 struct dpaa2_dpio_dev *dpaa2_get_qbman_swp(int cpu_id)
296 struct dpaa2_dpio_dev *dpio_dev = NULL;
299 /* Get DPIO dev handle from list using index */
300 TAILQ_FOREACH(dpio_dev, &dpio_dev_list, next) {
301 if (dpio_dev && rte_atomic16_test_and_set(&dpio_dev->ref_count))
307 PMD_DRV_LOG(DEBUG, "New Portal=0x%x (%d) affined thread - %lu",
308 dpio_dev, dpio_dev->index, syscall(SYS_gettid));
310 ret = dpaa2_configure_stashing(dpio_dev, cpu_id);
312 PMD_DRV_LOG(ERR, "dpaa2_configure_stashing failed");
318 dpaa2_affine_qbman_swp(void)
320 unsigned int lcore_id = rte_lcore_id();
321 uint64_t tid = syscall(SYS_gettid);
323 if (lcore_id == LCORE_ID_ANY)
324 lcore_id = rte_get_master_lcore();
325 /* if the core id is not supported */
326 else if (lcore_id >= RTE_MAX_LCORE)
329 if (dpaa2_io_portal[lcore_id].dpio_dev) {
330 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
331 " between thread %lu and current %lu",
332 dpaa2_io_portal[lcore_id].dpio_dev,
333 dpaa2_io_portal[lcore_id].dpio_dev->index,
334 dpaa2_io_portal[lcore_id].net_tid,
336 RTE_PER_LCORE(_dpaa2_io).dpio_dev
337 = dpaa2_io_portal[lcore_id].dpio_dev;
338 rte_atomic16_inc(&dpaa2_io_portal
339 [lcore_id].dpio_dev->ref_count);
340 dpaa2_io_portal[lcore_id].net_tid = tid;
342 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
343 dpaa2_io_portal[lcore_id].dpio_dev,
344 dpaa2_io_portal[lcore_id].dpio_dev->index,
349 /* Populate the dpaa2_io_portal structure */
350 dpaa2_io_portal[lcore_id].dpio_dev = dpaa2_get_qbman_swp(lcore_id);
352 if (dpaa2_io_portal[lcore_id].dpio_dev) {
353 RTE_PER_LCORE(_dpaa2_io).dpio_dev
354 = dpaa2_io_portal[lcore_id].dpio_dev;
355 dpaa2_io_portal[lcore_id].net_tid = tid;
364 dpaa2_affine_qbman_swp_sec(void)
366 unsigned int lcore_id = rte_lcore_id();
367 uint64_t tid = syscall(SYS_gettid);
369 if (lcore_id == LCORE_ID_ANY)
370 lcore_id = rte_get_master_lcore();
371 /* if the core id is not supported */
372 else if (lcore_id >= RTE_MAX_LCORE)
375 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
376 PMD_DRV_LOG(INFO, "DPAA Portal=0x%x (%d) is being shared"
377 " between thread %lu and current %lu",
378 dpaa2_io_portal[lcore_id].sec_dpio_dev,
379 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
380 dpaa2_io_portal[lcore_id].sec_tid,
382 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
383 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
384 rte_atomic16_inc(&dpaa2_io_portal
385 [lcore_id].sec_dpio_dev->ref_count);
386 dpaa2_io_portal[lcore_id].sec_tid = tid;
388 PMD_DRV_LOG(DEBUG, "Old Portal=0x%x (%d) affined thread - %lu",
389 dpaa2_io_portal[lcore_id].sec_dpio_dev,
390 dpaa2_io_portal[lcore_id].sec_dpio_dev->index,
395 /* Populate the dpaa2_io_portal structure */
396 dpaa2_io_portal[lcore_id].sec_dpio_dev = dpaa2_get_qbman_swp(lcore_id);
398 if (dpaa2_io_portal[lcore_id].sec_dpio_dev) {
399 RTE_PER_LCORE(_dpaa2_io).sec_dpio_dev
400 = dpaa2_io_portal[lcore_id].sec_dpio_dev;
401 dpaa2_io_portal[lcore_id].sec_tid = tid;
409 dpaa2_create_dpio_device(int vdev_fd,
410 struct vfio_device_info *obj_info,
413 struct dpaa2_dpio_dev *dpio_dev;
414 struct vfio_region_info reg_info = { .argsz = sizeof(reg_info)};
416 if (obj_info->num_regions < NUM_DPIO_REGIONS) {
417 PMD_INIT_LOG(ERR, "ERROR, Not sufficient number "
418 "of DPIO regions.\n");
422 dpio_dev = rte_malloc(NULL, sizeof(struct dpaa2_dpio_dev),
423 RTE_CACHE_LINE_SIZE);
425 PMD_INIT_LOG(ERR, "Memory allocation failed for DPIO Device\n");
429 dpio_dev->dpio = NULL;
430 dpio_dev->hw_id = object_id;
431 rte_atomic16_init(&dpio_dev->ref_count);
432 /* Using single portal for all devices */
433 dpio_dev->mc_portal = rte_mcp_ptr_list[MC_PORTAL_INDEX];
436 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
437 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
442 dpio_dev->ce_size = reg_info.size;
443 dpio_dev->qbman_portal_ce_paddr = (uint64_t)mmap(NULL, reg_info.size,
444 PROT_WRITE | PROT_READ, MAP_SHARED,
445 vdev_fd, reg_info.offset);
448 if (ioctl(vdev_fd, VFIO_DEVICE_GET_REGION_INFO, ®_info)) {
449 PMD_INIT_LOG(ERR, "vfio: error getting region info\n");
454 dpio_dev->ci_size = reg_info.size;
455 dpio_dev->qbman_portal_ci_paddr = (uint64_t)mmap(NULL, reg_info.size,
456 PROT_WRITE | PROT_READ, MAP_SHARED,
457 vdev_fd, reg_info.offset);
459 if (configure_dpio_qbman_swp(dpio_dev)) {
461 "Fail to configure the dpio qbman portal for %d\n",
468 dpio_dev->index = io_space_count;
470 if (rte_dpaa2_vfio_setup_intr(&dpio_dev->intr_handle, vdev_fd, 1)) {
471 PMD_INIT_LOG(ERR, "Fail to setup interrupt for %d\n",
476 TAILQ_INSERT_TAIL(&dpio_dev_list, dpio_dev, next);
477 RTE_LOG(DEBUG, PMD, "DPAA2: Added [dpio.%d]\n", object_id);
483 dpaa2_free_dq_storage(struct queue_storage_info_t *q_storage)
487 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
488 if (q_storage->dq_storage[i])
489 rte_free(q_storage->dq_storage[i]);
494 dpaa2_alloc_dq_storage(struct queue_storage_info_t *q_storage)
498 for (i = 0; i < NUM_DQS_PER_QUEUE; i++) {
499 q_storage->dq_storage[i] = rte_malloc(NULL,
500 DPAA2_DQRR_RING_SIZE * sizeof(struct qbman_result),
501 RTE_CACHE_LINE_SIZE);
502 if (!q_storage->dq_storage[i])
508 rte_free(q_storage->dq_storage[i]);
513 static struct rte_dpaa2_object rte_dpaa2_dpio_obj = {
514 .dev_type = DPAA2_IO,
515 .create = dpaa2_create_dpio_device,
518 RTE_PMD_REGISTER_DPAA2_OBJECT(dpio, rte_dpaa2_dpio_obj);