1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016 Freescale Semiconductor, Inc. All rights reserved.
8 #ifndef _DPAA2_HW_PVT_H_
9 #define _DPAA2_HW_PVT_H_
11 #include <rte_eventdev.h>
13 #include <mc/fsl_mc_sys.h>
14 #include <fsl_qbman_portal.h>
22 #define lower_32_bits(x) ((uint32_t)(x))
23 #define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
25 #define SVR_LS1080A 0x87030000
26 #define SVR_LS2080A 0x87010000
27 #define SVR_LS2088A 0x87090000
28 #define SVR_LX2160A 0x87360000
31 #define VLAN_TAG_SIZE 4 /** < Vlan Header Length */
34 #define MAX_TX_RING_SLOTS 8
35 /** <Maximum number of slots available in TX ring*/
37 #define DPAA2_DQRR_RING_SIZE 16
38 /** <Maximum number of slots available in RX ring*/
40 #define MC_PORTAL_INDEX 0
41 #define NUM_DPIO_REGIONS 2
42 #define NUM_DQS_PER_QUEUE 2
44 /* Maximum release/acquire from QBMAN */
45 #define DPAA2_MBUF_MAX_ACQ_REL 7
48 #define DPAA2_MBUF_HW_ANNOTATION 64
49 #define DPAA2_FD_PTA_SIZE 0
51 #if (DPAA2_MBUF_HW_ANNOTATION + DPAA2_FD_PTA_SIZE) > RTE_PKTMBUF_HEADROOM
52 #error "Annotation requirement is more than RTE_PKTMBUF_HEADROOM"
55 /* we will re-use the HEADROOM for annotation in RX */
56 #define DPAA2_HW_BUF_RESERVE 0
57 #define DPAA2_PACKET_LAYOUT_ALIGN 64 /*changing from 256 */
59 #define DPAA2_DPCI_MAX_QUEUES 2
61 struct dpaa2_dpio_dev {
62 TAILQ_ENTRY(dpaa2_dpio_dev) next;
63 /**< Pointer to Next device instance */
64 uint16_t index; /**< Index of a instance in the list */
65 rte_atomic16_t ref_count;
66 /**< How many thread contexts are sharing this.*/
67 struct fsl_mc_io *dpio; /** handle to DPIO portal object */
69 struct qbman_swp *sw_portal; /** SW portal object */
70 const struct qbman_result *dqrr[4];
71 /**< DQRR Entry for this SW portal */
72 void *mc_portal; /**< MC Portal for configuring this device */
73 uintptr_t qbman_portal_ce_paddr;
74 /**< Physical address of Cache Enabled Area */
75 uintptr_t ce_size; /**< Size of the CE region */
76 uintptr_t qbman_portal_ci_paddr;
77 /**< Physical address of Cache Inhibit Area */
78 uintptr_t ci_size; /**< Size of the CI region */
79 struct rte_intr_handle intr_handle; /* Interrupt related info */
80 int32_t epoll_fd; /**< File descriptor created for interrupt polling */
81 int32_t hw_id; /**< An unique ID of this DPIO device instance */
86 struct dpaa2_dpbp_dev {
87 TAILQ_ENTRY(dpaa2_dpbp_dev) next;
88 /**< Pointer to Next device instance */
89 struct fsl_mc_io dpbp; /** handle to DPBP portal object */
91 rte_atomic16_t in_use;
92 uint32_t dpbp_id; /*HW ID for DPBP object */
95 struct queue_storage_info_t {
96 struct qbman_result *dq_storage[NUM_DQS_PER_QUEUE];
97 struct qbman_result *active_dqs;
104 typedef void (dpaa2_queue_cb_dqrr_t)(struct qbman_swp *swp,
105 const struct qbman_fd *fd,
106 const struct qbman_result *dq,
107 struct dpaa2_queue *rxq,
108 struct rte_event *ev);
111 struct rte_mempool *mb_pool; /**< mbuf pool to populate RX ring. */
113 int32_t eventfd; /*!< Event Fd of this queue */
114 uint32_t fqid; /*!< Unique ID of this queue */
115 uint8_t tc_index; /*!< traffic class identifier */
116 uint16_t flow_id; /*!< To be used by DPAA2 frmework */
121 struct queue_storage_info_t *q_storage;
122 struct qbman_result *cscn;
125 dpaa2_queue_cb_dqrr_t *cb;
128 struct swp_active_dqs {
129 struct qbman_result *global_active_dqs;
130 uint64_t reserved[7];
133 #define NUM_MAX_SWP 64
135 extern struct swp_active_dqs rte_global_active_dqs_list[NUM_MAX_SWP];
137 struct dpaa2_dpci_dev {
138 TAILQ_ENTRY(dpaa2_dpci_dev) next;
139 /**< Pointer to Next device instance */
140 struct fsl_mc_io dpci; /** handle to DPCI portal object */
142 rte_atomic16_t in_use;
143 uint32_t dpci_id; /*HW ID for DPCI object */
144 struct dpaa2_queue queue[DPAA2_DPCI_MAX_QUEUES];
147 /*! Global MCP list */
148 extern void *(*rte_mcp_ptr_list);
150 /* Refer to Table 7-3 in SEC BG */
155 /* FMT must be 00, MSB is final bit */
156 uint32_t fin_bpid_offset;
158 uint32_t reserved[3]; /* Not used currently */
165 uint32_t fin_bpid_offset;
168 /* There are three types of frames: Single, Scatter Gather and Frame Lists */
169 enum qbman_fd_format {
174 /*Macros to define operations on FD*/
175 #define DPAA2_SET_FD_ADDR(fd, addr) do { \
176 (fd)->simple.addr_lo = lower_32_bits((uint64_t)(addr)); \
177 (fd)->simple.addr_hi = upper_32_bits((uint64_t)(addr)); \
179 #define DPAA2_SET_FD_LEN(fd, length) ((fd)->simple.len = length)
180 #define DPAA2_SET_FD_BPID(fd, bpid) ((fd)->simple.bpid_offset |= bpid)
181 #define DPAA2_SET_FD_IVP(fd) (((fd)->simple.bpid_offset |= 0x00004000))
182 #define DPAA2_SET_FD_OFFSET(fd, offset) \
183 (((fd)->simple.bpid_offset |= (uint32_t)(offset) << 16))
184 #define DPAA2_SET_FD_INTERNAL_JD(fd, len) \
185 ((fd)->simple.frc = (0x80000000 | (len)))
186 #define DPAA2_GET_FD_FRC_PARSE_SUM(fd) \
187 ((uint16_t)(((fd)->simple.frc & 0xffff0000) >> 16))
188 #define DPAA2_SET_FD_FRC(fd, frc) ((fd)->simple.frc = frc)
189 #define DPAA2_RESET_FD_CTRL(fd) ((fd)->simple.ctrl = 0)
191 #define DPAA2_SET_FD_ASAL(fd, asal) ((fd)->simple.ctrl |= (asal << 16))
192 #define DPAA2_SET_FD_FLC(fd, addr) do { \
193 (fd)->simple.flc_lo = lower_32_bits((uint64_t)(addr)); \
194 (fd)->simple.flc_hi = upper_32_bits((uint64_t)(addr)); \
196 #define DPAA2_SET_FLE_INTERNAL_JD(fle, len) ((fle)->frc = (0x80000000 | (len)))
197 #define DPAA2_GET_FLE_ADDR(fle) \
198 (uint64_t)((((uint64_t)((fle)->addr_hi)) << 32) + (fle)->addr_lo)
199 #define DPAA2_SET_FLE_ADDR(fle, addr) do { \
200 (fle)->addr_lo = lower_32_bits((uint64_t)addr); \
201 (fle)->addr_hi = upper_32_bits((uint64_t)addr); \
203 #define DPAA2_GET_FLE_CTXT(fle) \
204 (uint64_t)((((uint64_t)((fle)->reserved[1])) << 32) + \
206 #define DPAA2_FLE_SAVE_CTXT(fle, addr) do { \
207 (fle)->reserved[0] = lower_32_bits((uint64_t)addr); \
208 (fle)->reserved[1] = upper_32_bits((uint64_t)addr); \
210 #define DPAA2_SET_FLE_OFFSET(fle, offset) \
211 ((fle)->fin_bpid_offset |= (uint32_t)(offset) << 16)
212 #define DPAA2_SET_FLE_BPID(fle, bpid) ((fle)->fin_bpid_offset |= (uint64_t)bpid)
213 #define DPAA2_GET_FLE_BPID(fle) ((fle)->fin_bpid_offset & 0x000000ff)
214 #define DPAA2_SET_FLE_FIN(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 31)
215 #define DPAA2_SET_FLE_IVP(fle) (((fle)->fin_bpid_offset |= 0x00004000))
216 #define DPAA2_SET_FD_COMPOUND_FMT(fd) \
217 ((fd)->simple.bpid_offset |= (uint32_t)1 << 28)
218 #define DPAA2_GET_FD_ADDR(fd) \
219 ((uint64_t)((((uint64_t)((fd)->simple.addr_hi)) << 32) + (fd)->simple.addr_lo))
221 #define DPAA2_GET_FD_LEN(fd) ((fd)->simple.len)
222 #define DPAA2_GET_FD_BPID(fd) (((fd)->simple.bpid_offset & 0x00003FFF))
223 #define DPAA2_GET_FD_IVP(fd) (((fd)->simple.bpid_offset & 0x00004000) >> 14)
224 #define DPAA2_GET_FD_OFFSET(fd) (((fd)->simple.bpid_offset & 0x0FFF0000) >> 16)
225 #define DPAA2_GET_FLE_OFFSET(fle) (((fle)->fin_bpid_offset & 0x0FFF0000) >> 16)
226 #define DPAA2_SET_FLE_SG_EXT(fle) ((fle)->fin_bpid_offset |= (uint64_t)1 << 29)
227 #define DPAA2_IS_SET_FLE_SG_EXT(fle) \
228 (((fle)->fin_bpid_offset & ((uint64_t)1 << 29)) ? 1 : 0)
230 #define DPAA2_INLINE_MBUF_FROM_BUF(buf, meta_data_size) \
231 ((struct rte_mbuf *)((uint64_t)(buf) - (meta_data_size)))
233 #define DPAA2_ASAL_VAL (DPAA2_MBUF_HW_ANNOTATION / 64)
235 #define DPAA2_FD_SET_FORMAT(fd, format) do { \
236 (fd)->simple.bpid_offset &= 0xCFFFFFFF; \
237 (fd)->simple.bpid_offset |= (uint32_t)format << 28; \
239 #define DPAA2_FD_GET_FORMAT(fd) (((fd)->simple.bpid_offset >> 28) & 0x3)
241 #define DPAA2_SG_SET_FINAL(sg, fin) do { \
242 (sg)->fin_bpid_offset &= 0x7FFFFFFF; \
243 (sg)->fin_bpid_offset |= (uint32_t)fin << 31; \
245 #define DPAA2_SG_IS_FINAL(sg) (!!((sg)->fin_bpid_offset >> 31))
246 /* Only Enqueue Error responses will be
247 * pushed on FQID_ERR of Enqueue FQ
249 #define DPAA2_EQ_RESP_ERR_FQ 0
250 /* All Enqueue responses will be pushed on address
251 * set with qbman_eq_desc_set_response
253 #define DPAA2_EQ_RESP_ALWAYS 1
255 #ifdef RTE_LIBRTE_DPAA2_USE_PHYS_IOVA
256 extern uint8_t dpaa2_virt_mode;
257 static void *dpaa2_mem_ptov(phys_addr_t paddr) __attribute__((unused));
258 /* todo - this is costly, need to write a fast coversion routine */
259 static void *dpaa2_mem_ptov(phys_addr_t paddr)
261 const struct rte_memseg *memseg;
265 return (void *)paddr;
267 memseg = rte_eal_get_physmem_layout();
269 for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
270 if (paddr >= memseg[i].iova &&
271 (char *)paddr < (char *)memseg[i].iova + memseg[i].len)
272 return (void *)(memseg[i].addr_64
273 + (paddr - memseg[i].iova));
278 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr) __attribute__((unused));
279 static phys_addr_t dpaa2_mem_vtop(uint64_t vaddr)
281 const struct rte_memseg *memseg;
287 memseg = rte_eal_get_physmem_layout();
289 for (i = 0; i < RTE_MAX_MEMSEG && memseg[i].addr_64 != 0; i++) {
290 if (vaddr >= memseg[i].addr_64 &&
291 vaddr < memseg[i].addr_64 + memseg[i].len)
292 return memseg[i].iova
293 + (vaddr - memseg[i].addr_64);
295 return (phys_addr_t)(NULL);
299 * When we are using Physical addresses as IO Virtual Addresses,
300 * Need to call conversion routines dpaa2_mem_vtop & dpaa2_mem_ptov
302 * These routines are called with help of below MACRO's
305 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_iova)
306 #define DPAA2_OP_VADDR_TO_IOVA(op) (op->phys_addr)
309 * macro to convert Virtual address to IOVA
311 #define DPAA2_VADDR_TO_IOVA(_vaddr) dpaa2_mem_vtop((uint64_t)(_vaddr))
314 * macro to convert IOVA to Virtual address
316 #define DPAA2_IOVA_TO_VADDR(_iova) dpaa2_mem_ptov((phys_addr_t)(_iova))
319 * macro to convert modify the memory containing IOVA to Virtual address
321 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type) \
322 {_mem = (_type)(dpaa2_mem_ptov((phys_addr_t)(_mem))); }
324 #else /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
326 #define DPAA2_MBUF_VADDR_TO_IOVA(mbuf) ((mbuf)->buf_addr)
327 #define DPAA2_OP_VADDR_TO_IOVA(op) (op)
328 #define DPAA2_VADDR_TO_IOVA(_vaddr) (_vaddr)
329 #define DPAA2_IOVA_TO_VADDR(_iova) (_iova)
330 #define DPAA2_MODIFY_IOVA_TO_VADDR(_mem, _type)
332 #endif /* RTE_LIBRTE_DPAA2_USE_PHYS_IOVA */
335 int check_swp_active_dqs(uint16_t dpio_index)
337 if (rte_global_active_dqs_list[dpio_index].global_active_dqs != NULL)
343 void clear_swp_active_dqs(uint16_t dpio_index)
345 rte_global_active_dqs_list[dpio_index].global_active_dqs = NULL;
349 struct qbman_result *get_swp_active_dqs(uint16_t dpio_index)
351 return rte_global_active_dqs_list[dpio_index].global_active_dqs;
355 void set_swp_active_dqs(uint16_t dpio_index, struct qbman_result *dqs)
357 rte_global_active_dqs_list[dpio_index].global_active_dqs = dqs;
359 struct dpaa2_dpbp_dev *dpaa2_alloc_dpbp_dev(void);
360 void dpaa2_free_dpbp_dev(struct dpaa2_dpbp_dev *dpbp);
361 int dpaa2_dpbp_supported(void);
363 struct dpaa2_dpci_dev *rte_dpaa2_alloc_dpci_dev(void);
364 void rte_dpaa2_free_dpci_dev(struct dpaa2_dpci_dev *dpci);