1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (C) 2014-2016 Freescale Semiconductor, Inc.
7 #include "qbman_portal.h"
9 /* QBMan portal management command codes */
10 #define QBMAN_MC_ACQUIRE 0x30
11 #define QBMAN_WQCHAN_CONFIGURE 0x46
13 /* CINH register offsets */
14 #define QBMAN_CINH_SWP_EQCR_PI 0x800
15 #define QBMAN_CINH_SWP_EQCR_CI 0x840
16 #define QBMAN_CINH_SWP_EQAR 0x8c0
17 #define QBMAN_CINH_SWP_DQPI 0xa00
18 #define QBMAN_CINH_SWP_DCAP 0xac0
19 #define QBMAN_CINH_SWP_SDQCR 0xb00
20 #define QBMAN_CINH_SWP_RAR 0xcc0
21 #define QBMAN_CINH_SWP_ISR 0xe00
22 #define QBMAN_CINH_SWP_IER 0xe40
23 #define QBMAN_CINH_SWP_ISDR 0xe80
24 #define QBMAN_CINH_SWP_IIR 0xec0
25 #define QBMAN_CINH_SWP_DQRR_ITR 0xa80
26 #define QBMAN_CINH_SWP_ITPR 0xf40
28 /* CENA register offsets */
29 #define QBMAN_CENA_SWP_EQCR(n) (0x000 + ((uint32_t)(n) << 6))
30 #define QBMAN_CENA_SWP_DQRR(n) (0x200 + ((uint32_t)(n) << 6))
31 #define QBMAN_CENA_SWP_RCR(n) (0x400 + ((uint32_t)(n) << 6))
32 #define QBMAN_CENA_SWP_CR 0x600
33 #define QBMAN_CENA_SWP_RR(vb) (0x700 + ((uint32_t)(vb) >> 1))
34 #define QBMAN_CENA_SWP_VDQCR 0x780
35 #define QBMAN_CENA_SWP_EQCR_CI 0x840
37 /* Reverse mapping of QBMAN_CENA_SWP_DQRR() */
38 #define QBMAN_IDX_FROM_DQRR(p) (((unsigned long)p & 0x1ff) >> 6)
40 /* QBMan FQ management command codes */
41 #define QBMAN_FQ_SCHEDULE 0x48
42 #define QBMAN_FQ_FORCE 0x49
43 #define QBMAN_FQ_XON 0x4d
44 #define QBMAN_FQ_XOFF 0x4e
46 /*******************************/
47 /* Pre-defined attribute codes */
48 /*******************************/
50 #define QBMAN_RESPONSE_VERB_MASK 0x7f
52 /*************************/
53 /* SDQCR attribute codes */
54 /*************************/
55 #define QB_SDQCR_FC_SHIFT 29
56 #define QB_SDQCR_FC_MASK 0x1
57 #define QB_SDQCR_DCT_SHIFT 24
58 #define QB_SDQCR_DCT_MASK 0x3
59 #define QB_SDQCR_TOK_SHIFT 16
60 #define QB_SDQCR_TOK_MASK 0xff
61 #define QB_SDQCR_SRC_SHIFT 0
62 #define QB_SDQCR_SRC_MASK 0xffff
64 /* opaque token for static dequeues */
65 #define QMAN_SDQCR_TOKEN 0xbb
67 enum qbman_sdqcr_dct {
68 qbman_sdqcr_dct_null = 0,
69 qbman_sdqcr_dct_prio_ics,
70 qbman_sdqcr_dct_active_ics,
71 qbman_sdqcr_dct_active
75 qbman_sdqcr_fc_one = 0,
76 qbman_sdqcr_fc_up_to_3 = 1
79 /* We need to keep track of which SWP triggered a pull command
80 * so keep an array of portal IDs and use the token field to
81 * be able to find the proper portal
83 #define MAX_QBMAN_PORTALS 64
84 static struct qbman_swp *portal_idx_map[MAX_QBMAN_PORTALS];
86 /*********************************/
87 /* Portal constructor/destructor */
88 /*********************************/
90 /* Software portals should always be in the power-on state when we initialise,
91 * due to the CCSR-based portal reset functionality that MC has.
93 * Erk! Turns out that QMan versions prior to 4.1 do not correctly reset DQRR
94 * valid-bits, so we need to support a workaround where we don't trust
95 * valid-bits when detecting new entries until any stale ring entries have been
96 * overwritten at least once. The idea is that we read PI for the first few
97 * entries, then switch to valid-bit after that. The trick is to clear the
98 * bug-work-around boolean once the PI wraps around the ring for the first time.
100 * Note: this still carries a slight additional cost once the decrementer hits
103 struct qbman_swp *qbman_swp_init(const struct qbman_swp_desc *d)
107 struct qbman_swp *p = malloc(sizeof(*p));
112 #ifdef QBMAN_CHECKING
113 p->mc.check = swp_mc_can_start;
115 p->mc.valid_bit = QB_VALID_BIT;
117 p->sdq |= qbman_sdqcr_dct_prio_ics << QB_SDQCR_DCT_SHIFT;
118 p->sdq |= qbman_sdqcr_fc_up_to_3 << QB_SDQCR_FC_SHIFT;
119 p->sdq |= QMAN_SDQCR_TOKEN << QB_SDQCR_TOK_SHIFT;
121 atomic_set(&p->vdq.busy, 1);
122 p->vdq.valid_bit = QB_VALID_BIT;
123 p->dqrr.next_idx = 0;
124 p->dqrr.valid_bit = QB_VALID_BIT;
125 qman_version = p->desc.qman_version;
126 if ((qman_version & 0xFFFF0000) < QMAN_REV_4100) {
127 p->dqrr.dqrr_size = 4;
128 p->dqrr.reset_bug = 1;
130 p->dqrr.dqrr_size = 8;
131 p->dqrr.reset_bug = 0;
134 ret = qbman_swp_sys_init(&p->sys, d, p->dqrr.dqrr_size);
137 pr_err("qbman_swp_sys_init() failed %d\n", ret);
140 /* SDQCR needs to be initialized to 0 when no channels are
141 * being dequeued from or else the QMan HW will indicate an
142 * error. The values that were calculated above will be
143 * applied when dequeues from a specific channel are enabled.
145 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_SDQCR, 0);
146 eqcr_pi = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_PI);
147 p->eqcr.pi = eqcr_pi & 0xF;
148 p->eqcr.pi_vb = eqcr_pi & QB_VALID_BIT;
149 p->eqcr.ci = qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_EQCR_CI) & 0xF;
150 p->eqcr.available = QBMAN_EQCR_SIZE - qm_cyc_diff(QBMAN_EQCR_SIZE,
151 p->eqcr.ci, p->eqcr.pi);
153 portal_idx_map[p->desc.idx] = p;
157 void qbman_swp_finish(struct qbman_swp *p)
159 #ifdef QBMAN_CHECKING
160 QBMAN_BUG_ON(p->mc.check != swp_mc_can_start);
162 qbman_swp_sys_finish(&p->sys);
163 portal_idx_map[p->desc.idx] = NULL;
167 const struct qbman_swp_desc *qbman_swp_get_desc(struct qbman_swp *p)
176 uint32_t qbman_swp_interrupt_get_vanish(struct qbman_swp *p)
178 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISDR);
181 void qbman_swp_interrupt_set_vanish(struct qbman_swp *p, uint32_t mask)
183 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISDR, mask);
186 uint32_t qbman_swp_interrupt_read_status(struct qbman_swp *p)
188 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ISR);
191 void qbman_swp_interrupt_clear_status(struct qbman_swp *p, uint32_t mask)
193 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ISR, mask);
196 uint32_t qbman_swp_dqrr_thrshld_read_status(struct qbman_swp *p)
198 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_DQRR_ITR);
201 void qbman_swp_dqrr_thrshld_write(struct qbman_swp *p, uint32_t mask)
203 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_DQRR_ITR, mask);
206 uint32_t qbman_swp_intr_timeout_read_status(struct qbman_swp *p)
208 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_ITPR);
211 void qbman_swp_intr_timeout_write(struct qbman_swp *p, uint32_t mask)
213 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_ITPR, mask);
216 uint32_t qbman_swp_interrupt_get_trigger(struct qbman_swp *p)
218 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IER);
221 void qbman_swp_interrupt_set_trigger(struct qbman_swp *p, uint32_t mask)
223 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IER, mask);
226 int qbman_swp_interrupt_get_inhibit(struct qbman_swp *p)
228 return qbman_cinh_read(&p->sys, QBMAN_CINH_SWP_IIR);
231 void qbman_swp_interrupt_set_inhibit(struct qbman_swp *p, int inhibit)
233 qbman_cinh_write(&p->sys, QBMAN_CINH_SWP_IIR, inhibit ? 0xffffffff : 0);
236 /***********************/
237 /* Management commands */
238 /***********************/
241 * Internal code common to all types of management commands.
244 void *qbman_swp_mc_start(struct qbman_swp *p)
247 #ifdef QBMAN_CHECKING
248 QBMAN_BUG_ON(p->mc.check != swp_mc_can_start);
250 ret = qbman_cena_write_start(&p->sys, QBMAN_CENA_SWP_CR);
251 #ifdef QBMAN_CHECKING
253 p->mc.check = swp_mc_can_submit;
258 void qbman_swp_mc_submit(struct qbman_swp *p, void *cmd, uint8_t cmd_verb)
261 #ifdef QBMAN_CHECKING
262 QBMAN_BUG_ON(!(p->mc.check != swp_mc_can_submit));
264 /* TBD: "|=" is going to hurt performance. Need to move as many fields
265 * out of word zero, and for those that remain, the "OR" needs to occur
266 * at the caller side. This debug check helps to catch cases where the
267 * caller wants to OR but has forgotten to do so.
269 QBMAN_BUG_ON((*v & cmd_verb) != *v);
270 *v = cmd_verb | p->mc.valid_bit;
271 qbman_cena_write_complete(&p->sys, QBMAN_CENA_SWP_CR, cmd);
272 #ifdef QBMAN_CHECKING
273 p->mc.check = swp_mc_can_poll;
277 void *qbman_swp_mc_result(struct qbman_swp *p)
280 #ifdef QBMAN_CHECKING
281 QBMAN_BUG_ON(p->mc.check != swp_mc_can_poll);
283 qbman_cena_invalidate_prefetch(&p->sys,
284 QBMAN_CENA_SWP_RR(p->mc.valid_bit));
285 ret = qbman_cena_read(&p->sys, QBMAN_CENA_SWP_RR(p->mc.valid_bit));
286 /* Remove the valid-bit - command completed if the rest is non-zero */
287 verb = ret[0] & ~QB_VALID_BIT;
290 #ifdef QBMAN_CHECKING
291 p->mc.check = swp_mc_can_start;
293 p->mc.valid_bit ^= QB_VALID_BIT;
301 #define QB_ENQUEUE_CMD_OPTIONS_SHIFT 0
302 enum qb_enqueue_commands {
304 enqueue_response_always = 1,
305 enqueue_rejects_to_fq = 2
308 #define QB_ENQUEUE_CMD_EC_OPTION_MASK 0x3
309 #define QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT 2
310 #define QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT 3
311 #define QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT 4
312 #define QB_ENQUEUE_CMD_DCA_PK_SHIFT 6
313 #define QB_ENQUEUE_CMD_DCA_EN_SHIFT 7
314 #define QB_ENQUEUE_CMD_NLIS_SHIFT 14
315 #define QB_ENQUEUE_CMD_IS_NESN_SHIFT 15
317 void qbman_eq_desc_clear(struct qbman_eq_desc *d)
319 memset(d, 0, sizeof(*d));
322 void qbman_eq_desc_set_no_orp(struct qbman_eq_desc *d, int respond_success)
324 d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT);
326 d->eq.verb |= enqueue_response_always;
328 d->eq.verb |= enqueue_rejects_to_fq;
331 void qbman_eq_desc_set_orp(struct qbman_eq_desc *d, int respond_success,
332 uint16_t opr_id, uint16_t seqnum, int incomplete)
334 d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT;
336 d->eq.verb |= enqueue_response_always;
338 d->eq.verb |= enqueue_rejects_to_fq;
340 d->eq.orpid = opr_id;
341 d->eq.seqnum = seqnum;
343 d->eq.seqnum |= 1 << QB_ENQUEUE_CMD_NLIS_SHIFT;
345 d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT);
348 void qbman_eq_desc_set_orp_hole(struct qbman_eq_desc *d, uint16_t opr_id,
351 d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT;
352 d->eq.verb &= ~QB_ENQUEUE_CMD_EC_OPTION_MASK;
353 d->eq.orpid = opr_id;
354 d->eq.seqnum = seqnum;
355 d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT);
356 d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_IS_NESN_SHIFT);
359 void qbman_eq_desc_set_orp_nesn(struct qbman_eq_desc *d, uint16_t opr_id,
362 d->eq.verb |= 1 << QB_ENQUEUE_CMD_ORP_ENABLE_SHIFT;
363 d->eq.verb &= ~QB_ENQUEUE_CMD_EC_OPTION_MASK;
364 d->eq.orpid = opr_id;
365 d->eq.seqnum = seqnum;
366 d->eq.seqnum &= ~(1 << QB_ENQUEUE_CMD_NLIS_SHIFT);
367 d->eq.seqnum |= 1 << QB_ENQUEUE_CMD_IS_NESN_SHIFT;
370 void qbman_eq_desc_set_response(struct qbman_eq_desc *d,
371 dma_addr_t storage_phys,
374 d->eq.rsp_addr = storage_phys;
378 void qbman_eq_desc_set_token(struct qbman_eq_desc *d, uint8_t token)
383 void qbman_eq_desc_set_fq(struct qbman_eq_desc *d, uint32_t fqid)
385 d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT);
389 void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid,
390 uint16_t qd_bin, uint8_t qd_prio)
392 d->eq.verb |= 1 << QB_ENQUEUE_CMD_TARGET_TYPE_SHIFT;
394 d->eq.qdbin = qd_bin;
395 d->eq.qpri = qd_prio;
398 void qbman_eq_desc_set_eqdi(struct qbman_eq_desc *d, int enable)
401 d->eq.verb |= 1 << QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT;
403 d->eq.verb &= ~(1 << QB_ENQUEUE_CMD_IRQ_ON_DISPATCH_SHIFT);
406 void qbman_eq_desc_set_dca(struct qbman_eq_desc *d, int enable,
407 uint8_t dqrr_idx, int park)
410 d->eq.dca = dqrr_idx;
412 d->eq.dca |= 1 << QB_ENQUEUE_CMD_DCA_PK_SHIFT;
414 d->eq.dca &= ~(1 << QB_ENQUEUE_CMD_DCA_PK_SHIFT);
415 d->eq.dca |= 1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT;
417 d->eq.dca &= ~(1 << QB_ENQUEUE_CMD_DCA_EN_SHIFT);
421 #define EQAR_IDX(eqar) ((eqar) & 0x7)
422 #define EQAR_VB(eqar) ((eqar) & 0x80)
423 #define EQAR_SUCCESS(eqar) ((eqar) & 0x100)
425 static int qbman_swp_enqueue_array_mode(struct qbman_swp *s,
426 const struct qbman_eq_desc *d,
427 const struct qbman_fd *fd)
430 const uint32_t *cl = qb_cl(d);
431 uint32_t eqar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_EQAR);
433 pr_debug("EQAR=%08x\n", eqar);
434 if (!EQAR_SUCCESS(eqar))
436 p = qbman_cena_write_start_wo_shadow(&s->sys,
437 QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
438 memcpy(&p[1], &cl[1], 28);
439 memcpy(&p[8], fd, sizeof(*fd));
440 /* Set the verb byte, have to substitute in the valid-bit */
442 p[0] = cl[0] | EQAR_VB(eqar);
443 qbman_cena_write_complete_wo_shadow(&s->sys,
444 QBMAN_CENA_SWP_EQCR(EQAR_IDX(eqar)));
448 static int qbman_swp_enqueue_ring_mode(struct qbman_swp *s,
449 const struct qbman_eq_desc *d,
450 const struct qbman_fd *fd)
453 const uint32_t *cl = qb_cl(d);
457 if (!s->eqcr.available) {
458 eqcr_ci = s->eqcr.ci;
459 s->eqcr.ci = qbman_cena_read_reg(&s->sys,
460 QBMAN_CENA_SWP_EQCR_CI) & 0xF;
461 diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
462 eqcr_ci, s->eqcr.ci);
463 s->eqcr.available += diff;
468 p = qbman_cena_write_start_wo_shadow(&s->sys,
469 QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7));
470 memcpy(&p[1], &cl[1], 28);
471 memcpy(&p[8], fd, sizeof(*fd));
474 /* Set the verb byte, have to substitute in the valid-bit */
475 p[0] = cl[0] | s->eqcr.pi_vb;
476 qbman_cena_write_complete_wo_shadow(&s->sys,
477 QBMAN_CENA_SWP_EQCR(s->eqcr.pi & 7));
481 if (!(s->eqcr.pi & 7))
482 s->eqcr.pi_vb ^= QB_VALID_BIT;
487 int qbman_swp_enqueue(struct qbman_swp *s, const struct qbman_eq_desc *d,
488 const struct qbman_fd *fd)
490 if (s->sys.eqcr_mode == qman_eqcr_vb_array)
491 return qbman_swp_enqueue_array_mode(s, d, fd);
492 else /* Use ring mode by default */
493 return qbman_swp_enqueue_ring_mode(s, d, fd);
496 int qbman_swp_enqueue_multiple(struct qbman_swp *s,
497 const struct qbman_eq_desc *d,
498 const struct qbman_fd *fd,
502 const uint32_t *cl = qb_cl(d);
503 uint32_t eqcr_ci, eqcr_pi;
505 int i, num_enqueued = 0;
508 if (!s->eqcr.available) {
509 eqcr_ci = s->eqcr.ci;
510 s->eqcr.ci = qbman_cena_read_reg(&s->sys,
511 QBMAN_CENA_SWP_EQCR_CI) & 0xF;
512 diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
513 eqcr_ci, s->eqcr.ci);
514 s->eqcr.available += diff;
519 eqcr_pi = s->eqcr.pi;
520 num_enqueued = (s->eqcr.available < num_frames) ?
521 s->eqcr.available : num_frames;
522 s->eqcr.available -= num_enqueued;
523 /* Fill in the EQCR ring */
524 for (i = 0; i < num_enqueued; i++) {
525 p = qbman_cena_write_start_wo_shadow(&s->sys,
526 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
527 memcpy(&p[1], &cl[1], 28);
528 memcpy(&p[8], &fd[i], sizeof(*fd));
535 /* Set the verb byte, have to substitute in the valid-bit */
536 eqcr_pi = s->eqcr.pi;
537 for (i = 0; i < num_enqueued; i++) {
538 p = qbman_cena_write_start_wo_shadow(&s->sys,
539 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
540 p[0] = cl[0] | s->eqcr.pi_vb;
544 s->eqcr.pi_vb ^= QB_VALID_BIT;
547 /* Flush all the cacheline without load/store in between */
548 eqcr_pi = s->eqcr.pi;
549 addr_cena = (uint64_t)s->sys.addr_cena;
550 for (i = 0; i < num_enqueued; i++) {
551 dcbf((uint64_t *)(addr_cena +
552 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
556 s->eqcr.pi = eqcr_pi;
561 int qbman_swp_enqueue_multiple_desc(struct qbman_swp *s,
562 const struct qbman_eq_desc *d,
563 const struct qbman_fd *fd,
568 uint32_t eqcr_ci, eqcr_pi;
570 int i, num_enqueued = 0;
573 if (!s->eqcr.available) {
574 eqcr_ci = s->eqcr.ci;
575 s->eqcr.ci = qbman_cena_read_reg(&s->sys,
576 QBMAN_CENA_SWP_EQCR_CI) & 0xF;
577 diff = qm_cyc_diff(QBMAN_EQCR_SIZE,
578 eqcr_ci, s->eqcr.ci);
579 s->eqcr.available += diff;
584 eqcr_pi = s->eqcr.pi;
585 num_enqueued = (s->eqcr.available < num_frames) ?
586 s->eqcr.available : num_frames;
587 s->eqcr.available -= num_enqueued;
588 /* Fill in the EQCR ring */
589 for (i = 0; i < num_enqueued; i++) {
590 p = qbman_cena_write_start_wo_shadow(&s->sys,
591 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
593 memcpy(&p[1], &cl[1], 28);
594 memcpy(&p[8], &fd[i], sizeof(*fd));
601 /* Set the verb byte, have to substitute in the valid-bit */
602 eqcr_pi = s->eqcr.pi;
603 for (i = 0; i < num_enqueued; i++) {
604 p = qbman_cena_write_start_wo_shadow(&s->sys,
605 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7));
607 p[0] = cl[0] | s->eqcr.pi_vb;
611 s->eqcr.pi_vb ^= QB_VALID_BIT;
614 /* Flush all the cacheline without load/store in between */
615 eqcr_pi = s->eqcr.pi;
616 addr_cena = (uint64_t)s->sys.addr_cena;
617 for (i = 0; i < num_enqueued; i++) {
618 dcbf((uint64_t *)(addr_cena +
619 QBMAN_CENA_SWP_EQCR(eqcr_pi & 7)));
623 s->eqcr.pi = eqcr_pi;
628 /*************************/
629 /* Static (push) dequeue */
630 /*************************/
632 void qbman_swp_push_get(struct qbman_swp *s, uint8_t channel_idx, int *enabled)
634 uint16_t src = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
636 QBMAN_BUG_ON(channel_idx > 15);
637 *enabled = src | (1 << channel_idx);
640 void qbman_swp_push_set(struct qbman_swp *s, uint8_t channel_idx, int enable)
644 QBMAN_BUG_ON(channel_idx > 15);
646 s->sdq |= 1 << channel_idx;
648 s->sdq &= ~(1 << channel_idx);
650 /* Read make the complete src map. If no channels are enabled
651 * the SDQCR must be 0 or else QMan will assert errors
653 dqsrc = (s->sdq >> QB_SDQCR_SRC_SHIFT) & QB_SDQCR_SRC_MASK;
655 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, s->sdq);
657 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_SDQCR, 0);
660 /***************************/
661 /* Volatile (pull) dequeue */
662 /***************************/
664 /* These should be const, eventually */
665 #define QB_VDQCR_VERB_DCT_SHIFT 0
666 #define QB_VDQCR_VERB_DT_SHIFT 2
667 #define QB_VDQCR_VERB_RLS_SHIFT 4
668 #define QB_VDQCR_VERB_WAE_SHIFT 5
672 qb_pull_dt_workqueue,
673 qb_pull_dt_framequeue
676 void qbman_pull_desc_clear(struct qbman_pull_desc *d)
678 memset(d, 0, sizeof(*d));
681 void qbman_pull_desc_set_storage(struct qbman_pull_desc *d,
682 struct qbman_result *storage,
683 dma_addr_t storage_phys,
686 d->pull.rsp_addr_virt = (uint64_t)storage;
689 d->pull.verb &= ~(1 << QB_VDQCR_VERB_RLS_SHIFT);
692 d->pull.verb |= 1 << QB_VDQCR_VERB_RLS_SHIFT;
694 d->pull.verb |= 1 << QB_VDQCR_VERB_WAE_SHIFT;
696 d->pull.verb &= ~(1 << QB_VDQCR_VERB_WAE_SHIFT);
698 d->pull.rsp_addr = storage_phys;
701 void qbman_pull_desc_set_numframes(struct qbman_pull_desc *d, uint8_t numframes)
703 d->pull.numf = numframes - 1;
706 void qbman_pull_desc_set_token(struct qbman_pull_desc *d, uint8_t token)
711 void qbman_pull_desc_set_fq(struct qbman_pull_desc *d, uint32_t fqid)
713 d->pull.verb |= 1 << QB_VDQCR_VERB_DCT_SHIFT;
714 d->pull.verb |= qb_pull_dt_framequeue << QB_VDQCR_VERB_DT_SHIFT;
715 d->pull.dq_src = fqid;
718 void qbman_pull_desc_set_wq(struct qbman_pull_desc *d, uint32_t wqid,
719 enum qbman_pull_type_e dct)
721 d->pull.verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
722 d->pull.verb |= qb_pull_dt_workqueue << QB_VDQCR_VERB_DT_SHIFT;
723 d->pull.dq_src = wqid;
726 void qbman_pull_desc_set_channel(struct qbman_pull_desc *d, uint32_t chid,
727 enum qbman_pull_type_e dct)
729 d->pull.verb |= dct << QB_VDQCR_VERB_DCT_SHIFT;
730 d->pull.verb |= qb_pull_dt_channel << QB_VDQCR_VERB_DT_SHIFT;
731 d->pull.dq_src = chid;
734 int qbman_swp_pull(struct qbman_swp *s, struct qbman_pull_desc *d)
737 uint32_t *cl = qb_cl(d);
739 if (!atomic_dec_and_test(&s->vdq.busy)) {
740 atomic_inc(&s->vdq.busy);
744 d->pull.tok = s->sys.idx + 1;
745 s->vdq.storage = (void *)d->pull.rsp_addr_virt;
746 p = qbman_cena_write_start_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
747 memcpy(&p[1], &cl[1], 12);
749 /* Set the verb byte, have to substitute in the valid-bit */
751 p[0] = cl[0] | s->vdq.valid_bit;
752 s->vdq.valid_bit ^= QB_VALID_BIT;
753 qbman_cena_write_complete_wo_shadow(&s->sys, QBMAN_CENA_SWP_VDQCR);
762 #define QMAN_DQRR_PI_MASK 0xf
764 #define QBMAN_RESULT_DQ 0x60
765 #define QBMAN_RESULT_FQRN 0x21
766 #define QBMAN_RESULT_FQRNI 0x22
767 #define QBMAN_RESULT_FQPN 0x24
768 #define QBMAN_RESULT_FQDAN 0x25
769 #define QBMAN_RESULT_CDAN 0x26
770 #define QBMAN_RESULT_CSCN_MEM 0x27
771 #define QBMAN_RESULT_CGCU 0x28
772 #define QBMAN_RESULT_BPSCN 0x29
773 #define QBMAN_RESULT_CSCN_WQ 0x2a
775 /* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry
776 * only once, so repeated calls can return a sequence of DQRR entries, without
777 * requiring they be consumed immediately or in any particular order.
779 const struct qbman_result *qbman_swp_dqrr_next(struct qbman_swp *s)
782 uint32_t response_verb;
784 const struct qbman_result *p;
786 /* Before using valid-bit to detect if something is there, we have to
787 * handle the case of the DQRR reset bug...
789 if (unlikely(s->dqrr.reset_bug)) {
790 /* We pick up new entries by cache-inhibited producer index,
791 * which means that a non-coherent mapping would require us to
792 * invalidate and read *only* once that PI has indicated that
793 * there's an entry here. The first trip around the DQRR ring
794 * will be much less efficient than all subsequent trips around
797 uint8_t pi = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_DQPI) &
800 /* there are new entries if pi != next_idx */
801 if (pi == s->dqrr.next_idx)
804 /* if next_idx is/was the last ring index, and 'pi' is
805 * different, we can disable the workaround as all the ring
806 * entries have now been DMA'd to so valid-bit checking is
807 * repaired. Note: this logic needs to be based on next_idx
808 * (which increments one at a time), rather than on pi (which
809 * can burst and wrap-around between our snapshots of it).
811 QBMAN_BUG_ON((s->dqrr.dqrr_size - 1) < 0);
812 if (s->dqrr.next_idx == (s->dqrr.dqrr_size - 1u)) {
813 pr_debug("DEBUG: next_idx=%d, pi=%d, clear reset bug\n",
814 s->dqrr.next_idx, pi);
815 s->dqrr.reset_bug = 0;
817 qbman_cena_invalidate_prefetch(&s->sys,
818 QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
820 p = qbman_cena_read_wo_shadow(&s->sys,
821 QBMAN_CENA_SWP_DQRR(s->dqrr.next_idx));
824 /* If the valid-bit isn't of the expected polarity, nothing there. Note,
825 * in the DQRR reset bug workaround, we shouldn't need to skip these
826 * check, because we've already determined that a new entry is available
827 * and we've invalidated the cacheline before reading it, so the
828 * valid-bit behaviour is repaired and should tell us what we already
829 * knew from reading PI.
831 if ((verb & QB_VALID_BIT) != s->dqrr.valid_bit)
834 /* There's something there. Move "next_idx" attention to the next ring
835 * entry (and prefetch it) before returning what we found.
838 if (s->dqrr.next_idx == s->dqrr.dqrr_size) {
839 s->dqrr.next_idx = 0;
840 s->dqrr.valid_bit ^= QB_VALID_BIT;
842 /* If this is the final response to a volatile dequeue command
843 * indicate that the vdq is no longer busy
846 response_verb = verb & QBMAN_RESPONSE_VERB_MASK;
847 if ((response_verb == QBMAN_RESULT_DQ) &&
848 (flags & QBMAN_DQ_STAT_VOLATILE) &&
849 (flags & QBMAN_DQ_STAT_EXPIRED))
850 atomic_inc(&s->vdq.busy);
855 /* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */
856 void qbman_swp_dqrr_consume(struct qbman_swp *s,
857 const struct qbman_result *dq)
859 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, QBMAN_IDX_FROM_DQRR(dq));
862 /* Consume DQRR entries previously returned from qbman_swp_dqrr_next(). */
863 void qbman_swp_dqrr_idx_consume(struct qbman_swp *s,
866 qbman_cinh_write(&s->sys, QBMAN_CINH_SWP_DCAP, dqrr_index);
869 /*********************************/
870 /* Polling user-provided storage */
871 /*********************************/
872 int qbman_result_has_new_result(struct qbman_swp *s,
873 struct qbman_result *dq)
879 * Set token to be 0 so we will detect change back to 1
880 * next time the looping is traversed. Const is cast away here
881 * as we want users to treat the dequeue responses as read only.
883 ((struct qbman_result *)dq)->dq.tok = 0;
886 * VDQCR "no longer busy" hook - not quite the same as DQRR, because the
887 * fact "VDQCR" shows busy doesn't mean that we hold the result that
888 * makes it available. Eg. we may be looking at our 10th dequeue result,
889 * having released VDQCR after the 1st result and it is now busy due to
890 * some other command!
892 if (s->vdq.storage == dq) {
893 s->vdq.storage = NULL;
894 atomic_inc(&s->vdq.busy);
900 int qbman_check_new_result(struct qbman_result *dq)
906 * Set token to be 0 so we will detect change back to 1
907 * next time the looping is traversed. Const is cast away here
908 * as we want users to treat the dequeue responses as read only.
910 ((struct qbman_result *)dq)->dq.tok = 0;
915 int qbman_check_command_complete(struct qbman_result *dq)
922 s = portal_idx_map[dq->dq.tok - 1];
924 * VDQCR "no longer busy" hook - not quite the same as DQRR, because the
925 * fact "VDQCR" shows busy doesn't mean that we hold the result that
926 * makes it available. Eg. we may be looking at our 10th dequeue result,
927 * having released VDQCR after the 1st result and it is now busy due to
928 * some other command!
930 if (s->vdq.storage == dq) {
931 s->vdq.storage = NULL;
932 atomic_inc(&s->vdq.busy);
938 /********************************/
939 /* Categorising qbman results */
940 /********************************/
942 static inline int __qbman_result_is_x(const struct qbman_result *dq,
945 uint8_t response_verb = dq->dq.verb & QBMAN_RESPONSE_VERB_MASK;
947 return (response_verb == x);
950 int qbman_result_is_DQ(const struct qbman_result *dq)
952 return __qbman_result_is_x(dq, QBMAN_RESULT_DQ);
955 int qbman_result_is_FQDAN(const struct qbman_result *dq)
957 return __qbman_result_is_x(dq, QBMAN_RESULT_FQDAN);
960 int qbman_result_is_CDAN(const struct qbman_result *dq)
962 return __qbman_result_is_x(dq, QBMAN_RESULT_CDAN);
965 int qbman_result_is_CSCN(const struct qbman_result *dq)
967 return __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_MEM) ||
968 __qbman_result_is_x(dq, QBMAN_RESULT_CSCN_WQ);
971 int qbman_result_is_BPSCN(const struct qbman_result *dq)
973 return __qbman_result_is_x(dq, QBMAN_RESULT_BPSCN);
976 int qbman_result_is_CGCU(const struct qbman_result *dq)
978 return __qbman_result_is_x(dq, QBMAN_RESULT_CGCU);
981 int qbman_result_is_FQRN(const struct qbman_result *dq)
983 return __qbman_result_is_x(dq, QBMAN_RESULT_FQRN);
986 int qbman_result_is_FQRNI(const struct qbman_result *dq)
988 return __qbman_result_is_x(dq, QBMAN_RESULT_FQRNI);
991 int qbman_result_is_FQPN(const struct qbman_result *dq)
993 return __qbman_result_is_x(dq, QBMAN_RESULT_FQPN);
996 /*********************************/
997 /* Parsing frame dequeue results */
998 /*********************************/
1000 /* These APIs assume qbman_result_is_DQ() is TRUE */
1002 uint8_t qbman_result_DQ_flags(const struct qbman_result *dq)
1007 uint16_t qbman_result_DQ_seqnum(const struct qbman_result *dq)
1009 return dq->dq.seqnum;
1012 uint16_t qbman_result_DQ_odpid(const struct qbman_result *dq)
1014 return dq->dq.oprid;
1017 uint32_t qbman_result_DQ_fqid(const struct qbman_result *dq)
1022 uint32_t qbman_result_DQ_byte_count(const struct qbman_result *dq)
1024 return dq->dq.fq_byte_cnt;
1027 uint32_t qbman_result_DQ_frame_count(const struct qbman_result *dq)
1029 return dq->dq.fq_frm_cnt;
1032 uint64_t qbman_result_DQ_fqd_ctx(const struct qbman_result *dq)
1034 return dq->dq.fqd_ctx;
1037 const struct qbman_fd *qbman_result_DQ_fd(const struct qbman_result *dq)
1039 return (const struct qbman_fd *)&dq->dq.fd[0];
1042 /**************************************/
1043 /* Parsing state-change notifications */
1044 /**************************************/
1045 uint8_t qbman_result_SCN_state(const struct qbman_result *scn)
1047 return scn->scn.state;
1050 uint32_t qbman_result_SCN_rid(const struct qbman_result *scn)
1052 return scn->scn.rid_tok;
1055 uint64_t qbman_result_SCN_ctx(const struct qbman_result *scn)
1057 return scn->scn.ctx;
1063 uint16_t qbman_result_bpscn_bpid(const struct qbman_result *scn)
1065 return (uint16_t)qbman_result_SCN_rid(scn) & 0x3FFF;
1068 int qbman_result_bpscn_has_free_bufs(const struct qbman_result *scn)
1070 return !(int)(qbman_result_SCN_state(scn) & 0x1);
1073 int qbman_result_bpscn_is_depleted(const struct qbman_result *scn)
1075 return (int)(qbman_result_SCN_state(scn) & 0x2);
1078 int qbman_result_bpscn_is_surplus(const struct qbman_result *scn)
1080 return (int)(qbman_result_SCN_state(scn) & 0x4);
1083 uint64_t qbman_result_bpscn_ctx(const struct qbman_result *scn)
1085 return qbman_result_SCN_ctx(scn);
1091 uint16_t qbman_result_cgcu_cgid(const struct qbman_result *scn)
1093 return (uint16_t)qbman_result_SCN_rid(scn) & 0xFFFF;
1096 uint64_t qbman_result_cgcu_icnt(const struct qbman_result *scn)
1098 return qbman_result_SCN_ctx(scn);
1101 /******************/
1102 /* Buffer release */
1103 /******************/
1104 #define QB_BR_RC_VALID_SHIFT 5
1105 #define QB_BR_RCDI_SHIFT 6
1107 void qbman_release_desc_clear(struct qbman_release_desc *d)
1109 memset(d, 0, sizeof(*d));
1110 d->br.verb = 1 << QB_BR_RC_VALID_SHIFT;
1113 void qbman_release_desc_set_bpid(struct qbman_release_desc *d, uint16_t bpid)
1118 void qbman_release_desc_set_rcdi(struct qbman_release_desc *d, int enable)
1121 d->br.verb |= 1 << QB_BR_RCDI_SHIFT;
1123 d->br.verb &= ~(1 << QB_BR_RCDI_SHIFT);
1126 #define RAR_IDX(rar) ((rar) & 0x7)
1127 #define RAR_VB(rar) ((rar) & 0x80)
1128 #define RAR_SUCCESS(rar) ((rar) & 0x100)
1130 int qbman_swp_release(struct qbman_swp *s, const struct qbman_release_desc *d,
1131 const uint64_t *buffers, unsigned int num_buffers)
1134 const uint32_t *cl = qb_cl(d);
1135 uint32_t rar = qbman_cinh_read(&s->sys, QBMAN_CINH_SWP_RAR);
1137 pr_debug("RAR=%08x\n", rar);
1138 if (!RAR_SUCCESS(rar))
1141 QBMAN_BUG_ON(!num_buffers || (num_buffers > 7));
1143 /* Start the release command */
1144 p = qbman_cena_write_start_wo_shadow(&s->sys,
1145 QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
1147 /* Copy the caller's buffer pointers to the command */
1148 u64_to_le32_copy(&p[2], buffers, num_buffers);
1150 /* Set the verb byte, have to substitute in the valid-bit and the number
1154 p[0] = cl[0] | RAR_VB(rar) | num_buffers;
1155 qbman_cena_write_complete_wo_shadow(&s->sys,
1156 QBMAN_CENA_SWP_RCR(RAR_IDX(rar)));
1161 /*******************/
1162 /* Buffer acquires */
1163 /*******************/
1164 struct qbman_acquire_desc {
1169 uint8_t reserved2[59];
1172 struct qbman_acquire_rslt {
1177 uint8_t reserved2[3];
1181 int qbman_swp_acquire(struct qbman_swp *s, uint16_t bpid, uint64_t *buffers,
1182 unsigned int num_buffers)
1184 struct qbman_acquire_desc *p;
1185 struct qbman_acquire_rslt *r;
1187 if (!num_buffers || (num_buffers > 7))
1190 /* Start the management command */
1191 p = qbman_swp_mc_start(s);
1196 /* Encode the caller-provided attributes */
1198 p->num = num_buffers;
1200 /* Complete the management command */
1201 r = qbman_swp_mc_complete(s, p, QBMAN_MC_ACQUIRE);
1203 pr_err("qbman: acquire from BPID %d failed, no response\n",
1208 /* Decode the outcome */
1209 QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != QBMAN_MC_ACQUIRE);
1211 /* Determine success or failure */
1212 if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
1213 pr_err("Acquire buffers from BPID 0x%x failed, code=0x%02x\n",
1218 QBMAN_BUG_ON(r->num > num_buffers);
1220 /* Copy the acquired buffers to the caller's array */
1221 u64_from_le32_copy(buffers, &r->buf[0], r->num);
1229 struct qbman_alt_fq_state_desc {
1231 uint8_t reserved[3];
1233 uint8_t reserved2[56];
1236 struct qbman_alt_fq_state_rslt {
1239 uint8_t reserved[62];
1242 #define ALT_FQ_FQID_MASK 0x00FFFFFF
1244 static int qbman_swp_alt_fq_state(struct qbman_swp *s, uint32_t fqid,
1245 uint8_t alt_fq_verb)
1247 struct qbman_alt_fq_state_desc *p;
1248 struct qbman_alt_fq_state_rslt *r;
1250 /* Start the management command */
1251 p = qbman_swp_mc_start(s);
1255 p->fqid = fqid & ALT_FQ_FQID_MASK;
1257 /* Complete the management command */
1258 r = qbman_swp_mc_complete(s, p, alt_fq_verb);
1260 pr_err("qbman: mgmt cmd failed, no response (verb=0x%x)\n",
1265 /* Decode the outcome */
1266 QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK) != alt_fq_verb);
1268 /* Determine success or failure */
1269 if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
1270 pr_err("ALT FQID %d failed: verb = 0x%08x, code = 0x%02x\n",
1271 fqid, alt_fq_verb, r->rslt);
1278 int qbman_swp_fq_schedule(struct qbman_swp *s, uint32_t fqid)
1280 return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_SCHEDULE);
1283 int qbman_swp_fq_force(struct qbman_swp *s, uint32_t fqid)
1285 return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_FORCE);
1288 int qbman_swp_fq_xon(struct qbman_swp *s, uint32_t fqid)
1290 return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XON);
1293 int qbman_swp_fq_xoff(struct qbman_swp *s, uint32_t fqid)
1295 return qbman_swp_alt_fq_state(s, fqid, QBMAN_FQ_XOFF);
1298 /**********************/
1299 /* Channel management */
1300 /**********************/
1302 struct qbman_cdan_ctrl_desc {
1310 uint8_t reserved3[48];
1314 struct qbman_cdan_ctrl_rslt {
1318 uint8_t reserved[60];
1321 /* Hide "ICD" for now as we don't use it, don't set it, and don't test it, so it
1322 * would be irresponsible to expose it.
1324 #define CODE_CDAN_WE_EN 0x1
1325 #define CODE_CDAN_WE_CTX 0x4
1327 static int qbman_swp_CDAN_set(struct qbman_swp *s, uint16_t channelid,
1328 uint8_t we_mask, uint8_t cdan_en,
1331 struct qbman_cdan_ctrl_desc *p;
1332 struct qbman_cdan_ctrl_rslt *r;
1334 /* Start the management command */
1335 p = qbman_swp_mc_start(s);
1339 /* Encode the caller-provided attributes */
1348 /* Complete the management command */
1349 r = qbman_swp_mc_complete(s, p, QBMAN_WQCHAN_CONFIGURE);
1351 pr_err("qbman: wqchan config failed, no response\n");
1355 /* Decode the outcome */
1356 QBMAN_BUG_ON((r->verb & QBMAN_RESPONSE_VERB_MASK)
1357 != QBMAN_WQCHAN_CONFIGURE);
1359 /* Determine success or failure */
1360 if (unlikely(r->rslt != QBMAN_MC_RSLT_OK)) {
1361 pr_err("CDAN cQID %d failed: code = 0x%02x\n",
1362 channelid, r->rslt);
1369 int qbman_swp_CDAN_set_context(struct qbman_swp *s, uint16_t channelid,
1372 return qbman_swp_CDAN_set(s, channelid,
1377 int qbman_swp_CDAN_enable(struct qbman_swp *s, uint16_t channelid)
1379 return qbman_swp_CDAN_set(s, channelid,
1384 int qbman_swp_CDAN_disable(struct qbman_swp *s, uint16_t channelid)
1386 return qbman_swp_CDAN_set(s, channelid,
1391 int qbman_swp_CDAN_set_context_enable(struct qbman_swp *s, uint16_t channelid,
1394 return qbman_swp_CDAN_set(s, channelid,
1395 CODE_CDAN_WE_EN | CODE_CDAN_WE_CTX,
1399 uint8_t qbman_get_dqrr_idx(const struct qbman_result *dqrr)
1401 return QBMAN_IDX_FROM_DQRR(dqrr);
1404 struct qbman_result *qbman_get_dqrr_from_idx(struct qbman_swp *s, uint8_t idx)
1406 struct qbman_result *dq;
1408 dq = qbman_cena_read(&s->sys, QBMAN_CENA_SWP_DQRR(idx));