1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
8 #define ROC_AURA_ID_MASK (BIT_ULL(16) - 1)
9 #define ROC_AURA_OP_LIMIT_MASK (BIT_ULL(36) - 1)
11 /* 16 CASP instructions can be outstanding in CN9k, but we use only 15
12 * outstanding CASPs as we run out of registers.
14 #define ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS 30
17 * Generate 64bit handle to have optimized alloc and free aura operation.
18 * 0 - ROC_AURA_ID_MASK for storing the aura_id.
19 * [ROC_AURA_ID_MASK+1, (2^64 - 1)] for storing the lf base address.
20 * This scheme is valid when OS can give ROC_AURA_ID_MASK
21 * aligned address for lf base address.
23 static inline uint64_t
24 roc_npa_aura_handle_gen(uint32_t aura_id, uintptr_t addr)
28 val = aura_id & ROC_AURA_ID_MASK;
29 return (uint64_t)addr | val;
32 static inline uint64_t
33 roc_npa_aura_handle_to_aura(uint64_t aura_handle)
35 return aura_handle & ROC_AURA_ID_MASK;
38 static inline uintptr_t
39 roc_npa_aura_handle_to_base(uint64_t aura_handle)
41 return (uintptr_t)(aura_handle & ~ROC_AURA_ID_MASK);
44 static inline uint64_t
45 roc_npa_aura_op_alloc(uint64_t aura_handle, const int drop)
47 uint64_t wdata = roc_npa_aura_handle_to_aura(aura_handle);
51 wdata |= BIT_ULL(63); /* DROP */
53 addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) +
54 NPA_LF_AURA_OP_ALLOCX(0));
55 return roc_atomic64_add_nosync(wdata, addr);
59 roc_npa_aura_op_free(uint64_t aura_handle, const int fabs, uint64_t iova)
61 uint64_t reg = roc_npa_aura_handle_to_aura(aura_handle);
63 roc_npa_aura_handle_to_base(aura_handle) + NPA_LF_AURA_OP_FREE0;
65 reg |= BIT_ULL(63); /* FABS */
67 roc_store_pair(iova, reg, addr);
70 static inline uint64_t
71 roc_npa_aura_op_cnt_get(uint64_t aura_handle)
77 wdata = roc_npa_aura_handle_to_aura(aura_handle) << 44;
78 addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) +
80 reg = roc_atomic64_add_nosync(wdata, addr);
82 if (reg & BIT_ULL(42) /* OP_ERR */)
85 return reg & 0xFFFFFFFFF;
89 roc_npa_aura_op_cnt_set(uint64_t aura_handle, const int sign, uint64_t count)
91 uint64_t reg = count & (BIT_ULL(36) - 1);
94 reg |= BIT_ULL(43); /* CNT_ADD */
96 reg |= (roc_npa_aura_handle_to_aura(aura_handle) << 44);
98 plt_write64(reg, roc_npa_aura_handle_to_base(aura_handle) +
102 static inline uint64_t
103 roc_npa_aura_op_limit_get(uint64_t aura_handle)
109 wdata = roc_npa_aura_handle_to_aura(aura_handle) << 44;
110 addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) +
111 NPA_LF_AURA_OP_LIMIT);
112 reg = roc_atomic64_add_nosync(wdata, addr);
114 if (reg & BIT_ULL(42) /* OP_ERR */)
117 return reg & ROC_AURA_OP_LIMIT_MASK;
121 roc_npa_aura_op_limit_set(uint64_t aura_handle, uint64_t limit)
123 uint64_t reg = limit & ROC_AURA_OP_LIMIT_MASK;
125 reg |= (roc_npa_aura_handle_to_aura(aura_handle) << 44);
127 plt_write64(reg, roc_npa_aura_handle_to_base(aura_handle) +
128 NPA_LF_AURA_OP_LIMIT);
131 static inline uint64_t
132 roc_npa_aura_op_available(uint64_t aura_handle)
138 wdata = roc_npa_aura_handle_to_aura(aura_handle) << 44;
139 addr = (int64_t *)(roc_npa_aura_handle_to_base(aura_handle) +
140 NPA_LF_POOL_OP_AVAILABLE);
141 reg = roc_atomic64_add_nosync(wdata, addr);
143 if (reg & BIT_ULL(42) /* OP_ERR */)
146 return reg & 0xFFFFFFFFF;
150 roc_npa_aura_op_bulk_free(uint64_t aura_handle, uint64_t const *buf,
151 unsigned int num, const int fabs)
155 for (i = 0; i < num; i++) {
156 const uint64_t inbuf = buf[i];
158 roc_npa_aura_op_free(aura_handle, fabs, inbuf);
162 static inline unsigned int
163 roc_npa_aura_bulk_alloc(uint64_t aura_handle, uint64_t *buf, unsigned int num,
166 #if defined(__aarch64__)
167 uint64_t wdata = roc_npa_aura_handle_to_aura(aura_handle);
168 unsigned int i, count;
172 wdata |= BIT_ULL(63); /* DROP */
174 addr = roc_npa_aura_handle_to_base(aura_handle) +
175 NPA_LF_AURA_OP_ALLOCX(0);
181 "mov v18.d[0], %[dst]\n"
182 "mov v18.d[1], %[loc]\n"
183 "mov v19.d[0], %[wdata]\n"
184 "mov v19.d[1], x30\n"
185 "mov v20.d[0], x24\n"
186 "mov v20.d[1], x25\n"
187 "mov v21.d[0], x26\n"
188 "mov v21.d[1], x27\n"
189 "mov v22.d[0], x28\n"
190 "mov v22.d[1], x29\n"
191 "mov x28, v19.d[0]\n"
192 "mov x29, v19.d[0]\n"
193 "mov x30, v18.d[1]\n"
194 "casp x0, x1, x28, x29, [x30]\n"
195 "casp x2, x3, x28, x29, [x30]\n"
196 "casp x4, x5, x28, x29, [x30]\n"
197 "casp x6, x7, x28, x29, [x30]\n"
198 "casp x8, x9, x28, x29, [x30]\n"
199 "casp x10, x11, x28, x29, [x30]\n"
200 "casp x12, x13, x28, x29, [x30]\n"
201 "casp x14, x15, x28, x29, [x30]\n"
202 "casp x16, x17, x28, x29, [x30]\n"
203 "casp x18, x19, x28, x29, [x30]\n"
204 "casp x20, x21, x28, x29, [x30]\n"
205 "casp x22, x23, x28, x29, [x30]\n"
206 "casp x24, x25, x28, x29, [x30]\n"
207 "casp x26, x27, x28, x29, [x30]\n"
208 "casp x28, x29, x28, x29, [x30]\n"
209 "mov x30, v18.d[0]\n"
210 "stp x0, x1, [x30]\n"
211 "stp x2, x3, [x30, #16]\n"
212 "stp x4, x5, [x30, #32]\n"
213 "stp x6, x7, [x30, #48]\n"
214 "stp x8, x9, [x30, #64]\n"
215 "stp x10, x11, [x30, #80]\n"
216 "stp x12, x13, [x30, #96]\n"
217 "stp x14, x15, [x30, #112]\n"
218 "stp x16, x17, [x30, #128]\n"
219 "stp x18, x19, [x30, #144]\n"
220 "stp x20, x21, [x30, #160]\n"
221 "stp x22, x23, [x30, #176]\n"
222 "stp x24, x25, [x30, #192]\n"
223 "stp x26, x27, [x30, #208]\n"
224 "stp x28, x29, [x30, #224]\n"
225 "mov %[dst], v18.d[0]\n"
226 "mov %[loc], v18.d[1]\n"
227 "mov %[wdata], v19.d[0]\n"
228 "mov x30, v19.d[1]\n"
229 "mov x24, v20.d[0]\n"
230 "mov x25, v20.d[1]\n"
231 "mov x26, v21.d[0]\n"
232 "mov x27, v21.d[1]\n"
233 "mov x28, v22.d[0]\n"
234 "mov x29, v22.d[1]\n"
236 : [wdata] "r"(wdata), [loc] "r"(addr), [dst] "r"(buf)
237 : "memory", "x0", "x1", "x2", "x3", "x4", "x5", "x6",
238 "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14",
239 "x15", "x16", "x17", "x18", "x19", "x20", "x21",
240 "x22", "x23", "v18", "v19", "v20", "v21", "v22");
245 "mov x16, %[wdata]\n"
246 "mov x17, %[wdata]\n"
247 "casp x0, x1, x16, x17, [%[loc]]\n"
248 "casp x2, x3, x16, x17, [%[loc]]\n"
249 "casp x4, x5, x16, x17, [%[loc]]\n"
250 "casp x6, x7, x16, x17, [%[loc]]\n"
251 "casp x8, x9, x16, x17, [%[loc]]\n"
252 "casp x10, x11, x16, x17, [%[loc]]\n"
253 "casp x12, x13, x16, x17, [%[loc]]\n"
254 "casp x14, x15, x16, x17, [%[loc]]\n"
255 "stp x0, x1, [%[dst]]\n"
256 "stp x2, x3, [%[dst], #16]\n"
257 "stp x4, x5, [%[dst], #32]\n"
258 "stp x6, x7, [%[dst], #48]\n"
259 "stp x8, x9, [%[dst], #64]\n"
260 "stp x10, x11, [%[dst], #80]\n"
261 "stp x12, x13, [%[dst], #96]\n"
262 "stp x14, x15, [%[dst], #112]\n"
264 : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr)
265 : "memory", "x0", "x1", "x2", "x3", "x4", "x5", "x6",
266 "x7", "x8", "x9", "x10", "x11", "x12", "x13", "x14",
273 "mov x16, %[wdata]\n"
274 "mov x17, %[wdata]\n"
275 "casp x0, x1, x16, x17, [%[loc]]\n"
276 "casp x2, x3, x16, x17, [%[loc]]\n"
277 "casp x4, x5, x16, x17, [%[loc]]\n"
278 "casp x6, x7, x16, x17, [%[loc]]\n"
279 "stp x0, x1, [%[dst]]\n"
280 "stp x2, x3, [%[dst], #16]\n"
281 "stp x4, x5, [%[dst], #32]\n"
282 "stp x6, x7, [%[dst], #48]\n"
284 : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr)
285 : "memory", "x0", "x1", "x2", "x3", "x4", "x5", "x6",
292 "mov x16, %[wdata]\n"
293 "mov x17, %[wdata]\n"
294 "casp x0, x1, x16, x17, [%[loc]]\n"
295 "casp x2, x3, x16, x17, [%[loc]]\n"
296 "stp x0, x1, [%[dst]]\n"
297 "stp x2, x3, [%[dst], #16]\n"
299 : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr)
300 : "memory", "x0", "x1", "x2", "x3", "x16", "x17"
306 "mov x16, %[wdata]\n"
307 "mov x17, %[wdata]\n"
308 "casp x0, x1, x16, x17, [%[loc]]\n"
309 "stp x0, x1, [%[dst]]\n"
311 : [wdata] "r" (wdata), [dst] "r" (buf), [loc] "r" (addr)
312 : "memory", "x0", "x1", "x16", "x17"
316 buf[0] = roc_npa_aura_op_alloc(aura_handle, drop);
320 /* Pack the pointers */
321 for (i = 0, count = 0; i < num; i++)
323 buf[count++] = buf[i];
327 unsigned int i, count;
329 for (i = 0, count = 0; i < num; i++) {
330 buf[count] = roc_npa_aura_op_alloc(aura_handle, drop);
339 static inline unsigned int
340 roc_npa_aura_op_bulk_alloc(uint64_t aura_handle, uint64_t *buf,
341 unsigned int num, const int drop, const int partial)
343 unsigned int chunk, count, num_alloc;
347 chunk = (num >= ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS) ?
348 ROC_CN9K_NPA_BULK_ALLOC_MAX_PTRS :
349 plt_align32prevpow2(num);
352 roc_npa_aura_bulk_alloc(aura_handle, buf, chunk, drop);
358 if (unlikely(num_alloc != chunk))
362 /* If the requested number of pointers was not allocated and if partial
363 * alloc is not desired, then free allocated pointers.
365 if (unlikely(num != 0 && !partial)) {
366 roc_npa_aura_op_bulk_free(aura_handle, buf - count, count, 1);
374 struct plt_pci_device *pci_dev;
376 #define ROC_NPA_MEM_SZ (1 * 1024)
377 uint8_t reserved[ROC_NPA_MEM_SZ] __plt_cache_aligned;
378 } __plt_cache_aligned;
380 int __roc_api roc_npa_dev_init(struct roc_npa *roc_npa);
381 int __roc_api roc_npa_dev_fini(struct roc_npa *roc_npa);
384 int __roc_api roc_npa_pool_create(uint64_t *aura_handle, uint32_t block_size,
385 uint32_t block_count, struct npa_aura_s *aura,
386 struct npa_pool_s *pool);
387 int __roc_api roc_npa_aura_limit_modify(uint64_t aura_handle,
388 uint16_t aura_limit);
389 int __roc_api roc_npa_pool_destroy(uint64_t aura_handle);
390 int __roc_api roc_npa_pool_range_update_check(uint64_t aura_handle);
391 void __roc_api roc_npa_aura_op_range_set(uint64_t aura_handle,
396 int __roc_api roc_npa_ctx_dump(void);
397 int __roc_api roc_npa_dump(void);
399 #endif /* _ROC_NPA_H_ */