drivers/common/cpt/cpt_ucode.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Cavium, Inc
   3  */
   4
   5 #ifndef _CPT_UCODE_H_
   6 #define _CPT_UCODE_H_
   7 #include <stdbool.h>
   8
   9 #include "cpt_common.h"
  10 #include "cpt_hw_types.h"
  11 #include "cpt_mcode_defines.h"
  12
  13 /*
  14  * This file defines functions that are interfaces to microcode spec.
  15  *
  16  */
  17
  18 static uint8_t zuc_d[32] = {
  19         0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
  20         0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
  21         0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
  22         0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC
  23 };
  24
  25 static __rte_always_inline int
  26 cpt_is_algo_supported(struct rte_crypto_sym_xform *xform)
  27 {
  28         /*
  29          * Microcode only supports the following combination.
  30          * Encryption followed by authentication
  31          * Authentication followed by decryption
  32          */
  33         if (xform->next) {
  34                 if ((xform->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
  35                     (xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
  36                     (xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)) {
  37                         /* Unsupported as of now by microcode */
  38                         CPT_LOG_DP_ERR("Unsupported combination");
  39                         return -1;
  40                 }
  41                 if ((xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER) &&
  42                     (xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH) &&
  43                     (xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT)) {
  44                         /* For GMAC auth there is no cipher operation */
  45                         if (xform->aead.algo != RTE_CRYPTO_AEAD_AES_GCM ||
  46                             xform->next->auth.algo !=
  47                             RTE_CRYPTO_AUTH_AES_GMAC) {
  48                                 /* Unsupported as of now by microcode */
  49                                 CPT_LOG_DP_ERR("Unsupported combination");
  50                                 return -1;
  51                         }
  52                 }
  53         }
  54         return 0;
  55 }
  56
  57 static __rte_always_inline void
  58 gen_key_snow3g(uint8_t *ck, uint32_t *keyx)
  59 {
  60         int i, base;
  61
  62         for (i = 0; i < 4; i++) {
  63                 base = 4 * i;
  64                 keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
  65                         (ck[base + 2] << 8) | (ck[base + 3]);
  66                 keyx[3 - i] = rte_cpu_to_be_32(keyx[3 - i]);
  67         }
  68 }
  69
  70 static __rte_always_inline void
  71 cpt_fc_salt_update(void *ctx,
  72                    uint8_t *salt)
  73 {
  74         struct cpt_ctx *cpt_ctx = ctx;
  75         memcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);
  76 }
  77
  78 static __rte_always_inline int
  79 cpt_fc_ciph_validate_key_aes(uint16_t key_len)
  80 {
  81         switch (key_len) {
  82         case CPT_BYTE_16:
  83         case CPT_BYTE_24:
  84         case CPT_BYTE_32:
  85                 return 0;
  86         default:
  87                 return -1;
  88         }
  89 }
  90
  91 static __rte_always_inline int
  92 cpt_fc_ciph_validate_key(cipher_type_t type, struct cpt_ctx *cpt_ctx,
  93                 uint16_t key_len)
  94 {
  95         int fc_type = 0;
  96         switch (type) {
  97         case PASSTHROUGH:
  98                 fc_type = FC_GEN;
  99                 break;
 100         case DES3_CBC:
 101         case DES3_ECB:
 102                 fc_type = FC_GEN;
 103                 break;
 104         case AES_CBC:
 105         case AES_ECB:
 106         case AES_CFB:
 107         case AES_CTR:
 108         case AES_GCM:
 109                 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
 110                         return -1;
 111                 fc_type = FC_GEN;
 112                 break;
 113         case AES_XTS:
 114                 key_len = key_len / 2;
 115                 if (unlikely(key_len == CPT_BYTE_24)) {
 116                         CPT_LOG_DP_ERR("Invalid AES key len for XTS");
 117                         return -1;
 118                 }
 119                 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
 120                         return -1;
 121                 fc_type = FC_GEN;
 122                 break;
 123         case ZUC_EEA3:
 124         case SNOW3G_UEA2:
 125                 if (unlikely(key_len != 16))
 126                         return -1;
 127                 /* No support for AEAD yet */
 128                 if (unlikely(cpt_ctx->hash_type))
 129                         return -1;
 130                 fc_type = ZUC_SNOW3G;
 131                 break;
 132         case KASUMI_F8_CBC:
 133         case KASUMI_F8_ECB:
 134                 if (unlikely(key_len != 16))
 135                         return -1;
 136                 /* No support for AEAD yet */
 137                 if (unlikely(cpt_ctx->hash_type))
 138                         return -1;
 139                 fc_type = KASUMI;
 140                 break;
 141         default:
 142                 return -1;
 143         }
 144         return fc_type;
 145 }
 146
 147 static __rte_always_inline void
 148 cpt_fc_ciph_set_key_passthrough(struct cpt_ctx *cpt_ctx, mc_fc_context_t *fctx)
 149 {
 150         cpt_ctx->enc_cipher = 0;
 151         CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
 152 }
 153
 154 static __rte_always_inline void
 155 cpt_fc_ciph_set_key_set_aes_key_type(mc_fc_context_t *fctx, uint16_t key_len)
 156 {
 157         mc_aes_type_t aes_key_type = 0;
 158         switch (key_len) {
 159         case CPT_BYTE_16:
 160                 aes_key_type = AES_128_BIT;
 161                 break;
 162         case CPT_BYTE_24:
 163                 aes_key_type = AES_192_BIT;
 164                 break;
 165         case CPT_BYTE_32:
 166                 aes_key_type = AES_256_BIT;
 167                 break;
 168         default:
 169                 /* This should not happen */
 170                 CPT_LOG_DP_ERR("Invalid AES key len");
 171                 return;
 172         }
 173         CPT_P_ENC_CTRL(fctx).aes_key = aes_key_type;
 174 }
 175
 176 static __rte_always_inline void
 177 cpt_fc_ciph_set_key_snow3g_uea2(struct cpt_ctx *cpt_ctx, uint8_t *key,
 178                 uint16_t key_len)
 179 {
 180         uint32_t keyx[4];
 181         cpt_ctx->snow3g = 1;
 182         gen_key_snow3g(key, keyx);
 183         memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
 184         cpt_ctx->fc_type = ZUC_SNOW3G;
 185         cpt_ctx->zsk_flags = 0;
 186 }
 187
 188 static __rte_always_inline void
 189 cpt_fc_ciph_set_key_zuc_eea3(struct cpt_ctx *cpt_ctx, uint8_t *key,
 190                 uint16_t key_len)
 191 {
 192         cpt_ctx->snow3g = 0;
 193         memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
 194         memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
 195         cpt_ctx->fc_type = ZUC_SNOW3G;
 196         cpt_ctx->zsk_flags = 0;
 197 }
 198
 199 static __rte_always_inline void
 200 cpt_fc_ciph_set_key_kasumi_f8_ecb(struct cpt_ctx *cpt_ctx, uint8_t *key,
 201                 uint16_t key_len)
 202 {
 203         cpt_ctx->k_ecb = 1;
 204         memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
 205         cpt_ctx->zsk_flags = 0;
 206         cpt_ctx->fc_type = KASUMI;
 207 }
 208
 209 static __rte_always_inline void
 210 cpt_fc_ciph_set_key_kasumi_f8_cbc(struct cpt_ctx *cpt_ctx, uint8_t *key,
 211                 uint16_t key_len)
 212 {
 213         memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
 214         cpt_ctx->zsk_flags = 0;
 215         cpt_ctx->fc_type = KASUMI;
 216 }
 217
 218 static __rte_always_inline int
 219 cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, uint8_t *key,
 220                     uint16_t key_len, uint8_t *salt)
 221 {
 222         struct cpt_ctx *cpt_ctx = ctx;
 223         mc_fc_context_t *fctx = &cpt_ctx->fctx;
 224         uint64_t *ctrl_flags = NULL;
 225         int fc_type;
 226
 227         /* Validate key before proceeding */
 228         fc_type = cpt_fc_ciph_validate_key(type, cpt_ctx, key_len);
 229         if (unlikely(fc_type == -1))
 230                 return -1;
 231
 232         if (fc_type == FC_GEN) {
 233                 cpt_ctx->fc_type = FC_GEN;
 234                 ctrl_flags = (uint64_t *)&(fctx->enc.enc_ctrl.flags);
 235                 *ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
 236                 /*
 237                  * We need to always say IV is from DPTR as user can
 238                  * sometimes iverride IV per operation.
 239                  */
 240                 CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_DPTR;
 241         }
 242
 243         switch (type) {
 244         case PASSTHROUGH:
 245                 cpt_fc_ciph_set_key_passthrough(cpt_ctx, fctx);
 246                 goto fc_success;
 247         case DES3_CBC:
 248                 /* CPT performs DES using 3DES with the 8B DES-key
 249                  * replicated 2 more times to match the 24B 3DES-key.
 250                  * Eg. If org. key is "0x0a 0x0b", then new key is
 251                  * "0x0a 0x0b 0x0a 0x0b 0x0a 0x0b"
 252                  */
 253                 if (key_len == 8) {
 254                         /* Skipping the first 8B as it will be copied
 255                          * in the regular code flow
 256                          */
 257                         memcpy(fctx->enc.encr_key+key_len, key, key_len);
 258                         memcpy(fctx->enc.encr_key+2*key_len, key, key_len);
 259                 }
 260                 break;
 261         case DES3_ECB:
 262                 /* For DES3_ECB IV need to be from CTX. */
 263                 CPT_P_ENC_CTRL(fctx).iv_source = CPT_FROM_CTX;
 264                 break;
 265         case AES_CBC:
 266         case AES_ECB:
 267         case AES_CFB:
 268         case AES_CTR:
 269                 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 270                 break;
 271         case AES_GCM:
 272                 /* Even though iv source is from dptr,
 273                  * aes_gcm salt is taken from ctx
 274                  */
 275                 if (salt) {
 276                         memcpy(fctx->enc.encr_iv, salt, 4);
 277                         /* Assuming it was just salt update
 278                          * and nothing else
 279                          */
 280                         if (!key)
 281                                 goto fc_success;
 282                 }
 283                 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 284                 break;
 285         case AES_XTS:
 286                 key_len = key_len / 2;
 287                 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 288
 289                 /* Copy key2 for XTS into ipad */
 290                 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
 291                 memcpy(fctx->hmac.ipad, &key[key_len], key_len);
 292                 break;
 293         case SNOW3G_UEA2:
 294                 cpt_fc_ciph_set_key_snow3g_uea2(cpt_ctx, key, key_len);
 295                 goto success;
 296         case ZUC_EEA3:
 297                 cpt_fc_ciph_set_key_zuc_eea3(cpt_ctx, key, key_len);
 298                 goto success;
 299         case KASUMI_F8_ECB:
 300                 cpt_fc_ciph_set_key_kasumi_f8_ecb(cpt_ctx, key, key_len);
 301                 goto success;
 302         case KASUMI_F8_CBC:
 303                 cpt_fc_ciph_set_key_kasumi_f8_cbc(cpt_ctx, key, key_len);
 304                 goto success;
 305         default:
 306                 break;
 307         }
 308
 309         /* Only for FC_GEN case */
 310
 311         /* For GMAC auth, cipher must be NULL */
 312         if (cpt_ctx->hash_type != GMAC_TYPE)
 313                 CPT_P_ENC_CTRL(fctx).enc_cipher = type;
 314
 315         memcpy(fctx->enc.encr_key, key, key_len);
 316
 317 fc_success:
 318         *ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
 319
 320 success:
 321         cpt_ctx->enc_cipher = type;
 322
 323         return 0;
 324 }
 325
 326 static __rte_always_inline uint32_t
 327 fill_sg_comp(sg_comp_t *list,
 328              uint32_t i,
 329              phys_addr_t dma_addr,
 330              uint32_t size)
 331 {
 332         sg_comp_t *to = &list[i>>2];
 333
 334         to->u.s.len[i%4] = rte_cpu_to_be_16(size);
 335         to->ptr[i%4] = rte_cpu_to_be_64(dma_addr);
 336         i++;
 337         return i;
 338 }
 339
 340 static __rte_always_inline uint32_t
 341 fill_sg_comp_from_buf(sg_comp_t *list,
 342                       uint32_t i,
 343                       buf_ptr_t *from)
 344 {
 345         sg_comp_t *to = &list[i>>2];
 346
 347         to->u.s.len[i%4] = rte_cpu_to_be_16(from->size);
 348         to->ptr[i%4] = rte_cpu_to_be_64(from->dma_addr);
 349         i++;
 350         return i;
 351 }
 352
 353 static __rte_always_inline uint32_t
 354 fill_sg_comp_from_buf_min(sg_comp_t *list,
 355                           uint32_t i,
 356                           buf_ptr_t *from,
 357                           uint32_t *psize)
 358 {
 359         sg_comp_t *to = &list[i >> 2];
 360         uint32_t size = *psize;
 361         uint32_t e_len;
 362
 363         e_len = (size > from->size) ? from->size : size;
 364         to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 365         to->ptr[i % 4] = rte_cpu_to_be_64(from->dma_addr);
 366         *psize -= e_len;
 367         i++;
 368         return i;
 369 }
 370
 371 /*
 372  * This fills the MC expected SGIO list
 373  * from IOV given by user.
 374  */
 375 static __rte_always_inline uint32_t
 376 fill_sg_comp_from_iov(sg_comp_t *list,
 377                       uint32_t i,
 378                       iov_ptr_t *from, uint32_t from_offset,
 379                       uint32_t *psize, buf_ptr_t *extra_buf,
 380                       uint32_t extra_offset)
 381 {
 382         int32_t j;
 383         uint32_t extra_len = extra_buf ? extra_buf->size : 0;
 384         uint32_t size = *psize - extra_len;
 385         buf_ptr_t *bufs;
 386
 387         bufs = from->bufs;
 388         for (j = 0; (j < from->buf_cnt) && size; j++) {
 389                 phys_addr_t e_dma_addr;
 390                 uint32_t e_len;
 391                 sg_comp_t *to = &list[i >> 2];
 392
 393                 if (!bufs[j].size)
 394                         continue;
 395
 396                 if (unlikely(from_offset)) {
 397                         if (from_offset >= bufs[j].size) {
 398                                 from_offset -= bufs[j].size;
 399                                 continue;
 400                         }
 401                         e_dma_addr = bufs[j].dma_addr + from_offset;
 402                         e_len = (size > (bufs[j].size - from_offset)) ?
 403                                 (bufs[j].size - from_offset) : size;
 404                         from_offset = 0;
 405                 } else {
 406                         e_dma_addr = bufs[j].dma_addr;
 407                         e_len = (size > bufs[j].size) ?
 408                                 bufs[j].size : size;
 409                 }
 410
 411                 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 412                 to->ptr[i % 4] = rte_cpu_to_be_64(e_dma_addr);
 413
 414                 if (extra_len && (e_len >= extra_offset)) {
 415                         /* Break the data at given offset */
 416                         uint32_t next_len = e_len - extra_offset;
 417                         phys_addr_t next_dma = e_dma_addr + extra_offset;
 418
 419                         if (!extra_offset) {
 420                                 i--;
 421                         } else {
 422                                 e_len = extra_offset;
 423                                 size -= e_len;
 424                                 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 425                         }
 426
 427                         /* Insert extra data ptr */
 428                         if (extra_len) {
 429                                 i++;
 430                                 to = &list[i >> 2];
 431                                 to->u.s.len[i % 4] =
 432                                         rte_cpu_to_be_16(extra_buf->size);
 433                                 to->ptr[i % 4] =
 434                                         rte_cpu_to_be_64(extra_buf->dma_addr);
 435
 436                                 /* size already decremented by extra len */
 437                         }
 438
 439                         /* insert the rest of the data */
 440                         if (next_len) {
 441                                 i++;
 442                                 to = &list[i >> 2];
 443                                 to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
 444                                 to->ptr[i % 4] = rte_cpu_to_be_64(next_dma);
 445                                 size -= next_len;
 446                         }
 447                         extra_len = 0;
 448
 449                 } else {
 450                         size -= e_len;
 451                 }
 452                 if (extra_offset)
 453                         extra_offset -= size;
 454                 i++;
 455         }
 456
 457         *psize = size;
 458         return (uint32_t)i;
 459 }
 460
 461 static __rte_always_inline void
 462 cpt_digest_gen_prep(uint32_t flags,
 463                     uint64_t d_lens,
 464                     digest_params_t *params,
 465                     void *op,
 466                     void **prep_req)
 467 {
 468         struct cpt_request_info *req;
 469         uint32_t size, i;
 470         int32_t m_size;
 471         uint16_t data_len, mac_len, key_len;
 472         auth_type_t hash_type;
 473         buf_ptr_t *meta_p;
 474         struct cpt_ctx *ctx;
 475         sg_comp_t *gather_comp;
 476         sg_comp_t *scatter_comp;
 477         uint8_t *in_buffer;
 478         uint32_t g_size_bytes, s_size_bytes;
 479         uint64_t dptr_dma, rptr_dma;
 480         vq_cmd_word0_t vq_cmd_w0;
 481         vq_cmd_word3_t vq_cmd_w3;
 482         void *c_vaddr, *m_vaddr;
 483         uint64_t c_dma, m_dma;
 484         opcode_info_t opcode;
 485
 486         ctx = params->ctx_buf.vaddr;
 487         meta_p = &params->meta_buf;
 488
 489         m_vaddr = meta_p->vaddr;
 490         m_dma = meta_p->dma_addr;
 491         m_size = meta_p->size;
 492
 493         /*
 494          * Save initial space that followed app data for completion code &
 495          * alternate completion code to fall in same cache line as app data
 496          */
 497         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
 498         m_dma += COMPLETION_CODE_SIZE;
 499         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
 500                 (uint8_t *)m_vaddr;
 501         c_vaddr = (uint8_t *)m_vaddr + size;
 502         c_dma = m_dma + size;
 503         size += sizeof(cpt_res_s_t);
 504
 505         m_vaddr = (uint8_t *)m_vaddr + size;
 506         m_dma += size;
 507         m_size -= size;
 508
 509         req = m_vaddr;
 510
 511         size = sizeof(struct cpt_request_info);
 512         m_vaddr = (uint8_t *)m_vaddr + size;
 513         m_dma += size;
 514         m_size -= size;
 515
 516         hash_type = ctx->hash_type;
 517         mac_len = ctx->mac_len;
 518         key_len = ctx->auth_key_len;
 519         data_len = AUTH_DLEN(d_lens);
 520
 521         /*GP op header */
 522         vq_cmd_w0.u64 = 0;
 523         vq_cmd_w0.s.param2 = ((uint16_t)hash_type << 8);
 524         if (ctx->hmac) {
 525                 opcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;
 526                 vq_cmd_w0.s.param1 = key_len;
 527                 vq_cmd_w0.s.dlen = data_len + ROUNDUP8(key_len);
 528         } else {
 529                 opcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;
 530                 vq_cmd_w0.s.param1 = 0;
 531                 vq_cmd_w0.s.dlen = data_len;
 532         }
 533
 534         opcode.s.minor = 0;
 535
 536         /* Null auth only case enters the if */
 537         if (unlikely(!hash_type && !ctx->enc_cipher)) {
 538                 opcode.s.major = CPT_MAJOR_OP_MISC;
 539                 /* Minor op is passthrough */
 540                 opcode.s.minor = 0x03;
 541                 /* Send out completion code only */
 542                 vq_cmd_w0.s.param2 = 0x1;
 543         }
 544
 545         vq_cmd_w0.s.opcode = opcode.flags;
 546
 547         /* DPTR has SG list */
 548         in_buffer = m_vaddr;
 549         dptr_dma = m_dma;
 550
 551         ((uint16_t *)in_buffer)[0] = 0;
 552         ((uint16_t *)in_buffer)[1] = 0;
 553
 554         /* TODO Add error check if space will be sufficient */
 555         gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
 556
 557         /*
 558          * Input gather list
 559          */
 560
 561         i = 0;
 562
 563         if (ctx->hmac) {
 564                 uint64_t k_dma = params->ctx_buf.dma_addr +
 565                         offsetof(struct cpt_ctx, auth_key);
 566                 /* Key */
 567                 i = fill_sg_comp(gather_comp, i, k_dma, ROUNDUP8(key_len));
 568         }
 569
 570         /* input data */
 571         size = data_len;
 572         if (size) {
 573                 i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,
 574                                           0, &size, NULL, 0);
 575                 if (unlikely(size)) {
 576                         CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short"
 577                                          " by %dB", size);
 578                         return;
 579                 }
 580         } else {
 581                 /*
 582                  * Looks like we need to support zero data
 583                  * gather ptr in case of hash & hmac
 584                  */
 585                 i++;
 586         }
 587         ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
 588         g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 589
 590         /*
 591          * Output Gather list
 592          */
 593
 594         i = 0;
 595         scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
 596
 597         if (flags & VALID_MAC_BUF) {
 598                 if (unlikely(params->mac_buf.size < mac_len)) {
 599                         CPT_LOG_DP_ERR("Insufficient MAC size");
 600                         return;
 601                 }
 602
 603                 size = mac_len;
 604                 i = fill_sg_comp_from_buf_min(scatter_comp, i,
 605                                               &params->mac_buf, &size);
 606         } else {
 607                 size = mac_len;
 608                 i = fill_sg_comp_from_iov(scatter_comp, i,
 609                                           params->src_iov, data_len,
 610                                           &size, NULL, 0);
 611                 if (unlikely(size)) {
 612                         CPT_LOG_DP_ERR("Insufficient dst IOV size, short by"
 613                                        " %dB", size);
 614                         return;
 615                 }
 616         }
 617
 618         ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
 619         s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 620
 621         size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
 622
 623         /* This is DPTR len incase of SG mode */
 624         vq_cmd_w0.s.dlen = size;
 625
 626         m_vaddr = (uint8_t *)m_vaddr + size;
 627         m_dma += size;
 628         m_size -= size;
 629
 630         /* cpt alternate completion address saved earlier */
 631         req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
 632         *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
 633         rptr_dma = c_dma - 8;
 634
 635         req->ist.ei1 = dptr_dma;
 636         req->ist.ei2 = rptr_dma;
 637
 638         /* vq command w3 */
 639         vq_cmd_w3.u64 = 0;
 640
 641         /* 16 byte aligned cpt res address */
 642         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
 643         *req->completion_addr = COMPLETION_CODE_INIT;
 644         req->comp_baddr  = c_dma;
 645
 646         /* Fill microcode part of instruction */
 647         req->ist.ei0 = vq_cmd_w0.u64;
 648         req->ist.ei3 = vq_cmd_w3.u64;
 649
 650         req->op = op;
 651
 652         *prep_req = req;
 653         return;
 654 }
 655
 656 static __rte_always_inline void
 657 cpt_enc_hmac_prep(uint32_t flags,
 658                   uint64_t d_offs,
 659                   uint64_t d_lens,
 660                   fc_params_t *fc_params,
 661                   void *op,
 662                   void **prep_req)
 663 {
 664         uint32_t iv_offset = 0;
 665         int32_t inputlen, outputlen, enc_dlen, auth_dlen;
 666         struct cpt_ctx *cpt_ctx;
 667         uint32_t cipher_type, hash_type;
 668         uint32_t mac_len, size;
 669         uint8_t iv_len = 16;
 670         struct cpt_request_info *req;
 671         buf_ptr_t *meta_p, *aad_buf = NULL;
 672         uint32_t encr_offset, auth_offset;
 673         uint32_t encr_data_len, auth_data_len, aad_len = 0;
 674         uint32_t passthrough_len = 0;
 675         void *m_vaddr, *offset_vaddr;
 676         uint64_t m_dma, offset_dma, ctx_dma;
 677         vq_cmd_word0_t vq_cmd_w0;
 678         vq_cmd_word3_t vq_cmd_w3;
 679         void *c_vaddr;
 680         uint64_t c_dma;
 681         int32_t m_size;
 682         opcode_info_t opcode;
 683
 684         meta_p = &fc_params->meta_buf;
 685         m_vaddr = meta_p->vaddr;
 686         m_dma = meta_p->dma_addr;
 687         m_size = meta_p->size;
 688
 689         encr_offset = ENCR_OFFSET(d_offs);
 690         auth_offset = AUTH_OFFSET(d_offs);
 691         encr_data_len = ENCR_DLEN(d_lens);
 692         auth_data_len = AUTH_DLEN(d_lens);
 693         if (unlikely(flags & VALID_AAD_BUF)) {
 694                 /*
 695                  * We dont support both aad
 696                  * and auth data separately
 697                  */
 698                 auth_data_len = 0;
 699                 auth_offset = 0;
 700                 aad_len = fc_params->aad_buf.size;
 701                 aad_buf = &fc_params->aad_buf;
 702         }
 703         cpt_ctx = fc_params->ctx_buf.vaddr;
 704         cipher_type = cpt_ctx->enc_cipher;
 705         hash_type = cpt_ctx->hash_type;
 706         mac_len = cpt_ctx->mac_len;
 707
 708         /*
 709          * Save initial space that followed app data for completion code &
 710          * alternate completion code to fall in same cache line as app data
 711          */
 712         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
 713         m_dma += COMPLETION_CODE_SIZE;
 714         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
 715                 (uint8_t *)m_vaddr;
 716
 717         c_vaddr = (uint8_t *)m_vaddr + size;
 718         c_dma = m_dma + size;
 719         size += sizeof(cpt_res_s_t);
 720
 721         m_vaddr = (uint8_t *)m_vaddr + size;
 722         m_dma += size;
 723         m_size -= size;
 724
 725         /* start cpt request info struct at 8 byte boundary */
 726         size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
 727                 (uint8_t *)m_vaddr;
 728
 729         req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
 730
 731         size += sizeof(struct cpt_request_info);
 732         m_vaddr = (uint8_t *)m_vaddr + size;
 733         m_dma += size;
 734         m_size -= size;
 735
 736         if (hash_type == GMAC_TYPE)
 737                 encr_data_len = 0;
 738
 739         if (unlikely(!(flags & VALID_IV_BUF))) {
 740                 iv_len = 0;
 741                 iv_offset = ENCR_IV_OFFSET(d_offs);
 742         }
 743
 744         if (unlikely(flags & VALID_AAD_BUF)) {
 745                 /*
 746                  * When AAD is given, data above encr_offset is pass through
 747                  * Since AAD is given as separate pointer and not as offset,
 748                  * this is a special case as we need to fragment input data
 749                  * into passthrough + encr_data and then insert AAD in between.
 750                  */
 751                 if (hash_type != GMAC_TYPE) {
 752                         passthrough_len = encr_offset;
 753                         auth_offset = passthrough_len + iv_len;
 754                         encr_offset = passthrough_len + aad_len + iv_len;
 755                         auth_data_len = aad_len + encr_data_len;
 756                 } else {
 757                         passthrough_len = 16 + aad_len;
 758                         auth_offset = passthrough_len + iv_len;
 759                         auth_data_len = aad_len;
 760                 }
 761         } else {
 762                 encr_offset += iv_len;
 763                 auth_offset += iv_len;
 764         }
 765
 766         /* Encryption */
 767         opcode.s.major = CPT_MAJOR_OP_FC;
 768         opcode.s.minor = 0;
 769
 770         auth_dlen = auth_offset + auth_data_len;
 771         enc_dlen = encr_data_len + encr_offset;
 772         if (unlikely(encr_data_len & 0xf)) {
 773                 if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
 774                         enc_dlen = ROUNDUP8(encr_data_len) + encr_offset;
 775                 else if (likely((cipher_type == AES_CBC) ||
 776                                 (cipher_type == AES_ECB)))
 777                         enc_dlen = ROUNDUP16(encr_data_len) + encr_offset;
 778         }
 779
 780         if (unlikely(hash_type == GMAC_TYPE)) {
 781                 encr_offset = auth_dlen;
 782                 enc_dlen = 0;
 783         }
 784
 785         if (unlikely(auth_dlen > enc_dlen)) {
 786                 inputlen = auth_dlen;
 787                 outputlen = auth_dlen + mac_len;
 788         } else {
 789                 inputlen = enc_dlen;
 790                 outputlen = enc_dlen + mac_len;
 791         }
 792
 793         /* GP op header */
 794         vq_cmd_w0.u64 = 0;
 795         vq_cmd_w0.s.param1 = encr_data_len;
 796         vq_cmd_w0.s.param2 = auth_data_len;
 797         /*
 798          * In 83XX since we have a limitation of
 799          * IV & Offset control word not part of instruction
 800          * and need to be part of Data Buffer, we check if
 801          * head room is there and then only do the Direct mode processing
 802          */
 803         if (likely((flags & SINGLE_BUF_INPLACE) &&
 804                    (flags & SINGLE_BUF_HEADTAILROOM))) {
 805                 void *dm_vaddr = fc_params->bufs[0].vaddr;
 806                 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
 807                 /*
 808                  * This flag indicates that there is 24 bytes head room and
 809                  * 8 bytes tail room available, so that we get to do
 810                  * DIRECT MODE with limitation
 811                  */
 812
 813                 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
 814                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
 815
 816                 /* DPTR */
 817                 req->ist.ei1 = offset_dma;
 818                 /* RPTR should just exclude offset control word */
 819                 req->ist.ei2 = dm_dma_addr - iv_len;
 820                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
 821                                                     + outputlen - iv_len);
 822
 823                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
 824
 825                 vq_cmd_w0.s.opcode = opcode.flags;
 826
 827                 if (likely(iv_len)) {
 828                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
 829                                                       + OFF_CTRL_LEN);
 830                         uint64_t *src = fc_params->iv_buf;
 831                         dest[0] = src[0];
 832                         dest[1] = src[1];
 833                 }
 834
 835                 *(uint64_t *)offset_vaddr =
 836                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
 837                                 ((uint64_t)iv_offset << 8) |
 838                                 ((uint64_t)auth_offset));
 839
 840         } else {
 841                 uint32_t i, g_size_bytes, s_size_bytes;
 842                 uint64_t dptr_dma, rptr_dma;
 843                 sg_comp_t *gather_comp;
 844                 sg_comp_t *scatter_comp;
 845                 uint8_t *in_buffer;
 846
 847                 /* This falls under strict SG mode */
 848                 offset_vaddr = m_vaddr;
 849                 offset_dma = m_dma;
 850                 size = OFF_CTRL_LEN + iv_len;
 851
 852                 m_vaddr = (uint8_t *)m_vaddr + size;
 853                 m_dma += size;
 854                 m_size -= size;
 855
 856                 opcode.s.major |= CPT_DMA_MODE;
 857
 858                 vq_cmd_w0.s.opcode = opcode.flags;
 859
 860                 if (likely(iv_len)) {
 861                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
 862                                                       + OFF_CTRL_LEN);
 863                         uint64_t *src = fc_params->iv_buf;
 864                         dest[0] = src[0];
 865                         dest[1] = src[1];
 866                 }
 867
 868                 *(uint64_t *)offset_vaddr =
 869                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
 870                                 ((uint64_t)iv_offset << 8) |
 871                                 ((uint64_t)auth_offset));
 872
 873                 /* DPTR has SG list */
 874                 in_buffer = m_vaddr;
 875                 dptr_dma = m_dma;
 876
 877                 ((uint16_t *)in_buffer)[0] = 0;
 878                 ((uint16_t *)in_buffer)[1] = 0;
 879
 880                 /* TODO Add error check if space will be sufficient */
 881                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
 882
 883                 /*
 884                  * Input Gather List
 885                  */
 886
 887                 i = 0;
 888
 889                 /* Offset control word that includes iv */
 890                 i = fill_sg_comp(gather_comp, i, offset_dma,
 891                                  OFF_CTRL_LEN + iv_len);
 892
 893                 /* Add input data */
 894                 size = inputlen - iv_len;
 895                 if (likely(size)) {
 896                         uint32_t aad_offset = aad_len ? passthrough_len : 0;
 897
 898                         if (unlikely(flags & SINGLE_BUF_INPLACE)) {
 899                                 i = fill_sg_comp_from_buf_min(gather_comp, i,
 900                                                               fc_params->bufs,
 901                                                               &size);
 902                         } else {
 903                                 i = fill_sg_comp_from_iov(gather_comp, i,
 904                                                           fc_params->src_iov,
 905                                                           0, &size,
 906                                                           aad_buf, aad_offset);
 907                         }
 908
 909                         if (unlikely(size)) {
 910                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
 911                                                " size %d needed", size);
 912                                 return;
 913                         }
 914                 }
 915                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
 916                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 917
 918                 /*
 919                  * Output Scatter list
 920                  */
 921                 i = 0;
 922                 scatter_comp =
 923                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
 924
 925                 /* Add IV */
 926                 if (likely(iv_len)) {
 927                         i = fill_sg_comp(scatter_comp, i,
 928                                          offset_dma + OFF_CTRL_LEN,
 929                                          iv_len);
 930                 }
 931
 932                 /* output data or output data + digest*/
 933                 if (unlikely(flags & VALID_MAC_BUF)) {
 934                         size = outputlen - iv_len - mac_len;
 935                         if (size) {
 936                                 uint32_t aad_offset =
 937                                         aad_len ? passthrough_len : 0;
 938
 939                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
 940                                         i = fill_sg_comp_from_buf_min(
 941                                                         scatter_comp,
 942                                                         i,
 943                                                         fc_params->bufs,
 944                                                         &size);
 945                                 } else {
 946                                         i = fill_sg_comp_from_iov(scatter_comp,
 947                                                         i,
 948                                                         fc_params->dst_iov,
 949                                                         0,
 950                                                         &size,
 951                                                         aad_buf,
 952                                                         aad_offset);
 953                                 }
 954                                 if (unlikely(size)) {
 955                                         CPT_LOG_DP_ERR("Insufficient buffer"
 956                                                        " space, size %d needed",
 957                                                        size);
 958                                         return;
 959                                 }
 960                         }
 961                         /* mac_data */
 962                         if (mac_len) {
 963                                 i = fill_sg_comp_from_buf(scatter_comp, i,
 964                                                           &fc_params->mac_buf);
 965                         }
 966                 } else {
 967                         /* Output including mac */
 968                         size = outputlen - iv_len;
 969                         if (likely(size)) {
 970                                 uint32_t aad_offset =
 971                                         aad_len ? passthrough_len : 0;
 972
 973                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
 974                                         i = fill_sg_comp_from_buf_min(
 975                                                         scatter_comp,
 976                                                         i,
 977                                                         fc_params->bufs,
 978                                                         &size);
 979                                 } else {
 980                                         i = fill_sg_comp_from_iov(scatter_comp,
 981                                                         i,
 982                                                         fc_params->dst_iov,
 983                                                         0,
 984                                                         &size,
 985                                                         aad_buf,
 986                                                         aad_offset);
 987                                 }
 988                                 if (unlikely(size)) {
 989                                         CPT_LOG_DP_ERR("Insufficient buffer"
 990                                                        " space, size %d needed",
 991                                                        size);
 992                                         return;
 993                                 }
 994                         }
 995                 }
 996                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
 997                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 998
 999                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1000
1001                 /* This is DPTR len incase of SG mode */
1002                 vq_cmd_w0.s.dlen = size;
1003
1004                 m_vaddr = (uint8_t *)m_vaddr + size;
1005                 m_dma += size;
1006                 m_size -= size;
1007
1008                 /* cpt alternate completion address saved earlier */
1009                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1010                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1011                 rptr_dma = c_dma - 8;
1012
1013                 req->ist.ei1 = dptr_dma;
1014                 req->ist.ei2 = rptr_dma;
1015         }
1016
1017         ctx_dma = fc_params->ctx_buf.dma_addr +
1018                 offsetof(struct cpt_ctx, fctx);
1019         /* vq command w3 */
1020         vq_cmd_w3.u64 = 0;
1021         vq_cmd_w3.s.grp = 0;
1022         vq_cmd_w3.s.cptr = ctx_dma;
1023
1024         /* 16 byte aligned cpt res address */
1025         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1026         *req->completion_addr = COMPLETION_CODE_INIT;
1027         req->comp_baddr  = c_dma;
1028
1029         /* Fill microcode part of instruction */
1030         req->ist.ei0 = vq_cmd_w0.u64;
1031         req->ist.ei3 = vq_cmd_w3.u64;
1032
1033         req->op  = op;
1034
1035         *prep_req = req;
1036         return;
1037 }
1038
1039 static __rte_always_inline void
1040 cpt_dec_hmac_prep(uint32_t flags,
1041                   uint64_t d_offs,
1042                   uint64_t d_lens,
1043                   fc_params_t *fc_params,
1044                   void *op,
1045                   void **prep_req)
1046 {
1047         uint32_t iv_offset = 0, size;
1048         int32_t inputlen, outputlen, enc_dlen, auth_dlen;
1049         struct cpt_ctx *cpt_ctx;
1050         int32_t hash_type, mac_len, m_size;
1051         uint8_t iv_len = 16;
1052         struct cpt_request_info *req;
1053         buf_ptr_t *meta_p, *aad_buf = NULL;
1054         uint32_t encr_offset, auth_offset;
1055         uint32_t encr_data_len, auth_data_len, aad_len = 0;
1056         uint32_t passthrough_len = 0;
1057         void *m_vaddr, *offset_vaddr;
1058         uint64_t m_dma, offset_dma, ctx_dma;
1059         opcode_info_t opcode;
1060         vq_cmd_word0_t vq_cmd_w0;
1061         vq_cmd_word3_t vq_cmd_w3;
1062         void *c_vaddr;
1063         uint64_t c_dma;
1064
1065         meta_p = &fc_params->meta_buf;
1066         m_vaddr = meta_p->vaddr;
1067         m_dma = meta_p->dma_addr;
1068         m_size = meta_p->size;
1069
1070         encr_offset = ENCR_OFFSET(d_offs);
1071         auth_offset = AUTH_OFFSET(d_offs);
1072         encr_data_len = ENCR_DLEN(d_lens);
1073         auth_data_len = AUTH_DLEN(d_lens);
1074
1075         if (unlikely(flags & VALID_AAD_BUF)) {
1076                 /*
1077                  * We dont support both aad
1078                  * and auth data separately
1079                  */
1080                 auth_data_len = 0;
1081                 auth_offset = 0;
1082                 aad_len = fc_params->aad_buf.size;
1083                 aad_buf = &fc_params->aad_buf;
1084         }
1085
1086         cpt_ctx = fc_params->ctx_buf.vaddr;
1087         hash_type = cpt_ctx->hash_type;
1088         mac_len = cpt_ctx->mac_len;
1089
1090         if (hash_type == GMAC_TYPE)
1091                 encr_data_len = 0;
1092
1093         if (unlikely(!(flags & VALID_IV_BUF))) {
1094                 iv_len = 0;
1095                 iv_offset = ENCR_IV_OFFSET(d_offs);
1096         }
1097
1098         if (unlikely(flags & VALID_AAD_BUF)) {
1099                 /*
1100                  * When AAD is given, data above encr_offset is pass through
1101                  * Since AAD is given as separate pointer and not as offset,
1102                  * this is a special case as we need to fragment input data
1103                  * into passthrough + encr_data and then insert AAD in between.
1104                  */
1105                 if (hash_type != GMAC_TYPE) {
1106                         passthrough_len = encr_offset;
1107                         auth_offset = passthrough_len + iv_len;
1108                         encr_offset = passthrough_len + aad_len + iv_len;
1109                         auth_data_len = aad_len + encr_data_len;
1110                 } else {
1111                         passthrough_len = 16 + aad_len;
1112                         auth_offset = passthrough_len + iv_len;
1113                         auth_data_len = aad_len;
1114                 }
1115         } else {
1116                 encr_offset += iv_len;
1117                 auth_offset += iv_len;
1118         }
1119
1120         /*
1121          * Save initial space that followed app data for completion code &
1122          * alternate completion code to fall in same cache line as app data
1123          */
1124         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1125         m_dma += COMPLETION_CODE_SIZE;
1126         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1127                (uint8_t *)m_vaddr;
1128         c_vaddr = (uint8_t *)m_vaddr + size;
1129         c_dma = m_dma + size;
1130         size += sizeof(cpt_res_s_t);
1131
1132         m_vaddr = (uint8_t *)m_vaddr + size;
1133         m_dma += size;
1134         m_size -= size;
1135
1136         /* start cpt request info structure at 8 byte alignment */
1137         size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
1138                 (uint8_t *)m_vaddr;
1139
1140         req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
1141
1142         size += sizeof(struct cpt_request_info);
1143         m_vaddr = (uint8_t *)m_vaddr + size;
1144         m_dma += size;
1145         m_size -= size;
1146
1147         /* Decryption */
1148         opcode.s.major = CPT_MAJOR_OP_FC;
1149         opcode.s.minor = 1;
1150
1151         enc_dlen = encr_offset + encr_data_len;
1152         auth_dlen = auth_offset + auth_data_len;
1153
1154         if (auth_dlen > enc_dlen) {
1155                 inputlen = auth_dlen + mac_len;
1156                 outputlen = auth_dlen;
1157         } else {
1158                 inputlen = enc_dlen + mac_len;
1159                 outputlen = enc_dlen;
1160         }
1161
1162         if (hash_type == GMAC_TYPE)
1163                 encr_offset = inputlen;
1164
1165         vq_cmd_w0.u64 = 0;
1166         vq_cmd_w0.s.param1 = encr_data_len;
1167         vq_cmd_w0.s.param2 = auth_data_len;
1168
1169         /*
1170          * In 83XX since we have a limitation of
1171          * IV & Offset control word not part of instruction
1172          * and need to be part of Data Buffer, we check if
1173          * head room is there and then only do the Direct mode processing
1174          */
1175         if (likely((flags & SINGLE_BUF_INPLACE) &&
1176                    (flags & SINGLE_BUF_HEADTAILROOM))) {
1177                 void *dm_vaddr = fc_params->bufs[0].vaddr;
1178                 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
1179                 /*
1180                  * This flag indicates that there is 24 bytes head room and
1181                  * 8 bytes tail room available, so that we get to do
1182                  * DIRECT MODE with limitation
1183                  */
1184
1185                 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
1186                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1187                 req->ist.ei1 = offset_dma;
1188
1189                 /* RPTR should just exclude offset control word */
1190                 req->ist.ei2 = dm_dma_addr - iv_len;
1191
1192                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr +
1193                                         outputlen - iv_len);
1194                 /* since this is decryption,
1195                  * don't touch the content of
1196                  * alternate ccode space as it contains
1197                  * hmac.
1198                  */
1199
1200                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1201
1202                 vq_cmd_w0.s.opcode = opcode.flags;
1203
1204                 if (likely(iv_len)) {
1205                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1206                                                       OFF_CTRL_LEN);
1207                         uint64_t *src = fc_params->iv_buf;
1208                         dest[0] = src[0];
1209                         dest[1] = src[1];
1210                 }
1211
1212                 *(uint64_t *)offset_vaddr =
1213                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1214                                 ((uint64_t)iv_offset << 8) |
1215                                 ((uint64_t)auth_offset));
1216
1217         } else {
1218                 uint64_t dptr_dma, rptr_dma;
1219                 uint32_t g_size_bytes, s_size_bytes;
1220                 sg_comp_t *gather_comp;
1221                 sg_comp_t *scatter_comp;
1222                 uint8_t *in_buffer;
1223                 uint8_t i = 0;
1224
1225                 /* This falls under strict SG mode */
1226                 offset_vaddr = m_vaddr;
1227                 offset_dma = m_dma;
1228                 size = OFF_CTRL_LEN + iv_len;
1229
1230                 m_vaddr = (uint8_t *)m_vaddr + size;
1231                 m_dma += size;
1232                 m_size -= size;
1233
1234                 opcode.s.major |= CPT_DMA_MODE;
1235
1236                 vq_cmd_w0.s.opcode = opcode.flags;
1237
1238                 if (likely(iv_len)) {
1239                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1240                                                       OFF_CTRL_LEN);
1241                         uint64_t *src = fc_params->iv_buf;
1242                         dest[0] = src[0];
1243                         dest[1] = src[1];
1244                 }
1245
1246                 *(uint64_t *)offset_vaddr =
1247                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1248                                 ((uint64_t)iv_offset << 8) |
1249                                 ((uint64_t)auth_offset));
1250
1251                 /* DPTR has SG list */
1252                 in_buffer = m_vaddr;
1253                 dptr_dma = m_dma;
1254
1255                 ((uint16_t *)in_buffer)[0] = 0;
1256                 ((uint16_t *)in_buffer)[1] = 0;
1257
1258                 /* TODO Add error check if space will be sufficient */
1259                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1260
1261                 /*
1262                  * Input Gather List
1263                  */
1264                 i = 0;
1265
1266                 /* Offset control word that includes iv */
1267                 i = fill_sg_comp(gather_comp, i, offset_dma,
1268                                  OFF_CTRL_LEN + iv_len);
1269
1270                 /* Add input data */
1271                 if (flags & VALID_MAC_BUF) {
1272                         size = inputlen - iv_len - mac_len;
1273                         if (size) {
1274                                 /* input data only */
1275                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1276                                         i = fill_sg_comp_from_buf_min(
1277                                                         gather_comp, i,
1278                                                         fc_params->bufs,
1279                                                         &size);
1280                                 } else {
1281                                         uint32_t aad_offset = aad_len ?
1282                                                 passthrough_len : 0;
1283
1284                                         i = fill_sg_comp_from_iov(gather_comp,
1285                                                         i,
1286                                                         fc_params->src_iov,
1287                                                         0, &size,
1288                                                         aad_buf,
1289                                                         aad_offset);
1290                                 }
1291                                 if (unlikely(size)) {
1292                                         CPT_LOG_DP_ERR("Insufficient buffer"
1293                                                        " space, size %d needed",
1294                                                        size);
1295                                         return;
1296                                 }
1297                         }
1298
1299                         /* mac data */
1300                         if (mac_len) {
1301                                 i = fill_sg_comp_from_buf(gather_comp, i,
1302                                                           &fc_params->mac_buf);
1303                         }
1304                 } else {
1305                         /* input data + mac */
1306                         size = inputlen - iv_len;
1307                         if (size) {
1308                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1309                                         i = fill_sg_comp_from_buf_min(
1310                                                         gather_comp, i,
1311                                                         fc_params->bufs,
1312                                                         &size);
1313                                 } else {
1314                                         uint32_t aad_offset = aad_len ?
1315                                                 passthrough_len : 0;
1316
1317                                         if (unlikely(!fc_params->src_iov)) {
1318                                                 CPT_LOG_DP_ERR("Bad input args");
1319                                                 return;
1320                                         }
1321
1322                                         i = fill_sg_comp_from_iov(
1323                                                         gather_comp, i,
1324                                                         fc_params->src_iov,
1325                                                         0, &size,
1326                                                         aad_buf,
1327                                                         aad_offset);
1328                                 }
1329
1330                                 if (unlikely(size)) {
1331                                         CPT_LOG_DP_ERR("Insufficient buffer"
1332                                                        " space, size %d needed",
1333                                                        size);
1334                                         return;
1335                                 }
1336                         }
1337                 }
1338                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1339                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1340
1341                 /*
1342                  * Output Scatter List
1343                  */
1344
1345                 i = 0;
1346                 scatter_comp =
1347                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1348
1349                 /* Add iv */
1350                 if (iv_len) {
1351                         i = fill_sg_comp(scatter_comp, i,
1352                                          offset_dma + OFF_CTRL_LEN,
1353                                          iv_len);
1354                 }
1355
1356                 /* Add output data */
1357                 size = outputlen - iv_len;
1358                 if (size) {
1359                         if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1360                                 /* handle single buffer here */
1361                                 i = fill_sg_comp_from_buf_min(scatter_comp, i,
1362                                                               fc_params->bufs,
1363                                                               &size);
1364                         } else {
1365                                 uint32_t aad_offset = aad_len ?
1366                                         passthrough_len : 0;
1367
1368                                 if (unlikely(!fc_params->dst_iov)) {
1369                                         CPT_LOG_DP_ERR("Bad input args");
1370                                         return;
1371                                 }
1372
1373                                 i = fill_sg_comp_from_iov(scatter_comp, i,
1374                                                           fc_params->dst_iov, 0,
1375                                                           &size, aad_buf,
1376                                                           aad_offset);
1377                         }
1378
1379                         if (unlikely(size)) {
1380                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1381                                                " size %d needed", size);
1382                                 return;
1383                         }
1384                 }
1385
1386                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1387                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1388
1389                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1390
1391                 /* This is DPTR len incase of SG mode */
1392                 vq_cmd_w0.s.dlen = size;
1393
1394                 m_vaddr = (uint8_t *)m_vaddr + size;
1395                 m_dma += size;
1396                 m_size -= size;
1397
1398                 /* cpt alternate completion address saved earlier */
1399                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1400                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1401                 rptr_dma = c_dma - 8;
1402                 size += COMPLETION_CODE_SIZE;
1403
1404                 req->ist.ei1 = dptr_dma;
1405                 req->ist.ei2 = rptr_dma;
1406         }
1407
1408         ctx_dma = fc_params->ctx_buf.dma_addr +
1409                 offsetof(struct cpt_ctx, fctx);
1410         /* vq command w3 */
1411         vq_cmd_w3.u64 = 0;
1412         vq_cmd_w3.s.grp = 0;
1413         vq_cmd_w3.s.cptr = ctx_dma;
1414
1415         /* 16 byte aligned cpt res address */
1416         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1417         *req->completion_addr = COMPLETION_CODE_INIT;
1418         req->comp_baddr  = c_dma;
1419
1420         /* Fill microcode part of instruction */
1421         req->ist.ei0 = vq_cmd_w0.u64;
1422         req->ist.ei3 = vq_cmd_w3.u64;
1423
1424         req->op = op;
1425
1426         *prep_req = req;
1427         return;
1428 }
1429
1430 static __rte_always_inline void
1431 cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
1432                         uint64_t d_offs,
1433                         uint64_t d_lens,
1434                         fc_params_t *params,
1435                         void *op,
1436                         void **prep_req)
1437 {
1438         uint32_t size;
1439         int32_t inputlen, outputlen;
1440         struct cpt_ctx *cpt_ctx;
1441         uint32_t mac_len = 0;
1442         uint8_t snow3g, j;
1443         struct cpt_request_info *req;
1444         buf_ptr_t *buf_p;
1445         uint32_t encr_offset = 0, auth_offset = 0;
1446         uint32_t encr_data_len = 0, auth_data_len = 0;
1447         int flags, iv_len = 16, m_size;
1448         void *m_vaddr, *c_vaddr;
1449         uint64_t m_dma, c_dma, offset_ctrl;
1450         uint64_t *offset_vaddr, offset_dma;
1451         uint32_t *iv_s, iv[4];
1452         vq_cmd_word0_t vq_cmd_w0;
1453         vq_cmd_word3_t vq_cmd_w3;
1454         opcode_info_t opcode;
1455
1456         buf_p = &params->meta_buf;
1457         m_vaddr = buf_p->vaddr;
1458         m_dma = buf_p->dma_addr;
1459         m_size = buf_p->size;
1460
1461         cpt_ctx = params->ctx_buf.vaddr;
1462         flags = cpt_ctx->zsk_flags;
1463         mac_len = cpt_ctx->mac_len;
1464         snow3g = cpt_ctx->snow3g;
1465
1466         /*
1467          * Save initial space that followed app data for completion code &
1468          * alternate completion code to fall in same cache line as app data
1469          */
1470         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1471         m_dma += COMPLETION_CODE_SIZE;
1472         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1473                 (uint8_t *)m_vaddr;
1474
1475         c_vaddr = (uint8_t *)m_vaddr + size;
1476         c_dma = m_dma + size;
1477         size += sizeof(cpt_res_s_t);
1478
1479         m_vaddr = (uint8_t *)m_vaddr + size;
1480         m_dma += size;
1481         m_size -= size;
1482
1483         /* Reserve memory for cpt request info */
1484         req = m_vaddr;
1485
1486         size = sizeof(struct cpt_request_info);
1487         m_vaddr = (uint8_t *)m_vaddr + size;
1488         m_dma += size;
1489         m_size -= size;
1490
1491         opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1492
1493         /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1494         opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
1495                           (0 << 3) | (flags & 0x7));
1496
1497         if (flags == 0x1) {
1498                 /*
1499                  * Microcode expects offsets in bytes
1500                  * TODO: Rounding off
1501                  */
1502                 auth_data_len = AUTH_DLEN(d_lens);
1503
1504                 /* EIA3 or UIA2 */
1505                 auth_offset = AUTH_OFFSET(d_offs);
1506                 auth_offset = auth_offset / 8;
1507
1508                 /* consider iv len */
1509                 auth_offset += iv_len;
1510
1511                 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
1512                 outputlen = mac_len;
1513
1514                 offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
1515
1516         } else {
1517                 /* EEA3 or UEA2 */
1518                 /*
1519                  * Microcode expects offsets in bytes
1520                  * TODO: Rounding off
1521                  */
1522                 encr_data_len = ENCR_DLEN(d_lens);
1523
1524                 encr_offset = ENCR_OFFSET(d_offs);
1525                 encr_offset = encr_offset / 8;
1526                 /* consider iv len */
1527                 encr_offset += iv_len;
1528
1529                 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
1530                 outputlen = inputlen;
1531
1532                 /* iv offset is 0 */
1533                 offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1534         }
1535
1536         /* IV */
1537         iv_s = (flags == 0x1) ? params->auth_iv_buf :
1538                 params->iv_buf;
1539
1540         if (snow3g) {
1541                 /*
1542                  * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1543                  * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1544                  */
1545
1546                 for (j = 0; j < 4; j++)
1547                         iv[j] = iv_s[3 - j];
1548         } else {
1549                 /* ZUC doesn't need a swap */
1550                 for (j = 0; j < 4; j++)
1551                         iv[j] = iv_s[j];
1552         }
1553
1554         /*
1555          * GP op header, lengths are expected in bits.
1556          */
1557         vq_cmd_w0.u64 = 0;
1558         vq_cmd_w0.s.param1 = encr_data_len;
1559         vq_cmd_w0.s.param2 = auth_data_len;
1560
1561         /*
1562          * In 83XX since we have a limitation of
1563          * IV & Offset control word not part of instruction
1564          * and need to be part of Data Buffer, we check if
1565          * head room is there and then only do the Direct mode processing
1566          */
1567         if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1568                    (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1569                 void *dm_vaddr = params->bufs[0].vaddr;
1570                 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1571                 /*
1572                  * This flag indicates that there is 24 bytes head room and
1573                  * 8 bytes tail room available, so that we get to do
1574                  * DIRECT MODE with limitation
1575                  */
1576
1577                 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1578                                             OFF_CTRL_LEN - iv_len);
1579                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1580
1581                 /* DPTR */
1582                 req->ist.ei1 = offset_dma;
1583                 /* RPTR should just exclude offset control word */
1584                 req->ist.ei2 = dm_dma_addr - iv_len;
1585                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1586                                                     + outputlen - iv_len);
1587
1588                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1589
1590                 vq_cmd_w0.s.opcode = opcode.flags;
1591
1592                 if (likely(iv_len)) {
1593                         uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1594                                                       + OFF_CTRL_LEN);
1595                         memcpy(iv_d, iv, 16);
1596                 }
1597
1598                 *offset_vaddr = offset_ctrl;
1599         } else {
1600                 uint32_t i, g_size_bytes, s_size_bytes;
1601                 uint64_t dptr_dma, rptr_dma;
1602                 sg_comp_t *gather_comp;
1603                 sg_comp_t *scatter_comp;
1604                 uint8_t *in_buffer;
1605                 uint32_t *iv_d;
1606
1607                 /* save space for iv */
1608                 offset_vaddr = m_vaddr;
1609                 offset_dma = m_dma;
1610
1611                 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1612                 m_dma += OFF_CTRL_LEN + iv_len;
1613                 m_size -= OFF_CTRL_LEN + iv_len;
1614
1615                 opcode.s.major |= CPT_DMA_MODE;
1616
1617                 vq_cmd_w0.s.opcode = opcode.flags;
1618
1619                 /* DPTR has SG list */
1620                 in_buffer = m_vaddr;
1621                 dptr_dma = m_dma;
1622
1623                 ((uint16_t *)in_buffer)[0] = 0;
1624                 ((uint16_t *)in_buffer)[1] = 0;
1625
1626                 /* TODO Add error check if space will be sufficient */
1627                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1628
1629                 /*
1630                  * Input Gather List
1631                  */
1632                 i = 0;
1633
1634                 /* Offset control word followed by iv */
1635
1636                 i = fill_sg_comp(gather_comp, i, offset_dma,
1637                                  OFF_CTRL_LEN + iv_len);
1638
1639                 /* iv offset is 0 */
1640                 *offset_vaddr = offset_ctrl;
1641
1642                 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1643                 memcpy(iv_d, iv, 16);
1644
1645                 /* input data */
1646                 size = inputlen - iv_len;
1647                 if (size) {
1648                         i = fill_sg_comp_from_iov(gather_comp, i,
1649                                                   params->src_iov,
1650                                                   0, &size, NULL, 0);
1651                         if (unlikely(size)) {
1652                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1653                                                " size %d needed", size);
1654                                 return;
1655                         }
1656                 }
1657                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1658                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1659
1660                 /*
1661                  * Output Scatter List
1662                  */
1663
1664                 i = 0;
1665                 scatter_comp =
1666                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1667
1668                 if (flags == 0x1) {
1669                         /* IV in SLIST only for EEA3 & UEA2 */
1670                         iv_len = 0;
1671                 }
1672
1673                 if (iv_len) {
1674                         i = fill_sg_comp(scatter_comp, i,
1675                                          offset_dma + OFF_CTRL_LEN, iv_len);
1676                 }
1677
1678                 /* Add output data */
1679                 if (req_flags & VALID_MAC_BUF) {
1680                         size = outputlen - iv_len - mac_len;
1681                         if (size) {
1682                                 i = fill_sg_comp_from_iov(scatter_comp, i,
1683                                                           params->dst_iov, 0,
1684                                                           &size, NULL, 0);
1685
1686                                 if (unlikely(size)) {
1687                                         CPT_LOG_DP_ERR("Insufficient buffer space,"
1688                                                        " size %d needed", size);
1689                                         return;
1690                                 }
1691                         }
1692
1693                         /* mac data */
1694                         if (mac_len) {
1695                                 i = fill_sg_comp_from_buf(scatter_comp, i,
1696                                                           &params->mac_buf);
1697                         }
1698                 } else {
1699                         /* Output including mac */
1700                         size = outputlen - iv_len;
1701                         if (size) {
1702                                 i = fill_sg_comp_from_iov(scatter_comp, i,
1703                                                           params->dst_iov, 0,
1704                                                           &size, NULL, 0);
1705
1706                                 if (unlikely(size)) {
1707                                         CPT_LOG_DP_ERR("Insufficient buffer space,"
1708                                                        " size %d needed", size);
1709                                         return;
1710                                 }
1711                         }
1712                 }
1713                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1714                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1715
1716                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1717
1718                 /* This is DPTR len incase of SG mode */
1719                 vq_cmd_w0.s.dlen = size;
1720
1721                 m_vaddr = (uint8_t *)m_vaddr + size;
1722                 m_dma += size;
1723                 m_size -= size;
1724
1725                 /* cpt alternate completion address saved earlier */
1726                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1727                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1728                 rptr_dma = c_dma - 8;
1729
1730                 req->ist.ei1 = dptr_dma;
1731                 req->ist.ei2 = rptr_dma;
1732         }
1733
1734         /* vq command w3 */
1735         vq_cmd_w3.u64 = 0;
1736         vq_cmd_w3.s.grp = 0;
1737         vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
1738                 offsetof(struct cpt_ctx, zs_ctx);
1739
1740         /* 16 byte aligned cpt res address */
1741         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1742         *req->completion_addr = COMPLETION_CODE_INIT;
1743         req->comp_baddr  = c_dma;
1744
1745         /* Fill microcode part of instruction */
1746         req->ist.ei0 = vq_cmd_w0.u64;
1747         req->ist.ei3 = vq_cmd_w3.u64;
1748
1749         req->op = op;
1750
1751         *prep_req = req;
1752         return;
1753 }
1754
1755 static __rte_always_inline void
1756 cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
1757                         uint64_t d_offs,
1758                         uint64_t d_lens,
1759                         fc_params_t *params,
1760                         void *op,
1761                         void **prep_req)
1762 {
1763         uint32_t size;
1764         int32_t inputlen = 0, outputlen;
1765         struct cpt_ctx *cpt_ctx;
1766         uint8_t snow3g, iv_len = 16;
1767         struct cpt_request_info *req;
1768         buf_ptr_t *buf_p;
1769         uint32_t encr_offset;
1770         uint32_t encr_data_len;
1771         int flags, m_size;
1772         void *m_vaddr, *c_vaddr;
1773         uint64_t m_dma, c_dma;
1774         uint64_t *offset_vaddr, offset_dma;
1775         uint32_t *iv_s, iv[4], j;
1776         vq_cmd_word0_t vq_cmd_w0;
1777         vq_cmd_word3_t vq_cmd_w3;
1778         opcode_info_t opcode;
1779
1780         buf_p = &params->meta_buf;
1781         m_vaddr = buf_p->vaddr;
1782         m_dma = buf_p->dma_addr;
1783         m_size = buf_p->size;
1784
1785         /*
1786          * Microcode expects offsets in bytes
1787          * TODO: Rounding off
1788          */
1789         encr_offset = ENCR_OFFSET(d_offs) / 8;
1790         encr_data_len = ENCR_DLEN(d_lens);
1791
1792         cpt_ctx = params->ctx_buf.vaddr;
1793         flags = cpt_ctx->zsk_flags;
1794         snow3g = cpt_ctx->snow3g;
1795         /*
1796          * Save initial space that followed app data for completion code &
1797          * alternate completion code to fall in same cache line as app data
1798          */
1799         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1800         m_dma += COMPLETION_CODE_SIZE;
1801         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1802                 (uint8_t *)m_vaddr;
1803
1804         c_vaddr = (uint8_t *)m_vaddr + size;
1805         c_dma = m_dma + size;
1806         size += sizeof(cpt_res_s_t);
1807
1808         m_vaddr = (uint8_t *)m_vaddr + size;
1809         m_dma += size;
1810         m_size -= size;
1811
1812         /* Reserve memory for cpt request info */
1813         req = m_vaddr;
1814
1815         size = sizeof(struct cpt_request_info);
1816         m_vaddr = (uint8_t *)m_vaddr + size;
1817         m_dma += size;
1818         m_size -= size;
1819
1820         opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1821
1822         /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1823         opcode.s.minor = ((1 << 6) | (snow3g << 5) | (0 << 4) |
1824                           (0 << 3) | (flags & 0x7));
1825
1826         /* consider iv len */
1827         encr_offset += iv_len;
1828
1829         inputlen = encr_offset +
1830                 (RTE_ALIGN(encr_data_len, 8) / 8);
1831         outputlen = inputlen;
1832
1833         /* IV */
1834         iv_s = params->iv_buf;
1835         if (snow3g) {
1836                 /*
1837                  * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1838                  * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1839                  */
1840
1841                 for (j = 0; j < 4; j++)
1842                         iv[j] = iv_s[3 - j];
1843         } else {
1844                 /* ZUC doesn't need a swap */
1845                 for (j = 0; j < 4; j++)
1846                         iv[j] = iv_s[j];
1847         }
1848
1849         /*
1850          * GP op header, lengths are expected in bits.
1851          */
1852         vq_cmd_w0.u64 = 0;
1853         vq_cmd_w0.s.param1 = encr_data_len;
1854
1855         /*
1856          * In 83XX since we have a limitation of
1857          * IV & Offset control word not part of instruction
1858          * and need to be part of Data Buffer, we check if
1859          * head room is there and then only do the Direct mode processing
1860          */
1861         if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1862                    (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1863                 void *dm_vaddr = params->bufs[0].vaddr;
1864                 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1865                 /*
1866                  * This flag indicates that there is 24 bytes head room and
1867                  * 8 bytes tail room available, so that we get to do
1868                  * DIRECT MODE with limitation
1869                  */
1870
1871                 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1872                                             OFF_CTRL_LEN - iv_len);
1873                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1874
1875                 /* DPTR */
1876                 req->ist.ei1 = offset_dma;
1877                 /* RPTR should just exclude offset control word */
1878                 req->ist.ei2 = dm_dma_addr - iv_len;
1879                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1880                                                     + outputlen - iv_len);
1881
1882                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1883
1884                 vq_cmd_w0.s.opcode = opcode.flags;
1885
1886                 if (likely(iv_len)) {
1887                         uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1888                                                       + OFF_CTRL_LEN);
1889                         memcpy(iv_d, iv, 16);
1890                 }
1891
1892                 /* iv offset is 0 */
1893                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1894         } else {
1895                 uint32_t i, g_size_bytes, s_size_bytes;
1896                 uint64_t dptr_dma, rptr_dma;
1897                 sg_comp_t *gather_comp;
1898                 sg_comp_t *scatter_comp;
1899                 uint8_t *in_buffer;
1900                 uint32_t *iv_d;
1901
1902                 /* save space for offset and iv... */
1903                 offset_vaddr = m_vaddr;
1904                 offset_dma = m_dma;
1905
1906                 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1907                 m_dma += OFF_CTRL_LEN + iv_len;
1908                 m_size -= OFF_CTRL_LEN + iv_len;
1909
1910                 opcode.s.major |= CPT_DMA_MODE;
1911
1912                 vq_cmd_w0.s.opcode = opcode.flags;
1913
1914                 /* DPTR has SG list */
1915                 in_buffer = m_vaddr;
1916                 dptr_dma = m_dma;
1917
1918                 ((uint16_t *)in_buffer)[0] = 0;
1919                 ((uint16_t *)in_buffer)[1] = 0;
1920
1921                 /* TODO Add error check if space will be sufficient */
1922                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1923
1924                 /*
1925                  * Input Gather List
1926                  */
1927                 i = 0;
1928
1929                 /* Offset control word */
1930
1931                 /* iv offset is 0 */
1932                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1933
1934                 i = fill_sg_comp(gather_comp, i, offset_dma,
1935                                  OFF_CTRL_LEN + iv_len);
1936
1937                 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1938                 memcpy(iv_d, iv, 16);
1939
1940                 /* Add input data */
1941                 size = inputlen - iv_len;
1942                 if (size) {
1943                         i = fill_sg_comp_from_iov(gather_comp, i,
1944                                                   params->src_iov,
1945                                                   0, &size, NULL, 0);
1946                         if (unlikely(size)) {
1947                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1948                                                " size %d needed", size);
1949                                 return;
1950                         }
1951                 }
1952                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1953                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1954
1955                 /*
1956                  * Output Scatter List
1957                  */
1958
1959                 i = 0;
1960                 scatter_comp =
1961                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1962
1963                 /* IV */
1964                 i = fill_sg_comp(scatter_comp, i,
1965                                  offset_dma + OFF_CTRL_LEN,
1966                                  iv_len);
1967
1968                 /* Add output data */
1969                 size = outputlen - iv_len;
1970                 if (size) {
1971                         i = fill_sg_comp_from_iov(scatter_comp, i,
1972                                                   params->dst_iov, 0,
1973                                                   &size, NULL, 0);
1974
1975                         if (unlikely(size)) {
1976                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1977                                                " size %d needed", size);
1978                                 return;
1979                         }
1980                 }
1981                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1982                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1983
1984                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1985
1986                 /* This is DPTR len incase of SG mode */
1987                 vq_cmd_w0.s.dlen = size;
1988
1989                 m_vaddr = (uint8_t *)m_vaddr + size;
1990                 m_dma += size;
1991                 m_size -= size;
1992
1993                 /* cpt alternate completion address saved earlier */
1994                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1995                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1996                 rptr_dma = c_dma - 8;
1997
1998                 req->ist.ei1 = dptr_dma;
1999                 req->ist.ei2 = rptr_dma;
2000         }
2001
2002         /* vq command w3 */
2003         vq_cmd_w3.u64 = 0;
2004         vq_cmd_w3.s.grp = 0;
2005         vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
2006                 offsetof(struct cpt_ctx, zs_ctx);
2007
2008         /* 16 byte aligned cpt res address */
2009         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2010         *req->completion_addr = COMPLETION_CODE_INIT;
2011         req->comp_baddr  = c_dma;
2012
2013         /* Fill microcode part of instruction */
2014         req->ist.ei0 = vq_cmd_w0.u64;
2015         req->ist.ei3 = vq_cmd_w3.u64;
2016
2017         req->op = op;
2018
2019         *prep_req = req;
2020         return;
2021 }
2022
2023 static __rte_always_inline void
2024 cpt_kasumi_enc_prep(uint32_t req_flags,
2025                     uint64_t d_offs,
2026                     uint64_t d_lens,
2027                     fc_params_t *params,
2028                     void *op,
2029                     void **prep_req)
2030 {
2031         uint32_t size;
2032         int32_t inputlen = 0, outputlen = 0;
2033         struct cpt_ctx *cpt_ctx;
2034         uint32_t mac_len = 0;
2035         uint8_t i = 0;
2036         struct cpt_request_info *req;
2037         buf_ptr_t *buf_p;
2038         uint32_t encr_offset, auth_offset;
2039         uint32_t encr_data_len, auth_data_len;
2040         int flags, m_size;
2041         uint8_t *iv_s, *iv_d, iv_len = 8;
2042         uint8_t dir = 0;
2043         void *m_vaddr, *c_vaddr;
2044         uint64_t m_dma, c_dma;
2045         uint64_t *offset_vaddr, offset_dma;
2046         vq_cmd_word0_t vq_cmd_w0;
2047         vq_cmd_word3_t vq_cmd_w3;
2048         opcode_info_t opcode;
2049         uint8_t *in_buffer;
2050         uint32_t g_size_bytes, s_size_bytes;
2051         uint64_t dptr_dma, rptr_dma;
2052         sg_comp_t *gather_comp;
2053         sg_comp_t *scatter_comp;
2054
2055         buf_p = &params->meta_buf;
2056         m_vaddr = buf_p->vaddr;
2057         m_dma = buf_p->dma_addr;
2058         m_size = buf_p->size;
2059
2060         encr_offset = ENCR_OFFSET(d_offs) / 8;
2061         auth_offset = AUTH_OFFSET(d_offs) / 8;
2062         encr_data_len = ENCR_DLEN(d_lens);
2063         auth_data_len = AUTH_DLEN(d_lens);
2064
2065         cpt_ctx = params->ctx_buf.vaddr;
2066         flags = cpt_ctx->zsk_flags;
2067         mac_len = cpt_ctx->mac_len;
2068
2069         if (flags == 0x0)
2070                 iv_s = params->iv_buf;
2071         else
2072                 iv_s = params->auth_iv_buf;
2073
2074         dir = iv_s[8] & 0x1;
2075
2076         /*
2077          * Save initial space that followed app data for completion code &
2078          * alternate completion code to fall in same cache line as app data
2079          */
2080         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2081         m_dma += COMPLETION_CODE_SIZE;
2082         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2083                 (uint8_t *)m_vaddr;
2084
2085         c_vaddr = (uint8_t *)m_vaddr + size;
2086         c_dma = m_dma + size;
2087         size += sizeof(cpt_res_s_t);
2088
2089         m_vaddr = (uint8_t *)m_vaddr + size;
2090         m_dma += size;
2091         m_size -= size;
2092
2093         /* Reserve memory for cpt request info */
2094         req = m_vaddr;
2095
2096         size = sizeof(struct cpt_request_info);
2097         m_vaddr = (uint8_t *)m_vaddr + size;
2098         m_dma += size;
2099         m_size -= size;
2100
2101         opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2102
2103         /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2104         opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2105                           (dir << 4) | (0 << 3) | (flags & 0x7));
2106
2107         /*
2108          * GP op header, lengths are expected in bits.
2109          */
2110         vq_cmd_w0.u64 = 0;
2111         vq_cmd_w0.s.param1 = encr_data_len;
2112         vq_cmd_w0.s.param2 = auth_data_len;
2113         vq_cmd_w0.s.opcode = opcode.flags;
2114
2115         /* consider iv len */
2116         if (flags == 0x0) {
2117                 encr_offset += iv_len;
2118                 auth_offset += iv_len;
2119         }
2120
2121         /* save space for offset ctrl and iv */
2122         offset_vaddr = m_vaddr;
2123         offset_dma = m_dma;
2124
2125         m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2126         m_dma += OFF_CTRL_LEN + iv_len;
2127         m_size -= OFF_CTRL_LEN + iv_len;
2128
2129         /* DPTR has SG list */
2130         in_buffer = m_vaddr;
2131         dptr_dma = m_dma;
2132
2133         ((uint16_t *)in_buffer)[0] = 0;
2134         ((uint16_t *)in_buffer)[1] = 0;
2135
2136         /* TODO Add error check if space will be sufficient */
2137         gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2138
2139         /*
2140          * Input Gather List
2141          */
2142         i = 0;
2143
2144         /* Offset control word followed by iv */
2145
2146         if (flags == 0x0) {
2147                 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
2148                 outputlen = inputlen;
2149                 /* iv offset is 0 */
2150                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2151         } else {
2152                 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
2153                 outputlen = mac_len;
2154                 /* iv offset is 0 */
2155                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
2156         }
2157
2158         i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2159
2160         /* IV */
2161         iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;
2162         memcpy(iv_d, iv_s, iv_len);
2163
2164         /* input data */
2165         size = inputlen - iv_len;
2166         if (size) {
2167                 i = fill_sg_comp_from_iov(gather_comp, i,
2168                                           params->src_iov, 0,
2169                                           &size, NULL, 0);
2170
2171                 if (unlikely(size)) {
2172                         CPT_LOG_DP_ERR("Insufficient buffer space,"
2173                                        " size %d needed", size);
2174                         return;
2175                 }
2176         }
2177         ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2178         g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2179
2180         /*
2181          * Output Scatter List
2182          */
2183
2184         i = 0;
2185         scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2186
2187         if (flags == 0x1) {
2188                 /* IV in SLIST only for F8 */
2189                 iv_len = 0;
2190         }
2191
2192         /* IV */
2193         if (iv_len) {
2194                 i = fill_sg_comp(scatter_comp, i,
2195                                  offset_dma + OFF_CTRL_LEN,
2196                                  iv_len);
2197         }
2198
2199         /* Add output data */
2200         if (req_flags & VALID_MAC_BUF) {
2201                 size = outputlen - iv_len - mac_len;
2202                 if (size) {
2203                         i = fill_sg_comp_from_iov(scatter_comp, i,
2204                                                   params->dst_iov, 0,
2205                                                   &size, NULL, 0);
2206
2207                         if (unlikely(size)) {
2208                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
2209                                                " size %d needed", size);
2210                                 return;
2211                         }
2212                 }
2213
2214                 /* mac data */
2215                 if (mac_len) {
2216                         i = fill_sg_comp_from_buf(scatter_comp, i,
2217                                                   &params->mac_buf);
2218                 }
2219         } else {
2220                 /* Output including mac */
2221                 size = outputlen - iv_len;
2222                 if (size) {
2223                         i = fill_sg_comp_from_iov(scatter_comp, i,
2224                                                   params->dst_iov, 0,
2225                                                   &size, NULL, 0);
2226
2227                         if (unlikely(size)) {
2228                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
2229                                                " size %d needed", size);
2230                                 return;
2231                         }
2232                 }
2233         }
2234         ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2235         s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2236
2237         size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2238
2239         /* This is DPTR len incase of SG mode */
2240         vq_cmd_w0.s.dlen = size;
2241
2242         m_vaddr = (uint8_t *)m_vaddr + size;
2243         m_dma += size;
2244         m_size -= size;
2245
2246         /* cpt alternate completion address saved earlier */
2247         req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2248         *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2249         rptr_dma = c_dma - 8;
2250
2251         req->ist.ei1 = dptr_dma;
2252         req->ist.ei2 = rptr_dma;
2253
2254         /* vq command w3 */
2255         vq_cmd_w3.u64 = 0;
2256         vq_cmd_w3.s.grp = 0;
2257         vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
2258                 offsetof(struct cpt_ctx, k_ctx);
2259
2260         /* 16 byte aligned cpt res address */
2261         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2262         *req->completion_addr = COMPLETION_CODE_INIT;
2263         req->comp_baddr  = c_dma;
2264
2265         /* Fill microcode part of instruction */
2266         req->ist.ei0 = vq_cmd_w0.u64;
2267         req->ist.ei3 = vq_cmd_w3.u64;
2268
2269         req->op = op;
2270
2271         *prep_req = req;
2272         return;
2273 }
2274
2275 static __rte_always_inline void
2276 cpt_kasumi_dec_prep(uint64_t d_offs,
2277                     uint64_t d_lens,
2278                     fc_params_t *params,
2279                     void *op,
2280                     void **prep_req)
2281 {
2282         uint32_t size;
2283         int32_t inputlen = 0, outputlen;
2284         struct cpt_ctx *cpt_ctx;
2285         uint8_t i = 0, iv_len = 8;
2286         struct cpt_request_info *req;
2287         buf_ptr_t *buf_p;
2288         uint32_t encr_offset;
2289         uint32_t encr_data_len;
2290         int flags, m_size;
2291         uint8_t dir = 0;
2292         void *m_vaddr, *c_vaddr;
2293         uint64_t m_dma, c_dma;
2294         uint64_t *offset_vaddr, offset_dma;
2295         vq_cmd_word0_t vq_cmd_w0;
2296         vq_cmd_word3_t vq_cmd_w3;
2297         opcode_info_t opcode;
2298         uint8_t *in_buffer;
2299         uint32_t g_size_bytes, s_size_bytes;
2300         uint64_t dptr_dma, rptr_dma;
2301         sg_comp_t *gather_comp;
2302         sg_comp_t *scatter_comp;
2303
2304         buf_p = &params->meta_buf;
2305         m_vaddr = buf_p->vaddr;
2306         m_dma = buf_p->dma_addr;
2307         m_size = buf_p->size;
2308
2309         encr_offset = ENCR_OFFSET(d_offs) / 8;
2310         encr_data_len = ENCR_DLEN(d_lens);
2311
2312         cpt_ctx = params->ctx_buf.vaddr;
2313         flags = cpt_ctx->zsk_flags;
2314         /*
2315          * Save initial space that followed app data for completion code &
2316          * alternate completion code to fall in same cache line as app data
2317          */
2318         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2319         m_dma += COMPLETION_CODE_SIZE;
2320         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2321                 (uint8_t *)m_vaddr;
2322
2323         c_vaddr = (uint8_t *)m_vaddr + size;
2324         c_dma = m_dma + size;
2325         size += sizeof(cpt_res_s_t);
2326
2327         m_vaddr = (uint8_t *)m_vaddr + size;
2328         m_dma += size;
2329         m_size -= size;
2330
2331         /* Reserve memory for cpt request info */
2332         req = m_vaddr;
2333
2334         size = sizeof(struct cpt_request_info);
2335         m_vaddr = (uint8_t *)m_vaddr + size;
2336         m_dma += size;
2337         m_size -= size;
2338
2339         opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2340
2341         /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2342         opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2343                           (dir << 4) | (0 << 3) | (flags & 0x7));
2344
2345         /*
2346          * GP op header, lengths are expected in bits.
2347          */
2348         vq_cmd_w0.u64 = 0;
2349         vq_cmd_w0.s.param1 = encr_data_len;
2350         vq_cmd_w0.s.opcode = opcode.flags;
2351
2352         /* consider iv len */
2353         encr_offset += iv_len;
2354
2355         inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);
2356         outputlen = inputlen;
2357
2358         /* save space for offset ctrl & iv */
2359         offset_vaddr = m_vaddr;
2360         offset_dma = m_dma;
2361
2362         m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2363         m_dma += OFF_CTRL_LEN + iv_len;
2364         m_size -= OFF_CTRL_LEN + iv_len;
2365
2366         /* DPTR has SG list */
2367         in_buffer = m_vaddr;
2368         dptr_dma = m_dma;
2369
2370         ((uint16_t *)in_buffer)[0] = 0;
2371         ((uint16_t *)in_buffer)[1] = 0;
2372
2373         /* TODO Add error check if space will be sufficient */
2374         gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2375
2376         /*
2377          * Input Gather List
2378          */
2379         i = 0;
2380
2381         /* Offset control word followed by iv */
2382         *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2383
2384         i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2385
2386         /* IV */
2387         memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,
2388                params->iv_buf, iv_len);
2389
2390         /* Add input data */
2391         size = inputlen - iv_len;
2392         if (size) {
2393                 i = fill_sg_comp_from_iov(gather_comp, i,
2394                                           params->src_iov,
2395                                           0, &size, NULL, 0);
2396                 if (unlikely(size)) {
2397                         CPT_LOG_DP_ERR("Insufficient buffer space,"
2398                                        " size %d needed", size);
2399                         return;
2400                 }
2401         }
2402         ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2403         g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2404
2405         /*
2406          * Output Scatter List
2407          */
2408
2409         i = 0;
2410         scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2411
2412         /* IV */
2413         i = fill_sg_comp(scatter_comp, i,
2414                          offset_dma + OFF_CTRL_LEN,
2415                          iv_len);
2416
2417         /* Add output data */
2418         size = outputlen - iv_len;
2419         if (size) {
2420                 i = fill_sg_comp_from_iov(scatter_comp, i,
2421                                           params->dst_iov, 0,
2422                                           &size, NULL, 0);
2423                 if (unlikely(size)) {
2424                         CPT_LOG_DP_ERR("Insufficient buffer space,"
2425                                        " size %d needed", size);
2426                         return;
2427                 }
2428         }
2429         ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2430         s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2431
2432         size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2433
2434         /* This is DPTR len incase of SG mode */
2435         vq_cmd_w0.s.dlen = size;
2436
2437         m_vaddr = (uint8_t *)m_vaddr + size;
2438         m_dma += size;
2439         m_size -= size;
2440
2441         /* cpt alternate completion address saved earlier */
2442         req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2443         *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2444         rptr_dma = c_dma - 8;
2445
2446         req->ist.ei1 = dptr_dma;
2447         req->ist.ei2 = rptr_dma;
2448
2449         /* vq command w3 */
2450         vq_cmd_w3.u64 = 0;
2451         vq_cmd_w3.s.grp = 0;
2452         vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
2453                 offsetof(struct cpt_ctx, k_ctx);
2454
2455         /* 16 byte aligned cpt res address */
2456         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2457         *req->completion_addr = COMPLETION_CODE_INIT;
2458         req->comp_baddr  = c_dma;
2459
2460         /* Fill microcode part of instruction */
2461         req->ist.ei0 = vq_cmd_w0.u64;
2462         req->ist.ei3 = vq_cmd_w3.u64;
2463
2464         req->op = op;
2465
2466         *prep_req = req;
2467         return;
2468 }
2469
2470 static __rte_always_inline void *
2471 cpt_fc_dec_hmac_prep(uint32_t flags,
2472                      uint64_t d_offs,
2473                      uint64_t d_lens,
2474                      fc_params_t *fc_params,
2475                      void *op)
2476 {
2477         struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2478         uint8_t fc_type;
2479         void *prep_req = NULL;
2480
2481         fc_type = ctx->fc_type;
2482
2483         if (likely(fc_type == FC_GEN)) {
2484                 cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2485                                   &prep_req);
2486         } else if (fc_type == ZUC_SNOW3G) {
2487                 cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params, op,
2488                                         &prep_req);
2489         } else if (fc_type == KASUMI) {
2490                 cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, op, &prep_req);
2491         }
2492
2493         /*
2494          * For AUTH_ONLY case,
2495          * MC only supports digest generation and verification
2496          * should be done in software by memcmp()
2497          */
2498
2499         return prep_req;
2500 }
2501
2502 static __rte_always_inline void *__hot
2503 cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
2504                      fc_params_t *fc_params, void *op)
2505 {
2506         struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2507         uint8_t fc_type;
2508         void *prep_req = NULL;
2509
2510         fc_type = ctx->fc_type;
2511
2512         /* Common api for rest of the ops */
2513         if (likely(fc_type == FC_GEN)) {
2514                 cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2515                                   &prep_req);
2516         } else if (fc_type == ZUC_SNOW3G) {
2517                 cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params, op,
2518                                         &prep_req);
2519         } else if (fc_type == KASUMI) {
2520                 cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params, op,
2521                                     &prep_req);
2522         } else if (fc_type == HASH_HMAC) {
2523                 cpt_digest_gen_prep(flags, d_lens, fc_params, op, &prep_req);
2524         }
2525
2526         return prep_req;
2527 }
2528
2529 static __rte_always_inline int
2530 cpt_fc_auth_set_key(void *ctx, auth_type_t type, uint8_t *key,
2531                     uint16_t key_len, uint16_t mac_len)
2532 {
2533         struct cpt_ctx *cpt_ctx = ctx;
2534         mc_fc_context_t *fctx = &cpt_ctx->fctx;
2535         uint64_t *ctrl_flags = NULL;
2536
2537         if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
2538                 uint32_t keyx[4];
2539
2540                 if (key_len != 16)
2541                         return -1;
2542                 /* No support for AEAD yet */
2543                 if (cpt_ctx->enc_cipher)
2544                         return -1;
2545                 /* For ZUC/SNOW3G/Kasumi */
2546                 switch (type) {
2547                 case SNOW3G_UIA2:
2548                         cpt_ctx->snow3g = 1;
2549                         gen_key_snow3g(key, keyx);
2550                         memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
2551                         cpt_ctx->fc_type = ZUC_SNOW3G;
2552                         cpt_ctx->zsk_flags = 0x1;
2553                         break;
2554                 case ZUC_EIA3:
2555                         cpt_ctx->snow3g = 0;
2556                         memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
2557                         memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
2558                         cpt_ctx->fc_type = ZUC_SNOW3G;
2559                         cpt_ctx->zsk_flags = 0x1;
2560                         break;
2561                 case KASUMI_F9_ECB:
2562                         /* Kasumi ECB mode */
2563                         cpt_ctx->k_ecb = 1;
2564                         memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
2565                         cpt_ctx->fc_type = KASUMI;
2566                         cpt_ctx->zsk_flags = 0x1;
2567                         break;
2568                 case KASUMI_F9_CBC:
2569                         memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
2570                         cpt_ctx->fc_type = KASUMI;
2571                         cpt_ctx->zsk_flags = 0x1;
2572                         break;
2573                 default:
2574                         return -1;
2575                 }
2576                 cpt_ctx->mac_len = 4;
2577                 cpt_ctx->hash_type = type;
2578                 return 0;
2579         }
2580
2581         if (!(cpt_ctx->fc_type == FC_GEN && !type)) {
2582                 if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher)
2583                         cpt_ctx->fc_type = HASH_HMAC;
2584         }
2585
2586         ctrl_flags = (uint64_t *)&fctx->enc.enc_ctrl.flags;
2587         *ctrl_flags = rte_be_to_cpu_64(*ctrl_flags);
2588
2589         /* For GMAC auth, cipher must be NULL */
2590         if (type == GMAC_TYPE)
2591                 CPT_P_ENC_CTRL(fctx).enc_cipher = 0;
2592
2593         CPT_P_ENC_CTRL(fctx).hash_type = cpt_ctx->hash_type = type;
2594         CPT_P_ENC_CTRL(fctx).mac_len = cpt_ctx->mac_len = mac_len;
2595
2596         if (key_len) {
2597                 cpt_ctx->hmac = 1;
2598                 memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key));
2599                 memcpy(cpt_ctx->auth_key, key, key_len);
2600                 cpt_ctx->auth_key_len = key_len;
2601                 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
2602                 memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
2603                 memcpy(fctx->hmac.opad, key, key_len);
2604                 CPT_P_ENC_CTRL(fctx).auth_input_type = 1;
2605         }
2606         *ctrl_flags = rte_cpu_to_be_64(*ctrl_flags);
2607         return 0;
2608 }
2609
2610 static __rte_always_inline int
2611 fill_sess_aead(struct rte_crypto_sym_xform *xform,
2612                  struct cpt_sess_misc *sess)
2613 {
2614         struct rte_crypto_aead_xform *aead_form;
2615         cipher_type_t enc_type = 0; /* NULL Cipher type */
2616         auth_type_t auth_type = 0; /* NULL Auth type */
2617         uint32_t cipher_key_len = 0;
2618         uint8_t zsk_flag = 0, aes_gcm = 0;
2619         aead_form = &xform->aead;
2620         void *ctx;
2621
2622         if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
2623            aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
2624                 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2625                 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2626         } else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
2627                 aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
2628                 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2629                 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2630         } else {
2631                 CPT_LOG_DP_ERR("Unknown cipher operation\n");
2632                 return -1;
2633         }
2634         switch (aead_form->algo) {
2635         case RTE_CRYPTO_AEAD_AES_GCM:
2636                 enc_type = AES_GCM;
2637                 cipher_key_len = 16;
2638                 aes_gcm = 1;
2639                 break;
2640         case RTE_CRYPTO_AEAD_AES_CCM:
2641                 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2642                                aead_form->algo);
2643                 return -1;
2644         default:
2645                 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2646                                aead_form->algo);
2647                 return -1;
2648         }
2649         if (aead_form->key.length < cipher_key_len) {
2650                 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2651                                (unsigned int long)aead_form->key.length);
2652                 return -1;
2653         }
2654         sess->zsk_flag = zsk_flag;
2655         sess->aes_gcm = aes_gcm;
2656         sess->mac_len = aead_form->digest_length;
2657         sess->iv_offset = aead_form->iv.offset;
2658         sess->iv_length = aead_form->iv.length;
2659         sess->aad_length = aead_form->aad_length;
2660         ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
2661
2662         cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
2663                         aead_form->key.length, NULL);
2664
2665         cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, aead_form->digest_length);
2666
2667         return 0;
2668 }
2669
2670 static __rte_always_inline int
2671 fill_sess_cipher(struct rte_crypto_sym_xform *xform,
2672                  struct cpt_sess_misc *sess)
2673 {
2674         struct rte_crypto_cipher_xform *c_form;
2675         cipher_type_t enc_type = 0; /* NULL Cipher type */
2676         uint32_t cipher_key_len = 0;
2677         uint8_t zsk_flag = 0, aes_gcm = 0, aes_ctr = 0, is_null = 0;
2678
2679         if (xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER)
2680                 return -1;
2681
2682         c_form = &xform->cipher;
2683
2684         if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
2685                 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2686         else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
2687                 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2688         else {
2689                 CPT_LOG_DP_ERR("Unknown cipher operation\n");
2690                 return -1;
2691         }
2692
2693         switch (c_form->algo) {
2694         case RTE_CRYPTO_CIPHER_AES_CBC:
2695                 enc_type = AES_CBC;
2696                 cipher_key_len = 16;
2697                 break;
2698         case RTE_CRYPTO_CIPHER_3DES_CBC:
2699                 enc_type = DES3_CBC;
2700                 cipher_key_len = 24;
2701                 break;
2702         case RTE_CRYPTO_CIPHER_DES_CBC:
2703                 /* DES is implemented using 3DES in hardware */
2704                 enc_type = DES3_CBC;
2705                 cipher_key_len = 8;
2706                 break;
2707         case RTE_CRYPTO_CIPHER_AES_CTR:
2708                 enc_type = AES_CTR;
2709                 cipher_key_len = 16;
2710                 aes_ctr = 1;
2711                 break;
2712         case RTE_CRYPTO_CIPHER_NULL:
2713                 enc_type = 0;
2714                 is_null = 1;
2715                 break;
2716         case RTE_CRYPTO_CIPHER_KASUMI_F8:
2717                 enc_type = KASUMI_F8_ECB;
2718                 cipher_key_len = 16;
2719                 zsk_flag = K_F8;
2720                 break;
2721         case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
2722                 enc_type = SNOW3G_UEA2;
2723                 cipher_key_len = 16;
2724                 zsk_flag = ZS_EA;
2725                 break;
2726         case RTE_CRYPTO_CIPHER_ZUC_EEA3:
2727                 enc_type = ZUC_EEA3;
2728                 cipher_key_len = 16;
2729                 zsk_flag = ZS_EA;
2730                 break;
2731         case RTE_CRYPTO_CIPHER_AES_XTS:
2732                 enc_type = AES_XTS;
2733                 cipher_key_len = 16;
2734                 break;
2735         case RTE_CRYPTO_CIPHER_3DES_ECB:
2736                 enc_type = DES3_ECB;
2737                 cipher_key_len = 24;
2738                 break;
2739         case RTE_CRYPTO_CIPHER_AES_ECB:
2740                 enc_type = AES_ECB;
2741                 cipher_key_len = 16;
2742                 break;
2743         case RTE_CRYPTO_CIPHER_3DES_CTR:
2744         case RTE_CRYPTO_CIPHER_AES_F8:
2745         case RTE_CRYPTO_CIPHER_ARC4:
2746                 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2747                                c_form->algo);
2748                 return -1;
2749         default:
2750                 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2751                                c_form->algo);
2752                 return -1;
2753         }
2754
2755         if (c_form->key.length < cipher_key_len) {
2756                 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2757                                (unsigned long) c_form->key.length);
2758                 return -1;
2759         }
2760
2761         sess->zsk_flag = zsk_flag;
2762         sess->aes_gcm = aes_gcm;
2763         sess->aes_ctr = aes_ctr;
2764         sess->iv_offset = c_form->iv.offset;
2765         sess->iv_length = c_form->iv.length;
2766         sess->is_null = is_null;
2767
2768         cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type, c_form->key.data,
2769                             c_form->key.length, NULL);
2770
2771         return 0;
2772 }
2773
2774 static __rte_always_inline int
2775 fill_sess_auth(struct rte_crypto_sym_xform *xform,
2776                struct cpt_sess_misc *sess)
2777 {
2778         struct rte_crypto_auth_xform *a_form;
2779         auth_type_t auth_type = 0; /* NULL Auth type */
2780         uint8_t zsk_flag = 0, aes_gcm = 0, is_null = 0;
2781
2782         if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
2783                 goto error_out;
2784
2785         a_form = &xform->auth;
2786
2787         if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2788                 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2789         else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2790                 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2791         else {
2792                 CPT_LOG_DP_ERR("Unknown auth operation");
2793                 return -1;
2794         }
2795
2796         if (a_form->key.length > 64) {
2797                 CPT_LOG_DP_ERR("Auth key length is big");
2798                 return -1;
2799         }
2800
2801         switch (a_form->algo) {
2802         case RTE_CRYPTO_AUTH_SHA1_HMAC:
2803                 /* Fall through */
2804         case RTE_CRYPTO_AUTH_SHA1:
2805                 auth_type = SHA1_TYPE;
2806                 break;
2807         case RTE_CRYPTO_AUTH_SHA256_HMAC:
2808         case RTE_CRYPTO_AUTH_SHA256:
2809                 auth_type = SHA2_SHA256;
2810                 break;
2811         case RTE_CRYPTO_AUTH_SHA512_HMAC:
2812         case RTE_CRYPTO_AUTH_SHA512:
2813                 auth_type = SHA2_SHA512;
2814                 break;
2815         case RTE_CRYPTO_AUTH_AES_GMAC:
2816                 auth_type = GMAC_TYPE;
2817                 aes_gcm = 1;
2818                 break;
2819         case RTE_CRYPTO_AUTH_SHA224_HMAC:
2820         case RTE_CRYPTO_AUTH_SHA224:
2821                 auth_type = SHA2_SHA224;
2822                 break;
2823         case RTE_CRYPTO_AUTH_SHA384_HMAC:
2824         case RTE_CRYPTO_AUTH_SHA384:
2825                 auth_type = SHA2_SHA384;
2826                 break;
2827         case RTE_CRYPTO_AUTH_MD5_HMAC:
2828         case RTE_CRYPTO_AUTH_MD5:
2829                 auth_type = MD5_TYPE;
2830                 break;
2831         case RTE_CRYPTO_AUTH_KASUMI_F9:
2832                 auth_type = KASUMI_F9_ECB;
2833                 /*
2834                  * Indicate that direction needs to be taken out
2835                  * from end of src
2836                  */
2837                 zsk_flag = K_F9;
2838                 break;
2839         case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
2840                 auth_type = SNOW3G_UIA2;
2841                 zsk_flag = ZS_IA;
2842                 break;
2843         case RTE_CRYPTO_AUTH_ZUC_EIA3:
2844                 auth_type = ZUC_EIA3;
2845                 zsk_flag = ZS_IA;
2846                 break;
2847         case RTE_CRYPTO_AUTH_NULL:
2848                 auth_type = 0;
2849                 is_null = 1;
2850                 break;
2851         case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
2852         case RTE_CRYPTO_AUTH_AES_CMAC:
2853         case RTE_CRYPTO_AUTH_AES_CBC_MAC:
2854                 CPT_LOG_DP_ERR("Crypto: Unsupported hash algo %u",
2855                                a_form->algo);
2856                 goto error_out;
2857         default:
2858                 CPT_LOG_DP_ERR("Crypto: Undefined Hash algo %u specified",
2859                                a_form->algo);
2860                 goto error_out;
2861         }
2862
2863         sess->zsk_flag = zsk_flag;
2864         sess->aes_gcm = aes_gcm;
2865         sess->mac_len = a_form->digest_length;
2866         sess->is_null = is_null;
2867         if (zsk_flag) {
2868                 sess->auth_iv_offset = a_form->iv.offset;
2869                 sess->auth_iv_length = a_form->iv.length;
2870         }
2871         cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type, a_form->key.data,
2872                             a_form->key.length, a_form->digest_length);
2873
2874         return 0;
2875
2876 error_out:
2877         return -1;
2878 }
2879
2880 static __rte_always_inline int
2881 fill_sess_gmac(struct rte_crypto_sym_xform *xform,
2882                  struct cpt_sess_misc *sess)
2883 {
2884         struct rte_crypto_auth_xform *a_form;
2885         cipher_type_t enc_type = 0; /* NULL Cipher type */
2886         auth_type_t auth_type = 0; /* NULL Auth type */
2887         uint8_t zsk_flag = 0, aes_gcm = 0;
2888         void *ctx;
2889
2890         if (xform->type != RTE_CRYPTO_SYM_XFORM_AUTH)
2891                 return -1;
2892
2893         a_form = &xform->auth;
2894
2895         if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2896                 sess->cpt_op |= CPT_OP_ENCODE;
2897         else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2898                 sess->cpt_op |= CPT_OP_DECODE;
2899         else {
2900                 CPT_LOG_DP_ERR("Unknown auth operation");
2901                 return -1;
2902         }
2903
2904         switch (a_form->algo) {
2905         case RTE_CRYPTO_AUTH_AES_GMAC:
2906                 enc_type = AES_GCM;
2907                 auth_type = GMAC_TYPE;
2908                 break;
2909         default:
2910                 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2911                                a_form->algo);
2912                 return -1;
2913         }
2914
2915         sess->zsk_flag = zsk_flag;
2916         sess->aes_gcm = aes_gcm;
2917         sess->is_gmac = 1;
2918         sess->iv_offset = a_form->iv.offset;
2919         sess->iv_length = a_form->iv.length;
2920         sess->mac_len = a_form->digest_length;
2921         ctx = (void *)((uint8_t *)sess + sizeof(struct cpt_sess_misc)),
2922
2923         cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
2924                         a_form->key.length, NULL);
2925         cpt_fc_auth_set_key(ctx, auth_type, NULL, 0, a_form->digest_length);
2926
2927         return 0;
2928 }
2929
2930 static __rte_always_inline void *
2931 alloc_op_meta(struct rte_mbuf *m_src,
2932               buf_ptr_t *buf,
2933               int32_t len,
2934               struct rte_mempool *cpt_meta_pool)
2935 {
2936         uint8_t *mdata;
2937
2938 #ifndef CPT_ALWAYS_USE_SEPARATE_BUF
2939         if (likely(m_src && (m_src->nb_segs == 1))) {
2940                 int32_t tailroom;
2941                 phys_addr_t mphys;
2942
2943                 /* Check if tailroom is sufficient to hold meta data */
2944                 tailroom = rte_pktmbuf_tailroom(m_src);
2945                 if (likely(tailroom > len + 8)) {
2946                         mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;
2947                         mphys = m_src->buf_physaddr + m_src->buf_len;
2948                         mdata -= len;
2949                         mphys -= len;
2950                         buf->vaddr = mdata;
2951                         buf->dma_addr = mphys;
2952                         buf->size = len;
2953                         /* Indicate that this is a mbuf allocated mdata */
2954                         mdata = (uint8_t *)((uint64_t)mdata | 1ull);
2955                         return mdata;
2956                 }
2957         }
2958 #else
2959         RTE_SET_USED(m_src);
2960 #endif
2961
2962         if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))
2963                 return NULL;
2964
2965         buf->vaddr = mdata;
2966         buf->dma_addr = rte_mempool_virt2iova(mdata);
2967         buf->size = len;
2968
2969         return mdata;
2970 }
2971
2972 /**
2973  * cpt_free_metabuf - free metabuf to mempool.
2974  * @param instance: pointer to instance.
2975  * @param objp: pointer to the metabuf.
2976  */
2977 static __rte_always_inline void
2978 free_op_meta(void *mdata, struct rte_mempool *cpt_meta_pool)
2979 {
2980         bool nofree = ((uintptr_t)mdata & 1ull);
2981
2982         if (likely(nofree))
2983                 return;
2984         rte_mempool_put(cpt_meta_pool, mdata);
2985 }
2986
2987 static __rte_always_inline uint32_t
2988 prepare_iov_from_pkt(struct rte_mbuf *pkt,
2989                      iov_ptr_t *iovec, uint32_t start_offset)
2990 {
2991         uint16_t index = 0;
2992         void *seg_data = NULL;
2993         phys_addr_t seg_phys;
2994         int32_t seg_size = 0;
2995
2996         if (!pkt) {
2997                 iovec->buf_cnt = 0;
2998                 return 0;
2999         }
3000
3001         if (!start_offset) {
3002                 seg_data = rte_pktmbuf_mtod(pkt, void *);
3003                 seg_phys = rte_pktmbuf_mtophys(pkt);
3004                 seg_size = pkt->data_len;
3005         } else {
3006                 while (start_offset >= pkt->data_len) {
3007                         start_offset -= pkt->data_len;
3008                         pkt = pkt->next;
3009                 }
3010
3011                 seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);
3012                 seg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset);
3013                 seg_size = pkt->data_len - start_offset;
3014                 if (!seg_size)
3015                         return 1;
3016         }
3017
3018         /* first seg */
3019         iovec->bufs[index].vaddr = seg_data;
3020         iovec->bufs[index].dma_addr = seg_phys;
3021         iovec->bufs[index].size = seg_size;
3022         index++;
3023         pkt = pkt->next;
3024
3025         while (unlikely(pkt != NULL)) {
3026                 seg_data = rte_pktmbuf_mtod(pkt, void *);
3027                 seg_phys = rte_pktmbuf_mtophys(pkt);
3028                 seg_size = pkt->data_len;
3029                 if (!seg_size)
3030                         break;
3031
3032                 iovec->bufs[index].vaddr = seg_data;
3033                 iovec->bufs[index].dma_addr = seg_phys;
3034                 iovec->bufs[index].size = seg_size;
3035
3036                 index++;
3037
3038                 pkt = pkt->next;
3039         }
3040
3041         iovec->buf_cnt = index;
3042         return 0;
3043 }
3044
3045 static __rte_always_inline uint32_t
3046 prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,
3047                              fc_params_t *param,
3048                              uint32_t *flags)
3049 {
3050         uint16_t index = 0;
3051         void *seg_data = NULL;
3052         phys_addr_t seg_phys;
3053         uint32_t seg_size = 0;
3054         iov_ptr_t *iovec;
3055
3056         seg_data = rte_pktmbuf_mtod(pkt, void *);
3057         seg_phys = rte_pktmbuf_mtophys(pkt);
3058         seg_size = pkt->data_len;
3059
3060         /* first seg */
3061         if (likely(!pkt->next)) {
3062                 uint32_t headroom, tailroom;
3063
3064                 *flags |= SINGLE_BUF_INPLACE;
3065                 headroom = rte_pktmbuf_headroom(pkt);
3066                 tailroom = rte_pktmbuf_tailroom(pkt);
3067                 if (likely((headroom >= 24) &&
3068                     (tailroom >= 8))) {
3069                         /* In 83XX this is prerequivisit for Direct mode */
3070                         *flags |= SINGLE_BUF_HEADTAILROOM;
3071                 }
3072                 param->bufs[0].vaddr = seg_data;
3073                 param->bufs[0].dma_addr = seg_phys;
3074                 param->bufs[0].size = seg_size;
3075                 return 0;
3076         }
3077         iovec = param->src_iov;
3078         iovec->bufs[index].vaddr = seg_data;
3079         iovec->bufs[index].dma_addr = seg_phys;
3080         iovec->bufs[index].size = seg_size;
3081         index++;
3082         pkt = pkt->next;
3083
3084         while (unlikely(pkt != NULL)) {
3085                 seg_data = rte_pktmbuf_mtod(pkt, void *);
3086                 seg_phys = rte_pktmbuf_mtophys(pkt);
3087                 seg_size = pkt->data_len;
3088
3089                 if (!seg_size)
3090                         break;
3091
3092                 iovec->bufs[index].vaddr = seg_data;
3093                 iovec->bufs[index].dma_addr = seg_phys;
3094                 iovec->bufs[index].size = seg_size;
3095
3096                 index++;
3097
3098                 pkt = pkt->next;
3099         }
3100
3101         iovec->buf_cnt = index;
3102         return 0;
3103 }
3104
3105 static __rte_always_inline int
3106 fill_fc_params(struct rte_crypto_op *cop,
3107                struct cpt_sess_misc *sess_misc,
3108                struct cpt_qp_meta_info *m_info,
3109                void **mdata_ptr,
3110                void **prep_req)
3111 {
3112         uint32_t space = 0;
3113         struct rte_crypto_sym_op *sym_op = cop->sym;
3114         void *mdata = NULL;
3115         uintptr_t *op;
3116         uint32_t mc_hash_off;
3117         uint32_t flags = 0;
3118         uint64_t d_offs, d_lens;
3119         struct rte_mbuf *m_src, *m_dst;
3120         uint8_t cpt_op = sess_misc->cpt_op;
3121         uint8_t zsk_flag = sess_misc->zsk_flag;
3122         uint8_t aes_gcm = sess_misc->aes_gcm;
3123         uint16_t mac_len = sess_misc->mac_len;
3124 #ifdef CPT_ALWAYS_USE_SG_MODE
3125         uint8_t inplace = 0;
3126 #else
3127         uint8_t inplace = 1;
3128 #endif
3129         fc_params_t fc_params;
3130         char src[SRC_IOV_SIZE];
3131         char dst[SRC_IOV_SIZE];
3132         uint32_t iv_buf[4];
3133         int ret;
3134
3135         if (likely(sess_misc->iv_length)) {
3136                 flags |= VALID_IV_BUF;
3137                 fc_params.iv_buf = rte_crypto_op_ctod_offset(cop,
3138                                    uint8_t *, sess_misc->iv_offset);
3139                 if (sess_misc->aes_ctr &&
3140                     unlikely(sess_misc->iv_length != 16)) {
3141                         memcpy((uint8_t *)iv_buf,
3142                                 rte_crypto_op_ctod_offset(cop,
3143                                 uint8_t *, sess_misc->iv_offset), 12);
3144                         iv_buf[3] = rte_cpu_to_be_32(0x1);
3145                         fc_params.iv_buf = iv_buf;
3146                 }
3147         }
3148
3149         if (zsk_flag) {
3150                 fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3151                                         uint8_t *,
3152                                         sess_misc->auth_iv_offset);
3153                 if (zsk_flag == K_F9) {
3154                         CPT_LOG_DP_ERR("Should not reach here for "
3155                         "kasumi F9\n");
3156                 }
3157                 if (zsk_flag != ZS_EA)
3158                         inplace = 0;
3159         }
3160         m_src = sym_op->m_src;
3161         m_dst = sym_op->m_dst;
3162
3163         if (aes_gcm) {
3164                 uint8_t *salt;
3165                 uint8_t *aad_data;
3166                 uint16_t aad_len;
3167
3168                 d_offs = sym_op->aead.data.offset;
3169                 d_lens = sym_op->aead.data.length;
3170                 mc_hash_off = sym_op->aead.data.offset +
3171                               sym_op->aead.data.length;
3172
3173                 aad_data = sym_op->aead.aad.data;
3174                 aad_len = sess_misc->aad_length;
3175                 if (likely((aad_data + aad_len) ==
3176                            rte_pktmbuf_mtod_offset(m_src,
3177                                 uint8_t *,
3178                                 sym_op->aead.data.offset))) {
3179                         d_offs = (d_offs - aad_len) | (d_offs << 16);
3180                         d_lens = (d_lens + aad_len) | (d_lens << 32);
3181                 } else {
3182                         fc_params.aad_buf.vaddr = sym_op->aead.aad.data;
3183                         fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;
3184                         fc_params.aad_buf.size = aad_len;
3185                         flags |= VALID_AAD_BUF;
3186                         inplace = 0;
3187                         d_offs = d_offs << 16;
3188                         d_lens = d_lens << 32;
3189                 }
3190
3191                 salt = fc_params.iv_buf;
3192                 if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3193                         cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3194                         sess_misc->salt = *(uint32_t *)salt;
3195                 }
3196                 fc_params.iv_buf = salt + 4;
3197                 if (likely(mac_len)) {
3198                         struct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst :
3199                                              m_src;
3200
3201                         if (!m)
3202                                 m = m_src;
3203
3204                         /* hmac immediately following data is best case */
3205                         if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3206                             mc_hash_off !=
3207                             (uint8_t *)sym_op->aead.digest.data)) {
3208                                 flags |= VALID_MAC_BUF;
3209                                 fc_params.mac_buf.size = sess_misc->mac_len;
3210                                 fc_params.mac_buf.vaddr =
3211                                   sym_op->aead.digest.data;
3212                                 fc_params.mac_buf.dma_addr =
3213                                  sym_op->aead.digest.phys_addr;
3214                                 inplace = 0;
3215                         }
3216                 }
3217         } else {
3218                 d_offs = sym_op->cipher.data.offset;
3219                 d_lens = sym_op->cipher.data.length;
3220                 mc_hash_off = sym_op->cipher.data.offset +
3221                               sym_op->cipher.data.length;
3222                 d_offs = (d_offs << 16) | sym_op->auth.data.offset;
3223                 d_lens = (d_lens << 32) | sym_op->auth.data.length;
3224
3225                 if (mc_hash_off < (sym_op->auth.data.offset +
3226                                    sym_op->auth.data.length)){
3227                         mc_hash_off = (sym_op->auth.data.offset +
3228                                        sym_op->auth.data.length);
3229                 }
3230                 /* for gmac, salt should be updated like in gcm */
3231                 if (unlikely(sess_misc->is_gmac)) {
3232                         uint8_t *salt;
3233                         salt = fc_params.iv_buf;
3234                         if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3235                                 cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3236                                 sess_misc->salt = *(uint32_t *)salt;
3237                         }
3238                         fc_params.iv_buf = salt + 4;
3239                 }
3240                 if (likely(mac_len)) {
3241                         struct rte_mbuf *m;
3242
3243                         m = (cpt_op & CPT_OP_ENCODE) ? m_dst : m_src;
3244                         if (!m)
3245                                 m = m_src;
3246
3247                         /* hmac immediately following data is best case */
3248                         if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3249                             mc_hash_off !=
3250                              (uint8_t *)sym_op->auth.digest.data)) {
3251                                 flags |= VALID_MAC_BUF;
3252                                 fc_params.mac_buf.size =
3253                                         sess_misc->mac_len;
3254                                 fc_params.mac_buf.vaddr =
3255                                         sym_op->auth.digest.data;
3256                                 fc_params.mac_buf.dma_addr =
3257                                 sym_op->auth.digest.phys_addr;
3258                                 inplace = 0;
3259                         }
3260                 }
3261         }
3262         fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);
3263         fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;
3264
3265         if (unlikely(sess_misc->is_null || sess_misc->cpt_op == CPT_OP_DECODE))
3266                 inplace = 0;
3267
3268         if (likely(!m_dst && inplace)) {
3269                 /* Case of single buffer without AAD buf or
3270                  * separate mac buf in place and
3271                  * not air crypto
3272                  */
3273                 fc_params.dst_iov = fc_params.src_iov = (void *)src;
3274
3275                 if (unlikely(prepare_iov_from_pkt_inplace(m_src,
3276                                                           &fc_params,
3277                                                           &flags))) {
3278                         CPT_LOG_DP_ERR("Prepare inplace src iov failed");
3279                         ret = -EINVAL;
3280                         goto err_exit;
3281                 }
3282
3283         } else {
3284                 /* Out of place processing */
3285                 fc_params.src_iov = (void *)src;
3286                 fc_params.dst_iov = (void *)dst;
3287
3288                 /* Store SG I/O in the api for reuse */
3289                 if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {
3290                         CPT_LOG_DP_ERR("Prepare src iov failed");
3291                         ret = -EINVAL;
3292                         goto err_exit;
3293                 }
3294
3295                 if (unlikely(m_dst != NULL)) {
3296                         uint32_t pkt_len;
3297
3298                         /* Try to make room as much as src has */
3299                         m_dst = sym_op->m_dst;
3300                         pkt_len = rte_pktmbuf_pkt_len(m_dst);
3301
3302                         if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {
3303                                 pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;
3304                                 if (!rte_pktmbuf_append(m_dst, pkt_len)) {
3305                                         CPT_LOG_DP_ERR("Not enough space in "
3306                                                        "m_dst %p, need %u"
3307                                                        " more",
3308                                                        m_dst, pkt_len);
3309                                         ret = -EINVAL;
3310                                         goto err_exit;
3311                                 }
3312                         }
3313
3314                         if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {
3315                                 CPT_LOG_DP_ERR("Prepare dst iov failed for "
3316                                                "m_dst %p", m_dst);
3317                                 ret = -EINVAL;
3318                                 goto err_exit;
3319                         }
3320                 } else {
3321                         fc_params.dst_iov = (void *)src;
3322                 }
3323         }
3324
3325         if (likely(flags & SINGLE_BUF_HEADTAILROOM))
3326                 mdata = alloc_op_meta(m_src, &fc_params.meta_buf,
3327                                       m_info->lb_mlen, m_info->pool);
3328         else
3329                 mdata = alloc_op_meta(NULL, &fc_params.meta_buf,
3330                                       m_info->sg_mlen, m_info->pool);
3331
3332         if (unlikely(mdata == NULL)) {
3333                 CPT_LOG_DP_ERR("Error allocating meta buffer for request");
3334                 ret = -ENOMEM;
3335                 goto err_exit;
3336         }
3337
3338         op = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull);
3339         op[0] = (uintptr_t)mdata;
3340         op[1] = (uintptr_t)cop;
3341         op[2] = op[3] = 0; /* Used to indicate auth verify */
3342         space += 4 * sizeof(uint64_t);
3343
3344         fc_params.meta_buf.vaddr = (uint8_t *)op + space;
3345         fc_params.meta_buf.dma_addr += space;
3346         fc_params.meta_buf.size -= space;
3347
3348         /* Finally prepare the instruction */
3349         if (cpt_op & CPT_OP_ENCODE)
3350                 *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
3351                                                  &fc_params, op);
3352         else
3353                 *prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,
3354                                                  &fc_params, op);
3355
3356         if (unlikely(*prep_req == NULL)) {
3357                 CPT_LOG_DP_ERR("Preparing request failed due to bad input arg");
3358                 ret = -EINVAL;
3359                 goto free_mdata_and_exit;
3360         }
3361
3362         *mdata_ptr = mdata;
3363
3364         return 0;
3365
3366 free_mdata_and_exit:
3367         free_op_meta(mdata, m_info->pool);
3368 err_exit:
3369         return ret;
3370 }
3371
3372 static __rte_always_inline void
3373 compl_auth_verify(struct rte_crypto_op *op,
3374                       uint8_t *gen_mac,
3375                       uint64_t mac_len)
3376 {
3377         uint8_t *mac;
3378         struct rte_crypto_sym_op *sym_op = op->sym;
3379
3380         if (sym_op->auth.digest.data)
3381                 mac = sym_op->auth.digest.data;
3382         else
3383                 mac = rte_pktmbuf_mtod_offset(sym_op->m_src,
3384                                               uint8_t *,
3385                                               sym_op->auth.data.length +
3386                                               sym_op->auth.data.offset);
3387         if (!mac) {
3388                 op->status = RTE_CRYPTO_OP_STATUS_ERROR;
3389                 return;
3390         }
3391
3392         if (memcmp(mac, gen_mac, mac_len))
3393                 op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
3394         else
3395                 op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
3396 }
3397
3398 static __rte_always_inline int
3399 instance_session_cfg(struct rte_crypto_sym_xform *xform, void *sess)
3400 {
3401         struct rte_crypto_sym_xform *chain;
3402
3403         CPT_PMD_INIT_FUNC_TRACE();
3404
3405         if (cpt_is_algo_supported(xform))
3406                 goto err;
3407
3408         chain = xform;
3409         while (chain) {
3410                 switch (chain->type) {
3411                 case RTE_CRYPTO_SYM_XFORM_AEAD:
3412                         if (fill_sess_aead(chain, sess))
3413                                 goto err;
3414                         break;
3415                 case RTE_CRYPTO_SYM_XFORM_CIPHER:
3416                         if (fill_sess_cipher(chain, sess))
3417                                 goto err;
3418                         break;
3419                 case RTE_CRYPTO_SYM_XFORM_AUTH:
3420                         if (chain->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC) {
3421                                 if (fill_sess_gmac(chain, sess))
3422                                         goto err;
3423                         } else {
3424                                 if (fill_sess_auth(chain, sess))
3425                                         goto err;
3426                         }
3427                         break;
3428                 default:
3429                         CPT_LOG_DP_ERR("Invalid crypto xform type");
3430                         break;
3431                 }
3432                 chain = chain->next;
3433         }
3434
3435         return 0;
3436
3437 err:
3438         return -1;
3439 }
3440
3441 static __rte_always_inline void
3442 find_kasumif9_direction_and_length(uint8_t *src,
3443                                    uint32_t counter_num_bytes,
3444                                    uint32_t *addr_length_in_bits,
3445                                    uint8_t *addr_direction)
3446 {
3447         uint8_t found = 0;
3448         uint32_t pos;
3449         uint8_t last_byte;
3450         while (!found && counter_num_bytes > 0) {
3451                 counter_num_bytes--;
3452                 if (src[counter_num_bytes] == 0x00)
3453                         continue;
3454                 pos = rte_bsf32(src[counter_num_bytes]);
3455                 if (pos == 7) {
3456                         if (likely(counter_num_bytes > 0)) {
3457                                 last_byte = src[counter_num_bytes - 1];
3458                                 *addr_direction  =  last_byte & 0x1;
3459                                 *addr_length_in_bits = counter_num_bytes * 8
3460                                                         - 1;
3461                         }
3462                 } else {
3463                         last_byte = src[counter_num_bytes];
3464                         *addr_direction = (last_byte >> (pos + 1)) & 0x1;
3465                         *addr_length_in_bits = counter_num_bytes * 8
3466                                                 + (8 - (pos + 2));
3467                 }
3468                 found = 1;
3469         }
3470 }
3471
3472 /*
3473  * This handles all auth only except AES_GMAC
3474  */
3475 static __rte_always_inline int
3476 fill_digest_params(struct rte_crypto_op *cop,
3477                    struct cpt_sess_misc *sess,
3478                    struct cpt_qp_meta_info *m_info,
3479                    void **mdata_ptr,
3480                    void **prep_req)
3481 {
3482         uint32_t space = 0;
3483         struct rte_crypto_sym_op *sym_op = cop->sym;
3484         void *mdata;
3485         phys_addr_t mphys;
3486         uint64_t *op;
3487         uint32_t auth_range_off;
3488         uint32_t flags = 0;
3489         uint64_t d_offs = 0, d_lens;
3490         struct rte_mbuf *m_src, *m_dst;
3491         uint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK;
3492         uint8_t zsk_flag = sess->zsk_flag;
3493         uint16_t mac_len = sess->mac_len;
3494         fc_params_t params;
3495         char src[SRC_IOV_SIZE];
3496         uint8_t iv_buf[16];
3497         int ret;
3498
3499         memset(&params, 0, sizeof(fc_params_t));
3500
3501         m_src = sym_op->m_src;
3502
3503         /* For just digest lets force mempool alloc */
3504         mdata = alloc_op_meta(NULL, &params.meta_buf, m_info->sg_mlen,
3505                               m_info->pool);
3506         if (mdata == NULL) {
3507                 ret = -ENOMEM;
3508                 goto err_exit;
3509         }
3510
3511         mphys = params.meta_buf.dma_addr;
3512
3513         op = mdata;
3514         op[0] = (uintptr_t)mdata;
3515         op[1] = (uintptr_t)cop;
3516         op[2] = op[3] = 0; /* Used to indicate auth verify */
3517         space += 4 * sizeof(uint64_t);
3518
3519         auth_range_off = sym_op->auth.data.offset;
3520
3521         flags = VALID_MAC_BUF;
3522         params.src_iov = (void *)src;
3523         if (unlikely(zsk_flag)) {
3524                 /*
3525                  * Since for Zuc, Kasumi, Snow3g offsets are in bits
3526                  * we will send pass through even for auth only case,
3527                  * let MC handle it
3528                  */
3529                 d_offs = auth_range_off;
3530                 auth_range_off = 0;
3531                 params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3532                                         uint8_t *, sess->auth_iv_offset);
3533                 if (zsk_flag == K_F9) {
3534                         uint32_t length_in_bits, num_bytes;
3535                         uint8_t *src, direction = 0;
3536                         uint32_t counter_num_bytes;
3537
3538                         memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,
3539                                                         uint8_t *), 8);
3540                         /*
3541                          * This is kasumi f9, take direction from
3542                          * source buffer
3543                          */
3544                         length_in_bits = cop->sym->auth.data.length;
3545                         num_bytes = (length_in_bits >> 3);
3546                         counter_num_bytes = num_bytes;
3547                         src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);
3548                         find_kasumif9_direction_and_length(src,
3549                                                 counter_num_bytes,
3550                                                 &length_in_bits,
3551                                                 &direction);
3552                         length_in_bits -= 64;
3553                         cop->sym->auth.data.offset += 64;
3554                         d_offs = cop->sym->auth.data.offset;
3555                         auth_range_off = d_offs / 8;
3556                         cop->sym->auth.data.length = length_in_bits;
3557
3558                         /* Store it at end of auth iv */
3559                         iv_buf[8] = direction;
3560                         params.auth_iv_buf = iv_buf;
3561                 }
3562         }
3563
3564         d_lens = sym_op->auth.data.length;
3565
3566         params.ctx_buf.vaddr = SESS_PRIV(sess);
3567         params.ctx_buf.dma_addr = sess->ctx_dma_addr;
3568
3569         if (auth_op == CPT_OP_AUTH_GENERATE) {
3570                 if (sym_op->auth.digest.data) {
3571                         /*
3572                          * Digest to be generated
3573                          * in separate buffer
3574                          */
3575                         params.mac_buf.size =
3576                                 sess->mac_len;
3577                         params.mac_buf.vaddr =
3578                                 sym_op->auth.digest.data;
3579                         params.mac_buf.dma_addr =
3580                                 sym_op->auth.digest.phys_addr;
3581                 } else {
3582                         uint32_t off = sym_op->auth.data.offset +
3583                                 sym_op->auth.data.length;
3584                         int32_t dlen, space;
3585
3586                         m_dst = sym_op->m_dst ?
3587                                 sym_op->m_dst : sym_op->m_src;
3588                         dlen = rte_pktmbuf_pkt_len(m_dst);
3589
3590                         space = off + mac_len - dlen;
3591                         if (space > 0)
3592                                 if (!rte_pktmbuf_append(m_dst, space)) {
3593                                         CPT_LOG_DP_ERR("Failed to extend "
3594                                                        "mbuf by %uB", space);
3595                                         ret = -EINVAL;
3596                                         goto free_mdata_and_exit;
3597                                 }
3598
3599                         params.mac_buf.vaddr =
3600                                 rte_pktmbuf_mtod_offset(m_dst, void *, off);
3601                         params.mac_buf.dma_addr =
3602                                 rte_pktmbuf_mtophys_offset(m_dst, off);
3603                         params.mac_buf.size = mac_len;
3604                 }
3605         } else {
3606                 /* Need space for storing generated mac */
3607                 params.mac_buf.vaddr = (uint8_t *)mdata + space;
3608                 params.mac_buf.dma_addr = mphys + space;
3609                 params.mac_buf.size = mac_len;
3610                 space += RTE_ALIGN_CEIL(mac_len, 8);
3611                 op[2] = (uintptr_t)params.mac_buf.vaddr;
3612                 op[3] = mac_len;
3613         }
3614
3615         params.meta_buf.vaddr = (uint8_t *)mdata + space;
3616         params.meta_buf.dma_addr = mphys + space;
3617         params.meta_buf.size -= space;
3618
3619         /* Out of place processing */
3620         params.src_iov = (void *)src;
3621
3622         /*Store SG I/O in the api for reuse */
3623         if (prepare_iov_from_pkt(m_src, params.src_iov, auth_range_off)) {
3624                 CPT_LOG_DP_ERR("Prepare src iov failed");
3625                 ret = -EINVAL;
3626                 goto free_mdata_and_exit;
3627         }
3628
3629         *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, &params, op);
3630         if (unlikely(*prep_req == NULL)) {
3631                 ret = -EINVAL;
3632                 goto free_mdata_and_exit;
3633         }
3634
3635         *mdata_ptr = mdata;
3636
3637         return 0;
3638
3639 free_mdata_and_exit:
3640         free_op_meta(mdata, m_info->pool);
3641 err_exit:
3642         return ret;
3643 }
3644
3645 #endif /*_CPT_UCODE_H_ */