drivers/common/cpt/cpt_ucode.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Cavium, Inc
   3  */
   4
   5 #ifndef _CPT_UCODE_H_
   6 #define _CPT_UCODE_H_
   7 #include <stdbool.h>
   8
   9 #include "cpt_common.h"
  10 #include "cpt_hw_types.h"
  11 #include "cpt_mcode_defines.h"
  12
  13 /*
  14  * This file defines functions that are interfaces to microcode spec.
  15  *
  16  */
  17
  18 static uint8_t zuc_d[32] = {
  19         0x44, 0xD7, 0x26, 0xBC, 0x62, 0x6B, 0x13, 0x5E,
  20         0x57, 0x89, 0x35, 0xE2, 0x71, 0x35, 0x09, 0xAF,
  21         0x4D, 0x78, 0x2F, 0x13, 0x6B, 0xC4, 0x1A, 0xF1,
  22         0x5E, 0x26, 0x3C, 0x4D, 0x78, 0x9A, 0x47, 0xAC
  23 };
  24
  25 static __rte_always_inline void
  26 gen_key_snow3g(const uint8_t *ck, uint32_t *keyx)
  27 {
  28         int i, base;
  29
  30         for (i = 0; i < 4; i++) {
  31                 base = 4 * i;
  32                 keyx[3 - i] = (ck[base] << 24) | (ck[base + 1] << 16) |
  33                         (ck[base + 2] << 8) | (ck[base + 3]);
  34                 keyx[3 - i] = rte_cpu_to_be_32(keyx[3 - i]);
  35         }
  36 }
  37
  38 static __rte_always_inline void
  39 cpt_fc_salt_update(void *ctx,
  40                    uint8_t *salt)
  41 {
  42         struct cpt_ctx *cpt_ctx = ctx;
  43         memcpy(&cpt_ctx->fctx.enc.encr_iv, salt, 4);
  44 }
  45
  46 static __rte_always_inline int
  47 cpt_fc_ciph_validate_key_aes(uint16_t key_len)
  48 {
  49         switch (key_len) {
  50         case CPT_BYTE_16:
  51         case CPT_BYTE_24:
  52         case CPT_BYTE_32:
  53                 return 0;
  54         default:
  55                 return -1;
  56         }
  57 }
  58
  59 static __rte_always_inline int
  60 cpt_fc_ciph_set_type(cipher_type_t type, struct cpt_ctx *ctx, uint16_t key_len)
  61 {
  62         int fc_type = 0;
  63         switch (type) {
  64         case PASSTHROUGH:
  65                 fc_type = FC_GEN;
  66                 break;
  67         case DES3_CBC:
  68         case DES3_ECB:
  69                 fc_type = FC_GEN;
  70                 break;
  71         case AES_CBC:
  72         case AES_ECB:
  73         case AES_CFB:
  74         case AES_CTR:
  75         case AES_GCM:
  76                 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
  77                         return -1;
  78                 fc_type = FC_GEN;
  79                 break;
  80         case AES_XTS:
  81                 key_len = key_len / 2;
  82                 if (unlikely(key_len == CPT_BYTE_24)) {
  83                         CPT_LOG_DP_ERR("Invalid AES key len for XTS");
  84                         return -1;
  85                 }
  86                 if (unlikely(cpt_fc_ciph_validate_key_aes(key_len) != 0))
  87                         return -1;
  88                 fc_type = FC_GEN;
  89                 break;
  90         case ZUC_EEA3:
  91         case SNOW3G_UEA2:
  92                 if (unlikely(key_len != 16))
  93                         return -1;
  94                 /* No support for AEAD yet */
  95                 if (unlikely(ctx->hash_type))
  96                         return -1;
  97                 fc_type = ZUC_SNOW3G;
  98                 break;
  99         case KASUMI_F8_CBC:
 100         case KASUMI_F8_ECB:
 101                 if (unlikely(key_len != 16))
 102                         return -1;
 103                 /* No support for AEAD yet */
 104                 if (unlikely(ctx->hash_type))
 105                         return -1;
 106                 fc_type = KASUMI;
 107                 break;
 108         default:
 109                 return -1;
 110         }
 111
 112         ctx->fc_type = fc_type;
 113         return 0;
 114 }
 115
 116 static __rte_always_inline void
 117 cpt_fc_ciph_set_key_passthrough(struct cpt_ctx *cpt_ctx, mc_fc_context_t *fctx)
 118 {
 119         cpt_ctx->enc_cipher = 0;
 120         fctx->enc.enc_cipher = 0;
 121 }
 122
 123 static __rte_always_inline void
 124 cpt_fc_ciph_set_key_set_aes_key_type(mc_fc_context_t *fctx, uint16_t key_len)
 125 {
 126         mc_aes_type_t aes_key_type = 0;
 127         switch (key_len) {
 128         case CPT_BYTE_16:
 129                 aes_key_type = AES_128_BIT;
 130                 break;
 131         case CPT_BYTE_24:
 132                 aes_key_type = AES_192_BIT;
 133                 break;
 134         case CPT_BYTE_32:
 135                 aes_key_type = AES_256_BIT;
 136                 break;
 137         default:
 138                 /* This should not happen */
 139                 CPT_LOG_DP_ERR("Invalid AES key len");
 140                 return;
 141         }
 142         fctx->enc.aes_key = aes_key_type;
 143 }
 144
 145 static __rte_always_inline void
 146 cpt_fc_ciph_set_key_snow3g_uea2(struct cpt_ctx *cpt_ctx, const uint8_t *key,
 147                 uint16_t key_len)
 148 {
 149         uint32_t keyx[4];
 150         cpt_ctx->snow3g = 1;
 151         gen_key_snow3g(key, keyx);
 152         memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
 153         cpt_ctx->zsk_flags = 0;
 154 }
 155
 156 static __rte_always_inline void
 157 cpt_fc_ciph_set_key_zuc_eea3(struct cpt_ctx *cpt_ctx, const uint8_t *key,
 158                 uint16_t key_len)
 159 {
 160         cpt_ctx->snow3g = 0;
 161         memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
 162         memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
 163         cpt_ctx->zsk_flags = 0;
 164 }
 165
 166 static __rte_always_inline void
 167 cpt_fc_ciph_set_key_kasumi_f8_ecb(struct cpt_ctx *cpt_ctx, const uint8_t *key,
 168                 uint16_t key_len)
 169 {
 170         cpt_ctx->k_ecb = 1;
 171         memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
 172         cpt_ctx->zsk_flags = 0;
 173 }
 174
 175 static __rte_always_inline void
 176 cpt_fc_ciph_set_key_kasumi_f8_cbc(struct cpt_ctx *cpt_ctx, const uint8_t *key,
 177                 uint16_t key_len)
 178 {
 179         memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
 180         cpt_ctx->zsk_flags = 0;
 181 }
 182
 183 static __rte_always_inline int
 184 cpt_fc_ciph_set_key(void *ctx, cipher_type_t type, const uint8_t *key,
 185                     uint16_t key_len, uint8_t *salt)
 186 {
 187         struct cpt_ctx *cpt_ctx = ctx;
 188         mc_fc_context_t *fctx = &cpt_ctx->fctx;
 189         int ret;
 190
 191         ret = cpt_fc_ciph_set_type(type, cpt_ctx, key_len);
 192         if (unlikely(ret))
 193                 return -1;
 194
 195         if (cpt_ctx->fc_type == FC_GEN) {
 196                 /*
 197                  * We need to always say IV is from DPTR as user can
 198                  * sometimes iverride IV per operation.
 199                  */
 200                 fctx->enc.iv_source = CPT_FROM_DPTR;
 201
 202                 if (cpt_ctx->auth_key_len > 64)
 203                         return -1;
 204         }
 205
 206         switch (type) {
 207         case PASSTHROUGH:
 208                 cpt_fc_ciph_set_key_passthrough(cpt_ctx, fctx);
 209                 goto success;
 210         case DES3_CBC:
 211                 /* CPT performs DES using 3DES with the 8B DES-key
 212                  * replicated 2 more times to match the 24B 3DES-key.
 213                  * Eg. If org. key is "0x0a 0x0b", then new key is
 214                  * "0x0a 0x0b 0x0a 0x0b 0x0a 0x0b"
 215                  */
 216                 if (key_len == 8) {
 217                         /* Skipping the first 8B as it will be copied
 218                          * in the regular code flow
 219                          */
 220                         memcpy(fctx->enc.encr_key+key_len, key, key_len);
 221                         memcpy(fctx->enc.encr_key+2*key_len, key, key_len);
 222                 }
 223                 break;
 224         case DES3_ECB:
 225                 /* For DES3_ECB IV need to be from CTX. */
 226                 fctx->enc.iv_source = CPT_FROM_CTX;
 227                 break;
 228         case AES_CBC:
 229         case AES_ECB:
 230         case AES_CFB:
 231         case AES_CTR:
 232                 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 233                 break;
 234         case AES_GCM:
 235                 /* Even though iv source is from dptr,
 236                  * aes_gcm salt is taken from ctx
 237                  */
 238                 if (salt) {
 239                         memcpy(fctx->enc.encr_iv, salt, 4);
 240                         /* Assuming it was just salt update
 241                          * and nothing else
 242                          */
 243                         if (!key)
 244                                 goto success;
 245                 }
 246                 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 247                 break;
 248         case AES_XTS:
 249                 key_len = key_len / 2;
 250                 cpt_fc_ciph_set_key_set_aes_key_type(fctx, key_len);
 251
 252                 /* Copy key2 for XTS into ipad */
 253                 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
 254                 memcpy(fctx->hmac.ipad, &key[key_len], key_len);
 255                 break;
 256         case SNOW3G_UEA2:
 257                 cpt_fc_ciph_set_key_snow3g_uea2(cpt_ctx, key, key_len);
 258                 goto success;
 259         case ZUC_EEA3:
 260                 cpt_fc_ciph_set_key_zuc_eea3(cpt_ctx, key, key_len);
 261                 goto success;
 262         case KASUMI_F8_ECB:
 263                 cpt_fc_ciph_set_key_kasumi_f8_ecb(cpt_ctx, key, key_len);
 264                 goto success;
 265         case KASUMI_F8_CBC:
 266                 cpt_fc_ciph_set_key_kasumi_f8_cbc(cpt_ctx, key, key_len);
 267                 goto success;
 268         default:
 269                 return -1;
 270         }
 271
 272         /* Only for FC_GEN case */
 273
 274         /* For GMAC auth, cipher must be NULL */
 275         if (cpt_ctx->hash_type != GMAC_TYPE)
 276                 fctx->enc.enc_cipher = type;
 277
 278         memcpy(fctx->enc.encr_key, key, key_len);
 279
 280 success:
 281         cpt_ctx->enc_cipher = type;
 282
 283         return 0;
 284 }
 285
 286 static __rte_always_inline uint32_t
 287 fill_sg_comp(sg_comp_t *list,
 288              uint32_t i,
 289              phys_addr_t dma_addr,
 290              uint32_t size)
 291 {
 292         sg_comp_t *to = &list[i>>2];
 293
 294         to->u.s.len[i%4] = rte_cpu_to_be_16(size);
 295         to->ptr[i%4] = rte_cpu_to_be_64(dma_addr);
 296         i++;
 297         return i;
 298 }
 299
 300 static __rte_always_inline uint32_t
 301 fill_sg_comp_from_buf(sg_comp_t *list,
 302                       uint32_t i,
 303                       buf_ptr_t *from)
 304 {
 305         sg_comp_t *to = &list[i>>2];
 306
 307         to->u.s.len[i%4] = rte_cpu_to_be_16(from->size);
 308         to->ptr[i%4] = rte_cpu_to_be_64(from->dma_addr);
 309         i++;
 310         return i;
 311 }
 312
 313 static __rte_always_inline uint32_t
 314 fill_sg_comp_from_buf_min(sg_comp_t *list,
 315                           uint32_t i,
 316                           buf_ptr_t *from,
 317                           uint32_t *psize)
 318 {
 319         sg_comp_t *to = &list[i >> 2];
 320         uint32_t size = *psize;
 321         uint32_t e_len;
 322
 323         e_len = (size > from->size) ? from->size : size;
 324         to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 325         to->ptr[i % 4] = rte_cpu_to_be_64(from->dma_addr);
 326         *psize -= e_len;
 327         i++;
 328         return i;
 329 }
 330
 331 /*
 332  * This fills the MC expected SGIO list
 333  * from IOV given by user.
 334  */
 335 static __rte_always_inline uint32_t
 336 fill_sg_comp_from_iov(sg_comp_t *list,
 337                       uint32_t i,
 338                       iov_ptr_t *from, uint32_t from_offset,
 339                       uint32_t *psize, buf_ptr_t *extra_buf,
 340                       uint32_t extra_offset)
 341 {
 342         int32_t j;
 343         uint32_t extra_len = extra_buf ? extra_buf->size : 0;
 344         uint32_t size = *psize;
 345         buf_ptr_t *bufs;
 346
 347         bufs = from->bufs;
 348         for (j = 0; (j < from->buf_cnt) && size; j++) {
 349                 phys_addr_t e_dma_addr;
 350                 uint32_t e_len;
 351                 sg_comp_t *to = &list[i >> 2];
 352
 353                 if (unlikely(from_offset)) {
 354                         if (from_offset >= bufs[j].size) {
 355                                 from_offset -= bufs[j].size;
 356                                 continue;
 357                         }
 358                         e_dma_addr = bufs[j].dma_addr + from_offset;
 359                         e_len = (size > (bufs[j].size - from_offset)) ?
 360                                 (bufs[j].size - from_offset) : size;
 361                         from_offset = 0;
 362                 } else {
 363                         e_dma_addr = bufs[j].dma_addr;
 364                         e_len = (size > bufs[j].size) ?
 365                                 bufs[j].size : size;
 366                 }
 367
 368                 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 369                 to->ptr[i % 4] = rte_cpu_to_be_64(e_dma_addr);
 370
 371                 if (extra_len && (e_len >= extra_offset)) {
 372                         /* Break the data at given offset */
 373                         uint32_t next_len = e_len - extra_offset;
 374                         phys_addr_t next_dma = e_dma_addr + extra_offset;
 375
 376                         if (!extra_offset) {
 377                                 i--;
 378                         } else {
 379                                 e_len = extra_offset;
 380                                 size -= e_len;
 381                                 to->u.s.len[i % 4] = rte_cpu_to_be_16(e_len);
 382                         }
 383
 384                         extra_len = RTE_MIN(extra_len, size);
 385                         /* Insert extra data ptr */
 386                         if (extra_len) {
 387                                 i++;
 388                                 to = &list[i >> 2];
 389                                 to->u.s.len[i % 4] =
 390                                         rte_cpu_to_be_16(extra_len);
 391                                 to->ptr[i % 4] =
 392                                         rte_cpu_to_be_64(extra_buf->dma_addr);
 393                                 size -= extra_len;
 394                         }
 395
 396                         next_len = RTE_MIN(next_len, size);
 397                         /* insert the rest of the data */
 398                         if (next_len) {
 399                                 i++;
 400                                 to = &list[i >> 2];
 401                                 to->u.s.len[i % 4] = rte_cpu_to_be_16(next_len);
 402                                 to->ptr[i % 4] = rte_cpu_to_be_64(next_dma);
 403                                 size -= next_len;
 404                         }
 405                         extra_len = 0;
 406
 407                 } else {
 408                         size -= e_len;
 409                 }
 410                 if (extra_offset)
 411                         extra_offset -= size;
 412                 i++;
 413         }
 414
 415         *psize = size;
 416         return (uint32_t)i;
 417 }
 418
 419 static __rte_always_inline void
 420 cpt_digest_gen_prep(uint32_t flags,
 421                     uint64_t d_lens,
 422                     digest_params_t *params,
 423                     void *op,
 424                     void **prep_req)
 425 {
 426         struct cpt_request_info *req;
 427         uint32_t size, i;
 428         uint16_t data_len, mac_len, key_len;
 429         auth_type_t hash_type;
 430         buf_ptr_t *meta_p;
 431         struct cpt_ctx *ctx;
 432         sg_comp_t *gather_comp;
 433         sg_comp_t *scatter_comp;
 434         uint8_t *in_buffer;
 435         uint32_t g_size_bytes, s_size_bytes;
 436         uint64_t dptr_dma, rptr_dma;
 437         vq_cmd_word0_t vq_cmd_w0;
 438         vq_cmd_word3_t vq_cmd_w3;
 439         void *c_vaddr, *m_vaddr;
 440         uint64_t c_dma, m_dma;
 441         opcode_info_t opcode;
 442
 443         ctx = params->ctx_buf.vaddr;
 444         meta_p = &params->meta_buf;
 445
 446         m_vaddr = meta_p->vaddr;
 447         m_dma = meta_p->dma_addr;
 448
 449         /*
 450          * Save initial space that followed app data for completion code &
 451          * alternate completion code to fall in same cache line as app data
 452          */
 453         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
 454         m_dma += COMPLETION_CODE_SIZE;
 455         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
 456                 (uint8_t *)m_vaddr;
 457         c_vaddr = (uint8_t *)m_vaddr + size;
 458         c_dma = m_dma + size;
 459         size += sizeof(cpt_res_s_t);
 460
 461         m_vaddr = (uint8_t *)m_vaddr + size;
 462         m_dma += size;
 463
 464         req = m_vaddr;
 465
 466         size = sizeof(struct cpt_request_info);
 467         m_vaddr = (uint8_t *)m_vaddr + size;
 468         m_dma += size;
 469
 470         hash_type = ctx->hash_type;
 471         mac_len = ctx->mac_len;
 472         key_len = ctx->auth_key_len;
 473         data_len = AUTH_DLEN(d_lens);
 474
 475         /*GP op header */
 476         vq_cmd_w0.u64 = 0;
 477         vq_cmd_w0.s.param2 = ((uint16_t)hash_type << 8);
 478         if (ctx->hmac) {
 479                 opcode.s.major = CPT_MAJOR_OP_HMAC | CPT_DMA_MODE;
 480                 vq_cmd_w0.s.param1 = key_len;
 481                 vq_cmd_w0.s.dlen = data_len + ROUNDUP8(key_len);
 482         } else {
 483                 opcode.s.major = CPT_MAJOR_OP_HASH | CPT_DMA_MODE;
 484                 vq_cmd_w0.s.param1 = 0;
 485                 vq_cmd_w0.s.dlen = data_len;
 486         }
 487
 488         opcode.s.minor = 0;
 489
 490         /* Null auth only case enters the if */
 491         if (unlikely(!hash_type && !ctx->enc_cipher)) {
 492                 opcode.s.major = CPT_MAJOR_OP_MISC;
 493                 /* Minor op is passthrough */
 494                 opcode.s.minor = 0x03;
 495                 /* Send out completion code only */
 496                 vq_cmd_w0.s.param2 = 0x1;
 497         }
 498
 499         vq_cmd_w0.s.opcode = opcode.flags;
 500
 501         /* DPTR has SG list */
 502         in_buffer = m_vaddr;
 503         dptr_dma = m_dma;
 504
 505         ((uint16_t *)in_buffer)[0] = 0;
 506         ((uint16_t *)in_buffer)[1] = 0;
 507
 508         /* TODO Add error check if space will be sufficient */
 509         gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
 510
 511         /*
 512          * Input gather list
 513          */
 514
 515         i = 0;
 516
 517         if (ctx->hmac) {
 518                 uint64_t k_dma = params->ctx_buf.dma_addr +
 519                         offsetof(struct cpt_ctx, auth_key);
 520                 /* Key */
 521                 i = fill_sg_comp(gather_comp, i, k_dma, ROUNDUP8(key_len));
 522         }
 523
 524         /* input data */
 525         size = data_len;
 526         if (size) {
 527                 i = fill_sg_comp_from_iov(gather_comp, i, params->src_iov,
 528                                           0, &size, NULL, 0);
 529                 if (unlikely(size)) {
 530                         CPT_LOG_DP_DEBUG("Insufficient dst IOV size, short"
 531                                          " by %dB", size);
 532                         return;
 533                 }
 534         } else {
 535                 /*
 536                  * Looks like we need to support zero data
 537                  * gather ptr in case of hash & hmac
 538                  */
 539                 i++;
 540         }
 541         ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
 542         g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 543
 544         /*
 545          * Output Gather list
 546          */
 547
 548         i = 0;
 549         scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
 550
 551         if (flags & VALID_MAC_BUF) {
 552                 if (unlikely(params->mac_buf.size < mac_len)) {
 553                         CPT_LOG_DP_ERR("Insufficient MAC size");
 554                         return;
 555                 }
 556
 557                 size = mac_len;
 558                 i = fill_sg_comp_from_buf_min(scatter_comp, i,
 559                                               &params->mac_buf, &size);
 560         } else {
 561                 size = mac_len;
 562                 i = fill_sg_comp_from_iov(scatter_comp, i,
 563                                           params->src_iov, data_len,
 564                                           &size, NULL, 0);
 565                 if (unlikely(size)) {
 566                         CPT_LOG_DP_ERR("Insufficient dst IOV size, short by"
 567                                        " %dB", size);
 568                         return;
 569                 }
 570         }
 571
 572         ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
 573         s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 574
 575         size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
 576
 577         /* This is DPTR len incase of SG mode */
 578         vq_cmd_w0.s.dlen = size;
 579
 580         m_vaddr = (uint8_t *)m_vaddr + size;
 581         m_dma += size;
 582
 583         /* cpt alternate completion address saved earlier */
 584         req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
 585         *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
 586         rptr_dma = c_dma - 8;
 587
 588         req->ist.ei1 = dptr_dma;
 589         req->ist.ei2 = rptr_dma;
 590
 591         /* vq command w3 */
 592         vq_cmd_w3.u64 = 0;
 593
 594         /* 16 byte aligned cpt res address */
 595         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
 596         *req->completion_addr = COMPLETION_CODE_INIT;
 597         req->comp_baddr  = c_dma;
 598
 599         /* Fill microcode part of instruction */
 600         req->ist.ei0 = vq_cmd_w0.u64;
 601         req->ist.ei3 = vq_cmd_w3.u64;
 602
 603         req->op = op;
 604
 605         *prep_req = req;
 606         return;
 607 }
 608
 609 static __rte_always_inline void
 610 cpt_enc_hmac_prep(uint32_t flags,
 611                   uint64_t d_offs,
 612                   uint64_t d_lens,
 613                   fc_params_t *fc_params,
 614                   void *op,
 615                   void **prep_req)
 616 {
 617         uint32_t iv_offset = 0;
 618         int32_t inputlen, outputlen, enc_dlen, auth_dlen;
 619         struct cpt_ctx *cpt_ctx;
 620         uint32_t cipher_type, hash_type;
 621         uint32_t mac_len, size;
 622         uint8_t iv_len = 16;
 623         struct cpt_request_info *req;
 624         buf_ptr_t *meta_p, *aad_buf = NULL;
 625         uint32_t encr_offset, auth_offset;
 626         uint32_t encr_data_len, auth_data_len, aad_len = 0;
 627         uint32_t passthrough_len = 0;
 628         void *m_vaddr, *offset_vaddr;
 629         uint64_t m_dma, offset_dma, ctx_dma;
 630         vq_cmd_word0_t vq_cmd_w0;
 631         vq_cmd_word3_t vq_cmd_w3;
 632         void *c_vaddr;
 633         uint64_t c_dma;
 634         opcode_info_t opcode;
 635
 636         meta_p = &fc_params->meta_buf;
 637         m_vaddr = meta_p->vaddr;
 638         m_dma = meta_p->dma_addr;
 639
 640         encr_offset = ENCR_OFFSET(d_offs);
 641         auth_offset = AUTH_OFFSET(d_offs);
 642         encr_data_len = ENCR_DLEN(d_lens);
 643         auth_data_len = AUTH_DLEN(d_lens);
 644         if (unlikely(flags & VALID_AAD_BUF)) {
 645                 /*
 646                  * We dont support both aad
 647                  * and auth data separately
 648                  */
 649                 auth_data_len = 0;
 650                 auth_offset = 0;
 651                 aad_len = fc_params->aad_buf.size;
 652                 aad_buf = &fc_params->aad_buf;
 653         }
 654         cpt_ctx = fc_params->ctx_buf.vaddr;
 655         cipher_type = cpt_ctx->enc_cipher;
 656         hash_type = cpt_ctx->hash_type;
 657         mac_len = cpt_ctx->mac_len;
 658
 659         /*
 660          * Save initial space that followed app data for completion code &
 661          * alternate completion code to fall in same cache line as app data
 662          */
 663         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
 664         m_dma += COMPLETION_CODE_SIZE;
 665         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
 666                 (uint8_t *)m_vaddr;
 667
 668         c_vaddr = (uint8_t *)m_vaddr + size;
 669         c_dma = m_dma + size;
 670         size += sizeof(cpt_res_s_t);
 671
 672         m_vaddr = (uint8_t *)m_vaddr + size;
 673         m_dma += size;
 674
 675         /* start cpt request info struct at 8 byte boundary */
 676         size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
 677                 (uint8_t *)m_vaddr;
 678
 679         req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
 680
 681         size += sizeof(struct cpt_request_info);
 682         m_vaddr = (uint8_t *)m_vaddr + size;
 683         m_dma += size;
 684
 685         if (hash_type == GMAC_TYPE)
 686                 encr_data_len = 0;
 687
 688         if (unlikely(!(flags & VALID_IV_BUF))) {
 689                 iv_len = 0;
 690                 iv_offset = ENCR_IV_OFFSET(d_offs);
 691         }
 692
 693         if (unlikely(flags & VALID_AAD_BUF)) {
 694                 /*
 695                  * When AAD is given, data above encr_offset is pass through
 696                  * Since AAD is given as separate pointer and not as offset,
 697                  * this is a special case as we need to fragment input data
 698                  * into passthrough + encr_data and then insert AAD in between.
 699                  */
 700                 if (hash_type != GMAC_TYPE) {
 701                         passthrough_len = encr_offset;
 702                         auth_offset = passthrough_len + iv_len;
 703                         encr_offset = passthrough_len + aad_len + iv_len;
 704                         auth_data_len = aad_len + encr_data_len;
 705                 } else {
 706                         passthrough_len = 16 + aad_len;
 707                         auth_offset = passthrough_len + iv_len;
 708                         auth_data_len = aad_len;
 709                 }
 710         } else {
 711                 encr_offset += iv_len;
 712                 auth_offset += iv_len;
 713         }
 714
 715         /* Encryption */
 716         opcode.s.major = CPT_MAJOR_OP_FC;
 717         opcode.s.minor = 0;
 718
 719         auth_dlen = auth_offset + auth_data_len;
 720         enc_dlen = encr_data_len + encr_offset;
 721         if (unlikely(encr_data_len & 0xf)) {
 722                 if ((cipher_type == DES3_CBC) || (cipher_type == DES3_ECB))
 723                         enc_dlen = ROUNDUP8(encr_data_len) + encr_offset;
 724                 else if (likely((cipher_type == AES_CBC) ||
 725                                 (cipher_type == AES_ECB)))
 726                         enc_dlen = ROUNDUP16(encr_data_len) + encr_offset;
 727         }
 728
 729         if (unlikely(hash_type == GMAC_TYPE)) {
 730                 encr_offset = auth_dlen;
 731                 enc_dlen = 0;
 732         }
 733
 734         if (unlikely(auth_dlen > enc_dlen)) {
 735                 inputlen = auth_dlen;
 736                 outputlen = auth_dlen + mac_len;
 737         } else {
 738                 inputlen = enc_dlen;
 739                 outputlen = enc_dlen + mac_len;
 740         }
 741
 742         /* GP op header */
 743         vq_cmd_w0.u64 = 0;
 744         vq_cmd_w0.s.param1 = encr_data_len;
 745         vq_cmd_w0.s.param2 = auth_data_len;
 746         /*
 747          * In 83XX since we have a limitation of
 748          * IV & Offset control word not part of instruction
 749          * and need to be part of Data Buffer, we check if
 750          * head room is there and then only do the Direct mode processing
 751          */
 752         if (likely((flags & SINGLE_BUF_INPLACE) &&
 753                    (flags & SINGLE_BUF_HEADTAILROOM))) {
 754                 void *dm_vaddr = fc_params->bufs[0].vaddr;
 755                 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
 756                 /*
 757                  * This flag indicates that there is 24 bytes head room and
 758                  * 8 bytes tail room available, so that we get to do
 759                  * DIRECT MODE with limitation
 760                  */
 761
 762                 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
 763                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
 764
 765                 /* DPTR */
 766                 req->ist.ei1 = offset_dma;
 767                 /* RPTR should just exclude offset control word */
 768                 req->ist.ei2 = dm_dma_addr - iv_len;
 769                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
 770                                                     + outputlen - iv_len);
 771
 772                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
 773
 774                 vq_cmd_w0.s.opcode = opcode.flags;
 775
 776                 if (likely(iv_len)) {
 777                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
 778                                                       + OFF_CTRL_LEN);
 779                         uint64_t *src = fc_params->iv_buf;
 780                         dest[0] = src[0];
 781                         dest[1] = src[1];
 782                 }
 783
 784                 *(uint64_t *)offset_vaddr =
 785                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
 786                                 ((uint64_t)iv_offset << 8) |
 787                                 ((uint64_t)auth_offset));
 788
 789         } else {
 790                 uint32_t i, g_size_bytes, s_size_bytes;
 791                 uint64_t dptr_dma, rptr_dma;
 792                 sg_comp_t *gather_comp;
 793                 sg_comp_t *scatter_comp;
 794                 uint8_t *in_buffer;
 795
 796                 /* This falls under strict SG mode */
 797                 offset_vaddr = m_vaddr;
 798                 offset_dma = m_dma;
 799                 size = OFF_CTRL_LEN + iv_len;
 800
 801                 m_vaddr = (uint8_t *)m_vaddr + size;
 802                 m_dma += size;
 803
 804                 opcode.s.major |= CPT_DMA_MODE;
 805
 806                 vq_cmd_w0.s.opcode = opcode.flags;
 807
 808                 if (likely(iv_len)) {
 809                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr
 810                                                       + OFF_CTRL_LEN);
 811                         uint64_t *src = fc_params->iv_buf;
 812                         dest[0] = src[0];
 813                         dest[1] = src[1];
 814                 }
 815
 816                 *(uint64_t *)offset_vaddr =
 817                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
 818                                 ((uint64_t)iv_offset << 8) |
 819                                 ((uint64_t)auth_offset));
 820
 821                 /* DPTR has SG list */
 822                 in_buffer = m_vaddr;
 823                 dptr_dma = m_dma;
 824
 825                 ((uint16_t *)in_buffer)[0] = 0;
 826                 ((uint16_t *)in_buffer)[1] = 0;
 827
 828                 /* TODO Add error check if space will be sufficient */
 829                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
 830
 831                 /*
 832                  * Input Gather List
 833                  */
 834
 835                 i = 0;
 836
 837                 /* Offset control word that includes iv */
 838                 i = fill_sg_comp(gather_comp, i, offset_dma,
 839                                  OFF_CTRL_LEN + iv_len);
 840
 841                 /* Add input data */
 842                 size = inputlen - iv_len;
 843                 if (likely(size)) {
 844                         uint32_t aad_offset = aad_len ? passthrough_len : 0;
 845
 846                         if (unlikely(flags & SINGLE_BUF_INPLACE)) {
 847                                 i = fill_sg_comp_from_buf_min(gather_comp, i,
 848                                                               fc_params->bufs,
 849                                                               &size);
 850                         } else {
 851                                 i = fill_sg_comp_from_iov(gather_comp, i,
 852                                                           fc_params->src_iov,
 853                                                           0, &size,
 854                                                           aad_buf, aad_offset);
 855                         }
 856
 857                         if (unlikely(size)) {
 858                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
 859                                                " size %d needed", size);
 860                                 return;
 861                         }
 862                 }
 863                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
 864                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 865
 866                 /*
 867                  * Output Scatter list
 868                  */
 869                 i = 0;
 870                 scatter_comp =
 871                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
 872
 873                 /* Add IV */
 874                 if (likely(iv_len)) {
 875                         i = fill_sg_comp(scatter_comp, i,
 876                                          offset_dma + OFF_CTRL_LEN,
 877                                          iv_len);
 878                 }
 879
 880                 /* output data or output data + digest*/
 881                 if (unlikely(flags & VALID_MAC_BUF)) {
 882                         size = outputlen - iv_len - mac_len;
 883                         if (size) {
 884                                 uint32_t aad_offset =
 885                                         aad_len ? passthrough_len : 0;
 886
 887                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
 888                                         i = fill_sg_comp_from_buf_min(
 889                                                         scatter_comp,
 890                                                         i,
 891                                                         fc_params->bufs,
 892                                                         &size);
 893                                 } else {
 894                                         i = fill_sg_comp_from_iov(scatter_comp,
 895                                                         i,
 896                                                         fc_params->dst_iov,
 897                                                         0,
 898                                                         &size,
 899                                                         aad_buf,
 900                                                         aad_offset);
 901                                 }
 902                                 if (unlikely(size)) {
 903                                         CPT_LOG_DP_ERR("Insufficient buffer"
 904                                                        " space, size %d needed",
 905                                                        size);
 906                                         return;
 907                                 }
 908                         }
 909                         /* mac_data */
 910                         if (mac_len) {
 911                                 i = fill_sg_comp_from_buf(scatter_comp, i,
 912                                                           &fc_params->mac_buf);
 913                         }
 914                 } else {
 915                         /* Output including mac */
 916                         size = outputlen - iv_len;
 917                         if (likely(size)) {
 918                                 uint32_t aad_offset =
 919                                         aad_len ? passthrough_len : 0;
 920
 921                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
 922                                         i = fill_sg_comp_from_buf_min(
 923                                                         scatter_comp,
 924                                                         i,
 925                                                         fc_params->bufs,
 926                                                         &size);
 927                                 } else {
 928                                         i = fill_sg_comp_from_iov(scatter_comp,
 929                                                         i,
 930                                                         fc_params->dst_iov,
 931                                                         0,
 932                                                         &size,
 933                                                         aad_buf,
 934                                                         aad_offset);
 935                                 }
 936                                 if (unlikely(size)) {
 937                                         CPT_LOG_DP_ERR("Insufficient buffer"
 938                                                        " space, size %d needed",
 939                                                        size);
 940                                         return;
 941                                 }
 942                         }
 943                 }
 944                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
 945                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
 946
 947                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
 948
 949                 /* This is DPTR len incase of SG mode */
 950                 vq_cmd_w0.s.dlen = size;
 951
 952                 m_vaddr = (uint8_t *)m_vaddr + size;
 953                 m_dma += size;
 954
 955                 /* cpt alternate completion address saved earlier */
 956                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
 957                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
 958                 rptr_dma = c_dma - 8;
 959
 960                 req->ist.ei1 = dptr_dma;
 961                 req->ist.ei2 = rptr_dma;
 962         }
 963
 964         ctx_dma = fc_params->ctx_buf.dma_addr +
 965                 offsetof(struct cpt_ctx, fctx);
 966         /* vq command w3 */
 967         vq_cmd_w3.u64 = 0;
 968         vq_cmd_w3.s.grp = 0;
 969         vq_cmd_w3.s.cptr = ctx_dma;
 970
 971         /* 16 byte aligned cpt res address */
 972         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
 973         *req->completion_addr = COMPLETION_CODE_INIT;
 974         req->comp_baddr  = c_dma;
 975
 976         /* Fill microcode part of instruction */
 977         req->ist.ei0 = vq_cmd_w0.u64;
 978         req->ist.ei3 = vq_cmd_w3.u64;
 979
 980         req->op  = op;
 981
 982         *prep_req = req;
 983         return;
 984 }
 985
 986 static __rte_always_inline void
 987 cpt_dec_hmac_prep(uint32_t flags,
 988                   uint64_t d_offs,
 989                   uint64_t d_lens,
 990                   fc_params_t *fc_params,
 991                   void *op,
 992                   void **prep_req)
 993 {
 994         uint32_t iv_offset = 0, size;
 995         int32_t inputlen, outputlen, enc_dlen, auth_dlen;
 996         struct cpt_ctx *cpt_ctx;
 997         int32_t hash_type, mac_len;
 998         uint8_t iv_len = 16;
 999         struct cpt_request_info *req;
1000         buf_ptr_t *meta_p, *aad_buf = NULL;
1001         uint32_t encr_offset, auth_offset;
1002         uint32_t encr_data_len, auth_data_len, aad_len = 0;
1003         uint32_t passthrough_len = 0;
1004         void *m_vaddr, *offset_vaddr;
1005         uint64_t m_dma, offset_dma, ctx_dma;
1006         opcode_info_t opcode;
1007         vq_cmd_word0_t vq_cmd_w0;
1008         vq_cmd_word3_t vq_cmd_w3;
1009         void *c_vaddr;
1010         uint64_t c_dma;
1011
1012         meta_p = &fc_params->meta_buf;
1013         m_vaddr = meta_p->vaddr;
1014         m_dma = meta_p->dma_addr;
1015
1016         encr_offset = ENCR_OFFSET(d_offs);
1017         auth_offset = AUTH_OFFSET(d_offs);
1018         encr_data_len = ENCR_DLEN(d_lens);
1019         auth_data_len = AUTH_DLEN(d_lens);
1020
1021         if (unlikely(flags & VALID_AAD_BUF)) {
1022                 /*
1023                  * We dont support both aad
1024                  * and auth data separately
1025                  */
1026                 auth_data_len = 0;
1027                 auth_offset = 0;
1028                 aad_len = fc_params->aad_buf.size;
1029                 aad_buf = &fc_params->aad_buf;
1030         }
1031
1032         cpt_ctx = fc_params->ctx_buf.vaddr;
1033         hash_type = cpt_ctx->hash_type;
1034         mac_len = cpt_ctx->mac_len;
1035
1036         if (hash_type == GMAC_TYPE)
1037                 encr_data_len = 0;
1038
1039         if (unlikely(!(flags & VALID_IV_BUF))) {
1040                 iv_len = 0;
1041                 iv_offset = ENCR_IV_OFFSET(d_offs);
1042         }
1043
1044         if (unlikely(flags & VALID_AAD_BUF)) {
1045                 /*
1046                  * When AAD is given, data above encr_offset is pass through
1047                  * Since AAD is given as separate pointer and not as offset,
1048                  * this is a special case as we need to fragment input data
1049                  * into passthrough + encr_data and then insert AAD in between.
1050                  */
1051                 if (hash_type != GMAC_TYPE) {
1052                         passthrough_len = encr_offset;
1053                         auth_offset = passthrough_len + iv_len;
1054                         encr_offset = passthrough_len + aad_len + iv_len;
1055                         auth_data_len = aad_len + encr_data_len;
1056                 } else {
1057                         passthrough_len = 16 + aad_len;
1058                         auth_offset = passthrough_len + iv_len;
1059                         auth_data_len = aad_len;
1060                 }
1061         } else {
1062                 encr_offset += iv_len;
1063                 auth_offset += iv_len;
1064         }
1065
1066         /*
1067          * Save initial space that followed app data for completion code &
1068          * alternate completion code to fall in same cache line as app data
1069          */
1070         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1071         m_dma += COMPLETION_CODE_SIZE;
1072         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1073                (uint8_t *)m_vaddr;
1074         c_vaddr = (uint8_t *)m_vaddr + size;
1075         c_dma = m_dma + size;
1076         size += sizeof(cpt_res_s_t);
1077
1078         m_vaddr = (uint8_t *)m_vaddr + size;
1079         m_dma += size;
1080
1081         /* start cpt request info structure at 8 byte alignment */
1082         size = (uint8_t *)RTE_PTR_ALIGN(m_vaddr, 8) -
1083                 (uint8_t *)m_vaddr;
1084
1085         req = (struct cpt_request_info *)((uint8_t *)m_vaddr + size);
1086
1087         size += sizeof(struct cpt_request_info);
1088         m_vaddr = (uint8_t *)m_vaddr + size;
1089         m_dma += size;
1090
1091         /* Decryption */
1092         opcode.s.major = CPT_MAJOR_OP_FC;
1093         opcode.s.minor = 1;
1094
1095         enc_dlen = encr_offset + encr_data_len;
1096         auth_dlen = auth_offset + auth_data_len;
1097
1098         if (auth_dlen > enc_dlen) {
1099                 inputlen = auth_dlen + mac_len;
1100                 outputlen = auth_dlen;
1101         } else {
1102                 inputlen = enc_dlen + mac_len;
1103                 outputlen = enc_dlen;
1104         }
1105
1106         if (hash_type == GMAC_TYPE)
1107                 encr_offset = inputlen;
1108
1109         vq_cmd_w0.u64 = 0;
1110         vq_cmd_w0.s.param1 = encr_data_len;
1111         vq_cmd_w0.s.param2 = auth_data_len;
1112
1113         /*
1114          * In 83XX since we have a limitation of
1115          * IV & Offset control word not part of instruction
1116          * and need to be part of Data Buffer, we check if
1117          * head room is there and then only do the Direct mode processing
1118          */
1119         if (likely((flags & SINGLE_BUF_INPLACE) &&
1120                    (flags & SINGLE_BUF_HEADTAILROOM))) {
1121                 void *dm_vaddr = fc_params->bufs[0].vaddr;
1122                 uint64_t dm_dma_addr = fc_params->bufs[0].dma_addr;
1123                 /*
1124                  * This flag indicates that there is 24 bytes head room and
1125                  * 8 bytes tail room available, so that we get to do
1126                  * DIRECT MODE with limitation
1127                  */
1128
1129                 offset_vaddr = (uint8_t *)dm_vaddr - OFF_CTRL_LEN - iv_len;
1130                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1131                 req->ist.ei1 = offset_dma;
1132
1133                 /* RPTR should just exclude offset control word */
1134                 req->ist.ei2 = dm_dma_addr - iv_len;
1135
1136                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr +
1137                                         outputlen - iv_len);
1138                 /* since this is decryption,
1139                  * don't touch the content of
1140                  * alternate ccode space as it contains
1141                  * hmac.
1142                  */
1143
1144                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1145
1146                 vq_cmd_w0.s.opcode = opcode.flags;
1147
1148                 if (likely(iv_len)) {
1149                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1150                                                       OFF_CTRL_LEN);
1151                         uint64_t *src = fc_params->iv_buf;
1152                         dest[0] = src[0];
1153                         dest[1] = src[1];
1154                 }
1155
1156                 *(uint64_t *)offset_vaddr =
1157                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1158                                 ((uint64_t)iv_offset << 8) |
1159                                 ((uint64_t)auth_offset));
1160
1161         } else {
1162                 uint64_t dptr_dma, rptr_dma;
1163                 uint32_t g_size_bytes, s_size_bytes;
1164                 sg_comp_t *gather_comp;
1165                 sg_comp_t *scatter_comp;
1166                 uint8_t *in_buffer;
1167                 uint8_t i = 0;
1168
1169                 /* This falls under strict SG mode */
1170                 offset_vaddr = m_vaddr;
1171                 offset_dma = m_dma;
1172                 size = OFF_CTRL_LEN + iv_len;
1173
1174                 m_vaddr = (uint8_t *)m_vaddr + size;
1175                 m_dma += size;
1176
1177                 opcode.s.major |= CPT_DMA_MODE;
1178
1179                 vq_cmd_w0.s.opcode = opcode.flags;
1180
1181                 if (likely(iv_len)) {
1182                         uint64_t *dest = (uint64_t *)((uint8_t *)offset_vaddr +
1183                                                       OFF_CTRL_LEN);
1184                         uint64_t *src = fc_params->iv_buf;
1185                         dest[0] = src[0];
1186                         dest[1] = src[1];
1187                 }
1188
1189                 *(uint64_t *)offset_vaddr =
1190                         rte_cpu_to_be_64(((uint64_t)encr_offset << 16) |
1191                                 ((uint64_t)iv_offset << 8) |
1192                                 ((uint64_t)auth_offset));
1193
1194                 /* DPTR has SG list */
1195                 in_buffer = m_vaddr;
1196                 dptr_dma = m_dma;
1197
1198                 ((uint16_t *)in_buffer)[0] = 0;
1199                 ((uint16_t *)in_buffer)[1] = 0;
1200
1201                 /* TODO Add error check if space will be sufficient */
1202                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1203
1204                 /*
1205                  * Input Gather List
1206                  */
1207                 i = 0;
1208
1209                 /* Offset control word that includes iv */
1210                 i = fill_sg_comp(gather_comp, i, offset_dma,
1211                                  OFF_CTRL_LEN + iv_len);
1212
1213                 /* Add input data */
1214                 if (flags & VALID_MAC_BUF) {
1215                         size = inputlen - iv_len - mac_len;
1216                         if (size) {
1217                                 /* input data only */
1218                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1219                                         i = fill_sg_comp_from_buf_min(
1220                                                         gather_comp, i,
1221                                                         fc_params->bufs,
1222                                                         &size);
1223                                 } else {
1224                                         uint32_t aad_offset = aad_len ?
1225                                                 passthrough_len : 0;
1226
1227                                         i = fill_sg_comp_from_iov(gather_comp,
1228                                                         i,
1229                                                         fc_params->src_iov,
1230                                                         0, &size,
1231                                                         aad_buf,
1232                                                         aad_offset);
1233                                 }
1234                                 if (unlikely(size)) {
1235                                         CPT_LOG_DP_ERR("Insufficient buffer"
1236                                                        " space, size %d needed",
1237                                                        size);
1238                                         return;
1239                                 }
1240                         }
1241
1242                         /* mac data */
1243                         if (mac_len) {
1244                                 i = fill_sg_comp_from_buf(gather_comp, i,
1245                                                           &fc_params->mac_buf);
1246                         }
1247                 } else {
1248                         /* input data + mac */
1249                         size = inputlen - iv_len;
1250                         if (size) {
1251                                 if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1252                                         i = fill_sg_comp_from_buf_min(
1253                                                         gather_comp, i,
1254                                                         fc_params->bufs,
1255                                                         &size);
1256                                 } else {
1257                                         uint32_t aad_offset = aad_len ?
1258                                                 passthrough_len : 0;
1259
1260                                         if (unlikely(!fc_params->src_iov)) {
1261                                                 CPT_LOG_DP_ERR("Bad input args");
1262                                                 return;
1263                                         }
1264
1265                                         i = fill_sg_comp_from_iov(
1266                                                         gather_comp, i,
1267                                                         fc_params->src_iov,
1268                                                         0, &size,
1269                                                         aad_buf,
1270                                                         aad_offset);
1271                                 }
1272
1273                                 if (unlikely(size)) {
1274                                         CPT_LOG_DP_ERR("Insufficient buffer"
1275                                                        " space, size %d needed",
1276                                                        size);
1277                                         return;
1278                                 }
1279                         }
1280                 }
1281                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1282                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1283
1284                 /*
1285                  * Output Scatter List
1286                  */
1287
1288                 i = 0;
1289                 scatter_comp =
1290                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1291
1292                 /* Add iv */
1293                 if (iv_len) {
1294                         i = fill_sg_comp(scatter_comp, i,
1295                                          offset_dma + OFF_CTRL_LEN,
1296                                          iv_len);
1297                 }
1298
1299                 /* Add output data */
1300                 size = outputlen - iv_len;
1301                 if (size) {
1302                         if (unlikely(flags & SINGLE_BUF_INPLACE)) {
1303                                 /* handle single buffer here */
1304                                 i = fill_sg_comp_from_buf_min(scatter_comp, i,
1305                                                               fc_params->bufs,
1306                                                               &size);
1307                         } else {
1308                                 uint32_t aad_offset = aad_len ?
1309                                         passthrough_len : 0;
1310
1311                                 if (unlikely(!fc_params->dst_iov)) {
1312                                         CPT_LOG_DP_ERR("Bad input args");
1313                                         return;
1314                                 }
1315
1316                                 i = fill_sg_comp_from_iov(scatter_comp, i,
1317                                                           fc_params->dst_iov, 0,
1318                                                           &size, aad_buf,
1319                                                           aad_offset);
1320                         }
1321
1322                         if (unlikely(size)) {
1323                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1324                                                " size %d needed", size);
1325                                 return;
1326                         }
1327                 }
1328
1329                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1330                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1331
1332                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1333
1334                 /* This is DPTR len incase of SG mode */
1335                 vq_cmd_w0.s.dlen = size;
1336
1337                 m_vaddr = (uint8_t *)m_vaddr + size;
1338                 m_dma += size;
1339
1340                 /* cpt alternate completion address saved earlier */
1341                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1342                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1343                 rptr_dma = c_dma - 8;
1344                 size += COMPLETION_CODE_SIZE;
1345
1346                 req->ist.ei1 = dptr_dma;
1347                 req->ist.ei2 = rptr_dma;
1348         }
1349
1350         ctx_dma = fc_params->ctx_buf.dma_addr +
1351                 offsetof(struct cpt_ctx, fctx);
1352         /* vq command w3 */
1353         vq_cmd_w3.u64 = 0;
1354         vq_cmd_w3.s.grp = 0;
1355         vq_cmd_w3.s.cptr = ctx_dma;
1356
1357         /* 16 byte aligned cpt res address */
1358         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1359         *req->completion_addr = COMPLETION_CODE_INIT;
1360         req->comp_baddr  = c_dma;
1361
1362         /* Fill microcode part of instruction */
1363         req->ist.ei0 = vq_cmd_w0.u64;
1364         req->ist.ei3 = vq_cmd_w3.u64;
1365
1366         req->op = op;
1367
1368         *prep_req = req;
1369         return;
1370 }
1371
1372 static __rte_always_inline void
1373 cpt_zuc_snow3g_enc_prep(uint32_t req_flags,
1374                         uint64_t d_offs,
1375                         uint64_t d_lens,
1376                         fc_params_t *params,
1377                         void *op,
1378                         void **prep_req)
1379 {
1380         uint32_t size;
1381         int32_t inputlen, outputlen;
1382         struct cpt_ctx *cpt_ctx;
1383         uint32_t mac_len = 0;
1384         uint8_t snow3g, j;
1385         struct cpt_request_info *req;
1386         buf_ptr_t *buf_p;
1387         uint32_t encr_offset = 0, auth_offset = 0;
1388         uint32_t encr_data_len = 0, auth_data_len = 0;
1389         int flags, iv_len = 16;
1390         void *m_vaddr, *c_vaddr;
1391         uint64_t m_dma, c_dma, offset_ctrl;
1392         uint64_t *offset_vaddr, offset_dma;
1393         uint32_t *iv_s, iv[4];
1394         vq_cmd_word0_t vq_cmd_w0;
1395         vq_cmd_word3_t vq_cmd_w3;
1396         opcode_info_t opcode;
1397
1398         buf_p = &params->meta_buf;
1399         m_vaddr = buf_p->vaddr;
1400         m_dma = buf_p->dma_addr;
1401
1402         cpt_ctx = params->ctx_buf.vaddr;
1403         flags = cpt_ctx->zsk_flags;
1404         mac_len = cpt_ctx->mac_len;
1405         snow3g = cpt_ctx->snow3g;
1406
1407         /*
1408          * Save initial space that followed app data for completion code &
1409          * alternate completion code to fall in same cache line as app data
1410          */
1411         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1412         m_dma += COMPLETION_CODE_SIZE;
1413         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1414                 (uint8_t *)m_vaddr;
1415
1416         c_vaddr = (uint8_t *)m_vaddr + size;
1417         c_dma = m_dma + size;
1418         size += sizeof(cpt_res_s_t);
1419
1420         m_vaddr = (uint8_t *)m_vaddr + size;
1421         m_dma += size;
1422
1423         /* Reserve memory for cpt request info */
1424         req = m_vaddr;
1425
1426         size = sizeof(struct cpt_request_info);
1427         m_vaddr = (uint8_t *)m_vaddr + size;
1428         m_dma += size;
1429
1430         opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1431
1432         /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1433
1434         opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
1435                           (0 << 3) | (flags & 0x7));
1436
1437         if (flags == 0x1) {
1438                 /*
1439                  * Microcode expects offsets in bytes
1440                  * TODO: Rounding off
1441                  */
1442                 auth_data_len = AUTH_DLEN(d_lens);
1443
1444                 /* EIA3 or UIA2 */
1445                 auth_offset = AUTH_OFFSET(d_offs);
1446                 auth_offset = auth_offset / 8;
1447
1448                 /* consider iv len */
1449                 auth_offset += iv_len;
1450
1451                 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
1452                 outputlen = mac_len;
1453
1454                 offset_ctrl = rte_cpu_to_be_64((uint64_t)auth_offset);
1455
1456         } else {
1457                 /* EEA3 or UEA2 */
1458                 /*
1459                  * Microcode expects offsets in bytes
1460                  * TODO: Rounding off
1461                  */
1462                 encr_data_len = ENCR_DLEN(d_lens);
1463
1464                 encr_offset = ENCR_OFFSET(d_offs);
1465                 encr_offset = encr_offset / 8;
1466                 /* consider iv len */
1467                 encr_offset += iv_len;
1468
1469                 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
1470                 outputlen = inputlen;
1471
1472                 /* iv offset is 0 */
1473                 offset_ctrl = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1474         }
1475
1476         /* IV */
1477         iv_s = (flags == 0x1) ? params->auth_iv_buf :
1478                 params->iv_buf;
1479
1480         if (snow3g) {
1481                 /*
1482                  * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1483                  * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1484                  */
1485
1486                 for (j = 0; j < 4; j++)
1487                         iv[j] = iv_s[3 - j];
1488         } else {
1489                 /* ZUC doesn't need a swap */
1490                 for (j = 0; j < 4; j++)
1491                         iv[j] = iv_s[j];
1492         }
1493
1494         /*
1495          * GP op header, lengths are expected in bits.
1496          */
1497         vq_cmd_w0.u64 = 0;
1498         vq_cmd_w0.s.param1 = encr_data_len;
1499         vq_cmd_w0.s.param2 = auth_data_len;
1500
1501         /*
1502          * In 83XX since we have a limitation of
1503          * IV & Offset control word not part of instruction
1504          * and need to be part of Data Buffer, we check if
1505          * head room is there and then only do the Direct mode processing
1506          */
1507         if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1508                    (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1509                 void *dm_vaddr = params->bufs[0].vaddr;
1510                 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1511                 /*
1512                  * This flag indicates that there is 24 bytes head room and
1513                  * 8 bytes tail room available, so that we get to do
1514                  * DIRECT MODE with limitation
1515                  */
1516
1517                 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1518                                             OFF_CTRL_LEN - iv_len);
1519                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1520
1521                 /* DPTR */
1522                 req->ist.ei1 = offset_dma;
1523                 /* RPTR should just exclude offset control word */
1524                 req->ist.ei2 = dm_dma_addr - iv_len;
1525                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1526                                                     + outputlen - iv_len);
1527
1528                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1529
1530                 vq_cmd_w0.s.opcode = opcode.flags;
1531
1532                 if (likely(iv_len)) {
1533                         uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1534                                                       + OFF_CTRL_LEN);
1535                         memcpy(iv_d, iv, 16);
1536                 }
1537
1538                 *offset_vaddr = offset_ctrl;
1539         } else {
1540                 uint32_t i, g_size_bytes, s_size_bytes;
1541                 uint64_t dptr_dma, rptr_dma;
1542                 sg_comp_t *gather_comp;
1543                 sg_comp_t *scatter_comp;
1544                 uint8_t *in_buffer;
1545                 uint32_t *iv_d;
1546
1547                 /* save space for iv */
1548                 offset_vaddr = m_vaddr;
1549                 offset_dma = m_dma;
1550
1551                 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1552                 m_dma += OFF_CTRL_LEN + iv_len;
1553
1554                 opcode.s.major |= CPT_DMA_MODE;
1555
1556                 vq_cmd_w0.s.opcode = opcode.flags;
1557
1558                 /* DPTR has SG list */
1559                 in_buffer = m_vaddr;
1560                 dptr_dma = m_dma;
1561
1562                 ((uint16_t *)in_buffer)[0] = 0;
1563                 ((uint16_t *)in_buffer)[1] = 0;
1564
1565                 /* TODO Add error check if space will be sufficient */
1566                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1567
1568                 /*
1569                  * Input Gather List
1570                  */
1571                 i = 0;
1572
1573                 /* Offset control word followed by iv */
1574
1575                 i = fill_sg_comp(gather_comp, i, offset_dma,
1576                                  OFF_CTRL_LEN + iv_len);
1577
1578                 /* iv offset is 0 */
1579                 *offset_vaddr = offset_ctrl;
1580
1581                 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1582                 memcpy(iv_d, iv, 16);
1583
1584                 /* input data */
1585                 size = inputlen - iv_len;
1586                 if (size) {
1587                         i = fill_sg_comp_from_iov(gather_comp, i,
1588                                                   params->src_iov,
1589                                                   0, &size, NULL, 0);
1590                         if (unlikely(size)) {
1591                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1592                                                " size %d needed", size);
1593                                 return;
1594                         }
1595                 }
1596                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1597                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1598
1599                 /*
1600                  * Output Scatter List
1601                  */
1602
1603                 i = 0;
1604                 scatter_comp =
1605                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1606
1607                 if (flags == 0x1) {
1608                         /* IV in SLIST only for EEA3 & UEA2 */
1609                         iv_len = 0;
1610                 }
1611
1612                 if (iv_len) {
1613                         i = fill_sg_comp(scatter_comp, i,
1614                                          offset_dma + OFF_CTRL_LEN, iv_len);
1615                 }
1616
1617                 /* Add output data */
1618                 if (req_flags & VALID_MAC_BUF) {
1619                         size = outputlen - iv_len - mac_len;
1620                         if (size) {
1621                                 i = fill_sg_comp_from_iov(scatter_comp, i,
1622                                                           params->dst_iov, 0,
1623                                                           &size, NULL, 0);
1624
1625                                 if (unlikely(size)) {
1626                                         CPT_LOG_DP_ERR("Insufficient buffer space,"
1627                                                        " size %d needed", size);
1628                                         return;
1629                                 }
1630                         }
1631
1632                         /* mac data */
1633                         if (mac_len) {
1634                                 i = fill_sg_comp_from_buf(scatter_comp, i,
1635                                                           &params->mac_buf);
1636                         }
1637                 } else {
1638                         /* Output including mac */
1639                         size = outputlen - iv_len;
1640                         if (size) {
1641                                 i = fill_sg_comp_from_iov(scatter_comp, i,
1642                                                           params->dst_iov, 0,
1643                                                           &size, NULL, 0);
1644
1645                                 if (unlikely(size)) {
1646                                         CPT_LOG_DP_ERR("Insufficient buffer space,"
1647                                                        " size %d needed", size);
1648                                         return;
1649                                 }
1650                         }
1651                 }
1652                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1653                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1654
1655                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1656
1657                 /* This is DPTR len incase of SG mode */
1658                 vq_cmd_w0.s.dlen = size;
1659
1660                 m_vaddr = (uint8_t *)m_vaddr + size;
1661                 m_dma += size;
1662
1663                 /* cpt alternate completion address saved earlier */
1664                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1665                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1666                 rptr_dma = c_dma - 8;
1667
1668                 req->ist.ei1 = dptr_dma;
1669                 req->ist.ei2 = rptr_dma;
1670         }
1671
1672         /* vq command w3 */
1673         vq_cmd_w3.u64 = 0;
1674         vq_cmd_w3.s.grp = 0;
1675         vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
1676                 offsetof(struct cpt_ctx, zs_ctx);
1677
1678         /* 16 byte aligned cpt res address */
1679         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1680         *req->completion_addr = COMPLETION_CODE_INIT;
1681         req->comp_baddr  = c_dma;
1682
1683         /* Fill microcode part of instruction */
1684         req->ist.ei0 = vq_cmd_w0.u64;
1685         req->ist.ei3 = vq_cmd_w3.u64;
1686
1687         req->op = op;
1688
1689         *prep_req = req;
1690         return;
1691 }
1692
1693 static __rte_always_inline void
1694 cpt_zuc_snow3g_dec_prep(uint32_t req_flags,
1695                         uint64_t d_offs,
1696                         uint64_t d_lens,
1697                         fc_params_t *params,
1698                         void *op,
1699                         void **prep_req)
1700 {
1701         uint32_t size;
1702         int32_t inputlen = 0, outputlen;
1703         struct cpt_ctx *cpt_ctx;
1704         uint8_t snow3g, iv_len = 16;
1705         struct cpt_request_info *req;
1706         buf_ptr_t *buf_p;
1707         uint32_t encr_offset;
1708         uint32_t encr_data_len;
1709         int flags;
1710         void *m_vaddr, *c_vaddr;
1711         uint64_t m_dma, c_dma;
1712         uint64_t *offset_vaddr, offset_dma;
1713         uint32_t *iv_s, iv[4], j;
1714         vq_cmd_word0_t vq_cmd_w0;
1715         vq_cmd_word3_t vq_cmd_w3;
1716         opcode_info_t opcode;
1717
1718         buf_p = &params->meta_buf;
1719         m_vaddr = buf_p->vaddr;
1720         m_dma = buf_p->dma_addr;
1721
1722         /*
1723          * Microcode expects offsets in bytes
1724          * TODO: Rounding off
1725          */
1726         encr_offset = ENCR_OFFSET(d_offs) / 8;
1727         encr_data_len = ENCR_DLEN(d_lens);
1728
1729         cpt_ctx = params->ctx_buf.vaddr;
1730         flags = cpt_ctx->zsk_flags;
1731         snow3g = cpt_ctx->snow3g;
1732         /*
1733          * Save initial space that followed app data for completion code &
1734          * alternate completion code to fall in same cache line as app data
1735          */
1736         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
1737         m_dma += COMPLETION_CODE_SIZE;
1738         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
1739                 (uint8_t *)m_vaddr;
1740
1741         c_vaddr = (uint8_t *)m_vaddr + size;
1742         c_dma = m_dma + size;
1743         size += sizeof(cpt_res_s_t);
1744
1745         m_vaddr = (uint8_t *)m_vaddr + size;
1746         m_dma += size;
1747
1748         /* Reserve memory for cpt request info */
1749         req = m_vaddr;
1750
1751         size = sizeof(struct cpt_request_info);
1752         m_vaddr = (uint8_t *)m_vaddr + size;
1753         m_dma += size;
1754
1755         opcode.s.major = CPT_MAJOR_OP_ZUC_SNOW3G;
1756
1757         /* indicates CPTR ctx, operation type, KEY & IV mode from DPTR */
1758
1759         opcode.s.minor = ((1 << 7) | (snow3g << 5) | (0 << 4) |
1760                           (0 << 3) | (flags & 0x7));
1761
1762         /* consider iv len */
1763         encr_offset += iv_len;
1764
1765         inputlen = encr_offset +
1766                 (RTE_ALIGN(encr_data_len, 8) / 8);
1767         outputlen = inputlen;
1768
1769         /* IV */
1770         iv_s = params->iv_buf;
1771         if (snow3g) {
1772                 /*
1773                  * DPDK seems to provide it in form of IV3 IV2 IV1 IV0
1774                  * and BigEndian, MC needs it as IV0 IV1 IV2 IV3
1775                  */
1776
1777                 for (j = 0; j < 4; j++)
1778                         iv[j] = iv_s[3 - j];
1779         } else {
1780                 /* ZUC doesn't need a swap */
1781                 for (j = 0; j < 4; j++)
1782                         iv[j] = iv_s[j];
1783         }
1784
1785         /*
1786          * GP op header, lengths are expected in bits.
1787          */
1788         vq_cmd_w0.u64 = 0;
1789         vq_cmd_w0.s.param1 = encr_data_len;
1790
1791         /*
1792          * In 83XX since we have a limitation of
1793          * IV & Offset control word not part of instruction
1794          * and need to be part of Data Buffer, we check if
1795          * head room is there and then only do the Direct mode processing
1796          */
1797         if (likely((req_flags & SINGLE_BUF_INPLACE) &&
1798                    (req_flags & SINGLE_BUF_HEADTAILROOM))) {
1799                 void *dm_vaddr = params->bufs[0].vaddr;
1800                 uint64_t dm_dma_addr = params->bufs[0].dma_addr;
1801                 /*
1802                  * This flag indicates that there is 24 bytes head room and
1803                  * 8 bytes tail room available, so that we get to do
1804                  * DIRECT MODE with limitation
1805                  */
1806
1807                 offset_vaddr = (uint64_t *)((uint8_t *)dm_vaddr -
1808                                             OFF_CTRL_LEN - iv_len);
1809                 offset_dma = dm_dma_addr - OFF_CTRL_LEN - iv_len;
1810
1811                 /* DPTR */
1812                 req->ist.ei1 = offset_dma;
1813                 /* RPTR should just exclude offset control word */
1814                 req->ist.ei2 = dm_dma_addr - iv_len;
1815                 req->alternate_caddr = (uint64_t *)((uint8_t *)dm_vaddr
1816                                                     + outputlen - iv_len);
1817
1818                 vq_cmd_w0.s.dlen = inputlen + OFF_CTRL_LEN;
1819
1820                 vq_cmd_w0.s.opcode = opcode.flags;
1821
1822                 if (likely(iv_len)) {
1823                         uint32_t *iv_d = (uint32_t *)((uint8_t *)offset_vaddr
1824                                                       + OFF_CTRL_LEN);
1825                         memcpy(iv_d, iv, 16);
1826                 }
1827
1828                 /* iv offset is 0 */
1829                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1830         } else {
1831                 uint32_t i, g_size_bytes, s_size_bytes;
1832                 uint64_t dptr_dma, rptr_dma;
1833                 sg_comp_t *gather_comp;
1834                 sg_comp_t *scatter_comp;
1835                 uint8_t *in_buffer;
1836                 uint32_t *iv_d;
1837
1838                 /* save space for offset and iv... */
1839                 offset_vaddr = m_vaddr;
1840                 offset_dma = m_dma;
1841
1842                 m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
1843                 m_dma += OFF_CTRL_LEN + iv_len;
1844
1845                 opcode.s.major |= CPT_DMA_MODE;
1846
1847                 vq_cmd_w0.s.opcode = opcode.flags;
1848
1849                 /* DPTR has SG list */
1850                 in_buffer = m_vaddr;
1851                 dptr_dma = m_dma;
1852
1853                 ((uint16_t *)in_buffer)[0] = 0;
1854                 ((uint16_t *)in_buffer)[1] = 0;
1855
1856                 /* TODO Add error check if space will be sufficient */
1857                 gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
1858
1859                 /*
1860                  * Input Gather List
1861                  */
1862                 i = 0;
1863
1864                 /* Offset control word */
1865
1866                 /* iv offset is 0 */
1867                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
1868
1869                 i = fill_sg_comp(gather_comp, i, offset_dma,
1870                                  OFF_CTRL_LEN + iv_len);
1871
1872                 iv_d = (uint32_t *)((uint8_t *)offset_vaddr + OFF_CTRL_LEN);
1873                 memcpy(iv_d, iv, 16);
1874
1875                 /* Add input data */
1876                 size = inputlen - iv_len;
1877                 if (size) {
1878                         i = fill_sg_comp_from_iov(gather_comp, i,
1879                                                   params->src_iov,
1880                                                   0, &size, NULL, 0);
1881                         if (unlikely(size)) {
1882                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1883                                                " size %d needed", size);
1884                                 return;
1885                         }
1886                 }
1887                 ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
1888                 g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1889
1890                 /*
1891                  * Output Scatter List
1892                  */
1893
1894                 i = 0;
1895                 scatter_comp =
1896                         (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
1897
1898                 /* IV */
1899                 i = fill_sg_comp(scatter_comp, i,
1900                                  offset_dma + OFF_CTRL_LEN,
1901                                  iv_len);
1902
1903                 /* Add output data */
1904                 size = outputlen - iv_len;
1905                 if (size) {
1906                         i = fill_sg_comp_from_iov(scatter_comp, i,
1907                                                   params->dst_iov, 0,
1908                                                   &size, NULL, 0);
1909
1910                         if (unlikely(size)) {
1911                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
1912                                                " size %d needed", size);
1913                                 return;
1914                         }
1915                 }
1916                 ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
1917                 s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
1918
1919                 size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
1920
1921                 /* This is DPTR len incase of SG mode */
1922                 vq_cmd_w0.s.dlen = size;
1923
1924                 m_vaddr = (uint8_t *)m_vaddr + size;
1925                 m_dma += size;
1926
1927                 /* cpt alternate completion address saved earlier */
1928                 req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
1929                 *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
1930                 rptr_dma = c_dma - 8;
1931
1932                 req->ist.ei1 = dptr_dma;
1933                 req->ist.ei2 = rptr_dma;
1934         }
1935
1936         /* vq command w3 */
1937         vq_cmd_w3.u64 = 0;
1938         vq_cmd_w3.s.grp = 0;
1939         vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
1940                 offsetof(struct cpt_ctx, zs_ctx);
1941
1942         /* 16 byte aligned cpt res address */
1943         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
1944         *req->completion_addr = COMPLETION_CODE_INIT;
1945         req->comp_baddr  = c_dma;
1946
1947         /* Fill microcode part of instruction */
1948         req->ist.ei0 = vq_cmd_w0.u64;
1949         req->ist.ei3 = vq_cmd_w3.u64;
1950
1951         req->op = op;
1952
1953         *prep_req = req;
1954         return;
1955 }
1956
1957 static __rte_always_inline void
1958 cpt_kasumi_enc_prep(uint32_t req_flags,
1959                     uint64_t d_offs,
1960                     uint64_t d_lens,
1961                     fc_params_t *params,
1962                     void *op,
1963                     void **prep_req)
1964 {
1965         uint32_t size;
1966         int32_t inputlen = 0, outputlen = 0;
1967         struct cpt_ctx *cpt_ctx;
1968         uint32_t mac_len = 0;
1969         uint8_t i = 0;
1970         struct cpt_request_info *req;
1971         buf_ptr_t *buf_p;
1972         uint32_t encr_offset, auth_offset;
1973         uint32_t encr_data_len, auth_data_len;
1974         int flags;
1975         uint8_t *iv_s, *iv_d, iv_len = 8;
1976         uint8_t dir = 0;
1977         void *m_vaddr, *c_vaddr;
1978         uint64_t m_dma, c_dma;
1979         uint64_t *offset_vaddr, offset_dma;
1980         vq_cmd_word0_t vq_cmd_w0;
1981         vq_cmd_word3_t vq_cmd_w3;
1982         opcode_info_t opcode;
1983         uint8_t *in_buffer;
1984         uint32_t g_size_bytes, s_size_bytes;
1985         uint64_t dptr_dma, rptr_dma;
1986         sg_comp_t *gather_comp;
1987         sg_comp_t *scatter_comp;
1988
1989         buf_p = &params->meta_buf;
1990         m_vaddr = buf_p->vaddr;
1991         m_dma = buf_p->dma_addr;
1992
1993         encr_offset = ENCR_OFFSET(d_offs) / 8;
1994         auth_offset = AUTH_OFFSET(d_offs) / 8;
1995         encr_data_len = ENCR_DLEN(d_lens);
1996         auth_data_len = AUTH_DLEN(d_lens);
1997
1998         cpt_ctx = params->ctx_buf.vaddr;
1999         flags = cpt_ctx->zsk_flags;
2000         mac_len = cpt_ctx->mac_len;
2001
2002         if (flags == 0x0)
2003                 iv_s = params->iv_buf;
2004         else
2005                 iv_s = params->auth_iv_buf;
2006
2007         dir = iv_s[8] & 0x1;
2008
2009         /*
2010          * Save initial space that followed app data for completion code &
2011          * alternate completion code to fall in same cache line as app data
2012          */
2013         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2014         m_dma += COMPLETION_CODE_SIZE;
2015         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2016                 (uint8_t *)m_vaddr;
2017
2018         c_vaddr = (uint8_t *)m_vaddr + size;
2019         c_dma = m_dma + size;
2020         size += sizeof(cpt_res_s_t);
2021
2022         m_vaddr = (uint8_t *)m_vaddr + size;
2023         m_dma += size;
2024
2025         /* Reserve memory for cpt request info */
2026         req = m_vaddr;
2027
2028         size = sizeof(struct cpt_request_info);
2029         m_vaddr = (uint8_t *)m_vaddr + size;
2030         m_dma += size;
2031
2032         opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2033
2034         /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2035         opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2036                           (dir << 4) | (0 << 3) | (flags & 0x7));
2037
2038         /*
2039          * GP op header, lengths are expected in bits.
2040          */
2041         vq_cmd_w0.u64 = 0;
2042         vq_cmd_w0.s.param1 = encr_data_len;
2043         vq_cmd_w0.s.param2 = auth_data_len;
2044         vq_cmd_w0.s.opcode = opcode.flags;
2045
2046         /* consider iv len */
2047         if (flags == 0x0) {
2048                 encr_offset += iv_len;
2049                 auth_offset += iv_len;
2050         }
2051
2052         /* save space for offset ctrl and iv */
2053         offset_vaddr = m_vaddr;
2054         offset_dma = m_dma;
2055
2056         m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2057         m_dma += OFF_CTRL_LEN + iv_len;
2058
2059         /* DPTR has SG list */
2060         in_buffer = m_vaddr;
2061         dptr_dma = m_dma;
2062
2063         ((uint16_t *)in_buffer)[0] = 0;
2064         ((uint16_t *)in_buffer)[1] = 0;
2065
2066         /* TODO Add error check if space will be sufficient */
2067         gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2068
2069         /*
2070          * Input Gather List
2071          */
2072         i = 0;
2073
2074         /* Offset control word followed by iv */
2075
2076         if (flags == 0x0) {
2077                 inputlen = encr_offset + (RTE_ALIGN(encr_data_len, 8) / 8);
2078                 outputlen = inputlen;
2079                 /* iv offset is 0 */
2080                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2081         } else {
2082                 inputlen = auth_offset + (RTE_ALIGN(auth_data_len, 8) / 8);
2083                 outputlen = mac_len;
2084                 /* iv offset is 0 */
2085                 *offset_vaddr = rte_cpu_to_be_64((uint64_t)auth_offset);
2086         }
2087
2088         i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2089
2090         /* IV */
2091         iv_d = (uint8_t *)offset_vaddr + OFF_CTRL_LEN;
2092         memcpy(iv_d, iv_s, iv_len);
2093
2094         /* input data */
2095         size = inputlen - iv_len;
2096         if (size) {
2097                 i = fill_sg_comp_from_iov(gather_comp, i,
2098                                           params->src_iov, 0,
2099                                           &size, NULL, 0);
2100
2101                 if (unlikely(size)) {
2102                         CPT_LOG_DP_ERR("Insufficient buffer space,"
2103                                        " size %d needed", size);
2104                         return;
2105                 }
2106         }
2107         ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2108         g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2109
2110         /*
2111          * Output Scatter List
2112          */
2113
2114         i = 0;
2115         scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2116
2117         if (flags == 0x1) {
2118                 /* IV in SLIST only for F8 */
2119                 iv_len = 0;
2120         }
2121
2122         /* IV */
2123         if (iv_len) {
2124                 i = fill_sg_comp(scatter_comp, i,
2125                                  offset_dma + OFF_CTRL_LEN,
2126                                  iv_len);
2127         }
2128
2129         /* Add output data */
2130         if (req_flags & VALID_MAC_BUF) {
2131                 size = outputlen - iv_len - mac_len;
2132                 if (size) {
2133                         i = fill_sg_comp_from_iov(scatter_comp, i,
2134                                                   params->dst_iov, 0,
2135                                                   &size, NULL, 0);
2136
2137                         if (unlikely(size)) {
2138                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
2139                                                " size %d needed", size);
2140                                 return;
2141                         }
2142                 }
2143
2144                 /* mac data */
2145                 if (mac_len) {
2146                         i = fill_sg_comp_from_buf(scatter_comp, i,
2147                                                   &params->mac_buf);
2148                 }
2149         } else {
2150                 /* Output including mac */
2151                 size = outputlen - iv_len;
2152                 if (size) {
2153                         i = fill_sg_comp_from_iov(scatter_comp, i,
2154                                                   params->dst_iov, 0,
2155                                                   &size, NULL, 0);
2156
2157                         if (unlikely(size)) {
2158                                 CPT_LOG_DP_ERR("Insufficient buffer space,"
2159                                                " size %d needed", size);
2160                                 return;
2161                         }
2162                 }
2163         }
2164         ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2165         s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2166
2167         size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2168
2169         /* This is DPTR len incase of SG mode */
2170         vq_cmd_w0.s.dlen = size;
2171
2172         m_vaddr = (uint8_t *)m_vaddr + size;
2173         m_dma += size;
2174
2175         /* cpt alternate completion address saved earlier */
2176         req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2177         *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2178         rptr_dma = c_dma - 8;
2179
2180         req->ist.ei1 = dptr_dma;
2181         req->ist.ei2 = rptr_dma;
2182
2183         /* vq command w3 */
2184         vq_cmd_w3.u64 = 0;
2185         vq_cmd_w3.s.grp = 0;
2186         vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
2187                 offsetof(struct cpt_ctx, k_ctx);
2188
2189         /* 16 byte aligned cpt res address */
2190         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2191         *req->completion_addr = COMPLETION_CODE_INIT;
2192         req->comp_baddr  = c_dma;
2193
2194         /* Fill microcode part of instruction */
2195         req->ist.ei0 = vq_cmd_w0.u64;
2196         req->ist.ei3 = vq_cmd_w3.u64;
2197
2198         req->op = op;
2199
2200         *prep_req = req;
2201         return;
2202 }
2203
2204 static __rte_always_inline void
2205 cpt_kasumi_dec_prep(uint64_t d_offs,
2206                     uint64_t d_lens,
2207                     fc_params_t *params,
2208                     void *op,
2209                     void **prep_req)
2210 {
2211         uint32_t size;
2212         int32_t inputlen = 0, outputlen;
2213         struct cpt_ctx *cpt_ctx;
2214         uint8_t i = 0, iv_len = 8;
2215         struct cpt_request_info *req;
2216         buf_ptr_t *buf_p;
2217         uint32_t encr_offset;
2218         uint32_t encr_data_len;
2219         int flags;
2220         uint8_t dir = 0;
2221         void *m_vaddr, *c_vaddr;
2222         uint64_t m_dma, c_dma;
2223         uint64_t *offset_vaddr, offset_dma;
2224         vq_cmd_word0_t vq_cmd_w0;
2225         vq_cmd_word3_t vq_cmd_w3;
2226         opcode_info_t opcode;
2227         uint8_t *in_buffer;
2228         uint32_t g_size_bytes, s_size_bytes;
2229         uint64_t dptr_dma, rptr_dma;
2230         sg_comp_t *gather_comp;
2231         sg_comp_t *scatter_comp;
2232
2233         buf_p = &params->meta_buf;
2234         m_vaddr = buf_p->vaddr;
2235         m_dma = buf_p->dma_addr;
2236
2237         encr_offset = ENCR_OFFSET(d_offs) / 8;
2238         encr_data_len = ENCR_DLEN(d_lens);
2239
2240         cpt_ctx = params->ctx_buf.vaddr;
2241         flags = cpt_ctx->zsk_flags;
2242         /*
2243          * Save initial space that followed app data for completion code &
2244          * alternate completion code to fall in same cache line as app data
2245          */
2246         m_vaddr = (uint8_t *)m_vaddr + COMPLETION_CODE_SIZE;
2247         m_dma += COMPLETION_CODE_SIZE;
2248         size = (uint8_t *)RTE_PTR_ALIGN((uint8_t *)m_vaddr, 16) -
2249                 (uint8_t *)m_vaddr;
2250
2251         c_vaddr = (uint8_t *)m_vaddr + size;
2252         c_dma = m_dma + size;
2253         size += sizeof(cpt_res_s_t);
2254
2255         m_vaddr = (uint8_t *)m_vaddr + size;
2256         m_dma += size;
2257
2258         /* Reserve memory for cpt request info */
2259         req = m_vaddr;
2260
2261         size = sizeof(struct cpt_request_info);
2262         m_vaddr = (uint8_t *)m_vaddr + size;
2263         m_dma += size;
2264
2265         opcode.s.major = CPT_MAJOR_OP_KASUMI | CPT_DMA_MODE;
2266
2267         /* indicates ECB/CBC, direction, ctx from cptr, iv from dptr */
2268         opcode.s.minor = ((1 << 6) | (cpt_ctx->k_ecb << 5) |
2269                           (dir << 4) | (0 << 3) | (flags & 0x7));
2270
2271         /*
2272          * GP op header, lengths are expected in bits.
2273          */
2274         vq_cmd_w0.u64 = 0;
2275         vq_cmd_w0.s.param1 = encr_data_len;
2276         vq_cmd_w0.s.opcode = opcode.flags;
2277
2278         /* consider iv len */
2279         encr_offset += iv_len;
2280
2281         inputlen = iv_len + (RTE_ALIGN(encr_data_len, 8) / 8);
2282         outputlen = inputlen;
2283
2284         /* save space for offset ctrl & iv */
2285         offset_vaddr = m_vaddr;
2286         offset_dma = m_dma;
2287
2288         m_vaddr = (uint8_t *)m_vaddr + OFF_CTRL_LEN + iv_len;
2289         m_dma += OFF_CTRL_LEN + iv_len;
2290
2291         /* DPTR has SG list */
2292         in_buffer = m_vaddr;
2293         dptr_dma = m_dma;
2294
2295         ((uint16_t *)in_buffer)[0] = 0;
2296         ((uint16_t *)in_buffer)[1] = 0;
2297
2298         /* TODO Add error check if space will be sufficient */
2299         gather_comp = (sg_comp_t *)((uint8_t *)m_vaddr + 8);
2300
2301         /*
2302          * Input Gather List
2303          */
2304         i = 0;
2305
2306         /* Offset control word followed by iv */
2307         *offset_vaddr = rte_cpu_to_be_64((uint64_t)encr_offset << 16);
2308
2309         i = fill_sg_comp(gather_comp, i, offset_dma, OFF_CTRL_LEN + iv_len);
2310
2311         /* IV */
2312         memcpy((uint8_t *)offset_vaddr + OFF_CTRL_LEN,
2313                params->iv_buf, iv_len);
2314
2315         /* Add input data */
2316         size = inputlen - iv_len;
2317         if (size) {
2318                 i = fill_sg_comp_from_iov(gather_comp, i,
2319                                           params->src_iov,
2320                                           0, &size, NULL, 0);
2321                 if (unlikely(size)) {
2322                         CPT_LOG_DP_ERR("Insufficient buffer space,"
2323                                        " size %d needed", size);
2324                         return;
2325                 }
2326         }
2327         ((uint16_t *)in_buffer)[2] = rte_cpu_to_be_16(i);
2328         g_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2329
2330         /*
2331          * Output Scatter List
2332          */
2333
2334         i = 0;
2335         scatter_comp = (sg_comp_t *)((uint8_t *)gather_comp + g_size_bytes);
2336
2337         /* IV */
2338         i = fill_sg_comp(scatter_comp, i,
2339                          offset_dma + OFF_CTRL_LEN,
2340                          iv_len);
2341
2342         /* Add output data */
2343         size = outputlen - iv_len;
2344         if (size) {
2345                 i = fill_sg_comp_from_iov(scatter_comp, i,
2346                                           params->dst_iov, 0,
2347                                           &size, NULL, 0);
2348                 if (unlikely(size)) {
2349                         CPT_LOG_DP_ERR("Insufficient buffer space,"
2350                                        " size %d needed", size);
2351                         return;
2352                 }
2353         }
2354         ((uint16_t *)in_buffer)[3] = rte_cpu_to_be_16(i);
2355         s_size_bytes = ((i + 3) / 4) * sizeof(sg_comp_t);
2356
2357         size = g_size_bytes + s_size_bytes + SG_LIST_HDR_SIZE;
2358
2359         /* This is DPTR len incase of SG mode */
2360         vq_cmd_w0.s.dlen = size;
2361
2362         m_vaddr = (uint8_t *)m_vaddr + size;
2363         m_dma += size;
2364
2365         /* cpt alternate completion address saved earlier */
2366         req->alternate_caddr = (uint64_t *)((uint8_t *)c_vaddr - 8);
2367         *req->alternate_caddr = ~((uint64_t)COMPLETION_CODE_INIT);
2368         rptr_dma = c_dma - 8;
2369
2370         req->ist.ei1 = dptr_dma;
2371         req->ist.ei2 = rptr_dma;
2372
2373         /* vq command w3 */
2374         vq_cmd_w3.u64 = 0;
2375         vq_cmd_w3.s.grp = 0;
2376         vq_cmd_w3.s.cptr = params->ctx_buf.dma_addr +
2377                 offsetof(struct cpt_ctx, k_ctx);
2378
2379         /* 16 byte aligned cpt res address */
2380         req->completion_addr = (uint64_t *)((uint8_t *)c_vaddr);
2381         *req->completion_addr = COMPLETION_CODE_INIT;
2382         req->comp_baddr  = c_dma;
2383
2384         /* Fill microcode part of instruction */
2385         req->ist.ei0 = vq_cmd_w0.u64;
2386         req->ist.ei3 = vq_cmd_w3.u64;
2387
2388         req->op = op;
2389
2390         *prep_req = req;
2391         return;
2392 }
2393
2394 static __rte_always_inline void *
2395 cpt_fc_dec_hmac_prep(uint32_t flags,
2396                      uint64_t d_offs,
2397                      uint64_t d_lens,
2398                      fc_params_t *fc_params,
2399                      void *op)
2400 {
2401         struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2402         uint8_t fc_type;
2403         void *prep_req = NULL;
2404
2405         fc_type = ctx->fc_type;
2406
2407         if (likely(fc_type == FC_GEN)) {
2408                 cpt_dec_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2409                                   &prep_req);
2410         } else if (fc_type == ZUC_SNOW3G) {
2411                 cpt_zuc_snow3g_dec_prep(flags, d_offs, d_lens, fc_params, op,
2412                                         &prep_req);
2413         } else if (fc_type == KASUMI) {
2414                 cpt_kasumi_dec_prep(d_offs, d_lens, fc_params, op, &prep_req);
2415         }
2416
2417         /*
2418          * For AUTH_ONLY case,
2419          * MC only supports digest generation and verification
2420          * should be done in software by memcmp()
2421          */
2422
2423         return prep_req;
2424 }
2425
2426 static __rte_always_inline void *__rte_hot
2427 cpt_fc_enc_hmac_prep(uint32_t flags, uint64_t d_offs, uint64_t d_lens,
2428                      fc_params_t *fc_params, void *op)
2429 {
2430         struct cpt_ctx *ctx = fc_params->ctx_buf.vaddr;
2431         uint8_t fc_type;
2432         void *prep_req = NULL;
2433
2434         fc_type = ctx->fc_type;
2435
2436         /* Common api for rest of the ops */
2437         if (likely(fc_type == FC_GEN)) {
2438                 cpt_enc_hmac_prep(flags, d_offs, d_lens, fc_params, op,
2439                                   &prep_req);
2440         } else if (fc_type == ZUC_SNOW3G) {
2441                 cpt_zuc_snow3g_enc_prep(flags, d_offs, d_lens, fc_params, op,
2442                                         &prep_req);
2443         } else if (fc_type == KASUMI) {
2444                 cpt_kasumi_enc_prep(flags, d_offs, d_lens, fc_params, op,
2445                                     &prep_req);
2446         } else if (fc_type == HASH_HMAC) {
2447                 cpt_digest_gen_prep(flags, d_lens, fc_params, op, &prep_req);
2448         }
2449
2450         return prep_req;
2451 }
2452
2453 static __rte_always_inline int
2454 cpt_fc_auth_set_key(void *ctx, auth_type_t type, const uint8_t *key,
2455                     uint16_t key_len, uint16_t mac_len)
2456 {
2457         struct cpt_ctx *cpt_ctx = ctx;
2458         mc_fc_context_t *fctx = &cpt_ctx->fctx;
2459
2460         if ((type >= ZUC_EIA3) && (type <= KASUMI_F9_ECB)) {
2461                 uint32_t keyx[4];
2462
2463                 if (key_len != 16)
2464                         return -1;
2465                 /* No support for AEAD yet */
2466                 if (cpt_ctx->enc_cipher)
2467                         return -1;
2468                 /* For ZUC/SNOW3G/Kasumi */
2469                 switch (type) {
2470                 case SNOW3G_UIA2:
2471                         cpt_ctx->snow3g = 1;
2472                         gen_key_snow3g(key, keyx);
2473                         memcpy(cpt_ctx->zs_ctx.ci_key, keyx, key_len);
2474                         cpt_ctx->fc_type = ZUC_SNOW3G;
2475                         cpt_ctx->zsk_flags = 0x1;
2476                         break;
2477                 case ZUC_EIA3:
2478                         cpt_ctx->snow3g = 0;
2479                         memcpy(cpt_ctx->zs_ctx.ci_key, key, key_len);
2480                         memcpy(cpt_ctx->zs_ctx.zuc_const, zuc_d, 32);
2481                         cpt_ctx->fc_type = ZUC_SNOW3G;
2482                         cpt_ctx->zsk_flags = 0x1;
2483                         break;
2484                 case KASUMI_F9_ECB:
2485                         /* Kasumi ECB mode */
2486                         cpt_ctx->k_ecb = 1;
2487                         memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
2488                         cpt_ctx->fc_type = KASUMI;
2489                         cpt_ctx->zsk_flags = 0x1;
2490                         break;
2491                 case KASUMI_F9_CBC:
2492                         memcpy(cpt_ctx->k_ctx.ci_key, key, key_len);
2493                         cpt_ctx->fc_type = KASUMI;
2494                         cpt_ctx->zsk_flags = 0x1;
2495                         break;
2496                 default:
2497                         return -1;
2498                 }
2499                 cpt_ctx->mac_len = 4;
2500                 cpt_ctx->hash_type = type;
2501                 return 0;
2502         }
2503
2504         if (!(cpt_ctx->fc_type == FC_GEN && !type)) {
2505                 if (!cpt_ctx->fc_type || !cpt_ctx->enc_cipher)
2506                         cpt_ctx->fc_type = HASH_HMAC;
2507         }
2508
2509         if (cpt_ctx->fc_type == FC_GEN && key_len > 64)
2510                 return -1;
2511
2512         /* For GMAC auth, cipher must be NULL */
2513         if (type == GMAC_TYPE)
2514                 fctx->enc.enc_cipher = 0;
2515
2516         fctx->enc.hash_type = cpt_ctx->hash_type = type;
2517         fctx->enc.mac_len = cpt_ctx->mac_len = mac_len;
2518
2519         if (key_len) {
2520                 cpt_ctx->hmac = 1;
2521                 memset(cpt_ctx->auth_key, 0, sizeof(cpt_ctx->auth_key));
2522                 memcpy(cpt_ctx->auth_key, key, key_len);
2523                 cpt_ctx->auth_key_len = key_len;
2524                 memset(fctx->hmac.ipad, 0, sizeof(fctx->hmac.ipad));
2525                 memset(fctx->hmac.opad, 0, sizeof(fctx->hmac.opad));
2526
2527                 if (key_len <= 64)
2528                         memcpy(fctx->hmac.opad, key, key_len);
2529                 fctx->enc.auth_input_type = 1;
2530         }
2531         return 0;
2532 }
2533
2534 static __rte_always_inline int
2535 fill_sess_aead(struct rte_crypto_sym_xform *xform,
2536                  struct cpt_sess_misc *sess)
2537 {
2538         struct rte_crypto_aead_xform *aead_form;
2539         cipher_type_t enc_type = 0; /* NULL Cipher type */
2540         auth_type_t auth_type = 0; /* NULL Auth type */
2541         uint32_t cipher_key_len = 0;
2542         uint8_t aes_gcm = 0;
2543         aead_form = &xform->aead;
2544         void *ctx = SESS_PRIV(sess);
2545
2546         if (aead_form->op == RTE_CRYPTO_AEAD_OP_ENCRYPT &&
2547            aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
2548                 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2549                 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2550         } else if (aead_form->op == RTE_CRYPTO_AEAD_OP_DECRYPT &&
2551                 aead_form->algo == RTE_CRYPTO_AEAD_AES_GCM) {
2552                 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2553                 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2554         } else {
2555                 CPT_LOG_DP_ERR("Unknown cipher operation\n");
2556                 return -1;
2557         }
2558         switch (aead_form->algo) {
2559         case RTE_CRYPTO_AEAD_AES_GCM:
2560                 enc_type = AES_GCM;
2561                 cipher_key_len = 16;
2562                 aes_gcm = 1;
2563                 break;
2564         case RTE_CRYPTO_AEAD_AES_CCM:
2565                 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2566                                aead_form->algo);
2567                 return -1;
2568         default:
2569                 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2570                                aead_form->algo);
2571                 return -1;
2572         }
2573         if (aead_form->key.length < cipher_key_len) {
2574                 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2575                                (unsigned int long)aead_form->key.length);
2576                 return -1;
2577         }
2578         sess->zsk_flag = 0;
2579         sess->aes_gcm = aes_gcm;
2580         sess->mac_len = aead_form->digest_length;
2581         sess->iv_offset = aead_form->iv.offset;
2582         sess->iv_length = aead_form->iv.length;
2583         sess->aad_length = aead_form->aad_length;
2584
2585         if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, aead_form->key.data,
2586                         aead_form->key.length, NULL)))
2587                 return -1;
2588
2589         if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
2590                         aead_form->digest_length)))
2591                 return -1;
2592
2593         return 0;
2594 }
2595
2596 static __rte_always_inline int
2597 fill_sess_cipher(struct rte_crypto_sym_xform *xform,
2598                  struct cpt_sess_misc *sess)
2599 {
2600         struct rte_crypto_cipher_xform *c_form;
2601         cipher_type_t enc_type = 0; /* NULL Cipher type */
2602         uint32_t cipher_key_len = 0;
2603         uint8_t zsk_flag = 0, aes_ctr = 0, is_null = 0;
2604
2605         c_form = &xform->cipher;
2606
2607         if (c_form->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
2608                 sess->cpt_op |= CPT_OP_CIPHER_ENCRYPT;
2609         else if (c_form->op == RTE_CRYPTO_CIPHER_OP_DECRYPT)
2610                 sess->cpt_op |= CPT_OP_CIPHER_DECRYPT;
2611         else {
2612                 CPT_LOG_DP_ERR("Unknown cipher operation\n");
2613                 return -1;
2614         }
2615
2616         switch (c_form->algo) {
2617         case RTE_CRYPTO_CIPHER_AES_CBC:
2618                 enc_type = AES_CBC;
2619                 cipher_key_len = 16;
2620                 break;
2621         case RTE_CRYPTO_CIPHER_3DES_CBC:
2622                 enc_type = DES3_CBC;
2623                 cipher_key_len = 24;
2624                 break;
2625         case RTE_CRYPTO_CIPHER_DES_CBC:
2626                 /* DES is implemented using 3DES in hardware */
2627                 enc_type = DES3_CBC;
2628                 cipher_key_len = 8;
2629                 break;
2630         case RTE_CRYPTO_CIPHER_AES_CTR:
2631                 enc_type = AES_CTR;
2632                 cipher_key_len = 16;
2633                 aes_ctr = 1;
2634                 break;
2635         case RTE_CRYPTO_CIPHER_NULL:
2636                 enc_type = 0;
2637                 is_null = 1;
2638                 break;
2639         case RTE_CRYPTO_CIPHER_KASUMI_F8:
2640                 enc_type = KASUMI_F8_ECB;
2641                 cipher_key_len = 16;
2642                 zsk_flag = K_F8;
2643                 break;
2644         case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
2645                 enc_type = SNOW3G_UEA2;
2646                 cipher_key_len = 16;
2647                 zsk_flag = ZS_EA;
2648                 break;
2649         case RTE_CRYPTO_CIPHER_ZUC_EEA3:
2650                 enc_type = ZUC_EEA3;
2651                 cipher_key_len = 16;
2652                 zsk_flag = ZS_EA;
2653                 break;
2654         case RTE_CRYPTO_CIPHER_AES_XTS:
2655                 enc_type = AES_XTS;
2656                 cipher_key_len = 16;
2657                 break;
2658         case RTE_CRYPTO_CIPHER_3DES_ECB:
2659                 enc_type = DES3_ECB;
2660                 cipher_key_len = 24;
2661                 break;
2662         case RTE_CRYPTO_CIPHER_AES_ECB:
2663                 enc_type = AES_ECB;
2664                 cipher_key_len = 16;
2665                 break;
2666         case RTE_CRYPTO_CIPHER_3DES_CTR:
2667         case RTE_CRYPTO_CIPHER_AES_F8:
2668         case RTE_CRYPTO_CIPHER_ARC4:
2669                 CPT_LOG_DP_ERR("Crypto: Unsupported cipher algo %u",
2670                                c_form->algo);
2671                 return -1;
2672         default:
2673                 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2674                                c_form->algo);
2675                 return -1;
2676         }
2677
2678         if (c_form->key.length < cipher_key_len) {
2679                 CPT_LOG_DP_ERR("Invalid cipher params keylen %lu",
2680                                (unsigned long) c_form->key.length);
2681                 return -1;
2682         }
2683
2684         sess->zsk_flag = zsk_flag;
2685         sess->aes_gcm = 0;
2686         sess->aes_ctr = aes_ctr;
2687         sess->iv_offset = c_form->iv.offset;
2688         sess->iv_length = c_form->iv.length;
2689         sess->is_null = is_null;
2690
2691         if (unlikely(cpt_fc_ciph_set_key(SESS_PRIV(sess), enc_type,
2692                         c_form->key.data, c_form->key.length, NULL)))
2693                 return -1;
2694
2695         return 0;
2696 }
2697
2698 static __rte_always_inline int
2699 fill_sess_auth(struct rte_crypto_sym_xform *xform,
2700                struct cpt_sess_misc *sess)
2701 {
2702         struct rte_crypto_auth_xform *a_form;
2703         auth_type_t auth_type = 0; /* NULL Auth type */
2704         uint8_t zsk_flag = 0, aes_gcm = 0, is_null = 0;
2705
2706         a_form = &xform->auth;
2707
2708         if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2709                 sess->cpt_op |= CPT_OP_AUTH_VERIFY;
2710         else if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2711                 sess->cpt_op |= CPT_OP_AUTH_GENERATE;
2712         else {
2713                 CPT_LOG_DP_ERR("Unknown auth operation");
2714                 return -1;
2715         }
2716
2717         switch (a_form->algo) {
2718         case RTE_CRYPTO_AUTH_SHA1_HMAC:
2719                 /* Fall through */
2720         case RTE_CRYPTO_AUTH_SHA1:
2721                 auth_type = SHA1_TYPE;
2722                 break;
2723         case RTE_CRYPTO_AUTH_SHA256_HMAC:
2724         case RTE_CRYPTO_AUTH_SHA256:
2725                 auth_type = SHA2_SHA256;
2726                 break;
2727         case RTE_CRYPTO_AUTH_SHA512_HMAC:
2728         case RTE_CRYPTO_AUTH_SHA512:
2729                 auth_type = SHA2_SHA512;
2730                 break;
2731         case RTE_CRYPTO_AUTH_AES_GMAC:
2732                 auth_type = GMAC_TYPE;
2733                 aes_gcm = 1;
2734                 break;
2735         case RTE_CRYPTO_AUTH_SHA224_HMAC:
2736         case RTE_CRYPTO_AUTH_SHA224:
2737                 auth_type = SHA2_SHA224;
2738                 break;
2739         case RTE_CRYPTO_AUTH_SHA384_HMAC:
2740         case RTE_CRYPTO_AUTH_SHA384:
2741                 auth_type = SHA2_SHA384;
2742                 break;
2743         case RTE_CRYPTO_AUTH_MD5_HMAC:
2744         case RTE_CRYPTO_AUTH_MD5:
2745                 auth_type = MD5_TYPE;
2746                 break;
2747         case RTE_CRYPTO_AUTH_KASUMI_F9:
2748                 auth_type = KASUMI_F9_ECB;
2749                 /*
2750                  * Indicate that direction needs to be taken out
2751                  * from end of src
2752                  */
2753                 zsk_flag = K_F9;
2754                 break;
2755         case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
2756                 auth_type = SNOW3G_UIA2;
2757                 zsk_flag = ZS_IA;
2758                 break;
2759         case RTE_CRYPTO_AUTH_ZUC_EIA3:
2760                 auth_type = ZUC_EIA3;
2761                 zsk_flag = ZS_IA;
2762                 break;
2763         case RTE_CRYPTO_AUTH_NULL:
2764                 auth_type = 0;
2765                 is_null = 1;
2766                 break;
2767         case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
2768         case RTE_CRYPTO_AUTH_AES_CMAC:
2769         case RTE_CRYPTO_AUTH_AES_CBC_MAC:
2770                 CPT_LOG_DP_ERR("Crypto: Unsupported hash algo %u",
2771                                a_form->algo);
2772                 return -1;
2773         default:
2774                 CPT_LOG_DP_ERR("Crypto: Undefined Hash algo %u specified",
2775                                a_form->algo);
2776                 return -1;
2777         }
2778
2779         sess->zsk_flag = zsk_flag;
2780         sess->aes_gcm = aes_gcm;
2781         sess->mac_len = a_form->digest_length;
2782         sess->is_null = is_null;
2783         if (zsk_flag) {
2784                 sess->auth_iv_offset = a_form->iv.offset;
2785                 sess->auth_iv_length = a_form->iv.length;
2786         }
2787         if (unlikely(cpt_fc_auth_set_key(SESS_PRIV(sess), auth_type,
2788                         a_form->key.data, a_form->key.length,
2789                         a_form->digest_length)))
2790                 return -1;
2791
2792         return 0;
2793 }
2794
2795 static __rte_always_inline int
2796 fill_sess_gmac(struct rte_crypto_sym_xform *xform,
2797                  struct cpt_sess_misc *sess)
2798 {
2799         struct rte_crypto_auth_xform *a_form;
2800         cipher_type_t enc_type = 0; /* NULL Cipher type */
2801         auth_type_t auth_type = 0; /* NULL Auth type */
2802         void *ctx = SESS_PRIV(sess);
2803
2804         a_form = &xform->auth;
2805
2806         if (a_form->op == RTE_CRYPTO_AUTH_OP_GENERATE)
2807                 sess->cpt_op |= CPT_OP_ENCODE;
2808         else if (a_form->op == RTE_CRYPTO_AUTH_OP_VERIFY)
2809                 sess->cpt_op |= CPT_OP_DECODE;
2810         else {
2811                 CPT_LOG_DP_ERR("Unknown auth operation");
2812                 return -1;
2813         }
2814
2815         switch (a_form->algo) {
2816         case RTE_CRYPTO_AUTH_AES_GMAC:
2817                 enc_type = AES_GCM;
2818                 auth_type = GMAC_TYPE;
2819                 break;
2820         default:
2821                 CPT_LOG_DP_ERR("Crypto: Undefined cipher algo %u specified",
2822                                a_form->algo);
2823                 return -1;
2824         }
2825
2826         sess->zsk_flag = 0;
2827         sess->aes_gcm = 0;
2828         sess->is_gmac = 1;
2829         sess->iv_offset = a_form->iv.offset;
2830         sess->iv_length = a_form->iv.length;
2831         sess->mac_len = a_form->digest_length;
2832
2833         if (unlikely(cpt_fc_ciph_set_key(ctx, enc_type, a_form->key.data,
2834                         a_form->key.length, NULL)))
2835                 return -1;
2836
2837         if (unlikely(cpt_fc_auth_set_key(ctx, auth_type, NULL, 0,
2838                         a_form->digest_length)))
2839                 return -1;
2840
2841         return 0;
2842 }
2843
2844 static __rte_always_inline void *
2845 alloc_op_meta(struct rte_mbuf *m_src,
2846               buf_ptr_t *buf,
2847               int32_t len,
2848               struct rte_mempool *cpt_meta_pool)
2849 {
2850         uint8_t *mdata;
2851
2852 #ifndef CPT_ALWAYS_USE_SEPARATE_BUF
2853         if (likely(m_src && (m_src->nb_segs == 1))) {
2854                 int32_t tailroom;
2855                 phys_addr_t mphys;
2856
2857                 /* Check if tailroom is sufficient to hold meta data */
2858                 tailroom = rte_pktmbuf_tailroom(m_src);
2859                 if (likely(tailroom > len + 8)) {
2860                         mdata = (uint8_t *)m_src->buf_addr + m_src->buf_len;
2861                         mphys = m_src->buf_physaddr + m_src->buf_len;
2862                         mdata -= len;
2863                         mphys -= len;
2864                         buf->vaddr = mdata;
2865                         buf->dma_addr = mphys;
2866                         buf->size = len;
2867                         /* Indicate that this is a mbuf allocated mdata */
2868                         mdata = (uint8_t *)((uint64_t)mdata | 1ull);
2869                         return mdata;
2870                 }
2871         }
2872 #else
2873         RTE_SET_USED(m_src);
2874 #endif
2875
2876         if (unlikely(rte_mempool_get(cpt_meta_pool, (void **)&mdata) < 0))
2877                 return NULL;
2878
2879         buf->vaddr = mdata;
2880         buf->dma_addr = rte_mempool_virt2iova(mdata);
2881         buf->size = len;
2882
2883         return mdata;
2884 }
2885
2886 /**
2887  * cpt_free_metabuf - free metabuf to mempool.
2888  * @param instance: pointer to instance.
2889  * @param objp: pointer to the metabuf.
2890  */
2891 static __rte_always_inline void
2892 free_op_meta(void *mdata, struct rte_mempool *cpt_meta_pool)
2893 {
2894         bool nofree = ((uintptr_t)mdata & 1ull);
2895
2896         if (likely(nofree))
2897                 return;
2898         rte_mempool_put(cpt_meta_pool, mdata);
2899 }
2900
2901 static __rte_always_inline uint32_t
2902 prepare_iov_from_pkt(struct rte_mbuf *pkt,
2903                      iov_ptr_t *iovec, uint32_t start_offset)
2904 {
2905         uint16_t index = 0;
2906         void *seg_data = NULL;
2907         phys_addr_t seg_phys;
2908         int32_t seg_size = 0;
2909
2910         if (!pkt) {
2911                 iovec->buf_cnt = 0;
2912                 return 0;
2913         }
2914
2915         if (!start_offset) {
2916                 seg_data = rte_pktmbuf_mtod(pkt, void *);
2917                 seg_phys = rte_pktmbuf_mtophys(pkt);
2918                 seg_size = pkt->data_len;
2919         } else {
2920                 while (start_offset >= pkt->data_len) {
2921                         start_offset -= pkt->data_len;
2922                         pkt = pkt->next;
2923                 }
2924
2925                 seg_data = rte_pktmbuf_mtod_offset(pkt, void *, start_offset);
2926                 seg_phys = rte_pktmbuf_mtophys_offset(pkt, start_offset);
2927                 seg_size = pkt->data_len - start_offset;
2928                 if (!seg_size)
2929                         return 1;
2930         }
2931
2932         /* first seg */
2933         iovec->bufs[index].vaddr = seg_data;
2934         iovec->bufs[index].dma_addr = seg_phys;
2935         iovec->bufs[index].size = seg_size;
2936         index++;
2937         pkt = pkt->next;
2938
2939         while (unlikely(pkt != NULL)) {
2940                 seg_data = rte_pktmbuf_mtod(pkt, void *);
2941                 seg_phys = rte_pktmbuf_mtophys(pkt);
2942                 seg_size = pkt->data_len;
2943                 if (!seg_size)
2944                         break;
2945
2946                 iovec->bufs[index].vaddr = seg_data;
2947                 iovec->bufs[index].dma_addr = seg_phys;
2948                 iovec->bufs[index].size = seg_size;
2949
2950                 index++;
2951
2952                 pkt = pkt->next;
2953         }
2954
2955         iovec->buf_cnt = index;
2956         return 0;
2957 }
2958
2959 static __rte_always_inline uint32_t
2960 prepare_iov_from_pkt_inplace(struct rte_mbuf *pkt,
2961                              fc_params_t *param,
2962                              uint32_t *flags)
2963 {
2964         uint16_t index = 0;
2965         void *seg_data = NULL;
2966         phys_addr_t seg_phys;
2967         uint32_t seg_size = 0;
2968         iov_ptr_t *iovec;
2969
2970         seg_data = rte_pktmbuf_mtod(pkt, void *);
2971         seg_phys = rte_pktmbuf_mtophys(pkt);
2972         seg_size = pkt->data_len;
2973
2974         /* first seg */
2975         if (likely(!pkt->next)) {
2976                 uint32_t headroom, tailroom;
2977
2978                 *flags |= SINGLE_BUF_INPLACE;
2979                 headroom = rte_pktmbuf_headroom(pkt);
2980                 tailroom = rte_pktmbuf_tailroom(pkt);
2981                 if (likely((headroom >= 24) &&
2982                     (tailroom >= 8))) {
2983                         /* In 83XX this is prerequivisit for Direct mode */
2984                         *flags |= SINGLE_BUF_HEADTAILROOM;
2985                 }
2986                 param->bufs[0].vaddr = seg_data;
2987                 param->bufs[0].dma_addr = seg_phys;
2988                 param->bufs[0].size = seg_size;
2989                 return 0;
2990         }
2991         iovec = param->src_iov;
2992         iovec->bufs[index].vaddr = seg_data;
2993         iovec->bufs[index].dma_addr = seg_phys;
2994         iovec->bufs[index].size = seg_size;
2995         index++;
2996         pkt = pkt->next;
2997
2998         while (unlikely(pkt != NULL)) {
2999                 seg_data = rte_pktmbuf_mtod(pkt, void *);
3000                 seg_phys = rte_pktmbuf_mtophys(pkt);
3001                 seg_size = pkt->data_len;
3002
3003                 if (!seg_size)
3004                         break;
3005
3006                 iovec->bufs[index].vaddr = seg_data;
3007                 iovec->bufs[index].dma_addr = seg_phys;
3008                 iovec->bufs[index].size = seg_size;
3009
3010                 index++;
3011
3012                 pkt = pkt->next;
3013         }
3014
3015         iovec->buf_cnt = index;
3016         return 0;
3017 }
3018
3019 static __rte_always_inline int
3020 fill_fc_params(struct rte_crypto_op *cop,
3021                struct cpt_sess_misc *sess_misc,
3022                struct cpt_qp_meta_info *m_info,
3023                void **mdata_ptr,
3024                void **prep_req)
3025 {
3026         uint32_t space = 0;
3027         struct rte_crypto_sym_op *sym_op = cop->sym;
3028         void *mdata = NULL;
3029         uintptr_t *op;
3030         uint32_t mc_hash_off;
3031         uint32_t flags = 0;
3032         uint64_t d_offs, d_lens;
3033         struct rte_mbuf *m_src, *m_dst;
3034         uint8_t cpt_op = sess_misc->cpt_op;
3035 #ifdef CPT_ALWAYS_USE_SG_MODE
3036         uint8_t inplace = 0;
3037 #else
3038         uint8_t inplace = 1;
3039 #endif
3040         fc_params_t fc_params;
3041         char src[SRC_IOV_SIZE];
3042         char dst[SRC_IOV_SIZE];
3043         uint32_t iv_buf[4];
3044         int ret;
3045
3046         if (likely(sess_misc->iv_length)) {
3047                 flags |= VALID_IV_BUF;
3048                 fc_params.iv_buf = rte_crypto_op_ctod_offset(cop,
3049                                    uint8_t *, sess_misc->iv_offset);
3050                 if (sess_misc->aes_ctr &&
3051                     unlikely(sess_misc->iv_length != 16)) {
3052                         memcpy((uint8_t *)iv_buf,
3053                                 rte_crypto_op_ctod_offset(cop,
3054                                 uint8_t *, sess_misc->iv_offset), 12);
3055                         iv_buf[3] = rte_cpu_to_be_32(0x1);
3056                         fc_params.iv_buf = iv_buf;
3057                 }
3058         }
3059
3060         if (sess_misc->zsk_flag) {
3061                 fc_params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3062                                         uint8_t *,
3063                                         sess_misc->auth_iv_offset);
3064                 if (sess_misc->zsk_flag != ZS_EA)
3065                         inplace = 0;
3066         }
3067         m_src = sym_op->m_src;
3068         m_dst = sym_op->m_dst;
3069
3070         if (sess_misc->aes_gcm) {
3071                 uint8_t *salt;
3072                 uint8_t *aad_data;
3073                 uint16_t aad_len;
3074
3075                 d_offs = sym_op->aead.data.offset;
3076                 d_lens = sym_op->aead.data.length;
3077                 mc_hash_off = sym_op->aead.data.offset +
3078                               sym_op->aead.data.length;
3079
3080                 aad_data = sym_op->aead.aad.data;
3081                 aad_len = sess_misc->aad_length;
3082                 if (likely((aad_data + aad_len) ==
3083                            rte_pktmbuf_mtod_offset(m_src,
3084                                 uint8_t *,
3085                                 sym_op->aead.data.offset))) {
3086                         d_offs = (d_offs - aad_len) | (d_offs << 16);
3087                         d_lens = (d_lens + aad_len) | (d_lens << 32);
3088                 } else {
3089                         fc_params.aad_buf.vaddr = sym_op->aead.aad.data;
3090                         fc_params.aad_buf.dma_addr = sym_op->aead.aad.phys_addr;
3091                         fc_params.aad_buf.size = aad_len;
3092                         flags |= VALID_AAD_BUF;
3093                         inplace = 0;
3094                         d_offs = d_offs << 16;
3095                         d_lens = d_lens << 32;
3096                 }
3097
3098                 salt = fc_params.iv_buf;
3099                 if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3100                         cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3101                         sess_misc->salt = *(uint32_t *)salt;
3102                 }
3103                 fc_params.iv_buf = salt + 4;
3104                 if (likely(sess_misc->mac_len)) {
3105                         struct rte_mbuf *m = (cpt_op & CPT_OP_ENCODE) ? m_dst :
3106                                              m_src;
3107
3108                         if (!m)
3109                                 m = m_src;
3110
3111                         /* hmac immediately following data is best case */
3112                         if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3113                             mc_hash_off !=
3114                             (uint8_t *)sym_op->aead.digest.data)) {
3115                                 flags |= VALID_MAC_BUF;
3116                                 fc_params.mac_buf.size = sess_misc->mac_len;
3117                                 fc_params.mac_buf.vaddr =
3118                                   sym_op->aead.digest.data;
3119                                 fc_params.mac_buf.dma_addr =
3120                                  sym_op->aead.digest.phys_addr;
3121                                 inplace = 0;
3122                         }
3123                 }
3124         } else {
3125                 d_offs = sym_op->cipher.data.offset;
3126                 d_lens = sym_op->cipher.data.length;
3127                 mc_hash_off = sym_op->cipher.data.offset +
3128                               sym_op->cipher.data.length;
3129                 d_offs = (d_offs << 16) | sym_op->auth.data.offset;
3130                 d_lens = (d_lens << 32) | sym_op->auth.data.length;
3131
3132                 if (mc_hash_off < (sym_op->auth.data.offset +
3133                                    sym_op->auth.data.length)){
3134                         mc_hash_off = (sym_op->auth.data.offset +
3135                                        sym_op->auth.data.length);
3136                 }
3137                 /* for gmac, salt should be updated like in gcm */
3138                 if (unlikely(sess_misc->is_gmac)) {
3139                         uint8_t *salt;
3140                         salt = fc_params.iv_buf;
3141                         if (unlikely(*(uint32_t *)salt != sess_misc->salt)) {
3142                                 cpt_fc_salt_update(SESS_PRIV(sess_misc), salt);
3143                                 sess_misc->salt = *(uint32_t *)salt;
3144                         }
3145                         fc_params.iv_buf = salt + 4;
3146                 }
3147                 if (likely(sess_misc->mac_len)) {
3148                         struct rte_mbuf *m;
3149
3150                         m = (cpt_op & CPT_OP_ENCODE) ? m_dst : m_src;
3151                         if (!m)
3152                                 m = m_src;
3153
3154                         /* hmac immediately following data is best case */
3155                         if (unlikely(rte_pktmbuf_mtod(m, uint8_t *) +
3156                             mc_hash_off !=
3157                              (uint8_t *)sym_op->auth.digest.data)) {
3158                                 flags |= VALID_MAC_BUF;
3159                                 fc_params.mac_buf.size =
3160                                         sess_misc->mac_len;
3161                                 fc_params.mac_buf.vaddr =
3162                                         sym_op->auth.digest.data;
3163                                 fc_params.mac_buf.dma_addr =
3164                                 sym_op->auth.digest.phys_addr;
3165                                 inplace = 0;
3166                         }
3167                 }
3168         }
3169         fc_params.ctx_buf.vaddr = SESS_PRIV(sess_misc);
3170         fc_params.ctx_buf.dma_addr = sess_misc->ctx_dma_addr;
3171
3172         if (unlikely(sess_misc->is_null || sess_misc->cpt_op == CPT_OP_DECODE))
3173                 inplace = 0;
3174
3175         if (likely(!m_dst && inplace)) {
3176                 /* Case of single buffer without AAD buf or
3177                  * separate mac buf in place and
3178                  * not air crypto
3179                  */
3180                 fc_params.dst_iov = fc_params.src_iov = (void *)src;
3181
3182                 if (unlikely(prepare_iov_from_pkt_inplace(m_src,
3183                                                           &fc_params,
3184                                                           &flags))) {
3185                         CPT_LOG_DP_ERR("Prepare inplace src iov failed");
3186                         ret = -EINVAL;
3187                         goto err_exit;
3188                 }
3189
3190         } else {
3191                 /* Out of place processing */
3192                 fc_params.src_iov = (void *)src;
3193                 fc_params.dst_iov = (void *)dst;
3194
3195                 /* Store SG I/O in the api for reuse */
3196                 if (prepare_iov_from_pkt(m_src, fc_params.src_iov, 0)) {
3197                         CPT_LOG_DP_ERR("Prepare src iov failed");
3198                         ret = -EINVAL;
3199                         goto err_exit;
3200                 }
3201
3202                 if (unlikely(m_dst != NULL)) {
3203                         uint32_t pkt_len;
3204
3205                         /* Try to make room as much as src has */
3206                         pkt_len = rte_pktmbuf_pkt_len(m_dst);
3207
3208                         if (unlikely(pkt_len < rte_pktmbuf_pkt_len(m_src))) {
3209                                 pkt_len = rte_pktmbuf_pkt_len(m_src) - pkt_len;
3210                                 if (!rte_pktmbuf_append(m_dst, pkt_len)) {
3211                                         CPT_LOG_DP_ERR("Not enough space in "
3212                                                        "m_dst %p, need %u"
3213                                                        " more",
3214                                                        m_dst, pkt_len);
3215                                         ret = -EINVAL;
3216                                         goto err_exit;
3217                                 }
3218                         }
3219
3220                         if (prepare_iov_from_pkt(m_dst, fc_params.dst_iov, 0)) {
3221                                 CPT_LOG_DP_ERR("Prepare dst iov failed for "
3222                                                "m_dst %p", m_dst);
3223                                 ret = -EINVAL;
3224                                 goto err_exit;
3225                         }
3226                 } else {
3227                         fc_params.dst_iov = (void *)src;
3228                 }
3229         }
3230
3231         if (likely(flags & SINGLE_BUF_HEADTAILROOM))
3232                 mdata = alloc_op_meta(m_src, &fc_params.meta_buf,
3233                                       m_info->lb_mlen, m_info->pool);
3234         else
3235                 mdata = alloc_op_meta(NULL, &fc_params.meta_buf,
3236                                       m_info->sg_mlen, m_info->pool);
3237
3238         if (unlikely(mdata == NULL)) {
3239                 CPT_LOG_DP_ERR("Error allocating meta buffer for request");
3240                 ret = -ENOMEM;
3241                 goto err_exit;
3242         }
3243
3244         op = (uintptr_t *)((uintptr_t)mdata & (uintptr_t)~1ull);
3245         op[0] = (uintptr_t)mdata;
3246         op[1] = (uintptr_t)cop;
3247         op[2] = op[3] = 0; /* Used to indicate auth verify */
3248         space += 4 * sizeof(uint64_t);
3249
3250         fc_params.meta_buf.vaddr = (uint8_t *)op + space;
3251         fc_params.meta_buf.dma_addr += space;
3252         fc_params.meta_buf.size -= space;
3253
3254         /* Finally prepare the instruction */
3255         if (cpt_op & CPT_OP_ENCODE)
3256                 *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens,
3257                                                  &fc_params, op);
3258         else
3259                 *prep_req = cpt_fc_dec_hmac_prep(flags, d_offs, d_lens,
3260                                                  &fc_params, op);
3261
3262         if (unlikely(*prep_req == NULL)) {
3263                 CPT_LOG_DP_ERR("Preparing request failed due to bad input arg");
3264                 ret = -EINVAL;
3265                 goto free_mdata_and_exit;
3266         }
3267
3268         *mdata_ptr = mdata;
3269
3270         return 0;
3271
3272 free_mdata_and_exit:
3273         free_op_meta(mdata, m_info->pool);
3274 err_exit:
3275         return ret;
3276 }
3277
3278 static __rte_always_inline void
3279 compl_auth_verify(struct rte_crypto_op *op,
3280                       uint8_t *gen_mac,
3281                       uint64_t mac_len)
3282 {
3283         uint8_t *mac;
3284         struct rte_crypto_sym_op *sym_op = op->sym;
3285
3286         if (sym_op->auth.digest.data)
3287                 mac = sym_op->auth.digest.data;
3288         else
3289                 mac = rte_pktmbuf_mtod_offset(sym_op->m_src,
3290                                               uint8_t *,
3291                                               sym_op->auth.data.length +
3292                                               sym_op->auth.data.offset);
3293         if (!mac) {
3294                 op->status = RTE_CRYPTO_OP_STATUS_ERROR;
3295                 return;
3296         }
3297
3298         if (memcmp(mac, gen_mac, mac_len))
3299                 op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
3300         else
3301                 op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
3302 }
3303
3304 static __rte_always_inline void
3305 find_kasumif9_direction_and_length(uint8_t *src,
3306                                    uint32_t counter_num_bytes,
3307                                    uint32_t *addr_length_in_bits,
3308                                    uint8_t *addr_direction)
3309 {
3310         uint8_t found = 0;
3311         uint32_t pos;
3312         uint8_t last_byte;
3313         while (!found && counter_num_bytes > 0) {
3314                 counter_num_bytes--;
3315                 if (src[counter_num_bytes] == 0x00)
3316                         continue;
3317                 pos = rte_bsf32(src[counter_num_bytes]);
3318                 if (pos == 7) {
3319                         if (likely(counter_num_bytes > 0)) {
3320                                 last_byte = src[counter_num_bytes - 1];
3321                                 *addr_direction  =  last_byte & 0x1;
3322                                 *addr_length_in_bits = counter_num_bytes * 8
3323                                                         - 1;
3324                         }
3325                 } else {
3326                         last_byte = src[counter_num_bytes];
3327                         *addr_direction = (last_byte >> (pos + 1)) & 0x1;
3328                         *addr_length_in_bits = counter_num_bytes * 8
3329                                                 + (8 - (pos + 2));
3330                 }
3331                 found = 1;
3332         }
3333 }
3334
3335 /*
3336  * This handles all auth only except AES_GMAC
3337  */
3338 static __rte_always_inline int
3339 fill_digest_params(struct rte_crypto_op *cop,
3340                    struct cpt_sess_misc *sess,
3341                    struct cpt_qp_meta_info *m_info,
3342                    void **mdata_ptr,
3343                    void **prep_req)
3344 {
3345         uint32_t space = 0;
3346         struct rte_crypto_sym_op *sym_op = cop->sym;
3347         void *mdata;
3348         phys_addr_t mphys;
3349         uint64_t *op;
3350         uint32_t auth_range_off;
3351         uint32_t flags = 0;
3352         uint64_t d_offs = 0, d_lens;
3353         struct rte_mbuf *m_src, *m_dst;
3354         uint16_t auth_op = sess->cpt_op & CPT_OP_AUTH_MASK;
3355         uint16_t mac_len = sess->mac_len;
3356         fc_params_t params;
3357         char src[SRC_IOV_SIZE];
3358         uint8_t iv_buf[16];
3359         int ret;
3360
3361         memset(&params, 0, sizeof(fc_params_t));
3362
3363         m_src = sym_op->m_src;
3364
3365         /* For just digest lets force mempool alloc */
3366         mdata = alloc_op_meta(NULL, &params.meta_buf, m_info->sg_mlen,
3367                               m_info->pool);
3368         if (mdata == NULL) {
3369                 ret = -ENOMEM;
3370                 goto err_exit;
3371         }
3372
3373         mphys = params.meta_buf.dma_addr;
3374
3375         op = mdata;
3376         op[0] = (uintptr_t)mdata;
3377         op[1] = (uintptr_t)cop;
3378         op[2] = op[3] = 0; /* Used to indicate auth verify */
3379         space += 4 * sizeof(uint64_t);
3380
3381         auth_range_off = sym_op->auth.data.offset;
3382
3383         flags = VALID_MAC_BUF;
3384         params.src_iov = (void *)src;
3385         if (unlikely(sess->zsk_flag)) {
3386                 /*
3387                  * Since for Zuc, Kasumi, Snow3g offsets are in bits
3388                  * we will send pass through even for auth only case,
3389                  * let MC handle it
3390                  */
3391                 d_offs = auth_range_off;
3392                 auth_range_off = 0;
3393                 params.auth_iv_buf = rte_crypto_op_ctod_offset(cop,
3394                                         uint8_t *, sess->auth_iv_offset);
3395                 if (sess->zsk_flag == K_F9) {
3396                         uint32_t length_in_bits, num_bytes;
3397                         uint8_t *src, direction = 0;
3398
3399                         memcpy(iv_buf, rte_pktmbuf_mtod(cop->sym->m_src,
3400                                                         uint8_t *), 8);
3401                         /*
3402                          * This is kasumi f9, take direction from
3403                          * source buffer
3404                          */
3405                         length_in_bits = cop->sym->auth.data.length;
3406                         num_bytes = (length_in_bits >> 3);
3407                         src = rte_pktmbuf_mtod(cop->sym->m_src, uint8_t *);
3408                         find_kasumif9_direction_and_length(src,
3409                                                 num_bytes,
3410                                                 &length_in_bits,
3411                                                 &direction);
3412                         length_in_bits -= 64;
3413                         cop->sym->auth.data.offset += 64;
3414                         d_offs = cop->sym->auth.data.offset;
3415                         auth_range_off = d_offs / 8;
3416                         cop->sym->auth.data.length = length_in_bits;
3417
3418                         /* Store it at end of auth iv */
3419                         iv_buf[8] = direction;
3420                         params.auth_iv_buf = iv_buf;
3421                 }
3422         }
3423
3424         d_lens = sym_op->auth.data.length;
3425
3426         params.ctx_buf.vaddr = SESS_PRIV(sess);
3427         params.ctx_buf.dma_addr = sess->ctx_dma_addr;
3428
3429         if (auth_op == CPT_OP_AUTH_GENERATE) {
3430                 if (sym_op->auth.digest.data) {
3431                         /*
3432                          * Digest to be generated
3433                          * in separate buffer
3434                          */
3435                         params.mac_buf.size =
3436                                 sess->mac_len;
3437                         params.mac_buf.vaddr =
3438                                 sym_op->auth.digest.data;
3439                         params.mac_buf.dma_addr =
3440                                 sym_op->auth.digest.phys_addr;
3441                 } else {
3442                         uint32_t off = sym_op->auth.data.offset +
3443                                 sym_op->auth.data.length;
3444                         int32_t dlen, space;
3445
3446                         m_dst = sym_op->m_dst ?
3447                                 sym_op->m_dst : sym_op->m_src;
3448                         dlen = rte_pktmbuf_pkt_len(m_dst);
3449
3450                         space = off + mac_len - dlen;
3451                         if (space > 0)
3452                                 if (!rte_pktmbuf_append(m_dst, space)) {
3453                                         CPT_LOG_DP_ERR("Failed to extend "
3454                                                        "mbuf by %uB", space);
3455                                         ret = -EINVAL;
3456                                         goto free_mdata_and_exit;
3457                                 }
3458
3459                         params.mac_buf.vaddr =
3460                                 rte_pktmbuf_mtod_offset(m_dst, void *, off);
3461                         params.mac_buf.dma_addr =
3462                                 rte_pktmbuf_mtophys_offset(m_dst, off);
3463                         params.mac_buf.size = mac_len;
3464                 }
3465         } else {
3466                 /* Need space for storing generated mac */
3467                 params.mac_buf.vaddr = (uint8_t *)mdata + space;
3468                 params.mac_buf.dma_addr = mphys + space;
3469                 params.mac_buf.size = mac_len;
3470                 space += RTE_ALIGN_CEIL(mac_len, 8);
3471                 op[2] = (uintptr_t)params.mac_buf.vaddr;
3472                 op[3] = mac_len;
3473         }
3474
3475         params.meta_buf.vaddr = (uint8_t *)mdata + space;
3476         params.meta_buf.dma_addr = mphys + space;
3477         params.meta_buf.size -= space;
3478
3479         /* Out of place processing */
3480         params.src_iov = (void *)src;
3481
3482         /*Store SG I/O in the api for reuse */
3483         if (prepare_iov_from_pkt(m_src, params.src_iov, auth_range_off)) {
3484                 CPT_LOG_DP_ERR("Prepare src iov failed");
3485                 ret = -EINVAL;
3486                 goto free_mdata_and_exit;
3487         }
3488
3489         *prep_req = cpt_fc_enc_hmac_prep(flags, d_offs, d_lens, &params, op);
3490         if (unlikely(*prep_req == NULL)) {
3491                 ret = -EINVAL;
3492                 goto free_mdata_and_exit;
3493         }
3494
3495         *mdata_ptr = mdata;
3496
3497         return 0;
3498
3499 free_mdata_and_exit:
3500         free_op_meta(mdata, m_info->pool);
3501 err_exit:
3502         return ret;
3503 }
3504
3505 #endif /*_CPT_UCODE_H_ */