1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
10 #include <rte_mempool.h>
11 #include <rte_class.h>
12 #include <rte_malloc.h>
13 #include <rte_eal_paging.h>
15 #include "mlx5_common.h"
16 #include "mlx5_common_os.h"
17 #include "mlx5_common_mp.h"
18 #include "mlx5_common_log.h"
19 #include "mlx5_common_defs.h"
20 #include "mlx5_common_private.h"
22 uint8_t haswell_broadwell_cpu;
24 /* In case this is an x86_64 intel processor to check if
25 * we should use relaxed ordering.
27 #ifdef RTE_ARCH_X86_64
29 * This function returns processor identification and feature information
32 * @param eax, ebx, ecx, edx
33 * Pointers to the registers that will hold cpu information.
35 * The main category of information returned.
37 static inline void mlx5_cpu_id(unsigned int level,
38 unsigned int *eax, unsigned int *ebx,
39 unsigned int *ecx, unsigned int *edx)
42 : "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
47 RTE_LOG_REGISTER_DEFAULT(mlx5_common_logtype, NOTICE)
49 /* Head of list of drivers. */
50 static TAILQ_HEAD(mlx5_drivers, mlx5_class_driver) drivers_list =
51 TAILQ_HEAD_INITIALIZER(drivers_list);
53 /* Head of devices. */
54 static TAILQ_HEAD(mlx5_devices, mlx5_common_device) devices_list =
55 TAILQ_HEAD_INITIALIZER(devices_list);
56 static pthread_mutex_t devices_list_lock;
60 unsigned int drv_class;
62 { .name = "vdpa", .drv_class = MLX5_CLASS_VDPA },
63 { .name = "eth", .drv_class = MLX5_CLASS_ETH },
64 /* Keep class "net" for backward compatibility. */
65 { .name = "net", .drv_class = MLX5_CLASS_ETH },
66 { .name = "regex", .drv_class = MLX5_CLASS_REGEX },
67 { .name = "compress", .drv_class = MLX5_CLASS_COMPRESS },
68 { .name = "crypto", .drv_class = MLX5_CLASS_CRYPTO },
72 class_name_to_value(const char *class_name)
76 for (i = 0; i < RTE_DIM(mlx5_classes); i++) {
77 if (strcmp(class_name, mlx5_classes[i].name) == 0)
78 return mlx5_classes[i].drv_class;
83 static struct mlx5_class_driver *
84 driver_get(uint32_t class)
86 struct mlx5_class_driver *driver;
88 TAILQ_FOREACH(driver, &drivers_list, next) {
89 if ((uint32_t)driver->drv_class == class)
96 * Verify and store value for devargs.
99 * Key argument to verify.
101 * Value associated with key.
106 * 0 on success, a negative errno value otherwise and rte_errno is set.
109 mlx5_common_args_check_handler(const char *key, const char *val, void *opaque)
111 struct mlx5_common_dev_config *config = opaque;
115 tmp = strtol(val, NULL, 0);
118 DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer.", key, val);
121 if (strcmp(key, "tx_db_nc") == 0) {
122 if (tmp != MLX5_TXDB_CACHED &&
123 tmp != MLX5_TXDB_NCACHED &&
124 tmp != MLX5_TXDB_HEURISTIC) {
125 DRV_LOG(ERR, "Invalid Tx doorbell mapping parameter.");
130 } else if (strcmp(key, "mr_ext_memseg_en") == 0) {
131 config->mr_ext_memseg_en = !!tmp;
132 } else if (strcmp(key, "mr_mempool_reg_en") == 0) {
133 config->mr_mempool_reg_en = !!tmp;
134 } else if (strcmp(key, "sys_mem_en") == 0) {
135 config->sys_mem_en = !!tmp;
141 * Parse common device parameters.
144 * Device arguments structure.
146 * Pointer to device configuration structure.
149 * 0 on success, a negative errno value otherwise and rte_errno is set.
152 mlx5_common_config_get(struct rte_devargs *devargs,
153 struct mlx5_common_dev_config *config)
155 struct rte_kvargs *kvlist;
159 config->mr_ext_memseg_en = 1;
160 config->mr_mempool_reg_en = 1;
161 config->sys_mem_en = 0;
162 config->dbnc = MLX5_ARG_UNSET;
165 kvlist = rte_kvargs_parse(devargs->args, NULL);
166 if (kvlist == NULL) {
170 ret = rte_kvargs_process(kvlist, NULL, mlx5_common_args_check_handler,
174 rte_kvargs_free(kvlist);
175 DRV_LOG(DEBUG, "mr_ext_memseg_en is %u.", config->mr_ext_memseg_en);
176 DRV_LOG(DEBUG, "mr_mempool_reg_en is %u.", config->mr_mempool_reg_en);
177 DRV_LOG(DEBUG, "sys_mem_en is %u.", config->sys_mem_en);
178 DRV_LOG(DEBUG, "Tx doorbell mapping parameter is %d.", config->dbnc);
183 devargs_class_handler(__rte_unused const char *key,
184 const char *class_names, void *opaque)
193 scratch = strdup(class_names);
194 if (scratch == NULL) {
198 found = strtok_r(scratch, ":", &refstr);
203 /* Extract each individual class name. Multiple
204 * classes can be supplied as class=net:regex:foo:bar.
206 class_val = class_name_to_value(found);
207 /* Check if its a valid class. */
213 found = strtok_r(NULL, ":", &refstr);
214 } while (found != NULL);
218 DRV_LOG(ERR, "Invalid mlx5 class options: %s.\n", class_names);
223 parse_class_options(const struct rte_devargs *devargs)
225 struct rte_kvargs *kvlist;
230 if (devargs->cls != NULL && devargs->cls->name != NULL)
231 /* Global syntax, only one class type. */
232 return class_name_to_value(devargs->cls->name);
233 /* Legacy devargs support multiple classes. */
234 kvlist = rte_kvargs_parse(devargs->args, NULL);
237 rte_kvargs_process(kvlist, RTE_DEVARGS_KEY_CLASS,
238 devargs_class_handler, &ret);
239 rte_kvargs_free(kvlist);
243 static const unsigned int mlx5_class_invalid_combinations[] = {
244 MLX5_CLASS_ETH | MLX5_CLASS_VDPA,
245 /* New class combination should be added here. */
249 is_valid_class_combination(uint32_t user_classes)
253 /* Verify if user specified unsupported combination. */
254 for (i = 0; i < RTE_DIM(mlx5_class_invalid_combinations); i++) {
255 if ((mlx5_class_invalid_combinations[i] & user_classes) ==
256 mlx5_class_invalid_combinations[i])
259 /* Not found any invalid class combination. */
264 mlx5_bus_match(const struct mlx5_class_driver *drv,
265 const struct rte_device *dev)
267 if (mlx5_dev_is_pci(dev))
268 return mlx5_dev_pci_match(drv, dev);
272 static struct mlx5_common_device *
273 to_mlx5_device(const struct rte_device *rte_dev)
275 struct mlx5_common_device *cdev;
277 TAILQ_FOREACH(cdev, &devices_list, next) {
278 if (rte_dev == cdev->dev)
285 mlx5_dev_to_pci_str(const struct rte_device *dev, char *addr, size_t size)
287 struct rte_pci_addr pci_addr = { 0 };
290 if (mlx5_dev_is_pci(dev)) {
291 /* Input might be <BDF>, format PCI address to <DBDF>. */
292 ret = rte_pci_addr_parse(dev->name, &pci_addr);
295 rte_pci_device_name(&pci_addr, addr, size);
298 #ifdef RTE_EXEC_ENV_LINUX
299 return mlx5_auxiliary_get_pci_str(RTE_DEV_TO_AUXILIARY_CONST(dev),
308 * Register the mempool for the protection domain.
311 * Pointer to the mlx5 common device.
313 * Mempool being registered.
316 * 0 on success, (-1) on failure and rte_errno is set.
319 mlx5_dev_mempool_register(struct mlx5_common_device *cdev,
320 struct rte_mempool *mp)
322 return mlx5_mr_mempool_register(cdev, mp);
326 * Unregister the mempool from the protection domain.
329 * Pointer to the mlx5 common device.
331 * Mempool being unregistered.
334 mlx5_dev_mempool_unregister(struct mlx5_common_device *cdev,
335 struct rte_mempool *mp)
337 if (mlx5_mr_mempool_unregister(cdev, mp) < 0)
338 DRV_LOG(WARNING, "Failed to unregister mempool %s for PD %p: %s",
339 mp->name, cdev->pd, rte_strerror(rte_errno));
343 * rte_mempool_walk() callback to register mempools for the protection domain.
346 * The mempool being walked.
348 * Pointer to the device shared context.
351 mlx5_dev_mempool_register_cb(struct rte_mempool *mp, void *arg)
353 struct mlx5_common_device *cdev = arg;
356 ret = mlx5_dev_mempool_register(cdev, mp);
357 if (ret < 0 && rte_errno != EEXIST)
359 "Failed to register existing mempool %s for PD %p: %s",
360 mp->name, cdev->pd, rte_strerror(rte_errno));
364 * rte_mempool_walk() callback to unregister mempools
365 * from the protection domain.
368 * The mempool being walked.
370 * Pointer to the device shared context.
373 mlx5_dev_mempool_unregister_cb(struct rte_mempool *mp, void *arg)
375 mlx5_dev_mempool_unregister((struct mlx5_common_device *)arg, mp);
379 * Mempool life cycle callback for mlx5 common devices.
382 * Mempool life cycle event.
384 * Associated mempool.
386 * Pointer to a device shared context.
389 mlx5_dev_mempool_event_cb(enum rte_mempool_event event, struct rte_mempool *mp,
392 struct mlx5_common_device *cdev = arg;
393 bool extmem = rte_pktmbuf_priv_flags(mp) &
394 RTE_PKTMBUF_POOL_F_PINNED_EXT_BUF;
397 case RTE_MEMPOOL_EVENT_READY:
400 if (mlx5_dev_mempool_register(cdev, mp) < 0)
402 "Failed to register new mempool %s for PD %p: %s",
403 mp->name, cdev->pd, rte_strerror(rte_errno));
405 case RTE_MEMPOOL_EVENT_DESTROY:
406 mlx5_dev_mempool_unregister(cdev, mp);
412 mlx5_dev_mempool_subscribe(struct mlx5_common_device *cdev)
416 if (!cdev->config.mr_mempool_reg_en)
418 rte_rwlock_write_lock(&cdev->mr_scache.mprwlock);
419 if (cdev->mr_scache.mp_cb_registered)
421 /* Callback for this device may be already registered. */
422 ret = rte_mempool_event_callback_register(mlx5_dev_mempool_event_cb,
424 if (ret != 0 && rte_errno != EEXIST)
426 /* Register mempools only once for this device. */
428 rte_mempool_walk(mlx5_dev_mempool_register_cb, cdev);
430 cdev->mr_scache.mp_cb_registered = 1;
432 rte_rwlock_write_unlock(&cdev->mr_scache.mprwlock);
437 mlx5_dev_mempool_unsubscribe(struct mlx5_common_device *cdev)
441 if (!cdev->mr_scache.mp_cb_registered ||
442 !cdev->config.mr_mempool_reg_en)
444 /* Stop watching for mempool events and unregister all mempools. */
445 ret = rte_mempool_event_callback_unregister(mlx5_dev_mempool_event_cb,
448 rte_mempool_walk(mlx5_dev_mempool_unregister_cb, cdev);
452 * Callback for memory event.
462 mlx5_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,
463 size_t len, void *arg __rte_unused)
465 struct mlx5_common_device *cdev;
467 /* Must be called from the primary process. */
468 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
469 switch (event_type) {
470 case RTE_MEM_EVENT_FREE:
471 pthread_mutex_lock(&devices_list_lock);
472 /* Iterate all the existing mlx5 devices. */
473 TAILQ_FOREACH(cdev, &devices_list, next)
474 mlx5_free_mr_by_addr(&cdev->mr_scache,
475 mlx5_os_get_ctx_device_name
478 pthread_mutex_unlock(&devices_list_lock);
480 case RTE_MEM_EVENT_ALLOC:
487 * Uninitialize all HW global of device context.
490 * Pointer to mlx5 device structure.
493 * 0 on success, a negative errno value otherwise and rte_errno is set.
496 mlx5_dev_hw_global_release(struct mlx5_common_device *cdev)
498 if (cdev->pd != NULL) {
499 claim_zero(mlx5_os_dealloc_pd(cdev->pd));
502 if (cdev->ctx != NULL) {
503 claim_zero(mlx5_glue->close_device(cdev->ctx));
509 * Initialize all HW global of device context.
512 * Pointer to mlx5 device structure.
514 * Chosen classes come from user device arguments.
517 * 0 on success, a negative errno value otherwise and rte_errno is set.
520 mlx5_dev_hw_global_prepare(struct mlx5_common_device *cdev, uint32_t classes)
524 /* Create context device */
525 ret = mlx5_os_open_device(cdev, classes);
528 /* Allocate Protection Domain object and extract its pdn. */
529 ret = mlx5_os_pd_create(cdev);
532 /* All actions taken below are relevant only when DevX is supported */
533 if (cdev->config.devx == 0)
535 /* Query HCA attributes. */
536 ret = mlx5_devx_cmd_query_hca_attr(cdev->ctx, &cdev->config.hca_attr);
538 DRV_LOG(ERR, "Unable to read HCA capabilities.");
544 mlx5_dev_hw_global_release(cdev);
549 mlx5_common_dev_release(struct mlx5_common_device *cdev)
551 pthread_mutex_lock(&devices_list_lock);
552 TAILQ_REMOVE(&devices_list, cdev, next);
553 pthread_mutex_unlock(&devices_list_lock);
554 if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
555 if (TAILQ_EMPTY(&devices_list))
556 rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB",
558 mlx5_dev_mempool_unsubscribe(cdev);
559 mlx5_mr_release_cache(&cdev->mr_scache);
560 mlx5_dev_hw_global_release(cdev);
565 static struct mlx5_common_device *
566 mlx5_common_dev_create(struct rte_device *eal_dev, uint32_t classes)
568 struct mlx5_common_device *cdev;
571 cdev = rte_zmalloc("mlx5_common_device", sizeof(*cdev), 0);
573 DRV_LOG(ERR, "Device allocation failure.");
578 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
580 /* Parse device parameters. */
581 ret = mlx5_common_config_get(eal_dev->devargs, &cdev->config);
583 DRV_LOG(ERR, "Failed to process device arguments: %s",
584 strerror(rte_errno));
588 mlx5_malloc_mem_select(cdev->config.sys_mem_en);
589 /* Initialize all HW global of device context. */
590 ret = mlx5_dev_hw_global_prepare(cdev, classes);
592 DRV_LOG(ERR, "Failed to initialize device context.");
596 /* Initialize global MR cache resources and update its functions. */
597 ret = mlx5_mr_create_cache(&cdev->mr_scache, eal_dev->numa_node);
599 DRV_LOG(ERR, "Failed to initialize global MR share cache.");
600 mlx5_dev_hw_global_release(cdev);
604 /* Register callback function for global shared MR cache management. */
605 if (TAILQ_EMPTY(&devices_list))
606 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
607 mlx5_mr_mem_event_cb, NULL);
609 pthread_mutex_lock(&devices_list_lock);
610 TAILQ_INSERT_HEAD(&devices_list, cdev, next);
611 pthread_mutex_unlock(&devices_list_lock);
616 drivers_remove(struct mlx5_common_device *cdev, uint32_t enabled_classes)
618 struct mlx5_class_driver *driver;
619 int local_ret = -ENODEV;
623 enabled_classes &= cdev->classes_loaded;
624 while (enabled_classes) {
625 driver = driver_get(RTE_BIT64(i));
626 if (driver != NULL) {
627 local_ret = driver->remove(cdev);
629 cdev->classes_loaded &= ~RTE_BIT64(i);
633 enabled_classes &= ~RTE_BIT64(i);
636 if (local_ret != 0 && ret == 0)
642 drivers_probe(struct mlx5_common_device *cdev, uint32_t user_classes)
644 struct mlx5_class_driver *driver;
645 uint32_t enabled_classes = 0;
649 TAILQ_FOREACH(driver, &drivers_list, next) {
650 if ((driver->drv_class & user_classes) == 0)
652 if (!mlx5_bus_match(driver, cdev->dev))
654 already_loaded = cdev->classes_loaded & driver->drv_class;
655 if (already_loaded && driver->probe_again == 0) {
656 DRV_LOG(ERR, "Device %s is already probed",
661 ret = driver->probe(cdev);
663 DRV_LOG(ERR, "Failed to load driver %s",
667 enabled_classes |= driver->drv_class;
669 cdev->classes_loaded |= enabled_classes;
672 /* Only unload drivers which are enabled which were enabled
673 * in this probe instance.
675 drivers_remove(cdev, enabled_classes);
680 mlx5_common_dev_probe(struct rte_device *eal_dev)
682 struct mlx5_common_device *cdev;
683 uint32_t classes = 0;
684 bool new_device = false;
687 DRV_LOG(INFO, "probe device \"%s\".", eal_dev->name);
688 ret = parse_class_options(eal_dev->devargs);
690 DRV_LOG(ERR, "Unsupported mlx5 class type: %s",
691 eal_dev->devargs->args);
696 /* Default to net class. */
697 classes = MLX5_CLASS_ETH;
698 cdev = to_mlx5_device(eal_dev);
700 cdev = mlx5_common_dev_create(eal_dev, classes);
706 * Validate combination here.
707 * For new device, the classes_loaded field is 0 and it check only
708 * the classes given as user device arguments.
710 ret = is_valid_class_combination(classes | cdev->classes_loaded);
712 DRV_LOG(ERR, "Unsupported mlx5 classes combination.");
715 ret = drivers_probe(cdev, classes);
721 mlx5_common_dev_release(cdev);
726 mlx5_common_dev_remove(struct rte_device *eal_dev)
728 struct mlx5_common_device *cdev;
731 cdev = to_mlx5_device(eal_dev);
734 /* Matching device found, cleanup and unload drivers. */
735 ret = drivers_remove(cdev, cdev->classes_loaded);
737 mlx5_common_dev_release(cdev);
742 * Callback to DMA map external memory to a device.
745 * Pointer to the generic device.
747 * Starting virtual address of memory to be mapped.
749 * Starting IOVA address of memory to be mapped.
751 * Length of memory segment being mapped.
754 * 0 on success, negative value on error.
757 mlx5_common_dev_dma_map(struct rte_device *rte_dev, void *addr,
758 uint64_t iova __rte_unused, size_t len)
760 struct mlx5_common_device *dev;
763 dev = to_mlx5_device(rte_dev);
766 "Unable to find matching mlx5 device to device %s",
771 mr = mlx5_create_mr_ext(dev->pd, (uintptr_t)addr, len,
772 SOCKET_ID_ANY, dev->mr_scache.reg_mr_cb);
774 DRV_LOG(WARNING, "Device %s unable to DMA map", rte_dev->name);
778 rte_rwlock_write_lock(&dev->mr_scache.rwlock);
779 LIST_INSERT_HEAD(&dev->mr_scache.mr_list, mr, mr);
780 /* Insert to the global cache table. */
781 mlx5_mr_insert_cache(&dev->mr_scache, mr);
782 rte_rwlock_write_unlock(&dev->mr_scache.rwlock);
787 * Callback to DMA unmap external memory to a device.
790 * Pointer to the generic device.
792 * Starting virtual address of memory to be unmapped.
794 * Starting IOVA address of memory to be unmapped.
796 * Length of memory segment being unmapped.
799 * 0 on success, negative value on error.
802 mlx5_common_dev_dma_unmap(struct rte_device *rte_dev, void *addr,
803 uint64_t iova __rte_unused, size_t len __rte_unused)
805 struct mlx5_common_device *dev;
806 struct mr_cache_entry entry;
809 dev = to_mlx5_device(rte_dev);
812 "Unable to find matching mlx5 device to device %s.",
817 rte_rwlock_read_lock(&dev->mr_scache.rwlock);
818 mr = mlx5_mr_lookup_list(&dev->mr_scache, &entry, (uintptr_t)addr);
820 rte_rwlock_read_unlock(&dev->mr_scache.rwlock);
822 "Address 0x%" PRIxPTR " wasn't registered to device %s",
823 (uintptr_t)addr, rte_dev->name);
828 DRV_LOG(DEBUG, "MR(%p) is removed from list.", (void *)mr);
829 mlx5_mr_free(mr, dev->mr_scache.dereg_mr_cb);
830 mlx5_mr_rebuild_cache(&dev->mr_scache);
832 * No explicit wmb is needed after updating dev_gen due to
833 * store-release ordering in unlock that provides the
834 * implicit barrier at the software visible level.
836 ++dev->mr_scache.dev_gen;
837 DRV_LOG(DEBUG, "Broadcasting local cache flush, gen=%d.",
838 dev->mr_scache.dev_gen);
839 rte_rwlock_read_unlock(&dev->mr_scache.rwlock);
844 mlx5_class_driver_register(struct mlx5_class_driver *driver)
846 mlx5_common_driver_on_register_pci(driver);
847 TAILQ_INSERT_TAIL(&drivers_list, driver, next);
850 static void mlx5_common_driver_init(void)
852 mlx5_common_pci_init();
853 #ifdef RTE_EXEC_ENV_LINUX
854 mlx5_common_auxiliary_init();
858 static bool mlx5_common_initialized;
861 * One time innitialization routine for run-time dependency on glue library
862 * for multiple PMDs. Each mlx5 PMD that depends on mlx5_common module,
863 * must invoke in its constructor.
866 mlx5_common_init(void)
868 if (mlx5_common_initialized)
871 pthread_mutex_init(&devices_list_lock, NULL);
872 mlx5_glue_constructor();
873 mlx5_common_driver_init();
874 mlx5_common_initialized = true;
878 * This function is responsible of initializing the variable
879 * haswell_broadwell_cpu by checking if the cpu is intel
880 * and reading the data returned from mlx5_cpu_id().
881 * since haswell and broadwell cpus don't have improved performance
882 * when using relaxed ordering we want to check the cpu type before
883 * before deciding whether to enable RO or not.
884 * if the cpu is haswell or broadwell the variable will be set to 1
885 * otherwise it will be 0.
887 RTE_INIT_PRIO(mlx5_is_haswell_broadwell_cpu, LOG)
889 #ifdef RTE_ARCH_X86_64
890 unsigned int broadwell_models[4] = {0x3d, 0x47, 0x4F, 0x56};
891 unsigned int haswell_models[4] = {0x3c, 0x3f, 0x45, 0x46};
892 unsigned int i, model, family, brand_id, vendor;
893 unsigned int signature_intel_ebx = 0x756e6547;
894 unsigned int extended_model;
895 unsigned int eax = 0;
896 unsigned int ebx = 0;
897 unsigned int ecx = 0;
898 unsigned int edx = 0;
901 mlx5_cpu_id(0, &eax, &ebx, &ecx, &edx);
905 haswell_broadwell_cpu = 0;
908 mlx5_cpu_id(1, &eax, &ebx, &ecx, &edx);
909 model = (eax >> 4) & 0x0f;
910 family = (eax >> 8) & 0x0f;
911 brand_id = ebx & 0xff;
912 extended_model = (eax >> 12) & 0xf0;
913 /* Check if the processor is Haswell or Broadwell */
914 if (vendor == signature_intel_ebx) {
916 model += extended_model;
917 if (brand_id == 0 && family == 0x6) {
918 for (i = 0; i < RTE_DIM(broadwell_models); i++)
919 if (model == broadwell_models[i]) {
920 haswell_broadwell_cpu = 1;
923 for (i = 0; i < RTE_DIM(haswell_models); i++)
924 if (model == haswell_models[i]) {
925 haswell_broadwell_cpu = 1;
931 haswell_broadwell_cpu = 0;
935 * Allocate the User Access Region with DevX on specified device.
936 * This routine handles the following UAR allocation issues:
938 * - Try to allocate the UAR with the most appropriate memory mapping
939 * type from the ones supported by the host.
941 * - Try to allocate the UAR with non-NULL base address OFED 5.0.x and
942 * Upstream rdma_core before v29 returned the NULL as UAR base address
943 * if UAR was not the first object in the UAR page.
944 * It caused the PMD failure and we should try to get another UAR till
945 * we get the first one with non-NULL base address returned.
948 * Pointer to mlx5 device structure to perform allocation on its context.
951 * UAR object pointer on success, NULL otherwise and rte_errno is set.
954 mlx5_devx_alloc_uar(struct mlx5_common_device *cdev)
957 uint32_t retry, uar_mapping;
960 for (retry = 0; retry < MLX5_ALLOC_UAR_RETRY; ++retry) {
961 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
962 /* Control the mapping type according to the settings. */
963 uar_mapping = (cdev->config.dbnc == MLX5_TXDB_NCACHED) ?
964 MLX5DV_UAR_ALLOC_TYPE_NC : MLX5DV_UAR_ALLOC_TYPE_BF;
967 * It seems we have no way to control the memory mapping type
968 * for the UAR, the default "Write-Combining" type is supposed.
972 uar = mlx5_glue->devx_alloc_uar(cdev->ctx, uar_mapping);
973 #ifdef MLX5DV_UAR_ALLOC_TYPE_NC
974 if (!uar && uar_mapping == MLX5DV_UAR_ALLOC_TYPE_BF) {
976 * In some environments like virtual machine the
977 * Write Combining mapped might be not supported and
978 * UAR allocation fails. We tried "Non-Cached" mapping
981 DRV_LOG(DEBUG, "Failed to allocate DevX UAR (BF)");
982 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_NC;
983 uar = mlx5_glue->devx_alloc_uar(cdev->ctx, uar_mapping);
984 } else if (!uar && uar_mapping == MLX5DV_UAR_ALLOC_TYPE_NC) {
986 * If Verbs/kernel does not support "Non-Cached"
987 * try the "Write-Combining".
989 DRV_LOG(DEBUG, "Failed to allocate DevX UAR (NC)");
990 uar_mapping = MLX5DV_UAR_ALLOC_TYPE_BF;
991 uar = mlx5_glue->devx_alloc_uar(cdev->ctx, uar_mapping);
995 DRV_LOG(ERR, "Failed to allocate DevX UAR (BF/NC)");
999 base_addr = mlx5_os_get_devx_uar_base_addr(uar);
1003 * The UARs are allocated by rdma_core within the
1004 * IB device context, on context closure all UARs
1005 * will be freed, should be no memory/object leakage.
1007 DRV_LOG(DEBUG, "Retrying to allocate DevX UAR");
1010 /* Check whether we finally succeeded with valid UAR allocation. */
1012 DRV_LOG(ERR, "Failed to allocate DevX UAR (NULL base)");
1016 * Return void * instead of struct mlx5dv_devx_uar *
1017 * is for compatibility with older rdma-core library headers.
1024 mlx5_devx_uar_release(struct mlx5_uar *uar)
1026 if (uar->obj != NULL)
1027 mlx5_glue->devx_free_uar(uar->obj);
1028 memset(uar, 0, sizeof(*uar));
1032 mlx5_devx_uar_prepare(struct mlx5_common_device *cdev, struct mlx5_uar *uar)
1034 off_t uar_mmap_offset;
1035 const size_t page_size = rte_mem_page_size();
1039 if (page_size == (size_t)-1) {
1040 DRV_LOG(ERR, "Failed to get mem page size");
1044 uar_obj = mlx5_devx_alloc_uar(cdev);
1045 if (uar_obj == NULL || mlx5_os_get_devx_uar_reg_addr(uar_obj) == NULL) {
1047 DRV_LOG(ERR, "Failed to allocate UAR.");
1051 uar_mmap_offset = mlx5_os_get_devx_uar_mmap_offset(uar_obj);
1052 base_addr = mlx5_os_get_devx_uar_base_addr(uar_obj);
1053 uar->dbnc = mlx5_db_map_type_get(uar_mmap_offset, page_size);
1054 uar->bf_db.db = mlx5_os_get_devx_uar_reg_addr(uar_obj);
1055 uar->cq_db.db = RTE_PTR_ADD(base_addr, MLX5_CQ_DOORBELL);
1057 rte_spinlock_init(&uar->bf_sl);
1058 rte_spinlock_init(&uar->cq_sl);
1059 uar->bf_db.sl_p = &uar->bf_sl;
1060 uar->cq_db.sl_p = &uar->cq_sl;
1061 #endif /* RTE_ARCH_64 */
1065 RTE_PMD_EXPORT_NAME(mlx5_common_driver, __COUNTER__);