1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2019 Mellanox Technologies, Ltd
5 #ifndef RTE_PMD_MLX5_DEVX_CMDS_H_
6 #define RTE_PMD_MLX5_DEVX_CMDS_H_
12 /* This is limitation of libibverbs: in length variable type is u16. */
13 #define MLX5_DEVX_MAX_KLM_ENTRIES ((UINT16_MAX - \
14 MLX5_ST_SZ_DW(create_mkey_in) * 4) / (MLX5_ST_SZ_DW(klm) * 4))
16 struct mlx5_devx_mkey_attr {
21 uint32_t log_entity_size;
23 uint32_t relaxed_ordering:1;
24 struct mlx5_klm *klm_array;
28 /* HCA qos attributes. */
29 struct mlx5_hca_qos_attr {
30 uint32_t sup:1; /* Whether QOS is supported. */
31 uint32_t srtcm_sup:1; /* Whether srTCM mode is supported. */
32 uint32_t packet_pacing:1; /* Packet pacing is supported. */
33 uint32_t wqe_rate_pp:1; /* Packet pacing WQE rate mode. */
34 uint32_t flow_meter_reg_share:1;
35 /* Whether reg_c share is supported. */
36 uint8_t log_max_flow_meter;
37 /* Power of the maximum supported meters. */
38 uint8_t flow_meter_reg_c_ids;
39 /* Bitmap of the reg_Cs available for flow meter to use. */
43 struct mlx5_hca_vdpa_attr {
44 uint8_t virtio_queue_type;
46 uint32_t desc_tunnel_offload_type:1;
47 uint32_t eth_frame_offload_type:1;
48 uint32_t virtio_version_1_0:1;
53 uint32_t event_mode:3;
54 uint32_t log_doorbell_stride:5;
55 uint32_t log_doorbell_bar_size:5;
56 uint32_t queue_counters_valid:1;
57 uint32_t max_num_virtio_queues;
62 uint64_t doorbell_bar_offset;
65 /* HCA supports this number of time periods for LRO. */
66 #define MLX5_LRO_NUM_SUPP_PERIODS 4
69 struct mlx5_hca_attr {
70 uint32_t eswitch_manager:1;
71 uint32_t flow_counters_dump:1;
72 uint32_t log_max_rqt_size:5;
73 uint32_t parse_graph_flex_node:1;
74 uint8_t flow_counter_bulk_alloc_bitmap;
75 uint32_t eth_net_offloads:1;
77 uint32_t wqe_vlan_insert:1;
78 uint32_t wqe_inline_mode:2;
79 uint32_t vport_inline_mode:3;
80 uint32_t tunnel_stateless_geneve_rx:1;
81 uint32_t geneve_max_opt_len:1; /* 0x0: 14DW, 0x1: 63DW */
82 uint32_t tunnel_stateless_gtp:1;
84 uint32_t tunnel_lro_gre:1;
85 uint32_t tunnel_lro_vxlan:1;
86 uint32_t lro_max_msg_sz_mode:2;
87 uint32_t lro_timer_supported_periods[MLX5_LRO_NUM_SUPP_PERIODS];
88 uint32_t flex_parser_protocols;
90 uint32_t log_max_hairpin_queues:5;
91 uint32_t log_max_hairpin_wq_data_sz:5;
92 uint32_t log_max_hairpin_num_packets:5;
94 uint32_t relaxed_ordering_write:1;
95 uint32_t relaxed_ordering_read:1;
96 uint32_t wqe_index_ignore:1;
97 uint32_t cross_channel:1;
98 uint32_t non_wire_sq:1; /* SQ with non-wire ops is supported. */
99 uint32_t log_max_static_sq_wq:5; /* Static WQE size SQ. */
100 uint32_t dev_freq_khz; /* Timestamp counter frequency, kHz. */
102 uint32_t regexp_num_of_engines;
103 struct mlx5_hca_qos_attr qos;
104 struct mlx5_hca_vdpa_attr vdpa;
107 struct mlx5_devx_wq_attr {
109 uint32_t wq_signature:1;
110 uint32_t end_padding_mode:2;
112 uint32_t hds_skip_first_sge:1;
113 uint32_t log2_hds_buf_size:3;
114 uint32_t page_offset:5;
117 uint32_t uar_page:24;
121 uint32_t log_wq_stride:4;
122 uint32_t log_wq_pg_sz:5;
123 uint32_t log_wq_sz:5;
124 uint32_t dbr_umem_valid:1;
125 uint32_t wq_umem_valid:1;
126 uint32_t log_hairpin_num_packets:5;
127 uint32_t log_hairpin_data_sz:5;
128 uint32_t single_wqe_log_num_of_strides:4;
129 uint32_t two_byte_shift_en:1;
130 uint32_t single_stride_log_num_of_bytes:3;
131 uint32_t dbr_umem_id;
133 uint64_t wq_umem_offset;
136 /* Create RQ attributes structure, used by create RQ operation. */
137 struct mlx5_devx_create_rq_attr {
139 uint32_t delay_drop_en:1;
140 uint32_t scatter_fcs:1;
142 uint32_t mem_rq_type:4;
144 uint32_t flush_in_error_en:1;
146 uint32_t user_index:24;
148 uint32_t counter_set_id:8;
150 struct mlx5_devx_wq_attr wq_attr;
153 /* Modify RQ attributes structure, used by modify RQ operation. */
154 struct mlx5_devx_modify_rq_attr {
156 uint32_t rq_state:4; /* Current RQ state. */
157 uint32_t state:4; /* Required RQ state. */
158 uint32_t scatter_fcs:1;
160 uint32_t counter_set_id:8;
161 uint32_t hairpin_peer_sq:24;
162 uint32_t hairpin_peer_vhca:16;
163 uint64_t modify_bitmask;
164 uint32_t lwm:16; /* Contained WQ lwm. */
167 struct mlx5_rx_hash_field_select {
168 uint32_t l3_prot_type:1;
169 uint32_t l4_prot_type:1;
170 uint32_t selected_fields:30;
173 /* TIR attributes structure, used by TIR operations. */
174 struct mlx5_devx_tir_attr {
175 uint32_t disp_type:4;
176 uint32_t lro_timeout_period_usecs:16;
177 uint32_t lro_enable_mask:4;
178 uint32_t lro_max_msg_sz:8;
179 uint32_t inline_rqn:24;
180 uint32_t rx_hash_symmetric:1;
181 uint32_t tunneled_offload_en:1;
182 uint32_t indirect_table:24;
183 uint32_t rx_hash_fn:4;
184 uint32_t self_lb_block:2;
185 uint32_t transport_domain:24;
186 uint8_t rx_hash_toeplitz_key[MLX5_RSS_HASH_KEY_LEN];
187 struct mlx5_rx_hash_field_select rx_hash_field_selector_outer;
188 struct mlx5_rx_hash_field_select rx_hash_field_selector_inner;
191 /* RQT attributes structure, used by RQT operations. */
192 struct mlx5_devx_rqt_attr {
194 uint32_t rqt_max_size:16;
195 uint32_t rqt_actual_size:16;
199 /* TIS attributes structure. */
200 struct mlx5_devx_tis_attr {
201 uint32_t strict_lag_tx_port_affinity:1;
203 uint32_t lag_tx_port_affinity:4;
205 uint32_t transport_domain:24;
208 /* SQ attributes structure, used by SQ create operation. */
209 struct mlx5_devx_create_sq_attr {
211 uint32_t cd_master:1;
213 uint32_t flush_in_error_en:1;
214 uint32_t allow_multi_pkt_send_wqe:1;
215 uint32_t min_wqe_inline_mode:3;
218 uint32_t allow_swp:1;
221 uint32_t static_sq_wq:1;
222 uint32_t user_index:24;
224 uint32_t packet_pacing_rate_limit_index:16;
225 uint32_t tis_lst_sz:16;
227 struct mlx5_devx_wq_attr wq_attr;
230 /* SQ attributes structure, used by SQ modify operation. */
231 struct mlx5_devx_modify_sq_attr {
234 uint32_t hairpin_peer_rq:24;
235 uint32_t hairpin_peer_vhca:16;
239 /* CQ attributes structure, used by CQ operations. */
240 struct mlx5_devx_cq_attr {
241 uint32_t q_umem_valid:1;
242 uint32_t db_umem_valid:1;
243 uint32_t use_first_only:1;
244 uint32_t overrun_ignore:1;
246 uint32_t log_cq_size:5;
247 uint32_t log_page_size:5;
248 uint32_t uar_page_id;
250 uint64_t q_umem_offset;
252 uint64_t db_umem_offset;
257 /* Virtq attributes structure, used by VIRTQ operations. */
258 struct mlx5_devx_virtq_attr {
259 uint16_t hw_available_index;
260 uint16_t hw_used_index;
263 uint32_t virtio_version_1_0:1;
268 uint32_t event_mode:3;
270 uint32_t dirty_bitmap_dump_enable:1;
271 uint32_t dirty_bitmap_mkey;
272 uint32_t dirty_bitmap_size;
275 uint32_t queue_index;
277 uint32_t counters_obj_id;
278 uint64_t dirty_bitmap_addr;
282 uint64_t available_addr;
291 struct mlx5_devx_qp_attr {
293 uint32_t uar_index:24;
295 uint32_t log_page_size:5;
296 uint32_t rq_size:17; /* Must be power of 2. */
297 uint32_t log_rq_stride:3;
298 uint32_t sq_size:17; /* Must be power of 2. */
299 uint32_t dbr_umem_valid:1;
300 uint32_t dbr_umem_id;
301 uint64_t dbr_address;
303 uint64_t wq_umem_offset;
306 struct mlx5_devx_virtio_q_couners_attr {
307 uint64_t received_desc;
308 uint64_t completed_desc;
310 uint32_t bad_desc_errors;
311 uint32_t exceed_max_chain;
312 uint32_t invalid_buffer;
316 * graph flow match sample attributes structure,
317 * used by flex parser operations.
319 struct mlx5_devx_match_sample_attr {
320 uint32_t flow_match_sample_en:1;
321 uint32_t flow_match_sample_field_offset:16;
322 uint32_t flow_match_sample_offset_mode:4;
323 uint32_t flow_match_sample_field_offset_mask;
324 uint32_t flow_match_sample_field_offset_shift:4;
325 uint32_t flow_match_sample_field_base_offset:8;
326 uint32_t flow_match_sample_tunnel_mode:3;
327 uint32_t flow_match_sample_field_id;
330 /* graph node arc attributes structure, used by flex parser operations. */
331 struct mlx5_devx_graph_arc_attr {
332 uint32_t compare_condition_value:16;
333 uint32_t start_inner_tunnel:1;
334 uint32_t arc_parse_graph_node:8;
335 uint32_t parse_graph_node_handle;
338 /* Maximal number of samples per graph node. */
339 #define MLX5_GRAPH_NODE_SAMPLE_NUM 8
341 /* Maximal number of input/output arcs per graph node. */
342 #define MLX5_GRAPH_NODE_ARC_NUM 8
344 /* parse graph node attributes structure, used by flex parser operations. */
345 struct mlx5_devx_graph_node_attr {
346 uint32_t modify_field_select;
347 uint32_t header_length_mode:4;
348 uint32_t header_length_base_value:16;
349 uint32_t header_length_field_shift:4;
350 uint32_t header_length_field_offset:16;
351 uint32_t header_length_field_mask;
352 struct mlx5_devx_match_sample_attr sample[MLX5_GRAPH_NODE_SAMPLE_NUM];
353 uint32_t next_header_field_offset:16;
354 uint32_t next_header_field_size:5;
355 struct mlx5_devx_graph_arc_attr in[MLX5_GRAPH_NODE_ARC_NUM];
356 struct mlx5_devx_graph_arc_attr out[MLX5_GRAPH_NODE_ARC_NUM];
359 /* mlx5_devx_cmds.c */
362 struct mlx5_devx_obj *mlx5_devx_cmd_flow_counter_alloc(void *ctx,
365 int mlx5_devx_cmd_destroy(struct mlx5_devx_obj *obj);
367 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_obj *dcs,
368 int clear, uint32_t n_counters,
369 uint64_t *pkts, uint64_t *bytes,
370 uint32_t mkey, void *addr,
374 int mlx5_devx_cmd_query_hca_attr(void *ctx,
375 struct mlx5_hca_attr *attr);
377 struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(void *ctx,
378 struct mlx5_devx_mkey_attr *attr);
380 int mlx5_devx_get_out_command_status(void *out);
382 int mlx5_devx_cmd_qp_query_tis_td(void *qp, uint32_t tis_num,
385 struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(void *ctx,
386 struct mlx5_devx_create_rq_attr *rq_attr,
389 int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
390 struct mlx5_devx_modify_rq_attr *rq_attr);
392 struct mlx5_devx_obj *mlx5_devx_cmd_create_tir(void *ctx,
393 struct mlx5_devx_tir_attr *tir_attr);
395 struct mlx5_devx_obj *mlx5_devx_cmd_create_rqt(void *ctx,
396 struct mlx5_devx_rqt_attr *rqt_attr);
398 struct mlx5_devx_obj *mlx5_devx_cmd_create_sq(void *ctx,
399 struct mlx5_devx_create_sq_attr *sq_attr);
401 int mlx5_devx_cmd_modify_sq(struct mlx5_devx_obj *sq,
402 struct mlx5_devx_modify_sq_attr *sq_attr);
404 struct mlx5_devx_obj *mlx5_devx_cmd_create_tis(void *ctx,
405 struct mlx5_devx_tis_attr *tis_attr);
407 struct mlx5_devx_obj *mlx5_devx_cmd_create_td(void *ctx);
409 int mlx5_devx_cmd_flow_dump(void *fdb_domain, void *rx_domain, void *tx_domain,
412 struct mlx5_devx_obj *mlx5_devx_cmd_create_cq(void *ctx,
413 struct mlx5_devx_cq_attr *attr);
415 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtq(void *ctx,
416 struct mlx5_devx_virtq_attr *attr);
418 int mlx5_devx_cmd_modify_virtq(struct mlx5_devx_obj *virtq_obj,
419 struct mlx5_devx_virtq_attr *attr);
421 int mlx5_devx_cmd_query_virtq(struct mlx5_devx_obj *virtq_obj,
422 struct mlx5_devx_virtq_attr *attr);
424 struct mlx5_devx_obj *mlx5_devx_cmd_create_qp(void *ctx,
425 struct mlx5_devx_qp_attr *attr);
427 int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
428 uint32_t qp_st_mod_op, uint32_t remote_qp_id);
430 int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
431 struct mlx5_devx_rqt_attr *rqt_attr);
433 int mlx5_devx_cmd_query_parse_samples(struct mlx5_devx_obj *flex_obj,
434 uint32_t ids[], uint32_t num);
437 struct mlx5_devx_obj *mlx5_devx_cmd_create_flex_parser(void *ctx,
438 struct mlx5_devx_graph_node_attr *data);
441 int mlx5_devx_cmd_register_read(void *ctx, uint16_t reg_id,
442 uint32_t arg, uint32_t *data, uint32_t dw_cnt);
444 * Create virtio queue counters object DevX API.
450 * The DevX object created, NULL otherwise and rte_errno is set.
453 struct mlx5_devx_obj *mlx5_devx_cmd_create_virtio_q_counters(void *ctx);
456 * Query virtio queue counters object using DevX API.
458 * @param[in] couners_obj
459 * Pointer to virtq object structure.
460 * @param [in/out] attr
461 * Pointer to virtio queue counters attributes structure.
464 * 0 on success, a negative errno value otherwise and rte_errno is set.
467 int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
468 struct mlx5_devx_virtio_q_couners_attr *attr);
470 #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */