1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
12 #include <rte_byteorder.h>
14 #include <mlx5_glue.h>
15 #include "mlx5_autoconf.h"
17 /* RSS hash key size. */
18 #define MLX5_RSS_HASH_KEY_LEN 40
20 /* Get CQE owner bit. */
21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
29 /* Get CQE solicited event. */
30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
32 /* Invalidate a CQE. */
33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
35 /* Hardware index widths. */
36 #define MLX5_CQ_INDEX_WIDTH 24
37 #define MLX5_WQ_INDEX_WIDTH 16
39 /* WQE Segment sizes in bytes. */
40 #define MLX5_WSEG_SIZE 16u
41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
45 /* WQE/WQEBB size in bytes. */
46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
49 * Max size of a WQE session.
50 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
51 * the WQE size field in Control Segment is 6 bits wide.
53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
56 * Default minimum number of Tx queues for inlining packets.
57 * If there are less queues as specified we assume we have
58 * no enough CPU resources (cycles) to perform inlining,
59 * the PCIe throughput is not supposed as bottleneck and
60 * inlining is disabled.
62 #define MLX5_INLINE_MAX_TXQS 8u
63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
66 * Default packet length threshold to be inlined with
67 * enhanced MPW. If packet length exceeds the threshold
68 * the data are not inlined. Should be aligned in WQEBB
69 * boundary with accounting the title Control and Ethernet
72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
73 MLX5_DSEG_MIN_INLINE_SIZE)
75 * Maximal inline data length sent with enhanced MPW.
76 * Is based on maximal WQE size.
78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
79 MLX5_WQE_CSEG_SIZE - \
80 MLX5_WQE_ESEG_SIZE - \
81 MLX5_WQE_DSEG_SIZE + \
82 MLX5_DSEG_MIN_INLINE_SIZE)
84 * Minimal amount of packets to be sent with EMPW.
85 * This limits the minimal required size of sent EMPW.
86 * If there are no enough resources to built minimal
87 * EMPW the sending loop exits.
89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
91 * Maximal amount of packets to be sent with EMPW.
92 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
93 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
94 * without CQE generation request, being multiplied by
95 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
96 * in tx burst routine at the moment of freeing multiple mbufs.
98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
99 #define MLX5_MPW_MAX_PACKETS 6
100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
103 * Default packet length threshold to be inlined with
104 * ordinary SEND. Inlining saves the MR key search
105 * and extra PCIe data fetch transaction, but eats the
108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
109 MLX5_ESEG_MIN_INLINE_SIZE - \
110 MLX5_WQE_CSEG_SIZE - \
111 MLX5_WQE_ESEG_SIZE - \
114 * Maximal inline data length sent with ordinary SEND.
115 * Is based on maximal WQE size.
117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
118 MLX5_WQE_CSEG_SIZE - \
119 MLX5_WQE_ESEG_SIZE - \
120 MLX5_WQE_DSEG_SIZE + \
121 MLX5_ESEG_MIN_INLINE_SIZE)
123 /* Missed in mlx5dv.h, should define here. */
124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
129 #define MLX5_OPCODE_SEND_EN 0x17u
132 #ifndef HAVE_MLX5_OPCODE_WAIT
133 #define MLX5_OPCODE_WAIT 0x0fu
136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
137 #define MLX5_OPCODE_ACCESS_ASO 0x2du
140 /* CQE value to inform that VLAN is stripped. */
141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
158 /* IP is fragmented. */
159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
161 /* L2 header is valid. */
162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
164 /* L3 header is valid. */
165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
167 /* L4 header is valid. */
168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
170 /* Outer packet, 0 IPv4, 1 IPv6. */
171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
173 /* Tunnel packet bit in the CQE. */
174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
177 #define MLX5_CQE_LRO_PUSH_MASK 0x40
179 /* Mask for L4 type in the CQE hdr_type_etc field. */
180 #define MLX5_CQE_L4_TYPE_MASK 0x70
182 /* The bit index of L4 type in CQE hdr_type_etc field. */
183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
185 /* L4 type to indicate TCP packet without acknowledgment. */
186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
188 /* L4 type to indicate TCP packet with acknowledgment. */
189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
191 /* Inner L3 checksum offload (Tunneled packets only). */
192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
194 /* Inner L4 checksum offload (Tunneled packets only). */
195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
197 /* Outer L4 type is TCP. */
198 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
200 /* Outer L4 type is UDP. */
201 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
203 /* Outer L3 type is IPV4. */
204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
206 /* Outer L3 type is IPV6. */
207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
209 /* Inner L4 type is TCP. */
210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
212 /* Inner L4 type is UDP. */
213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
215 /* Inner L3 type is IPV4. */
216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
218 /* Inner L3 type is IPV6. */
219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
221 /* VLAN insertion flag. */
222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
224 /* Data inline segment flag. */
225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
227 /* Is flow mark valid. */
228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
234 /* INVALID is used by packets matching no flow rules. */
235 #define MLX5_FLOW_MARK_INVALID 0
237 /* Maximum allowed value to mark a packet. */
238 #define MLX5_FLOW_MARK_MAX 0xfffff0
240 /* Default mark value used when none is provided. */
241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
243 /* Default mark mask for metadata legacy mode. */
244 #define MLX5_FLOW_MARK_MASK 0xffffff
246 /* Byte length mask when mark is enable in miniCQE */
247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
249 /* Maximum number of DS in WQE. Limited by 6-bit field. */
250 #define MLX5_DSEG_MAX 63
252 /* The completion mode offset in the WQE control segment line 2. */
253 #define MLX5_COMP_MODE_OFFSET 2
255 /* Amount of data bytes in minimal inline data segment. */
256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
258 /* Amount of data bytes in minimal inline eth segment. */
259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
261 /* Amount of data bytes after eth data segment. */
262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
264 /* The maximum log value of segments per RQ WQE. */
265 #define MLX5_MAX_LOG_RQ_SEGS 5u
267 /* The alignment needed for WQ buffer. */
268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
270 /* The alignment needed for CQ buffer. */
271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
273 /* Completion mode. */
274 enum mlx5_completion_mode {
275 MLX5_COMP_ONLY_ERR = 0x0,
276 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
277 MLX5_COMP_ALWAYS = 0x2,
278 MLX5_COMP_CQE_AND_EQE = 0x3,
285 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
288 /* WQE Control segment. */
289 struct mlx5_wqe_cseg {
294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
296 /* Header of data segment. Minimal size Data Segment */
297 struct mlx5_wqe_dseg {
300 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
308 /* Subset of struct WQE Ethernet Segment. */
309 struct mlx5_wqe_eseg {
317 uint16_t inline_hdr_sz;
319 uint16_t inline_data;
326 uint32_t flow_metadata;
332 struct mlx5_wqe_qseg {
339 /* The title WQEBB, header of WQE. */
342 struct mlx5_wqe_cseg cseg;
345 struct mlx5_wqe_eseg eseg;
347 struct mlx5_wqe_dseg dseg[2];
348 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
352 /* WQE for Multi-Packet RQ. */
353 struct mlx5_wqe_mprq {
354 struct mlx5_wqe_srq_next_seg next_seg;
355 struct mlx5_wqe_data_seg dseg;
358 #define MLX5_MPRQ_LEN_MASK 0x000ffff
359 #define MLX5_MPRQ_LEN_SHIFT 0
360 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
361 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
362 #define MLX5_MPRQ_FILLER_MASK 0x80000000
363 #define MLX5_MPRQ_FILLER_SHIFT 31
365 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
367 /* CQ element structure - should be equal to the cache line size */
369 #if (RTE_CACHE_LINE_SIZE == 128)
375 uint8_t lro_tcppsh_abort_dupack;
377 uint16_t lro_tcp_win;
378 uint32_t lro_ack_seq_num;
379 uint32_t rx_hash_res;
380 uint8_t rx_hash_type;
384 uint16_t hdr_type_etc;
388 uint32_t flow_table_metadata;
392 uint32_t sop_drop_qpn;
393 uint16_t wqe_counter;
400 uint32_t sop_drop_qpn;
401 uint16_t wqe_counter;
406 /* MMO metadata segment */
408 #define MLX5_OPCODE_MMO 0x2f
409 #define MLX5_OPC_MOD_MMO_REGEX 0x4
411 struct mlx5_wqe_metadata_seg {
412 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
417 struct mlx5_ifc_regexp_mmo_control_bits {
418 uint8_t reserved_at_31[0x2];
420 uint8_t reserved_at_28[0x1];
421 uint8_t subset_id_0[0xc];
422 uint8_t reserved_at_16[0x4];
423 uint8_t subset_id_1[0xc];
425 uint8_t subset_id_2[0xc];
426 uint8_t reserved_at_16_1[0x4];
427 uint8_t subset_id_3[0xc];
430 struct mlx5_ifc_regexp_metadata_bits {
431 uint8_t rof_version[0x10];
432 uint8_t latency_count[0x10];
433 uint8_t instruction_count[0x10];
434 uint8_t primary_thread_count[0x10];
435 uint8_t match_count[0x8];
436 uint8_t detected_match_count[0x8];
437 uint8_t status[0x10];
438 uint8_t job_id[0x20];
439 uint8_t reserved[0x80];
442 struct mlx5_ifc_regexp_match_tuple_bits {
443 uint8_t length[0x10];
444 uint8_t start_ptr[0x10];
445 uint8_t rule_id[0x20];
448 /* Adding direct verbs to data-path. */
450 /* CQ sequence number mask. */
451 #define MLX5_CQ_SQN_MASK 0x3
453 /* CQ sequence number index. */
454 #define MLX5_CQ_SQN_OFFSET 28
456 /* CQ doorbell index mask. */
457 #define MLX5_CI_MASK 0xffffff
459 /* CQ doorbell offset. */
460 #define MLX5_CQ_ARM_DB 1
462 /* CQ doorbell offset*/
463 #define MLX5_CQ_DOORBELL 0x20
465 /* CQE format value. */
466 #define MLX5_COMPRESSED 0x3
468 /* CQ doorbell cmd types. */
469 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
470 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
472 /* Action type of header modification. */
474 MLX5_MODIFICATION_TYPE_SET = 0x1,
475 MLX5_MODIFICATION_TYPE_ADD = 0x2,
476 MLX5_MODIFICATION_TYPE_COPY = 0x3,
479 /* The field of packet to be modified. */
480 enum mlx5_modification_field {
481 MLX5_MODI_OUT_NONE = -1,
482 MLX5_MODI_OUT_SMAC_47_16 = 1,
483 MLX5_MODI_OUT_SMAC_15_0,
484 MLX5_MODI_OUT_ETHERTYPE,
485 MLX5_MODI_OUT_DMAC_47_16,
486 MLX5_MODI_OUT_DMAC_15_0,
487 MLX5_MODI_OUT_IP_DSCP,
488 MLX5_MODI_OUT_TCP_FLAGS,
489 MLX5_MODI_OUT_TCP_SPORT,
490 MLX5_MODI_OUT_TCP_DPORT,
491 MLX5_MODI_OUT_IPV4_TTL,
492 MLX5_MODI_OUT_UDP_SPORT,
493 MLX5_MODI_OUT_UDP_DPORT,
494 MLX5_MODI_OUT_SIPV6_127_96,
495 MLX5_MODI_OUT_SIPV6_95_64,
496 MLX5_MODI_OUT_SIPV6_63_32,
497 MLX5_MODI_OUT_SIPV6_31_0,
498 MLX5_MODI_OUT_DIPV6_127_96,
499 MLX5_MODI_OUT_DIPV6_95_64,
500 MLX5_MODI_OUT_DIPV6_63_32,
501 MLX5_MODI_OUT_DIPV6_31_0,
504 MLX5_MODI_OUT_FIRST_VID,
505 MLX5_MODI_IN_SMAC_47_16 = 0x31,
506 MLX5_MODI_IN_SMAC_15_0,
507 MLX5_MODI_IN_ETHERTYPE,
508 MLX5_MODI_IN_DMAC_47_16,
509 MLX5_MODI_IN_DMAC_15_0,
510 MLX5_MODI_IN_IP_DSCP,
511 MLX5_MODI_IN_TCP_FLAGS,
512 MLX5_MODI_IN_TCP_SPORT,
513 MLX5_MODI_IN_TCP_DPORT,
514 MLX5_MODI_IN_IPV4_TTL,
515 MLX5_MODI_IN_UDP_SPORT,
516 MLX5_MODI_IN_UDP_DPORT,
517 MLX5_MODI_IN_SIPV6_127_96,
518 MLX5_MODI_IN_SIPV6_95_64,
519 MLX5_MODI_IN_SIPV6_63_32,
520 MLX5_MODI_IN_SIPV6_31_0,
521 MLX5_MODI_IN_DIPV6_127_96,
522 MLX5_MODI_IN_DIPV6_95_64,
523 MLX5_MODI_IN_DIPV6_63_32,
524 MLX5_MODI_IN_DIPV6_31_0,
527 MLX5_MODI_OUT_IPV6_HOPLIMIT,
528 MLX5_MODI_IN_IPV6_HOPLIMIT,
529 MLX5_MODI_META_DATA_REG_A,
530 MLX5_MODI_META_DATA_REG_B = 0x50,
531 MLX5_MODI_META_REG_C_0,
532 MLX5_MODI_META_REG_C_1,
533 MLX5_MODI_META_REG_C_2,
534 MLX5_MODI_META_REG_C_3,
535 MLX5_MODI_META_REG_C_4,
536 MLX5_MODI_META_REG_C_5,
537 MLX5_MODI_META_REG_C_6,
538 MLX5_MODI_META_REG_C_7,
539 MLX5_MODI_OUT_TCP_SEQ_NUM,
540 MLX5_MODI_IN_TCP_SEQ_NUM,
541 MLX5_MODI_OUT_TCP_ACK_NUM,
542 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
545 /* Total number of metadata reg_c's. */
546 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
562 /* Modification sub command. */
563 struct mlx5_modification_cmd {
567 unsigned int length:5;
568 unsigned int rsvd0:3;
569 unsigned int offset:5;
570 unsigned int rsvd1:3;
571 unsigned int field:12;
572 unsigned int action_type:4;
579 unsigned int rsvd2:8;
580 unsigned int dst_offset:5;
581 unsigned int rsvd3:3;
582 unsigned int dst_field:12;
583 unsigned int rsvd4:4;
588 typedef uint32_t u32;
589 typedef uint16_t u16;
592 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
593 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
594 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
595 (&(__mlx5_nullp(typ)->fld)))
596 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
597 (__mlx5_bit_off(typ, fld) & 0x1f))
598 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
599 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
600 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
601 __mlx5_dw_bit_off(typ, fld))
602 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
603 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
604 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
605 (__mlx5_bit_off(typ, fld) & 0xf))
606 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
607 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
608 __mlx5_16_bit_off(typ, fld))
609 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
610 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
611 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
612 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
614 /* insert a value to a struct */
615 #define MLX5_SET(typ, p, fld, v) \
618 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
619 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
620 __mlx5_dw_off(typ, fld))) & \
621 (~__mlx5_dw_mask(typ, fld))) | \
622 (((_v) & __mlx5_mask(typ, fld)) << \
623 __mlx5_dw_bit_off(typ, fld))); \
626 #define MLX5_SET64(typ, p, fld, v) \
628 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
629 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
630 rte_cpu_to_be_64(v); \
633 #define MLX5_SET16(typ, p, fld, v) \
636 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
637 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
638 __mlx5_16_off(typ, fld))) & \
639 (~__mlx5_16_mask(typ, fld))) | \
640 (((_v) & __mlx5_mask16(typ, fld)) << \
641 __mlx5_16_bit_off(typ, fld))); \
644 #define MLX5_GET_VOLATILE(typ, p, fld) \
645 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
646 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
647 __mlx5_mask(typ, fld))
648 #define MLX5_GET(typ, p, fld) \
649 ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
650 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
651 __mlx5_mask(typ, fld))
652 #define MLX5_GET16(typ, p, fld) \
653 ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
654 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
655 __mlx5_mask16(typ, fld))
656 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
657 __mlx5_64_off(typ, fld)))
658 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
660 struct mlx5_ifc_fte_match_set_misc_bits {
661 u8 gre_c_present[0x1];
662 u8 reserved_at_1[0x1];
663 u8 gre_k_present[0x1];
664 u8 gre_s_present[0x1];
665 u8 source_vhci_port[0x4];
667 u8 reserved_at_20[0x10];
668 u8 source_port[0x10];
669 u8 outer_second_prio[0x3];
670 u8 outer_second_cfi[0x1];
671 u8 outer_second_vid[0xc];
672 u8 inner_second_prio[0x3];
673 u8 inner_second_cfi[0x1];
674 u8 inner_second_vid[0xc];
675 u8 outer_second_cvlan_tag[0x1];
676 u8 inner_second_cvlan_tag[0x1];
677 u8 outer_second_svlan_tag[0x1];
678 u8 inner_second_svlan_tag[0x1];
679 u8 reserved_at_64[0xc];
680 u8 gre_protocol[0x10];
684 u8 reserved_at_b8[0x8];
686 u8 reserved_at_e4[0x7];
688 u8 reserved_at_e0[0xc];
689 u8 outer_ipv6_flow_label[0x14];
690 u8 reserved_at_100[0xc];
691 u8 inner_ipv6_flow_label[0x14];
692 u8 reserved_at_120[0xa];
693 u8 geneve_opt_len[0x6];
694 u8 geneve_protocol_type[0x10];
695 u8 reserved_at_140[0xc0];
698 struct mlx5_ifc_ipv4_layout_bits {
699 u8 reserved_at_0[0x60];
703 struct mlx5_ifc_ipv6_layout_bits {
707 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
708 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
709 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
710 u8 reserved_at_0[0x80];
713 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
732 u8 reserved_at_c0[0x18];
733 u8 ip_ttl_hoplimit[0x8];
736 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
737 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
740 struct mlx5_ifc_fte_match_mpls_bits {
747 struct mlx5_ifc_fte_match_set_misc2_bits {
748 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
749 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
750 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
751 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
752 u8 metadata_reg_c_7[0x20];
753 u8 metadata_reg_c_6[0x20];
754 u8 metadata_reg_c_5[0x20];
755 u8 metadata_reg_c_4[0x20];
756 u8 metadata_reg_c_3[0x20];
757 u8 metadata_reg_c_2[0x20];
758 u8 metadata_reg_c_1[0x20];
759 u8 metadata_reg_c_0[0x20];
760 u8 metadata_reg_a[0x20];
761 u8 metadata_reg_b[0x20];
762 u8 reserved_at_1c0[0x40];
765 struct mlx5_ifc_fte_match_set_misc3_bits {
766 u8 inner_tcp_seq_num[0x20];
767 u8 outer_tcp_seq_num[0x20];
768 u8 inner_tcp_ack_num[0x20];
769 u8 outer_tcp_ack_num[0x20];
770 u8 reserved_at_auto1[0x8];
771 u8 outer_vxlan_gpe_vni[0x18];
772 u8 outer_vxlan_gpe_next_protocol[0x8];
773 u8 outer_vxlan_gpe_flags[0x8];
774 u8 reserved_at_a8[0x10];
775 u8 icmp_header_data[0x20];
776 u8 icmpv6_header_data[0x20];
781 u8 reserved_at_120[0x20];
783 u8 gtpu_msg_type[0x08];
784 u8 gtpu_msg_flags[0x08];
785 u8 reserved_at_170[0x90];
788 struct mlx5_ifc_fte_match_set_misc4_bits {
789 u8 prog_sample_field_value_0[0x20];
790 u8 prog_sample_field_id_0[0x20];
791 u8 prog_sample_field_value_1[0x20];
792 u8 prog_sample_field_id_1[0x20];
793 u8 prog_sample_field_value_2[0x20];
794 u8 prog_sample_field_id_2[0x20];
795 u8 prog_sample_field_value_3[0x20];
796 u8 prog_sample_field_id_3[0x20];
797 u8 reserved_at_100[0x100];
801 struct mlx5_ifc_fte_match_param_bits {
802 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
803 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
804 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
805 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
806 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
807 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
811 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
812 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
813 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
814 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
815 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
816 MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
820 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
821 MLX5_CMD_OP_CREATE_MKEY = 0x200,
822 MLX5_CMD_OP_CREATE_CQ = 0x400,
823 MLX5_CMD_OP_CREATE_QP = 0x500,
824 MLX5_CMD_OP_RST2INIT_QP = 0x502,
825 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
826 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
827 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
828 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
829 MLX5_CMD_OP_QP_2ERR = 0x507,
830 MLX5_CMD_OP_QP_2RST = 0x50A,
831 MLX5_CMD_OP_QUERY_QP = 0x50B,
832 MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
833 MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
834 MLX5_CMD_OP_SUSPEND_QP = 0x50F,
835 MLX5_CMD_OP_RESUME_QP = 0x510,
836 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
837 MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
838 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
839 MLX5_CMD_OP_CREATE_TIR = 0x900,
840 MLX5_CMD_OP_MODIFY_TIR = 0x901,
841 MLX5_CMD_OP_CREATE_SQ = 0X904,
842 MLX5_CMD_OP_MODIFY_SQ = 0X905,
843 MLX5_CMD_OP_CREATE_RQ = 0x908,
844 MLX5_CMD_OP_MODIFY_RQ = 0x909,
845 MLX5_CMD_OP_CREATE_TIS = 0x912,
846 MLX5_CMD_OP_QUERY_TIS = 0x915,
847 MLX5_CMD_OP_CREATE_RQT = 0x916,
848 MLX5_CMD_OP_MODIFY_RQT = 0x917,
849 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
850 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
851 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
852 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
853 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
854 MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
855 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
856 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
857 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
858 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
862 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
863 MLX5_MKC_ACCESS_MODE_KLM = 0x2,
864 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
867 #define MLX5_ADAPTER_PAGE_SHIFT 12
868 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
870 * The batch counter dcs id starts from 0x800000 and none batch counter
871 * starts from 0. As currently, the counter is changed to be indexed by
872 * pool index and the offset of the counter in the pool counters_raw array.
873 * It means now the counter index is same for batch and none batch counter.
874 * Add the 0x800000 batch counter offset to the batch counter index helps
875 * indicate the counter index is from batch or none batch container pool.
877 #define MLX5_CNT_BATCH_OFFSET 0x800000
879 /* The counter batch query requires ID align with 4. */
880 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
883 struct mlx5_ifc_alloc_flow_counter_out_bits {
885 u8 reserved_at_8[0x18];
887 u8 flow_counter_id[0x20];
888 u8 reserved_at_60[0x20];
891 struct mlx5_ifc_alloc_flow_counter_in_bits {
893 u8 reserved_at_10[0x10];
894 u8 reserved_at_20[0x10];
896 u8 flow_counter_id[0x20];
897 u8 reserved_at_40[0x18];
898 u8 flow_counter_bulk[0x8];
901 struct mlx5_ifc_dealloc_flow_counter_out_bits {
903 u8 reserved_at_8[0x18];
905 u8 reserved_at_40[0x40];
908 struct mlx5_ifc_dealloc_flow_counter_in_bits {
910 u8 reserved_at_10[0x10];
911 u8 reserved_at_20[0x10];
913 u8 flow_counter_id[0x20];
914 u8 reserved_at_60[0x20];
917 struct mlx5_ifc_traffic_counter_bits {
922 struct mlx5_ifc_query_flow_counter_out_bits {
924 u8 reserved_at_8[0x18];
926 u8 reserved_at_40[0x40];
927 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
930 struct mlx5_ifc_query_flow_counter_in_bits {
932 u8 reserved_at_10[0x10];
933 u8 reserved_at_20[0x10];
935 u8 reserved_at_40[0x20];
939 u8 dump_to_memory[0x1];
940 u8 num_of_counters[0x1e];
941 u8 flow_counter_id[0x20];
944 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
945 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
948 struct mlx5_ifc_klm_bits {
954 struct mlx5_ifc_mkc_bits {
955 u8 reserved_at_0[0x1];
957 u8 reserved_at_2[0x1];
958 u8 access_mode_4_2[0x3];
959 u8 reserved_at_6[0x7];
960 u8 relaxed_ordering_write[0x1];
961 u8 reserved_at_e[0x1];
962 u8 small_fence_on_rdma_read_response[0x1];
969 u8 access_mode_1_0[0x2];
970 u8 reserved_at_18[0x8];
975 u8 reserved_at_40[0x20];
980 u8 reserved_at_63[0x2];
981 u8 expected_sigerr_count[0x1];
982 u8 reserved_at_66[0x1];
990 u8 bsf_octword_size[0x20];
992 u8 reserved_at_120[0x80];
994 u8 translations_octword_size[0x20];
996 u8 reserved_at_1c0[0x19];
997 u8 relaxed_ordering_read[0x1];
998 u8 reserved_at_1da[0x1];
999 u8 log_page_size[0x5];
1001 u8 reserved_at_1e0[0x20];
1004 struct mlx5_ifc_create_mkey_out_bits {
1006 u8 reserved_at_8[0x18];
1010 u8 reserved_at_40[0x8];
1011 u8 mkey_index[0x18];
1013 u8 reserved_at_60[0x20];
1016 struct mlx5_ifc_create_mkey_in_bits {
1018 u8 reserved_at_10[0x10];
1020 u8 reserved_at_20[0x10];
1023 u8 reserved_at_40[0x20];
1026 u8 reserved_at_61[0x1f];
1028 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1030 u8 reserved_at_280[0x80];
1032 u8 translations_octword_actual_size[0x20];
1034 u8 mkey_umem_id[0x20];
1036 u8 mkey_umem_offset[0x40];
1038 u8 reserved_at_380[0x500];
1040 u8 klm_pas_mtt[][0x20];
1044 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1045 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1046 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1047 MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1048 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1051 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1052 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1053 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1054 (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1055 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1056 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1057 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1058 (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1061 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
1062 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
1066 MLX5_CAP_INLINE_MODE_L2,
1067 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1068 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1072 MLX5_INLINE_MODE_NONE,
1073 MLX5_INLINE_MODE_L2,
1074 MLX5_INLINE_MODE_IP,
1075 MLX5_INLINE_MODE_TCP_UDP,
1076 MLX5_INLINE_MODE_RESERVED4,
1077 MLX5_INLINE_MODE_INNER_L2,
1078 MLX5_INLINE_MODE_INNER_IP,
1079 MLX5_INLINE_MODE_INNER_TCP_UDP,
1082 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1083 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1084 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1085 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1086 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1087 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1088 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1089 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1090 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1091 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1092 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1094 struct mlx5_ifc_cmd_hca_cap_bits {
1095 u8 reserved_at_0[0x30];
1097 u8 reserved_at_40[0x40];
1098 u8 log_max_srq_sz[0x8];
1099 u8 log_max_qp_sz[0x8];
1100 u8 reserved_at_90[0x9];
1101 u8 wqe_index_ignore_cap[0x1];
1102 u8 dynamic_qp_allocation[0x1];
1105 u8 reserved_at_a1[0x3];
1106 u8 regexp_num_of_engines[0x4];
1107 u8 reserved_at_a8[0x3];
1108 u8 log_max_srq[0x5];
1109 u8 reserved_at_b0[0x3];
1110 u8 regexp_log_crspace_size[0x5];
1111 u8 reserved_at_b8[0x3];
1112 u8 scatter_fcs_w_decap_disable[0x1];
1113 u8 reserved_at_bc[0x4];
1114 u8 reserved_at_c0[0x8];
1115 u8 log_max_cq_sz[0x8];
1116 u8 reserved_at_d0[0xb];
1118 u8 log_max_eq_sz[0x8];
1119 u8 relaxed_ordering_write[0x1];
1120 u8 relaxed_ordering_read[0x1];
1121 u8 access_register_user[0x1];
1122 u8 log_max_mkey[0x5];
1123 u8 reserved_at_f0[0x8];
1124 u8 dump_fill_mkey[0x1];
1125 u8 reserved_at_f9[0x3];
1127 u8 max_indirection[0x8];
1128 u8 fixed_buffer_size[0x1];
1129 u8 log_max_mrw_sz[0x7];
1130 u8 force_teardown[0x1];
1131 u8 reserved_at_111[0x1];
1132 u8 log_max_bsf_list_size[0x6];
1133 u8 umr_extended_translation_offset[0x1];
1135 u8 log_max_klm_list_size[0x6];
1136 u8 non_wire_sq[0x1];
1137 u8 reserved_at_121[0x9];
1138 u8 log_max_ra_req_dc[0x6];
1139 u8 reserved_at_130[0x3];
1140 u8 log_max_static_sq_wq[0x5];
1141 u8 reserved_at_138[0x2];
1142 u8 log_max_ra_res_dc[0x6];
1143 u8 reserved_at_140[0xa];
1144 u8 log_max_ra_req_qp[0x6];
1145 u8 reserved_at_150[0xa];
1146 u8 log_max_ra_res_qp[0x6];
1148 u8 cc_query_allowed[0x1];
1149 u8 cc_modify_allowed[0x1];
1151 u8 cache_line_128byte[0x1];
1152 u8 reserved_at_165[0xa];
1154 u8 gid_table_size[0x10];
1155 u8 out_of_seq_cnt[0x1];
1156 u8 vport_counters[0x1];
1157 u8 retransmission_q_counters[0x1];
1159 u8 modify_rq_counter_set_id[0x1];
1160 u8 rq_delay_drop[0x1];
1162 u8 pkey_table_size[0x10];
1163 u8 vport_group_manager[0x1];
1164 u8 vhca_group_manager[0x1];
1167 u8 vnic_env_queue_counters[0x1];
1169 u8 nic_flow_table[0x1];
1170 u8 eswitch_manager[0x1];
1171 u8 device_memory[0x1];
1174 u8 local_ca_ack_delay[0x5];
1175 u8 port_module_event[0x1];
1176 u8 enhanced_error_q_counters[0x1];
1177 u8 ports_check[0x1];
1178 u8 reserved_at_1b3[0x1];
1179 u8 disable_link_up[0x1];
1183 u8 reserved_at_1c0[0x1];
1186 u8 log_max_msg[0x5];
1187 u8 reserved_at_1c8[0x4];
1189 u8 temp_warn_event[0x1];
1191 u8 general_notification_event[0x1];
1192 u8 reserved_at_1d3[0x2];
1196 u8 reserved_at_1d8[0x1];
1204 u8 stat_rate_support[0x10];
1205 u8 reserved_at_1f0[0xc];
1206 u8 cqe_version[0x4];
1207 u8 compact_address_vector[0x1];
1208 u8 striding_rq[0x1];
1209 u8 reserved_at_202[0x1];
1210 u8 ipoib_enhanced_offloads[0x1];
1211 u8 ipoib_basic_offloads[0x1];
1212 u8 reserved_at_205[0x1];
1213 u8 repeated_block_disabled[0x1];
1214 u8 umr_modify_entity_size_disabled[0x1];
1215 u8 umr_modify_atomic_disabled[0x1];
1216 u8 umr_indirect_mkey_disabled[0x1];
1218 u8 reserved_at_20c[0x3];
1219 u8 drain_sigerr[0x1];
1220 u8 cmdif_checksum[0x2];
1222 u8 reserved_at_213[0x1];
1223 u8 wq_signature[0x1];
1224 u8 sctr_data_cqe[0x1];
1225 u8 reserved_at_216[0x1];
1231 u8 eth_net_offloads[0x1];
1234 u8 reserved_at_21f[0x1];
1237 u8 cq_moderation[0x1];
1238 u8 reserved_at_223[0x3];
1239 u8 cq_eq_remap[0x1];
1241 u8 block_lb_mc[0x1];
1242 u8 reserved_at_229[0x1];
1243 u8 scqe_break_moderation[0x1];
1244 u8 cq_period_start_from_cqe[0x1];
1246 u8 reserved_at_22d[0x1];
1248 u8 vector_calc[0x1];
1249 u8 umr_ptr_rlky[0x1];
1251 u8 reserved_at_232[0x4];
1254 u8 set_deth_sqpn[0x1];
1255 u8 reserved_at_239[0x3];
1261 u8 reserved_at_241[0x9];
1263 u8 reserved_at_250[0x8];
1266 u8 driver_version[0x1];
1267 u8 pad_tx_eth_packet[0x1];
1268 u8 reserved_at_263[0x8];
1269 u8 log_bf_reg_size[0x5];
1270 u8 reserved_at_270[0xb];
1272 u8 num_lag_ports[0x4];
1273 u8 reserved_at_280[0x10];
1274 u8 max_wqe_sz_sq[0x10];
1275 u8 reserved_at_2a0[0x10];
1276 u8 max_wqe_sz_rq[0x10];
1277 u8 max_flow_counter_31_16[0x10];
1278 u8 max_wqe_sz_sq_dc[0x10];
1279 u8 reserved_at_2e0[0x7];
1280 u8 max_qp_mcg[0x19];
1281 u8 reserved_at_300[0x10];
1282 u8 flow_counter_bulk_alloc[0x08];
1283 u8 log_max_mcg[0x8];
1284 u8 reserved_at_320[0x3];
1285 u8 log_max_transport_domain[0x5];
1286 u8 reserved_at_328[0x3];
1288 u8 reserved_at_330[0xb];
1289 u8 log_max_xrcd[0x5];
1290 u8 nic_receive_steering_discard[0x1];
1291 u8 receive_discard_vport_down[0x1];
1292 u8 transmit_discard_vport_down[0x1];
1293 u8 reserved_at_343[0x5];
1294 u8 log_max_flow_counter_bulk[0x8];
1295 u8 max_flow_counter_15_0[0x10];
1297 u8 flow_counters_dump[0x1];
1298 u8 reserved_at_360[0x1];
1300 u8 reserved_at_368[0x3];
1302 u8 reserved_at_370[0x3];
1303 u8 log_max_tir[0x5];
1304 u8 reserved_at_378[0x3];
1305 u8 log_max_tis[0x5];
1306 u8 basic_cyclic_rcv_wqe[0x1];
1307 u8 reserved_at_381[0x2];
1308 u8 log_max_rmp[0x5];
1309 u8 reserved_at_388[0x3];
1310 u8 log_max_rqt[0x5];
1311 u8 reserved_at_390[0x3];
1312 u8 log_max_rqt_size[0x5];
1313 u8 reserved_at_398[0x3];
1314 u8 log_max_tis_per_sq[0x5];
1315 u8 ext_stride_num_range[0x1];
1316 u8 reserved_at_3a1[0x2];
1317 u8 log_max_stride_sz_rq[0x5];
1318 u8 reserved_at_3a8[0x3];
1319 u8 log_min_stride_sz_rq[0x5];
1320 u8 reserved_at_3b0[0x3];
1321 u8 log_max_stride_sz_sq[0x5];
1322 u8 reserved_at_3b8[0x3];
1323 u8 log_min_stride_sz_sq[0x5];
1325 u8 reserved_at_3c1[0x2];
1326 u8 log_max_hairpin_queues[0x5];
1327 u8 reserved_at_3c8[0x3];
1328 u8 log_max_hairpin_wq_data_sz[0x5];
1329 u8 reserved_at_3d0[0x3];
1330 u8 log_max_hairpin_num_packets[0x5];
1331 u8 reserved_at_3d8[0x3];
1332 u8 log_max_wq_sz[0x5];
1333 u8 nic_vport_change_event[0x1];
1334 u8 disable_local_lb_uc[0x1];
1335 u8 disable_local_lb_mc[0x1];
1336 u8 log_min_hairpin_wq_data_sz[0x5];
1337 u8 reserved_at_3e8[0x3];
1338 u8 log_max_vlan_list[0x5];
1339 u8 reserved_at_3f0[0x3];
1340 u8 log_max_current_mc_list[0x5];
1341 u8 reserved_at_3f8[0x3];
1342 u8 log_max_current_uc_list[0x5];
1343 u8 general_obj_types[0x40];
1344 u8 reserved_at_440[0x20];
1345 u8 reserved_at_460[0x10];
1346 u8 max_num_eqs[0x10];
1347 u8 reserved_at_480[0x3];
1348 u8 log_max_l2_table[0x5];
1349 u8 reserved_at_488[0x8];
1350 u8 log_uar_page_sz[0x10];
1351 u8 reserved_at_4a0[0x20];
1352 u8 device_frequency_mhz[0x20];
1353 u8 device_frequency_khz[0x20];
1354 u8 reserved_at_500[0x20];
1355 u8 num_of_uars_per_page[0x20];
1356 u8 flex_parser_protocols[0x20];
1357 u8 reserved_at_560[0x20];
1358 u8 reserved_at_580[0x3c];
1359 u8 mini_cqe_resp_stride_index[0x1];
1360 u8 cqe_128_always[0x1];
1361 u8 cqe_compression_128[0x1];
1362 u8 cqe_compression[0x1];
1363 u8 cqe_compression_timeout[0x10];
1364 u8 cqe_compression_max_num[0x10];
1365 u8 reserved_at_5e0[0x10];
1366 u8 tag_matching[0x1];
1367 u8 rndv_offload_rc[0x1];
1368 u8 rndv_offload_dc[0x1];
1369 u8 log_tag_matching_list_sz[0x5];
1370 u8 reserved_at_5f8[0x3];
1371 u8 log_max_xrq[0x5];
1372 u8 affiliate_nic_vport_criteria[0x8];
1373 u8 native_port_num[0x8];
1374 u8 num_vhca_ports[0x8];
1375 u8 reserved_at_618[0x6];
1376 u8 sw_owner_id[0x1];
1377 u8 reserved_at_61f[0x1e1];
1380 struct mlx5_ifc_qos_cap_bits {
1381 u8 packet_pacing[0x1];
1382 u8 esw_scheduling[0x1];
1383 u8 esw_bw_share[0x1];
1384 u8 esw_rate_limit[0x1];
1385 u8 reserved_at_4[0x1];
1386 u8 packet_pacing_burst_bound[0x1];
1387 u8 packet_pacing_typical_size[0x1];
1388 u8 flow_meter_srtcm[0x1];
1389 u8 reserved_at_8[0x8];
1390 u8 log_max_flow_meter[0x8];
1391 u8 flow_meter_reg_id[0x8];
1392 u8 wqe_rate_pp[0x1];
1393 u8 reserved_at_25[0x7];
1394 u8 flow_meter_reg_share[0x1];
1395 u8 reserved_at_2e[0x17];
1396 u8 packet_pacing_max_rate[0x20];
1397 u8 packet_pacing_min_rate[0x20];
1398 u8 reserved_at_80[0x10];
1399 u8 packet_pacing_rate_table_size[0x10];
1400 u8 esw_element_type[0x10];
1401 u8 esw_tsar_type[0x10];
1402 u8 reserved_at_c0[0x10];
1403 u8 max_qos_para_vport[0x10];
1404 u8 max_tsar_bw_share[0x20];
1405 u8 reserved_at_100[0x6e8];
1408 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1412 u8 lro_psh_flag[0x1];
1413 u8 lro_time_stamp[0x1];
1414 u8 lro_max_msg_sz_mode[0x2];
1415 u8 wqe_vlan_insert[0x1];
1416 u8 self_lb_en_modifiable[0x1];
1419 u8 max_lso_cap[0x5];
1420 u8 multi_pkt_send_wqe[0x2];
1421 u8 wqe_inline_mode[0x2];
1422 u8 rss_ind_tbl_cap[0x4];
1424 u8 scatter_fcs[0x1];
1425 u8 enhanced_multi_pkt_send_wqe[0x1];
1426 u8 tunnel_lso_const_out_ip_id[0x1];
1427 u8 tunnel_lro_gre[0x1];
1428 u8 tunnel_lro_vxlan[0x1];
1429 u8 tunnel_stateless_gre[0x1];
1430 u8 tunnel_stateless_vxlan[0x1];
1434 u8 reserved_at_23[0x8];
1435 u8 tunnel_stateless_gtp[0x1];
1436 u8 reserved_at_25[0x4];
1437 u8 max_vxlan_udp_ports[0x8];
1438 u8 reserved_at_38[0x6];
1439 u8 max_geneve_opt_len[0x1];
1440 u8 tunnel_stateless_geneve_rx[0x1];
1441 u8 reserved_at_40[0x10];
1442 u8 lro_min_mss_size[0x10];
1443 u8 reserved_at_60[0x120];
1444 u8 lro_timer_supported_periods[4][0x20];
1445 u8 reserved_at_200[0x600];
1449 MLX5_VIRTQ_TYPE_SPLIT = 0,
1450 MLX5_VIRTQ_TYPE_PACKED = 1,
1454 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1455 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1456 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1459 struct mlx5_ifc_virtio_emulation_cap_bits {
1460 u8 desc_tunnel_offload_type[0x1];
1461 u8 eth_frame_offload_type[0x1];
1462 u8 virtio_version_1_0[0x1];
1467 u8 reserved_at_7[0x1][0x9];
1469 u8 virtio_queue_type[0x8];
1470 u8 reserved_at_20[0x13];
1471 u8 log_doorbell_stride[0x5];
1472 u8 reserved_at_3b[0x3];
1473 u8 log_doorbell_bar_size[0x5];
1474 u8 doorbell_bar_offset[0x40];
1475 u8 reserved_at_80[0x8];
1476 u8 max_num_virtio_queues[0x18];
1477 u8 reserved_at_a0[0x60];
1478 u8 umem_1_buffer_param_a[0x20];
1479 u8 umem_1_buffer_param_b[0x20];
1480 u8 umem_2_buffer_param_a[0x20];
1481 u8 umem_2_buffer_param_b[0x20];
1482 u8 umem_3_buffer_param_a[0x20];
1483 u8 umem_3_buffer_param_b[0x20];
1484 u8 reserved_at_1c0[0x620];
1487 struct mlx5_ifc_flow_table_prop_layout_bits {
1490 u8 flow_counter[0x1];
1491 u8 flow_modify_en[0x1];
1492 u8 modify_root[0x1];
1493 u8 identified_miss_table[0x1];
1494 u8 flow_table_modify[0x1];
1497 u8 reset_root_to_default[0x1];
1500 u8 fpga_vendor_acceleration[0x1];
1502 u8 push_vlan_2[0x1];
1503 u8 reformat_and_vlan_action[0x1];
1504 u8 modify_and_vlan_action[0x1];
1506 u8 reformat_l3_tunnel_to_l2[0x1];
1507 u8 reformat_l2_to_l3_tunnel[0x1];
1508 u8 reformat_and_modify_action[0x1];
1509 u8 reserved_at_15[0x9];
1510 u8 sw_owner_v2[0x1];
1511 u8 reserved_at_1f[0x1];
1512 u8 reserved_at_20[0x2];
1513 u8 log_max_ft_size[0x6];
1514 u8 log_max_modify_header_context[0x8];
1515 u8 max_modify_header_actions[0x8];
1516 u8 max_ft_level[0x8];
1517 u8 reserved_at_40[0x8];
1518 u8 log_max_ft_sampler_num[8];
1519 u8 metadata_reg_b_width[0x8];
1520 u8 metadata_reg_a_width[0x8];
1521 u8 reserved_at_60[0x18];
1522 u8 log_max_ft_num[0x8];
1523 u8 reserved_at_80[0x10];
1524 u8 log_max_flow_counter[0x8];
1525 u8 log_max_destination[0x8];
1526 u8 reserved_at_a0[0x18];
1527 u8 log_max_flow[0x8];
1528 u8 reserved_at_c0[0x140];
1531 struct mlx5_ifc_flow_table_nic_cap_bits {
1532 u8 reserved_at_0[0x200];
1533 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
1536 union mlx5_ifc_hca_cap_union_bits {
1537 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1538 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1539 per_protocol_networking_offload_caps;
1540 struct mlx5_ifc_qos_cap_bits qos_cap;
1541 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1542 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1543 u8 reserved_at_0[0x8000];
1546 struct mlx5_ifc_set_action_in_bits {
1547 u8 action_type[0x4];
1549 u8 reserved_at_10[0x3];
1551 u8 reserved_at_18[0x3];
1556 struct mlx5_ifc_query_hca_cap_out_bits {
1558 u8 reserved_at_8[0x18];
1560 u8 reserved_at_40[0x40];
1561 union mlx5_ifc_hca_cap_union_bits capability;
1564 struct mlx5_ifc_query_hca_cap_in_bits {
1566 u8 reserved_at_10[0x10];
1567 u8 reserved_at_20[0x10];
1569 u8 reserved_at_40[0x40];
1572 struct mlx5_ifc_mac_address_layout_bits {
1573 u8 reserved_at_0[0x10];
1574 u8 mac_addr_47_32[0x10];
1575 u8 mac_addr_31_0[0x20];
1578 struct mlx5_ifc_nic_vport_context_bits {
1579 u8 reserved_at_0[0x5];
1580 u8 min_wqe_inline_mode[0x3];
1581 u8 reserved_at_8[0x15];
1582 u8 disable_mc_local_lb[0x1];
1583 u8 disable_uc_local_lb[0x1];
1585 u8 arm_change_event[0x1];
1586 u8 reserved_at_21[0x1a];
1587 u8 event_on_mtu[0x1];
1588 u8 event_on_promisc_change[0x1];
1589 u8 event_on_vlan_change[0x1];
1590 u8 event_on_mc_address_change[0x1];
1591 u8 event_on_uc_address_change[0x1];
1592 u8 reserved_at_40[0xc];
1593 u8 affiliation_criteria[0x4];
1594 u8 affiliated_vhca_id[0x10];
1595 u8 reserved_at_60[0xd0];
1597 u8 system_image_guid[0x40];
1600 u8 reserved_at_200[0x140];
1601 u8 qkey_violation_counter[0x10];
1602 u8 reserved_at_350[0x430];
1605 u8 promisc_all[0x1];
1606 u8 reserved_at_783[0x2];
1607 u8 allowed_list_type[0x3];
1608 u8 reserved_at_788[0xc];
1609 u8 allowed_list_size[0xc];
1610 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1611 u8 reserved_at_7e0[0x20];
1614 struct mlx5_ifc_query_nic_vport_context_out_bits {
1616 u8 reserved_at_8[0x18];
1618 u8 reserved_at_40[0x40];
1619 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1622 struct mlx5_ifc_query_nic_vport_context_in_bits {
1624 u8 reserved_at_10[0x10];
1625 u8 reserved_at_20[0x10];
1627 u8 other_vport[0x1];
1628 u8 reserved_at_41[0xf];
1629 u8 vport_number[0x10];
1630 u8 reserved_at_60[0x5];
1631 u8 allowed_list_type[0x3];
1632 u8 reserved_at_68[0x18];
1635 struct mlx5_ifc_tisc_bits {
1636 u8 strict_lag_tx_port_affinity[0x1];
1637 u8 reserved_at_1[0x3];
1638 u8 lag_tx_port_affinity[0x04];
1639 u8 reserved_at_8[0x4];
1641 u8 reserved_at_10[0x10];
1642 u8 reserved_at_20[0x100];
1643 u8 reserved_at_120[0x8];
1644 u8 transport_domain[0x18];
1645 u8 reserved_at_140[0x8];
1646 u8 underlay_qpn[0x18];
1647 u8 reserved_at_160[0x3a0];
1650 struct mlx5_ifc_query_tis_out_bits {
1652 u8 reserved_at_8[0x18];
1654 u8 reserved_at_40[0x40];
1655 struct mlx5_ifc_tisc_bits tis_context;
1658 struct mlx5_ifc_query_tis_in_bits {
1660 u8 reserved_at_10[0x10];
1661 u8 reserved_at_20[0x10];
1663 u8 reserved_at_40[0x8];
1665 u8 reserved_at_60[0x20];
1668 struct mlx5_ifc_alloc_transport_domain_out_bits {
1670 u8 reserved_at_8[0x18];
1672 u8 reserved_at_40[0x8];
1673 u8 transport_domain[0x18];
1674 u8 reserved_at_60[0x20];
1677 struct mlx5_ifc_alloc_transport_domain_in_bits {
1679 u8 reserved_at_10[0x10];
1680 u8 reserved_at_20[0x10];
1682 u8 reserved_at_40[0x40];
1686 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1687 MLX5_WQ_TYPE_CYCLIC = 0x1,
1688 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1689 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1693 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1694 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1697 struct mlx5_ifc_wq_bits {
1699 u8 wq_signature[0x1];
1700 u8 end_padding_mode[0x2];
1702 u8 reserved_at_8[0x18];
1703 u8 hds_skip_first_sge[0x1];
1704 u8 log2_hds_buf_size[0x3];
1705 u8 reserved_at_24[0x7];
1706 u8 page_offset[0x5];
1708 u8 reserved_at_40[0x8];
1710 u8 reserved_at_60[0x8];
1713 u8 hw_counter[0x20];
1714 u8 sw_counter[0x20];
1715 u8 reserved_at_100[0xc];
1716 u8 log_wq_stride[0x4];
1717 u8 reserved_at_110[0x3];
1718 u8 log_wq_pg_sz[0x5];
1719 u8 reserved_at_118[0x3];
1721 u8 dbr_umem_valid[0x1];
1722 u8 wq_umem_valid[0x1];
1723 u8 reserved_at_122[0x1];
1724 u8 log_hairpin_num_packets[0x5];
1725 u8 reserved_at_128[0x3];
1726 u8 log_hairpin_data_sz[0x5];
1727 u8 reserved_at_130[0x4];
1728 u8 single_wqe_log_num_of_strides[0x4];
1729 u8 two_byte_shift_en[0x1];
1730 u8 reserved_at_139[0x4];
1731 u8 single_stride_log_num_of_bytes[0x3];
1732 u8 dbr_umem_id[0x20];
1733 u8 wq_umem_id[0x20];
1734 u8 wq_umem_offset[0x40];
1735 u8 reserved_at_1c0[0x440];
1739 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1740 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
1744 MLX5_RQC_STATE_RST = 0x0,
1745 MLX5_RQC_STATE_RDY = 0x1,
1746 MLX5_RQC_STATE_ERR = 0x3,
1749 struct mlx5_ifc_rqc_bits {
1751 u8 delay_drop_en[0x1];
1752 u8 scatter_fcs[0x1];
1754 u8 mem_rq_type[0x4];
1756 u8 reserved_at_c[0x1];
1757 u8 flush_in_error_en[0x1];
1759 u8 reserved_at_f[0x11];
1760 u8 reserved_at_20[0x8];
1761 u8 user_index[0x18];
1762 u8 reserved_at_40[0x8];
1764 u8 counter_set_id[0x8];
1765 u8 reserved_at_68[0x18];
1766 u8 reserved_at_80[0x8];
1768 u8 reserved_at_a0[0x8];
1769 u8 hairpin_peer_sq[0x18];
1770 u8 reserved_at_c0[0x10];
1771 u8 hairpin_peer_vhca[0x10];
1772 u8 reserved_at_e0[0xa0];
1773 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1776 struct mlx5_ifc_create_rq_out_bits {
1778 u8 reserved_at_8[0x18];
1780 u8 reserved_at_40[0x8];
1782 u8 reserved_at_60[0x20];
1785 struct mlx5_ifc_create_rq_in_bits {
1788 u8 reserved_at_20[0x10];
1790 u8 reserved_at_40[0xc0];
1791 struct mlx5_ifc_rqc_bits ctx;
1794 struct mlx5_ifc_modify_rq_out_bits {
1796 u8 reserved_at_8[0x18];
1798 u8 reserved_at_40[0x40];
1801 struct mlx5_ifc_create_tis_out_bits {
1803 u8 reserved_at_8[0x18];
1805 u8 reserved_at_40[0x8];
1807 u8 reserved_at_60[0x20];
1810 struct mlx5_ifc_create_tis_in_bits {
1813 u8 reserved_at_20[0x10];
1815 u8 reserved_at_40[0xc0];
1816 struct mlx5_ifc_tisc_bits ctx;
1820 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1821 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1822 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1823 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1826 struct mlx5_ifc_modify_rq_in_bits {
1829 u8 reserved_at_20[0x10];
1832 u8 reserved_at_44[0x4];
1834 u8 reserved_at_60[0x20];
1835 u8 modify_bitmask[0x40];
1836 u8 reserved_at_c0[0x40];
1837 struct mlx5_ifc_rqc_bits ctx;
1841 MLX5_L3_PROT_TYPE_IPV4 = 0,
1842 MLX5_L3_PROT_TYPE_IPV6 = 1,
1846 MLX5_L4_PROT_TYPE_TCP = 0,
1847 MLX5_L4_PROT_TYPE_UDP = 1,
1851 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1852 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1853 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1854 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1855 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1858 struct mlx5_ifc_rx_hash_field_select_bits {
1859 u8 l3_prot_type[0x1];
1860 u8 l4_prot_type[0x1];
1861 u8 selected_fields[0x1e];
1865 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1866 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1870 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1871 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1875 MLX5_RX_HASH_FN_NONE = 0x0,
1876 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1877 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1881 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
1882 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
1886 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
1887 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
1890 struct mlx5_ifc_tirc_bits {
1891 u8 reserved_at_0[0x20];
1893 u8 reserved_at_24[0x1c];
1894 u8 reserved_at_40[0x40];
1895 u8 reserved_at_80[0x4];
1896 u8 lro_timeout_period_usecs[0x10];
1897 u8 lro_enable_mask[0x4];
1898 u8 lro_max_msg_sz[0x8];
1899 u8 reserved_at_a0[0x40];
1900 u8 reserved_at_e0[0x8];
1901 u8 inline_rqn[0x18];
1902 u8 rx_hash_symmetric[0x1];
1903 u8 reserved_at_101[0x1];
1904 u8 tunneled_offload_en[0x1];
1905 u8 reserved_at_103[0x5];
1906 u8 indirect_table[0x18];
1908 u8 reserved_at_124[0x2];
1909 u8 self_lb_block[0x2];
1910 u8 transport_domain[0x18];
1911 u8 rx_hash_toeplitz_key[10][0x20];
1912 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1913 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1914 u8 reserved_at_2c0[0x4c0];
1917 struct mlx5_ifc_create_tir_out_bits {
1919 u8 reserved_at_8[0x18];
1921 u8 reserved_at_40[0x8];
1923 u8 reserved_at_60[0x20];
1926 struct mlx5_ifc_create_tir_in_bits {
1929 u8 reserved_at_20[0x10];
1931 u8 reserved_at_40[0xc0];
1932 struct mlx5_ifc_tirc_bits ctx;
1936 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
1937 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
1938 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
1939 /* bit 3 - tunneled_offload_en modify not supported. */
1940 MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
1943 struct mlx5_ifc_modify_tir_out_bits {
1945 u8 reserved_at_8[0x18];
1947 u8 reserved_at_40[0x40];
1950 struct mlx5_ifc_modify_tir_in_bits {
1953 u8 reserved_at_20[0x10];
1955 u8 reserved_at_40[0x8];
1957 u8 reserved_at_60[0x20];
1958 u8 modify_bitmask[0x40];
1959 u8 reserved_at_c0[0x40];
1960 struct mlx5_ifc_tirc_bits ctx;
1964 MLX5_INLINE_Q_TYPE_RQ = 0x0,
1965 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
1968 struct mlx5_ifc_rq_num_bits {
1969 u8 reserved_at_0[0x8];
1973 struct mlx5_ifc_rqtc_bits {
1974 u8 reserved_at_0[0xa5];
1975 u8 list_q_type[0x3];
1976 u8 reserved_at_a8[0x8];
1977 u8 rqt_max_size[0x10];
1978 u8 reserved_at_c0[0x10];
1979 u8 rqt_actual_size[0x10];
1980 u8 reserved_at_e0[0x6a0];
1981 struct mlx5_ifc_rq_num_bits rq_num[];
1984 struct mlx5_ifc_create_rqt_out_bits {
1986 u8 reserved_at_8[0x18];
1988 u8 reserved_at_40[0x8];
1990 u8 reserved_at_60[0x20];
1994 #pragma GCC diagnostic ignored "-Wpedantic"
1996 struct mlx5_ifc_create_rqt_in_bits {
1999 u8 reserved_at_20[0x10];
2001 u8 reserved_at_40[0xc0];
2002 struct mlx5_ifc_rqtc_bits rqt_context;
2005 struct mlx5_ifc_modify_rqt_in_bits {
2008 u8 reserved_at_20[0x10];
2010 u8 reserved_at_40[0x8];
2012 u8 reserved_at_60[0x20];
2013 u8 modify_bitmask[0x40];
2014 u8 reserved_at_c0[0x40];
2015 struct mlx5_ifc_rqtc_bits rqt_context;
2018 #pragma GCC diagnostic error "-Wpedantic"
2021 struct mlx5_ifc_modify_rqt_out_bits {
2023 u8 reserved_at_8[0x18];
2025 u8 reserved_at_40[0x40];
2029 MLX5_SQC_STATE_RST = 0x0,
2030 MLX5_SQC_STATE_RDY = 0x1,
2031 MLX5_SQC_STATE_ERR = 0x3,
2034 struct mlx5_ifc_sqc_bits {
2038 u8 flush_in_error_en[0x1];
2039 u8 allow_multi_pkt_send_wqe[0x1];
2040 u8 min_wqe_inline_mode[0x3];
2046 u8 static_sq_wq[0x1];
2047 u8 reserved_at_11[0xf];
2048 u8 reserved_at_20[0x8];
2049 u8 user_index[0x18];
2050 u8 reserved_at_40[0x8];
2052 u8 reserved_at_60[0x8];
2053 u8 hairpin_peer_rq[0x18];
2054 u8 reserved_at_80[0x10];
2055 u8 hairpin_peer_vhca[0x10];
2056 u8 reserved_at_a0[0x50];
2057 u8 packet_pacing_rate_limit_index[0x10];
2058 u8 tis_lst_sz[0x10];
2059 u8 reserved_at_110[0x10];
2060 u8 reserved_at_120[0x40];
2061 u8 reserved_at_160[0x8];
2063 struct mlx5_ifc_wq_bits wq;
2066 struct mlx5_ifc_query_sq_in_bits {
2068 u8 reserved_at_10[0x10];
2069 u8 reserved_at_20[0x10];
2071 u8 reserved_at_40[0x8];
2073 u8 reserved_at_60[0x20];
2076 struct mlx5_ifc_modify_sq_out_bits {
2078 u8 reserved_at_8[0x18];
2080 u8 reserved_at_40[0x40];
2083 struct mlx5_ifc_modify_sq_in_bits {
2086 u8 reserved_at_20[0x10];
2089 u8 reserved_at_44[0x4];
2091 u8 reserved_at_60[0x20];
2092 u8 modify_bitmask[0x40];
2093 u8 reserved_at_c0[0x40];
2094 struct mlx5_ifc_sqc_bits ctx;
2097 struct mlx5_ifc_create_sq_out_bits {
2099 u8 reserved_at_8[0x18];
2101 u8 reserved_at_40[0x8];
2103 u8 reserved_at_60[0x20];
2106 struct mlx5_ifc_create_sq_in_bits {
2109 u8 reserved_at_20[0x10];
2111 u8 reserved_at_40[0xc0];
2112 struct mlx5_ifc_sqc_bits ctx;
2116 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2117 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2118 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2119 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2120 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2123 struct mlx5_ifc_flow_meter_parameters_bits {
2124 u8 valid[0x1]; // 00h
2125 u8 bucket_overflow[0x1];
2126 u8 start_color[0x2];
2127 u8 both_buckets_on_green[0x1];
2129 u8 reserved_at_1[0x19];
2130 u8 reserved_at_2[0x20]; //04h
2131 u8 reserved_at_3[0x3];
2132 u8 cbs_exponent[0x5]; // 08h
2133 u8 cbs_mantissa[0x8];
2134 u8 reserved_at_4[0x3];
2135 u8 cir_exponent[0x5];
2136 u8 cir_mantissa[0x8];
2137 u8 reserved_at_5[0x20]; // 0Ch
2138 u8 reserved_at_6[0x3];
2139 u8 ebs_exponent[0x5]; // 10h
2140 u8 ebs_mantissa[0x8];
2141 u8 reserved_at_7[0x3];
2142 u8 eir_exponent[0x5];
2143 u8 eir_mantissa[0x8];
2144 u8 reserved_at_8[0x60]; // 14h-1Ch
2148 MLX5_CQE_SIZE_64B = 0x0,
2149 MLX5_CQE_SIZE_128B = 0x1,
2152 struct mlx5_ifc_cqc_bits {
2155 u8 initiator_src_dct[0x1];
2156 u8 dbr_umem_valid[0x1];
2157 u8 reserved_at_7[0x1];
2160 u8 reserved_at_c[0x1];
2161 u8 scqe_break_moderation_en[0x1];
2163 u8 cq_period_mode[0x2];
2164 u8 cqe_comp_en[0x1];
2165 u8 mini_cqe_res_format[0x2];
2167 u8 reserved_at_18[0x1];
2168 u8 cqe_comp_layout[0x7];
2169 u8 dbr_umem_id[0x20];
2170 u8 reserved_at_40[0x14];
2171 u8 page_offset[0x6];
2172 u8 reserved_at_5a[0x2];
2173 u8 mini_cqe_res_format_ext[0x2];
2174 u8 cq_timestamp_format[0x2];
2175 u8 reserved_at_60[0x3];
2176 u8 log_cq_size[0x5];
2178 u8 reserved_at_80[0x4];
2180 u8 cq_max_count[0x10];
2181 u8 reserved_at_a0[0x18];
2183 u8 reserved_at_c0[0x3];
2184 u8 log_page_size[0x5];
2185 u8 reserved_at_c8[0x18];
2186 u8 reserved_at_e0[0x20];
2187 u8 reserved_at_100[0x8];
2188 u8 last_notified_index[0x18];
2189 u8 reserved_at_120[0x8];
2190 u8 last_solicit_index[0x18];
2191 u8 reserved_at_140[0x8];
2192 u8 consumer_counter[0x18];
2193 u8 reserved_at_160[0x8];
2194 u8 producer_counter[0x18];
2195 u8 local_partition_id[0xc];
2196 u8 process_id[0x14];
2197 u8 reserved_at_1A0[0x20];
2201 struct mlx5_ifc_create_cq_out_bits {
2203 u8 reserved_at_8[0x18];
2205 u8 reserved_at_40[0x8];
2207 u8 reserved_at_60[0x20];
2210 struct mlx5_ifc_create_cq_in_bits {
2213 u8 reserved_at_20[0x10];
2215 u8 reserved_at_40[0x40];
2216 struct mlx5_ifc_cqc_bits cq_context;
2217 u8 cq_umem_offset[0x40];
2218 u8 cq_umem_id[0x20];
2219 u8 cq_umem_valid[0x1];
2220 u8 reserved_at_2e1[0x1f];
2221 u8 reserved_at_300[0x580];
2226 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2227 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2228 MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2229 MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2232 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2234 u8 reserved_at_10[0x20];
2237 u8 reserved_at_60[0x20];
2240 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2242 u8 reserved_at_8[0x18];
2245 u8 reserved_at_60[0x20];
2248 struct mlx5_ifc_virtio_q_counters_bits {
2249 u8 modify_field_select[0x40];
2250 u8 reserved_at_40[0x40];
2251 u8 received_desc[0x40];
2252 u8 completed_desc[0x40];
2253 u8 error_cqes[0x20];
2254 u8 bad_desc_errors[0x20];
2255 u8 exceed_max_chain[0x20];
2256 u8 invalid_buffer[0x20];
2257 u8 reserved_at_180[0x50];
2260 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2261 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2262 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2265 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2266 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2267 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2270 MLX5_VIRTQ_STATE_INIT = 0,
2271 MLX5_VIRTQ_STATE_RDY = 1,
2272 MLX5_VIRTQ_STATE_SUSPEND = 2,
2273 MLX5_VIRTQ_STATE_ERROR = 3,
2277 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2278 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2279 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2282 struct mlx5_ifc_virtio_q_bits {
2283 u8 virtio_q_type[0x8];
2284 u8 reserved_at_8[0x5];
2286 u8 queue_index[0x10];
2287 u8 full_emulation[0x1];
2288 u8 virtio_version_1_0[0x1];
2289 u8 reserved_at_22[0x2];
2290 u8 offload_type[0x4];
2291 u8 event_qpn_or_msix[0x18];
2292 u8 doorbell_stride_idx[0x10];
2293 u8 queue_size[0x10];
2294 u8 device_emulation_id[0x20];
2297 u8 available_addr[0x40];
2298 u8 virtio_q_mkey[0x20];
2299 u8 reserved_at_160[0x18];
2302 u8 umem_1_size[0x20];
2303 u8 umem_1_offset[0x40];
2305 u8 umem_2_size[0x20];
2306 u8 umem_2_offset[0x40];
2308 u8 umem_3_size[0x20];
2309 u8 umem_3_offset[0x40];
2310 u8 counter_set_id[0x20];
2311 u8 reserved_at_320[0x8];
2313 u8 reserved_at_340[0xc0];
2316 struct mlx5_ifc_virtio_net_q_bits {
2317 u8 modify_field_select[0x40];
2318 u8 reserved_at_40[0x40];
2323 u8 reserved_at_84[0x6];
2324 u8 dirty_bitmap_dump_enable[0x1];
2325 u8 vhost_log_page[0x5];
2326 u8 reserved_at_90[0xc];
2328 u8 reserved_at_a0[0x8];
2329 u8 tisn_or_qpn[0x18];
2330 u8 dirty_bitmap_mkey[0x20];
2331 u8 dirty_bitmap_size[0x20];
2332 u8 dirty_bitmap_addr[0x40];
2333 u8 hw_available_index[0x10];
2334 u8 hw_used_index[0x10];
2335 u8 reserved_at_160[0xa0];
2336 struct mlx5_ifc_virtio_q_bits virtio_q_context;
2339 struct mlx5_ifc_create_virtq_in_bits {
2340 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2341 struct mlx5_ifc_virtio_net_q_bits virtq;
2344 struct mlx5_ifc_query_virtq_out_bits {
2345 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2346 struct mlx5_ifc_virtio_net_q_bits virtq;
2349 struct mlx5_ifc_flow_hit_aso_bits {
2350 u8 modify_field_select[0x40];
2351 u8 reserved_at_40[0x48];
2353 u8 reserved_at_a0[0x160];
2357 struct mlx5_ifc_create_flow_hit_aso_in_bits {
2358 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2359 struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
2362 enum mlx5_access_aso_op_mod {
2363 ASO_OP_MOD_IPSEC = 0x0,
2364 ASO_OP_MOD_CONNECTION_TRACKING = 0x1,
2365 ASO_OP_MOD_POLICER = 0x2,
2366 ASO_OP_MOD_RACE_AVOIDANCE = 0x3,
2367 ASO_OP_MOD_FLOW_HIT = 0x4,
2370 #define ASO_CSEG_DATA_MASK_MODE_OFFSET 30
2372 enum mlx5_aso_data_mask_mode {
2373 BITWISE_64BIT = 0x0,
2374 BYTEWISE_64BYTE = 0x1,
2375 CALCULATED_64BYTE = 0x2,
2378 #define ASO_CSEG_COND_0_OPER_OFFSET 20
2379 #define ASO_CSEG_COND_1_OPER_OFFSET 16
2381 enum mlx5_aso_pre_cond_op {
2382 ASO_OP_ALWAYS_FALSE = 0x0,
2383 ASO_OP_ALWAYS_TRUE = 0x1,
2385 ASO_OP_NOT_EQUAL = 0x3,
2386 ASO_OP_GREATER_OR_EQUAL = 0x4,
2387 ASO_OP_LESSER_OR_EQUAL = 0x5,
2388 ASO_OP_LESSER = 0x6,
2389 ASO_OP_GREATER = 0x7,
2390 ASO_OP_CYCLIC_GREATER = 0x8,
2391 ASO_OP_CYCLIC_LESSER = 0x9,
2394 #define ASO_CSEG_COND_OPER_OFFSET 6
2397 ASO_OPER_LOGICAL_AND = 0x0,
2398 ASO_OPER_LOGICAL_OR = 0x1,
2401 /* ASO WQE CTRL segment. */
2402 struct mlx5_aso_cseg {
2406 uint32_t operand_masks;
2407 uint32_t condition_0_data;
2408 uint32_t condition_0_mask;
2409 uint32_t condition_1_data;
2410 uint32_t condition_1_mask;
2411 uint64_t bitwise_data;
2415 #define MLX5_ASO_WQE_DSEG_SIZE 0x40
2417 /* ASO WQE Data segment. */
2418 struct mlx5_aso_dseg {
2419 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
2423 struct mlx5_aso_wqe {
2424 struct mlx5_wqe_cseg general_cseg;
2425 struct mlx5_aso_cseg aso_cseg;
2426 struct mlx5_aso_dseg aso_dseg;
2430 MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
2434 MLX5_QP_ST_RC = 0x0,
2438 MLX5_QP_PM_MIGRATED = 0x3,
2442 MLX5_NON_ZERO_RQ = 0x0,
2445 MLX5_ZERO_LEN_RQ = 0x3,
2448 struct mlx5_ifc_ads_bits {
2451 u8 reserved_at_2[0xe];
2452 u8 pkey_index[0x10];
2453 u8 reserved_at_20[0x8];
2457 u8 ack_timeout[0x5];
2458 u8 reserved_at_45[0x3];
2459 u8 src_addr_index[0x8];
2460 u8 reserved_at_50[0x4];
2463 u8 reserved_at_60[0x4];
2465 u8 flow_label[0x14];
2466 u8 rgid_rip[16][0x8];
2467 u8 reserved_at_100[0x4];
2470 u8 reserved_at_106[0x1];
2478 u8 vhca_port_num[0x8];
2479 u8 rmac_47_32[0x10];
2483 struct mlx5_ifc_qpc_bits {
2485 u8 lag_tx_port_affinity[0x4];
2487 u8 reserved_at_10[0x3];
2489 u8 reserved_at_15[0x1];
2490 u8 req_e2e_credit_mode[0x2];
2491 u8 offload_type[0x4];
2492 u8 end_padding_mode[0x2];
2493 u8 reserved_at_1e[0x2];
2494 u8 wq_signature[0x1];
2495 u8 block_lb_mc[0x1];
2496 u8 atomic_like_write_en[0x1];
2497 u8 latency_sensitive[0x1];
2498 u8 reserved_at_24[0x1];
2499 u8 drain_sigerr[0x1];
2500 u8 reserved_at_26[0x2];
2503 u8 log_msg_max[0x5];
2504 u8 reserved_at_48[0x1];
2505 u8 log_rq_size[0x4];
2506 u8 log_rq_stride[0x3];
2508 u8 log_sq_size[0x4];
2509 u8 reserved_at_55[0x6];
2511 u8 ulp_stateless_offload_mode[0x4];
2512 u8 counter_set_id[0x8];
2514 u8 reserved_at_80[0x8];
2515 u8 user_index[0x18];
2516 u8 reserved_at_a0[0x3];
2517 u8 log_page_size[0x5];
2518 u8 remote_qpn[0x18];
2519 struct mlx5_ifc_ads_bits primary_address_path;
2520 struct mlx5_ifc_ads_bits secondary_address_path;
2521 u8 log_ack_req_freq[0x4];
2522 u8 reserved_at_384[0x4];
2523 u8 log_sra_max[0x3];
2524 u8 reserved_at_38b[0x2];
2525 u8 retry_count[0x3];
2527 u8 reserved_at_393[0x1];
2529 u8 cur_rnr_retry[0x3];
2530 u8 cur_retry_count[0x3];
2531 u8 reserved_at_39b[0x5];
2532 u8 reserved_at_3a0[0x20];
2533 u8 reserved_at_3c0[0x8];
2534 u8 next_send_psn[0x18];
2535 u8 reserved_at_3e0[0x8];
2537 u8 reserved_at_400[0x8];
2539 u8 reserved_at_420[0x20];
2540 u8 reserved_at_440[0x8];
2541 u8 last_acked_psn[0x18];
2542 u8 reserved_at_460[0x8];
2544 u8 reserved_at_480[0x8];
2545 u8 log_rra_max[0x3];
2546 u8 reserved_at_48b[0x1];
2547 u8 atomic_mode[0x4];
2551 u8 reserved_at_493[0x1];
2552 u8 page_offset[0x6];
2553 u8 reserved_at_49a[0x3];
2554 u8 cd_slave_receive[0x1];
2555 u8 cd_slave_send[0x1];
2557 u8 reserved_at_4a0[0x3];
2558 u8 min_rnr_nak[0x5];
2559 u8 next_rcv_psn[0x18];
2560 u8 reserved_at_4c0[0x8];
2562 u8 reserved_at_4e0[0x8];
2566 u8 reserved_at_560[0x5];
2568 u8 srqn_rmpn_xrqn[0x18];
2569 u8 reserved_at_580[0x8];
2571 u8 hw_sq_wqebb_counter[0x10];
2572 u8 sw_sq_wqebb_counter[0x10];
2573 u8 hw_rq_counter[0x20];
2574 u8 sw_rq_counter[0x20];
2575 u8 reserved_at_600[0x20];
2576 u8 reserved_at_620[0xf];
2580 u8 dc_access_key[0x40];
2581 u8 reserved_at_680[0x3];
2582 u8 dbr_umem_valid[0x1];
2583 u8 reserved_at_684[0x9c];
2584 u8 dbr_umem_id[0x20];
2587 struct mlx5_ifc_create_qp_out_bits {
2589 u8 reserved_at_8[0x18];
2591 u8 reserved_at_40[0x8];
2593 u8 reserved_at_60[0x20];
2597 #pragma GCC diagnostic ignored "-Wpedantic"
2599 struct mlx5_ifc_create_qp_in_bits {
2602 u8 reserved_at_20[0x10];
2604 u8 reserved_at_40[0x40];
2605 u8 opt_param_mask[0x20];
2606 u8 reserved_at_a0[0x20];
2607 struct mlx5_ifc_qpc_bits qpc;
2608 u8 wq_umem_offset[0x40];
2609 u8 wq_umem_id[0x20];
2610 u8 wq_umem_valid[0x1];
2611 u8 reserved_at_861[0x1f];
2615 #pragma GCC diagnostic error "-Wpedantic"
2618 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2620 u8 reserved_at_8[0x18];
2622 u8 reserved_at_40[0x40];
2625 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2628 u8 reserved_at_20[0x10];
2630 u8 reserved_at_40[0x8];
2632 u8 reserved_at_60[0x20];
2633 u8 opt_param_mask[0x20];
2634 u8 reserved_at_a0[0x20];
2635 struct mlx5_ifc_qpc_bits qpc;
2636 u8 reserved_at_800[0x80];
2639 struct mlx5_ifc_sqd2rts_qp_out_bits {
2641 u8 reserved_at_8[0x18];
2643 u8 reserved_at_40[0x40];
2646 struct mlx5_ifc_sqd2rts_qp_in_bits {
2649 u8 reserved_at_20[0x10];
2651 u8 reserved_at_40[0x8];
2653 u8 reserved_at_60[0x20];
2654 u8 opt_param_mask[0x20];
2655 u8 reserved_at_a0[0x20];
2656 struct mlx5_ifc_qpc_bits qpc;
2657 u8 reserved_at_800[0x80];
2660 struct mlx5_ifc_rts2rts_qp_out_bits {
2662 u8 reserved_at_8[0x18];
2664 u8 reserved_at_40[0x40];
2667 struct mlx5_ifc_rts2rts_qp_in_bits {
2670 u8 reserved_at_20[0x10];
2672 u8 reserved_at_40[0x8];
2674 u8 reserved_at_60[0x20];
2675 u8 opt_param_mask[0x20];
2676 u8 reserved_at_a0[0x20];
2677 struct mlx5_ifc_qpc_bits qpc;
2678 u8 reserved_at_800[0x80];
2681 struct mlx5_ifc_rtr2rts_qp_out_bits {
2683 u8 reserved_at_8[0x18];
2685 u8 reserved_at_40[0x40];
2688 struct mlx5_ifc_rtr2rts_qp_in_bits {
2691 u8 reserved_at_20[0x10];
2693 u8 reserved_at_40[0x8];
2695 u8 reserved_at_60[0x20];
2696 u8 opt_param_mask[0x20];
2697 u8 reserved_at_a0[0x20];
2698 struct mlx5_ifc_qpc_bits qpc;
2699 u8 reserved_at_800[0x80];
2702 struct mlx5_ifc_rst2init_qp_out_bits {
2704 u8 reserved_at_8[0x18];
2706 u8 reserved_at_40[0x40];
2709 struct mlx5_ifc_rst2init_qp_in_bits {
2712 u8 reserved_at_20[0x10];
2714 u8 reserved_at_40[0x8];
2716 u8 reserved_at_60[0x20];
2717 u8 opt_param_mask[0x20];
2718 u8 reserved_at_a0[0x20];
2719 struct mlx5_ifc_qpc_bits qpc;
2720 u8 reserved_at_800[0x80];
2723 struct mlx5_ifc_init2rtr_qp_out_bits {
2725 u8 reserved_at_8[0x18];
2727 u8 reserved_at_40[0x40];
2730 struct mlx5_ifc_init2rtr_qp_in_bits {
2733 u8 reserved_at_20[0x10];
2735 u8 reserved_at_40[0x8];
2737 u8 reserved_at_60[0x20];
2738 u8 opt_param_mask[0x20];
2739 u8 reserved_at_a0[0x20];
2740 struct mlx5_ifc_qpc_bits qpc;
2741 u8 reserved_at_800[0x80];
2744 struct mlx5_ifc_init2init_qp_out_bits {
2746 u8 reserved_at_8[0x18];
2748 u8 reserved_at_40[0x40];
2751 struct mlx5_ifc_init2init_qp_in_bits {
2754 u8 reserved_at_20[0x10];
2756 u8 reserved_at_40[0x8];
2758 u8 reserved_at_60[0x20];
2759 u8 opt_param_mask[0x20];
2760 u8 reserved_at_a0[0x20];
2761 struct mlx5_ifc_qpc_bits qpc;
2762 u8 reserved_at_800[0x80];
2766 #pragma GCC diagnostic ignored "-Wpedantic"
2768 struct mlx5_ifc_query_qp_out_bits {
2770 u8 reserved_at_8[0x18];
2772 u8 reserved_at_40[0x40];
2773 u8 opt_param_mask[0x20];
2774 u8 reserved_at_a0[0x20];
2775 struct mlx5_ifc_qpc_bits qpc;
2776 u8 reserved_at_800[0x80];
2780 #pragma GCC diagnostic error "-Wpedantic"
2783 struct mlx5_ifc_query_qp_in_bits {
2785 u8 reserved_at_10[0x10];
2786 u8 reserved_at_20[0x10];
2788 u8 reserved_at_40[0x8];
2790 u8 reserved_at_60[0x20];
2794 MLX5_DATA_RATE = 0x0,
2795 MLX5_WQE_RATE = 0x1,
2798 struct mlx5_ifc_set_pp_rate_limit_context_bits {
2799 u8 rate_limit[0x20];
2800 u8 burst_upper_bound[0x20];
2801 u8 reserved_at_40[0xC];
2803 u8 typical_packet_size[0x10];
2804 u8 reserved_at_60[0x120];
2807 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
2810 #pragma GCC diagnostic ignored "-Wpedantic"
2812 struct mlx5_ifc_access_register_out_bits {
2814 u8 reserved_at_8[0x18];
2816 u8 reserved_at_40[0x40];
2817 u8 register_data[0][0x20];
2820 struct mlx5_ifc_access_register_in_bits {
2822 u8 reserved_at_10[0x10];
2823 u8 reserved_at_20[0x10];
2825 u8 reserved_at_40[0x10];
2826 u8 register_id[0x10];
2828 u8 register_data[0][0x20];
2831 #pragma GCC diagnostic error "-Wpedantic"
2835 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
2836 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
2840 MLX5_REGISTER_ID_MTUTC = 0x9055,
2843 struct mlx5_ifc_register_mtutc_bits {
2844 u8 time_stamp_mode[0x2];
2845 u8 time_stamp_state[0x2];
2846 u8 reserved_at_4[0x18];
2848 u8 freq_adjustment[0x20];
2849 u8 reserved_at_40[0x40];
2852 u8 time_adjustment[0x20];
2855 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
2856 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
2858 struct mlx5_ifc_parse_graph_arc_bits {
2859 u8 start_inner_tunnel[0x1];
2860 u8 reserved_at_1[0x7];
2861 u8 arc_parse_graph_node[0x8];
2862 u8 compare_condition_value[0x10];
2863 u8 parse_graph_node_handle[0x20];
2864 u8 reserved_at_40[0x40];
2867 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
2868 u8 flow_match_sample_en[0x1];
2869 u8 reserved_at_1[0x3];
2870 u8 flow_match_sample_offset_mode[0x4];
2871 u8 reserved_at_5[0x8];
2872 u8 flow_match_sample_field_offset[0x10];
2873 u8 reserved_at_32[0x4];
2874 u8 flow_match_sample_field_offset_shift[0x4];
2875 u8 flow_match_sample_field_base_offset[0x8];
2876 u8 reserved_at_48[0xd];
2877 u8 flow_match_sample_tunnel_mode[0x3];
2878 u8 flow_match_sample_field_offset_mask[0x20];
2879 u8 flow_match_sample_field_id[0x20];
2882 struct mlx5_ifc_parse_graph_flex_bits {
2883 u8 modify_field_select[0x40];
2884 u8 reserved_at_64[0x20];
2885 u8 header_length_base_value[0x10];
2886 u8 reserved_at_112[0x4];
2887 u8 header_length_field_shift[0x4];
2888 u8 reserved_at_120[0x4];
2889 u8 header_length_mode[0x4];
2890 u8 header_length_field_offset[0x10];
2891 u8 next_header_field_offset[0x10];
2892 u8 reserved_at_160[0x1b];
2893 u8 next_header_field_size[0x5];
2894 u8 header_length_field_mask[0x20];
2895 u8 reserved_at_224[0x20];
2896 struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
2897 struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
2898 struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
2901 struct mlx5_ifc_create_flex_parser_in_bits {
2902 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2903 struct mlx5_ifc_parse_graph_flex_bits flex;
2906 struct mlx5_ifc_create_flex_parser_out_bits {
2907 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2908 struct mlx5_ifc_parse_graph_flex_bits flex;
2911 struct mlx5_ifc_parse_graph_flex_out_bits {
2913 u8 reserved_at_8[0x18];
2915 u8 reserved_at_40[0x40];
2916 struct mlx5_ifc_parse_graph_flex_bits capability;
2919 struct regexp_params_field_select_bits {
2920 u8 reserved_at_0[0x1e];
2921 u8 stop_engine[0x1];
2925 struct mlx5_ifc_regexp_params_bits {
2926 u8 reserved_at_0[0x1f];
2927 u8 stop_engine[0x1];
2928 u8 db_umem_id[0x20];
2929 u8 db_umem_offset[0x40];
2930 u8 reserved_at_80[0x100];
2933 struct mlx5_ifc_set_regexp_params_in_bits {
2936 u8 reserved_at_20[0x10];
2938 u8 reserved_at_40[0x18];
2940 struct regexp_params_field_select_bits field_select;
2941 struct mlx5_ifc_regexp_params_bits regexp_params;
2944 struct mlx5_ifc_set_regexp_params_out_bits {
2946 u8 reserved_at_8[0x18];
2948 u8 reserved_at_18[0x40];
2951 struct mlx5_ifc_query_regexp_params_in_bits {
2954 u8 reserved_at_20[0x10];
2956 u8 reserved_at_40[0x18];
2961 struct mlx5_ifc_query_regexp_params_out_bits {
2963 u8 reserved_at_8[0x18];
2966 struct mlx5_ifc_regexp_params_bits regexp_params;
2969 struct mlx5_ifc_set_regexp_register_in_bits {
2972 u8 reserved_at_20[0x10];
2974 u8 reserved_at_40[0x18];
2976 u8 register_address[0x20];
2977 u8 register_data[0x20];
2981 struct mlx5_ifc_set_regexp_register_out_bits {
2983 u8 reserved_at_8[0x18];
2988 struct mlx5_ifc_query_regexp_register_in_bits {
2991 u8 reserved_at_20[0x10];
2993 u8 reserved_at_40[0x18];
2995 u8 register_address[0x20];
2998 struct mlx5_ifc_query_regexp_register_out_bits {
3000 u8 reserved_at_8[0x18];
3003 u8 register_data[0x20];
3006 /* CQE format mask. */
3007 #define MLX5E_CQE_FORMAT_MASK 0xc
3010 #define MLX5_OPC_MOD_MPW 0x01
3012 /* Compressed Rx CQE structure. */
3013 struct mlx5_mini_cqe8 {
3015 uint32_t rx_hash_result;
3019 uint16_t flow_tag_high;
3025 uint16_t stride_idx;
3028 uint16_t wqe_counter;
3029 uint8_t s_wqe_opcode;
3034 uint32_t byte_cnt_flow;
3039 /* Mini CQE responder format. */
3041 MLX5_CQE_RESP_FORMAT_HASH = 0x0,
3042 MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
3043 MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
3044 MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
3045 MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
3048 /* srTCM PRM flow meter parameters. */
3050 MLX5_FLOW_COLOR_RED = 0,
3051 MLX5_FLOW_COLOR_YELLOW,
3052 MLX5_FLOW_COLOR_GREEN,
3053 MLX5_FLOW_COLOR_UNDEFINED,
3056 /* Maximum value of srTCM metering parameters. */
3057 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
3058 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
3059 #define MLX5_SRTCM_EBS_MAX 0
3061 /* The bits meter color use. */
3062 #define MLX5_MTR_COLOR_BITS 8
3064 /* Length mode of dynamic flex parser graph node. */
3065 enum mlx5_parse_graph_node_len_mode {
3066 MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
3067 MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
3068 MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
3071 /* Offset mode of the samples of flex parser. */
3072 enum mlx5_parse_graph_flow_match_sample_offset_mode {
3073 MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
3074 MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
3075 MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
3078 /* Node index for an input / output arc of the flex parser graph. */
3079 enum mlx5_parse_graph_arc_node_index {
3080 MLX5_GRAPH_ARC_NODE_NULL = 0x0,
3081 MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
3082 MLX5_GRAPH_ARC_NODE_MAC = 0x2,
3083 MLX5_GRAPH_ARC_NODE_IP = 0x3,
3084 MLX5_GRAPH_ARC_NODE_GRE = 0x4,
3085 MLX5_GRAPH_ARC_NODE_UDP = 0x5,
3086 MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
3087 MLX5_GRAPH_ARC_NODE_TCP = 0x7,
3088 MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
3089 MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
3090 MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
3091 MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
3095 * Convert a user mark to flow mark.
3098 * Mark value to convert.
3101 * Converted mark value.
3103 static inline uint32_t
3104 mlx5_flow_mark_set(uint32_t val)
3109 * Add one to the user value to differentiate un-marked flows from
3110 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
3111 * remains untouched.
3113 if (val != MLX5_FLOW_MARK_DEFAULT)
3115 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3117 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
3118 * word, byte-swapped by the kernel on little-endian systems. In this
3119 * case, left-shifting the resulting big-endian value ensures the
3120 * least significant 24 bits are retained when converting it back.
3122 ret = rte_cpu_to_be_32(val) >> 8;
3130 * Convert a mark to user mark.
3133 * Mark value to convert.
3136 * Converted mark value.
3138 static inline uint32_t
3139 mlx5_flow_mark_get(uint32_t val)
3142 * Subtract one from the retrieved value. It was added by
3143 * mlx5_flow_mark_set() to distinguish unmarked flows.
3145 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3146 return (val >> 8) - 1;
3152 #endif /* RTE_PMD_MLX5_PRM_H_ */