regex/mlx5: support info query
[dpdk.git] / drivers / common / mlx5 / mlx5_prm.h
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright 2016 6WIND S.A.
3  * Copyright 2016 Mellanox Technologies, Ltd
4  */
5
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
8
9 /* Verbs header. */
10 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
11 #ifdef PEDANTIC
12 #pragma GCC diagnostic ignored "-Wpedantic"
13 #endif
14 #include <infiniband/mlx5dv.h>
15 #ifdef PEDANTIC
16 #pragma GCC diagnostic error "-Wpedantic"
17 #endif
18
19 #include <unistd.h>
20
21 #include <rte_vect.h>
22 #include <rte_byteorder.h>
23
24 #include "mlx5_autoconf.h"
25
26 /* RSS hash key size. */
27 #define MLX5_RSS_HASH_KEY_LEN 40
28
29 /* Get CQE owner bit. */
30 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
31
32 /* Get CQE format. */
33 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
34
35 /* Get CQE opcode. */
36 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
37
38 /* Get CQE solicited event. */
39 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
40
41 /* Invalidate a CQE. */
42 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
43
44 /* WQE Segment sizes in bytes. */
45 #define MLX5_WSEG_SIZE 16u
46 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
47 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
48 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
49
50 /* WQE/WQEBB size in bytes. */
51 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
52
53 /*
54  * Max size of a WQE session.
55  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
56  * the WQE size field in Control Segment is 6 bits wide.
57  */
58 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
59
60 /*
61  * Default minimum number of Tx queues for inlining packets.
62  * If there are less queues as specified we assume we have
63  * no enough CPU resources (cycles) to perform inlining,
64  * the PCIe throughput is not supposed as bottleneck and
65  * inlining is disabled.
66  */
67 #define MLX5_INLINE_MAX_TXQS 8u
68 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
69
70 /*
71  * Default packet length threshold to be inlined with
72  * enhanced MPW. If packet length exceeds the threshold
73  * the data are not inlined. Should be aligned in WQEBB
74  * boundary with accounting the title Control and Ethernet
75  * segments.
76  */
77 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
78                                   MLX5_DSEG_MIN_INLINE_SIZE)
79 /*
80  * Maximal inline data length sent with enhanced MPW.
81  * Is based on maximal WQE size.
82  */
83 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
84                                   MLX5_WQE_CSEG_SIZE - \
85                                   MLX5_WQE_ESEG_SIZE - \
86                                   MLX5_WQE_DSEG_SIZE + \
87                                   MLX5_DSEG_MIN_INLINE_SIZE)
88 /*
89  * Minimal amount of packets to be sent with EMPW.
90  * This limits the minimal required size of sent EMPW.
91  * If there are no enough resources to built minimal
92  * EMPW the sending loop exits.
93  */
94 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
95 /*
96  * Maximal amount of packets to be sent with EMPW.
97  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
98  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
99  * without CQE generation request, being multiplied by
100  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
101  * in tx burst routine at the moment of freeing multiple mbufs.
102  */
103 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
104 #define MLX5_MPW_MAX_PACKETS 6
105 #define MLX5_MPW_INLINE_MAX_PACKETS 6
106
107 /*
108  * Default packet length threshold to be inlined with
109  * ordinary SEND. Inlining saves the MR key search
110  * and extra PCIe data fetch transaction, but eats the
111  * CPU cycles.
112  */
113 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
114                                   MLX5_ESEG_MIN_INLINE_SIZE - \
115                                   MLX5_WQE_CSEG_SIZE - \
116                                   MLX5_WQE_ESEG_SIZE - \
117                                   MLX5_WQE_DSEG_SIZE)
118 /*
119  * Maximal inline data length sent with ordinary SEND.
120  * Is based on maximal WQE size.
121  */
122 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
123                                   MLX5_WQE_CSEG_SIZE - \
124                                   MLX5_WQE_ESEG_SIZE - \
125                                   MLX5_WQE_DSEG_SIZE + \
126                                   MLX5_ESEG_MIN_INLINE_SIZE)
127
128 /* Missed in mlv5dv.h, should define here. */
129 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
130
131 /* CQE value to inform that VLAN is stripped. */
132 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
133
134 /* IPv4 options. */
135 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
136
137 /* IPv6 packet. */
138 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
139
140 /* IPv4 packet. */
141 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
142
143 /* TCP packet. */
144 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
145
146 /* UDP packet. */
147 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
148
149 /* IP is fragmented. */
150 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
151
152 /* L2 header is valid. */
153 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
154
155 /* L3 header is valid. */
156 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
157
158 /* L4 header is valid. */
159 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
160
161 /* Outer packet, 0 IPv4, 1 IPv6. */
162 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
163
164 /* Tunnel packet bit in the CQE. */
165 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
166
167 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
168 #define MLX5_CQE_LRO_PUSH_MASK 0x40
169
170 /* Mask for L4 type in the CQE hdr_type_etc field. */
171 #define MLX5_CQE_L4_TYPE_MASK 0x70
172
173 /* The bit index of L4 type in CQE hdr_type_etc field. */
174 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
175
176 /* L4 type to indicate TCP packet without acknowledgment. */
177 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
178
179 /* L4 type to indicate TCP packet with acknowledgment. */
180 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
181
182 /* Inner L3 checksum offload (Tunneled packets only). */
183 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
184
185 /* Inner L4 checksum offload (Tunneled packets only). */
186 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
187
188 /* Outer L4 type is TCP. */
189 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
190
191 /* Outer L4 type is UDP. */
192 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
193
194 /* Outer L3 type is IPV4. */
195 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
196
197 /* Outer L3 type is IPV6. */
198 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
199
200 /* Inner L4 type is TCP. */
201 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
202
203 /* Inner L4 type is UDP. */
204 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
205
206 /* Inner L3 type is IPV4. */
207 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
208
209 /* Inner L3 type is IPV6. */
210 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
211
212 /* VLAN insertion flag. */
213 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
214
215 /* Data inline segment flag. */
216 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
217
218 /* Is flow mark valid. */
219 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
220 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
221 #else
222 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
223 #endif
224
225 /* INVALID is used by packets matching no flow rules. */
226 #define MLX5_FLOW_MARK_INVALID 0
227
228 /* Maximum allowed value to mark a packet. */
229 #define MLX5_FLOW_MARK_MAX 0xfffff0
230
231 /* Default mark value used when none is provided. */
232 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
233
234 /* Default mark mask for metadata legacy mode. */
235 #define MLX5_FLOW_MARK_MASK 0xffffff
236
237 /* Maximum number of DS in WQE. Limited by 6-bit field. */
238 #define MLX5_DSEG_MAX 63
239
240 /* The completion mode offset in the WQE control segment line 2. */
241 #define MLX5_COMP_MODE_OFFSET 2
242
243 /* Amount of data bytes in minimal inline data segment. */
244 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
245
246 /* Amount of data bytes in minimal inline eth segment. */
247 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
248
249 /* Amount of data bytes after eth data segment. */
250 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
251
252 /* The maximum log value of segments per RQ WQE. */
253 #define MLX5_MAX_LOG_RQ_SEGS 5u
254
255 /* The alignment needed for WQ buffer. */
256 #define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)
257
258 /* Completion mode. */
259 enum mlx5_completion_mode {
260         MLX5_COMP_ONLY_ERR = 0x0,
261         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
262         MLX5_COMP_ALWAYS = 0x2,
263         MLX5_COMP_CQE_AND_EQE = 0x3,
264 };
265
266 /* MPW mode. */
267 enum mlx5_mpw_mode {
268         MLX5_MPW_DISABLED,
269         MLX5_MPW,
270         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
271 };
272
273 /* WQE Control segment. */
274 struct mlx5_wqe_cseg {
275         uint32_t opcode;
276         uint32_t sq_ds;
277         uint32_t flags;
278         uint32_t misc;
279 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
280
281 /* Header of data segment. Minimal size Data Segment */
282 struct mlx5_wqe_dseg {
283         uint32_t bcount;
284         union {
285                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
286                 struct {
287                         uint32_t lkey;
288                         uint64_t pbuf;
289                 } __rte_packed;
290         };
291 } __rte_packed;
292
293 /* Subset of struct WQE Ethernet Segment. */
294 struct mlx5_wqe_eseg {
295         union {
296                 struct {
297                         uint32_t swp_offs;
298                         uint8_t cs_flags;
299                         uint8_t swp_flags;
300                         uint16_t mss;
301                         uint32_t metadata;
302                         uint16_t inline_hdr_sz;
303                         union {
304                                 uint16_t inline_data;
305                                 uint16_t vlan_tag;
306                         };
307                 } __rte_packed;
308                 struct {
309                         uint32_t offsets;
310                         uint32_t flags;
311                         uint32_t flow_metadata;
312                         uint32_t inline_hdr;
313                 } __rte_packed;
314         };
315 } __rte_packed;
316
317 /* The title WQEBB, header of WQE. */
318 struct mlx5_wqe {
319         union {
320                 struct mlx5_wqe_cseg cseg;
321                 uint32_t ctrl[4];
322         };
323         struct mlx5_wqe_eseg eseg;
324         union {
325                 struct mlx5_wqe_dseg dseg[2];
326                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
327         };
328 } __rte_packed;
329
330 /* WQE for Multi-Packet RQ. */
331 struct mlx5_wqe_mprq {
332         struct mlx5_wqe_srq_next_seg next_seg;
333         struct mlx5_wqe_data_seg dseg;
334 };
335
336 #define MLX5_MPRQ_LEN_MASK 0x000ffff
337 #define MLX5_MPRQ_LEN_SHIFT 0
338 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
339 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
340 #define MLX5_MPRQ_FILLER_MASK 0x80000000
341 #define MLX5_MPRQ_FILLER_SHIFT 31
342
343 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
344
345 /* CQ element structure - should be equal to the cache line size */
346 struct mlx5_cqe {
347 #if (RTE_CACHE_LINE_SIZE == 128)
348         uint8_t padding[64];
349 #endif
350         uint8_t pkt_info;
351         uint8_t rsvd0;
352         uint16_t wqe_id;
353         uint8_t lro_tcppsh_abort_dupack;
354         uint8_t lro_min_ttl;
355         uint16_t lro_tcp_win;
356         uint32_t lro_ack_seq_num;
357         uint32_t rx_hash_res;
358         uint8_t rx_hash_type;
359         uint8_t rsvd1[3];
360         uint16_t csum;
361         uint8_t rsvd2[6];
362         uint16_t hdr_type_etc;
363         uint16_t vlan_info;
364         uint8_t lro_num_seg;
365         uint8_t rsvd3[3];
366         uint32_t flow_table_metadata;
367         uint8_t rsvd4[4];
368         uint32_t byte_cnt;
369         uint64_t timestamp;
370         uint32_t sop_drop_qpn;
371         uint16_t wqe_counter;
372         uint8_t rsvd5;
373         uint8_t op_own;
374 };
375
376 /* Adding direct verbs to data-path. */
377
378 /* CQ sequence number mask. */
379 #define MLX5_CQ_SQN_MASK 0x3
380
381 /* CQ sequence number index. */
382 #define MLX5_CQ_SQN_OFFSET 28
383
384 /* CQ doorbell index mask. */
385 #define MLX5_CI_MASK 0xffffff
386
387 /* CQ doorbell offset. */
388 #define MLX5_CQ_ARM_DB 1
389
390 /* CQ doorbell offset*/
391 #define MLX5_CQ_DOORBELL 0x20
392
393 /* CQE format value. */
394 #define MLX5_COMPRESSED 0x3
395
396 /* CQ doorbell cmd types. */
397 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
398 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
399
400 /* Action type of header modification. */
401 enum {
402         MLX5_MODIFICATION_TYPE_SET = 0x1,
403         MLX5_MODIFICATION_TYPE_ADD = 0x2,
404         MLX5_MODIFICATION_TYPE_COPY = 0x3,
405 };
406
407 /* The field of packet to be modified. */
408 enum mlx5_modification_field {
409         MLX5_MODI_OUT_NONE = -1,
410         MLX5_MODI_OUT_SMAC_47_16 = 1,
411         MLX5_MODI_OUT_SMAC_15_0,
412         MLX5_MODI_OUT_ETHERTYPE,
413         MLX5_MODI_OUT_DMAC_47_16,
414         MLX5_MODI_OUT_DMAC_15_0,
415         MLX5_MODI_OUT_IP_DSCP,
416         MLX5_MODI_OUT_TCP_FLAGS,
417         MLX5_MODI_OUT_TCP_SPORT,
418         MLX5_MODI_OUT_TCP_DPORT,
419         MLX5_MODI_OUT_IPV4_TTL,
420         MLX5_MODI_OUT_UDP_SPORT,
421         MLX5_MODI_OUT_UDP_DPORT,
422         MLX5_MODI_OUT_SIPV6_127_96,
423         MLX5_MODI_OUT_SIPV6_95_64,
424         MLX5_MODI_OUT_SIPV6_63_32,
425         MLX5_MODI_OUT_SIPV6_31_0,
426         MLX5_MODI_OUT_DIPV6_127_96,
427         MLX5_MODI_OUT_DIPV6_95_64,
428         MLX5_MODI_OUT_DIPV6_63_32,
429         MLX5_MODI_OUT_DIPV6_31_0,
430         MLX5_MODI_OUT_SIPV4,
431         MLX5_MODI_OUT_DIPV4,
432         MLX5_MODI_OUT_FIRST_VID,
433         MLX5_MODI_IN_SMAC_47_16 = 0x31,
434         MLX5_MODI_IN_SMAC_15_0,
435         MLX5_MODI_IN_ETHERTYPE,
436         MLX5_MODI_IN_DMAC_47_16,
437         MLX5_MODI_IN_DMAC_15_0,
438         MLX5_MODI_IN_IP_DSCP,
439         MLX5_MODI_IN_TCP_FLAGS,
440         MLX5_MODI_IN_TCP_SPORT,
441         MLX5_MODI_IN_TCP_DPORT,
442         MLX5_MODI_IN_IPV4_TTL,
443         MLX5_MODI_IN_UDP_SPORT,
444         MLX5_MODI_IN_UDP_DPORT,
445         MLX5_MODI_IN_SIPV6_127_96,
446         MLX5_MODI_IN_SIPV6_95_64,
447         MLX5_MODI_IN_SIPV6_63_32,
448         MLX5_MODI_IN_SIPV6_31_0,
449         MLX5_MODI_IN_DIPV6_127_96,
450         MLX5_MODI_IN_DIPV6_95_64,
451         MLX5_MODI_IN_DIPV6_63_32,
452         MLX5_MODI_IN_DIPV6_31_0,
453         MLX5_MODI_IN_SIPV4,
454         MLX5_MODI_IN_DIPV4,
455         MLX5_MODI_OUT_IPV6_HOPLIMIT,
456         MLX5_MODI_IN_IPV6_HOPLIMIT,
457         MLX5_MODI_META_DATA_REG_A,
458         MLX5_MODI_META_DATA_REG_B = 0x50,
459         MLX5_MODI_META_REG_C_0,
460         MLX5_MODI_META_REG_C_1,
461         MLX5_MODI_META_REG_C_2,
462         MLX5_MODI_META_REG_C_3,
463         MLX5_MODI_META_REG_C_4,
464         MLX5_MODI_META_REG_C_5,
465         MLX5_MODI_META_REG_C_6,
466         MLX5_MODI_META_REG_C_7,
467         MLX5_MODI_OUT_TCP_SEQ_NUM,
468         MLX5_MODI_IN_TCP_SEQ_NUM,
469         MLX5_MODI_OUT_TCP_ACK_NUM,
470         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
471 };
472
473 /* Total number of metadata reg_c's. */
474 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
475
476 enum modify_reg {
477         REG_NONE = 0,
478         REG_A,
479         REG_B,
480         REG_C_0,
481         REG_C_1,
482         REG_C_2,
483         REG_C_3,
484         REG_C_4,
485         REG_C_5,
486         REG_C_6,
487         REG_C_7,
488 };
489
490 /* Modification sub command. */
491 struct mlx5_modification_cmd {
492         union {
493                 uint32_t data0;
494                 struct {
495                         unsigned int length:5;
496                         unsigned int rsvd0:3;
497                         unsigned int offset:5;
498                         unsigned int rsvd1:3;
499                         unsigned int field:12;
500                         unsigned int action_type:4;
501                 };
502         };
503         union {
504                 uint32_t data1;
505                 uint8_t data[4];
506                 struct {
507                         unsigned int rsvd2:8;
508                         unsigned int dst_offset:5;
509                         unsigned int rsvd3:3;
510                         unsigned int dst_field:12;
511                         unsigned int rsvd4:4;
512                 };
513         };
514 };
515
516 typedef uint32_t u32;
517 typedef uint16_t u16;
518 typedef uint8_t u8;
519
520 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
521 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
522 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
523                                   (&(__mlx5_nullp(typ)->fld)))
524 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
525                                     (__mlx5_bit_off(typ, fld) & 0x1f))
526 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
527 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
528 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
529                                   __mlx5_dw_bit_off(typ, fld))
530 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
531 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
532 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
533                                     (__mlx5_bit_off(typ, fld) & 0xf))
534 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
535 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
536                                   __mlx5_16_bit_off(typ, fld))
537 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
538 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
539 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
540 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
541
542 /* insert a value to a struct */
543 #define MLX5_SET(typ, p, fld, v) \
544         do { \
545                 u32 _v = v; \
546                 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
547                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
548                                   __mlx5_dw_off(typ, fld))) & \
549                                   (~__mlx5_dw_mask(typ, fld))) | \
550                                  (((_v) & __mlx5_mask(typ, fld)) << \
551                                    __mlx5_dw_bit_off(typ, fld))); \
552         } while (0)
553
554 #define MLX5_SET64(typ, p, fld, v) \
555         do { \
556                 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
557                 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
558                         rte_cpu_to_be_64(v); \
559         } while (0)
560
561 #define MLX5_SET16(typ, p, fld, v) \
562         do { \
563                 u16 _v = v; \
564                 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
565                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((__be16 *)(p) + \
566                                   __mlx5_16_off(typ, fld))) & \
567                                   (~__mlx5_16_mask(typ, fld))) | \
568                                  (((_v) & __mlx5_mask16(typ, fld)) << \
569                                   __mlx5_16_bit_off(typ, fld))); \
570         } while (0)
571
572 #define MLX5_GET(typ, p, fld) \
573         ((rte_be_to_cpu_32(*((__be32 *)(p) +\
574         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
575         __mlx5_mask(typ, fld))
576 #define MLX5_GET16(typ, p, fld) \
577         ((rte_be_to_cpu_16(*((__be16 *)(p) + \
578           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
579          __mlx5_mask16(typ, fld))
580 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
581                                                    __mlx5_64_off(typ, fld)))
582 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
583
584 struct mlx5_ifc_fte_match_set_misc_bits {
585         u8 gre_c_present[0x1];
586         u8 reserved_at_1[0x1];
587         u8 gre_k_present[0x1];
588         u8 gre_s_present[0x1];
589         u8 source_vhci_port[0x4];
590         u8 source_sqn[0x18];
591         u8 reserved_at_20[0x10];
592         u8 source_port[0x10];
593         u8 outer_second_prio[0x3];
594         u8 outer_second_cfi[0x1];
595         u8 outer_second_vid[0xc];
596         u8 inner_second_prio[0x3];
597         u8 inner_second_cfi[0x1];
598         u8 inner_second_vid[0xc];
599         u8 outer_second_cvlan_tag[0x1];
600         u8 inner_second_cvlan_tag[0x1];
601         u8 outer_second_svlan_tag[0x1];
602         u8 inner_second_svlan_tag[0x1];
603         u8 reserved_at_64[0xc];
604         u8 gre_protocol[0x10];
605         u8 gre_key_h[0x18];
606         u8 gre_key_l[0x8];
607         u8 vxlan_vni[0x18];
608         u8 reserved_at_b8[0x8];
609         u8 geneve_vni[0x18];
610         u8 reserved_at_e4[0x7];
611         u8 geneve_oam[0x1];
612         u8 reserved_at_e0[0xc];
613         u8 outer_ipv6_flow_label[0x14];
614         u8 reserved_at_100[0xc];
615         u8 inner_ipv6_flow_label[0x14];
616         u8 reserved_at_120[0xa];
617         u8 geneve_opt_len[0x6];
618         u8 geneve_protocol_type[0x10];
619         u8 reserved_at_140[0xc0];
620 };
621
622 struct mlx5_ifc_ipv4_layout_bits {
623         u8 reserved_at_0[0x60];
624         u8 ipv4[0x20];
625 };
626
627 struct mlx5_ifc_ipv6_layout_bits {
628         u8 ipv6[16][0x8];
629 };
630
631 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
632         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
633         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
634         u8 reserved_at_0[0x80];
635 };
636
637 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
638         u8 smac_47_16[0x20];
639         u8 smac_15_0[0x10];
640         u8 ethertype[0x10];
641         u8 dmac_47_16[0x20];
642         u8 dmac_15_0[0x10];
643         u8 first_prio[0x3];
644         u8 first_cfi[0x1];
645         u8 first_vid[0xc];
646         u8 ip_protocol[0x8];
647         u8 ip_dscp[0x6];
648         u8 ip_ecn[0x2];
649         u8 cvlan_tag[0x1];
650         u8 svlan_tag[0x1];
651         u8 frag[0x1];
652         u8 ip_version[0x4];
653         u8 tcp_flags[0x9];
654         u8 tcp_sport[0x10];
655         u8 tcp_dport[0x10];
656         u8 reserved_at_c0[0x18];
657         u8 ip_ttl_hoplimit[0x8];
658         u8 udp_sport[0x10];
659         u8 udp_dport[0x10];
660         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
661         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
662 };
663
664 struct mlx5_ifc_fte_match_mpls_bits {
665         u8 mpls_label[0x14];
666         u8 mpls_exp[0x3];
667         u8 mpls_s_bos[0x1];
668         u8 mpls_ttl[0x8];
669 };
670
671 struct mlx5_ifc_fte_match_set_misc2_bits {
672         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
673         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
674         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
675         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
676         u8 metadata_reg_c_7[0x20];
677         u8 metadata_reg_c_6[0x20];
678         u8 metadata_reg_c_5[0x20];
679         u8 metadata_reg_c_4[0x20];
680         u8 metadata_reg_c_3[0x20];
681         u8 metadata_reg_c_2[0x20];
682         u8 metadata_reg_c_1[0x20];
683         u8 metadata_reg_c_0[0x20];
684         u8 metadata_reg_a[0x20];
685         u8 metadata_reg_b[0x20];
686         u8 reserved_at_1c0[0x40];
687 };
688
689 struct mlx5_ifc_fte_match_set_misc3_bits {
690         u8 inner_tcp_seq_num[0x20];
691         u8 outer_tcp_seq_num[0x20];
692         u8 inner_tcp_ack_num[0x20];
693         u8 outer_tcp_ack_num[0x20];
694         u8 reserved_at_auto1[0x8];
695         u8 outer_vxlan_gpe_vni[0x18];
696         u8 outer_vxlan_gpe_next_protocol[0x8];
697         u8 outer_vxlan_gpe_flags[0x8];
698         u8 reserved_at_a8[0x10];
699         u8 icmp_header_data[0x20];
700         u8 icmpv6_header_data[0x20];
701         u8 icmp_type[0x8];
702         u8 icmp_code[0x8];
703         u8 icmpv6_type[0x8];
704         u8 icmpv6_code[0x8];
705         u8 reserved_at_120[0x20];
706         u8 gtpu_teid[0x20];
707         u8 gtpu_msg_type[0x08];
708         u8 gtpu_msg_flags[0x08];
709         u8 reserved_at_170[0x90];
710 };
711
712 /* Flow matcher. */
713 struct mlx5_ifc_fte_match_param_bits {
714         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
715         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
716         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
717         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
718         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
719 };
720
721 enum {
722         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
723         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
724         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
725         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
726         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
727 };
728
729 enum {
730         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
731         MLX5_CMD_OP_CREATE_MKEY = 0x200,
732         MLX5_CMD_OP_CREATE_CQ = 0x400,
733         MLX5_CMD_OP_CREATE_QP = 0x500,
734         MLX5_CMD_OP_RST2INIT_QP = 0x502,
735         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
736         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
737         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
738         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
739         MLX5_CMD_OP_QP_2ERR = 0x507,
740         MLX5_CMD_OP_QP_2RST = 0x50A,
741         MLX5_CMD_OP_QUERY_QP = 0x50B,
742         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
743         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
744         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
745         MLX5_CMD_OP_RESUME_QP = 0x510,
746         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
747         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
748         MLX5_CMD_OP_CREATE_TIR = 0x900,
749         MLX5_CMD_OP_CREATE_SQ = 0X904,
750         MLX5_CMD_OP_MODIFY_SQ = 0X905,
751         MLX5_CMD_OP_CREATE_RQ = 0x908,
752         MLX5_CMD_OP_MODIFY_RQ = 0x909,
753         MLX5_CMD_OP_CREATE_TIS = 0x912,
754         MLX5_CMD_OP_QUERY_TIS = 0x915,
755         MLX5_CMD_OP_CREATE_RQT = 0x916,
756         MLX5_CMD_OP_MODIFY_RQT = 0x917,
757         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
758         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
759         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
760         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
761         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
762 };
763
764 enum {
765         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
766         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
767         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
768 };
769
770 #define MLX5_ADAPTER_PAGE_SHIFT 12
771 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
772 /**
773  * The batch counter dcs id starts from 0x800000 and none batch counter
774  * starts from 0. As currently, the counter is changed to be indexed by
775  * pool index and the offset of the counter in the pool counters_raw array.
776  * It means now the counter index is same for batch and none batch counter.
777  * Add the 0x800000 batch counter offset to the batch counter index helps
778  * indicate the counter index is from batch or none batch container pool.
779  */
780 #define MLX5_CNT_BATCH_OFFSET 0x800000
781
782 /* Flow counters. */
783 struct mlx5_ifc_alloc_flow_counter_out_bits {
784         u8         status[0x8];
785         u8         reserved_at_8[0x18];
786         u8         syndrome[0x20];
787         u8         flow_counter_id[0x20];
788         u8         reserved_at_60[0x20];
789 };
790
791 struct mlx5_ifc_alloc_flow_counter_in_bits {
792         u8         opcode[0x10];
793         u8         reserved_at_10[0x10];
794         u8         reserved_at_20[0x10];
795         u8         op_mod[0x10];
796         u8         flow_counter_id[0x20];
797         u8         reserved_at_40[0x18];
798         u8         flow_counter_bulk[0x8];
799 };
800
801 struct mlx5_ifc_dealloc_flow_counter_out_bits {
802         u8         status[0x8];
803         u8         reserved_at_8[0x18];
804         u8         syndrome[0x20];
805         u8         reserved_at_40[0x40];
806 };
807
808 struct mlx5_ifc_dealloc_flow_counter_in_bits {
809         u8         opcode[0x10];
810         u8         reserved_at_10[0x10];
811         u8         reserved_at_20[0x10];
812         u8         op_mod[0x10];
813         u8         flow_counter_id[0x20];
814         u8         reserved_at_60[0x20];
815 };
816
817 struct mlx5_ifc_traffic_counter_bits {
818         u8         packets[0x40];
819         u8         octets[0x40];
820 };
821
822 struct mlx5_ifc_query_flow_counter_out_bits {
823         u8         status[0x8];
824         u8         reserved_at_8[0x18];
825         u8         syndrome[0x20];
826         u8         reserved_at_40[0x40];
827         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
828 };
829
830 struct mlx5_ifc_query_flow_counter_in_bits {
831         u8         opcode[0x10];
832         u8         reserved_at_10[0x10];
833         u8         reserved_at_20[0x10];
834         u8         op_mod[0x10];
835         u8         reserved_at_40[0x20];
836         u8         mkey[0x20];
837         u8         address[0x40];
838         u8         clear[0x1];
839         u8         dump_to_memory[0x1];
840         u8         num_of_counters[0x1e];
841         u8         flow_counter_id[0x20];
842 };
843
844 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
845 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
846
847
848 struct mlx5_ifc_klm_bits {
849         u8         byte_count[0x20];
850         u8         mkey[0x20];
851         u8         address[0x40];
852 };
853
854 struct mlx5_ifc_mkc_bits {
855         u8         reserved_at_0[0x1];
856         u8         free[0x1];
857         u8         reserved_at_2[0x1];
858         u8         access_mode_4_2[0x3];
859         u8         reserved_at_6[0x7];
860         u8         relaxed_ordering_write[0x1];
861         u8         reserved_at_e[0x1];
862         u8         small_fence_on_rdma_read_response[0x1];
863         u8         umr_en[0x1];
864         u8         a[0x1];
865         u8         rw[0x1];
866         u8         rr[0x1];
867         u8         lw[0x1];
868         u8         lr[0x1];
869         u8         access_mode_1_0[0x2];
870         u8         reserved_at_18[0x8];
871
872         u8         qpn[0x18];
873         u8         mkey_7_0[0x8];
874
875         u8         reserved_at_40[0x20];
876
877         u8         length64[0x1];
878         u8         bsf_en[0x1];
879         u8         sync_umr[0x1];
880         u8         reserved_at_63[0x2];
881         u8         expected_sigerr_count[0x1];
882         u8         reserved_at_66[0x1];
883         u8         en_rinval[0x1];
884         u8         pd[0x18];
885
886         u8         start_addr[0x40];
887
888         u8         len[0x40];
889
890         u8         bsf_octword_size[0x20];
891
892         u8         reserved_at_120[0x80];
893
894         u8         translations_octword_size[0x20];
895
896         u8         reserved_at_1c0[0x19];
897         u8                 relaxed_ordering_read[0x1];
898         u8                 reserved_at_1da[0x1];
899         u8         log_page_size[0x5];
900
901         u8         reserved_at_1e0[0x20];
902 };
903
904 struct mlx5_ifc_create_mkey_out_bits {
905         u8         status[0x8];
906         u8         reserved_at_8[0x18];
907
908         u8         syndrome[0x20];
909
910         u8         reserved_at_40[0x8];
911         u8         mkey_index[0x18];
912
913         u8         reserved_at_60[0x20];
914 };
915
916 struct mlx5_ifc_create_mkey_in_bits {
917         u8         opcode[0x10];
918         u8         reserved_at_10[0x10];
919
920         u8         reserved_at_20[0x10];
921         u8         op_mod[0x10];
922
923         u8         reserved_at_40[0x20];
924
925         u8         pg_access[0x1];
926         u8         reserved_at_61[0x1f];
927
928         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
929
930         u8         reserved_at_280[0x80];
931
932         u8         translations_octword_actual_size[0x20];
933
934         u8         mkey_umem_id[0x20];
935
936         u8         mkey_umem_offset[0x40];
937
938         u8         reserved_at_380[0x500];
939
940         u8         klm_pas_mtt[][0x20];
941 };
942
943 enum {
944         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
945         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
946         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
947         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
948 };
949
950 enum {
951         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),
952         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS = (1ULL << 0x1c),
953 };
954
955 enum {
956         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
957         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
958 };
959
960 enum {
961         MLX5_CAP_INLINE_MODE_L2,
962         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
963         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
964 };
965
966 enum {
967         MLX5_INLINE_MODE_NONE,
968         MLX5_INLINE_MODE_L2,
969         MLX5_INLINE_MODE_IP,
970         MLX5_INLINE_MODE_TCP_UDP,
971         MLX5_INLINE_MODE_RESERVED4,
972         MLX5_INLINE_MODE_INNER_L2,
973         MLX5_INLINE_MODE_INNER_IP,
974         MLX5_INLINE_MODE_INNER_TCP_UDP,
975 };
976
977 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
978 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
979 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
980 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
981 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
982 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
983 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
984 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
985 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
986 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
987 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
988
989 struct mlx5_ifc_cmd_hca_cap_bits {
990         u8 reserved_at_0[0x30];
991         u8 vhca_id[0x10];
992         u8 reserved_at_40[0x40];
993         u8 log_max_srq_sz[0x8];
994         u8 log_max_qp_sz[0x8];
995         u8 reserved_at_90[0xb];
996         u8 log_max_qp[0x5];
997         u8 regexp[0x1];
998         u8 reserved_at_a1[0x3];
999         u8 regexp_num_of_engines[0x4];
1000         u8 reserved_at_a8[0x3];
1001         u8 log_max_srq[0x5];
1002         u8 reserved_at_b0[0x3];
1003         u8 regexp_log_crspace_size[0x5];
1004         u8 reserved_at_b8[0x8];
1005         u8 reserved_at_c0[0x8];
1006         u8 log_max_cq_sz[0x8];
1007         u8 reserved_at_d0[0xb];
1008         u8 log_max_cq[0x5];
1009         u8 log_max_eq_sz[0x8];
1010         u8 relaxed_ordering_write[0x1];
1011         u8 relaxed_ordering_read[0x1];
1012         u8 log_max_mkey[0x6];
1013         u8 reserved_at_f0[0x8];
1014         u8 dump_fill_mkey[0x1];
1015         u8 reserved_at_f9[0x3];
1016         u8 log_max_eq[0x4];
1017         u8 max_indirection[0x8];
1018         u8 fixed_buffer_size[0x1];
1019         u8 log_max_mrw_sz[0x7];
1020         u8 force_teardown[0x1];
1021         u8 reserved_at_111[0x1];
1022         u8 log_max_bsf_list_size[0x6];
1023         u8 umr_extended_translation_offset[0x1];
1024         u8 null_mkey[0x1];
1025         u8 log_max_klm_list_size[0x6];
1026         u8 reserved_at_120[0xa];
1027         u8 log_max_ra_req_dc[0x6];
1028         u8 reserved_at_130[0xa];
1029         u8 log_max_ra_res_dc[0x6];
1030         u8 reserved_at_140[0xa];
1031         u8 log_max_ra_req_qp[0x6];
1032         u8 reserved_at_150[0xa];
1033         u8 log_max_ra_res_qp[0x6];
1034         u8 end_pad[0x1];
1035         u8 cc_query_allowed[0x1];
1036         u8 cc_modify_allowed[0x1];
1037         u8 start_pad[0x1];
1038         u8 cache_line_128byte[0x1];
1039         u8 reserved_at_165[0xa];
1040         u8 qcam_reg[0x1];
1041         u8 gid_table_size[0x10];
1042         u8 out_of_seq_cnt[0x1];
1043         u8 vport_counters[0x1];
1044         u8 retransmission_q_counters[0x1];
1045         u8 debug[0x1];
1046         u8 modify_rq_counter_set_id[0x1];
1047         u8 rq_delay_drop[0x1];
1048         u8 max_qp_cnt[0xa];
1049         u8 pkey_table_size[0x10];
1050         u8 vport_group_manager[0x1];
1051         u8 vhca_group_manager[0x1];
1052         u8 ib_virt[0x1];
1053         u8 eth_virt[0x1];
1054         u8 vnic_env_queue_counters[0x1];
1055         u8 ets[0x1];
1056         u8 nic_flow_table[0x1];
1057         u8 eswitch_manager[0x1];
1058         u8 device_memory[0x1];
1059         u8 mcam_reg[0x1];
1060         u8 pcam_reg[0x1];
1061         u8 local_ca_ack_delay[0x5];
1062         u8 port_module_event[0x1];
1063         u8 enhanced_error_q_counters[0x1];
1064         u8 ports_check[0x1];
1065         u8 reserved_at_1b3[0x1];
1066         u8 disable_link_up[0x1];
1067         u8 beacon_led[0x1];
1068         u8 port_type[0x2];
1069         u8 num_ports[0x8];
1070         u8 reserved_at_1c0[0x1];
1071         u8 pps[0x1];
1072         u8 pps_modify[0x1];
1073         u8 log_max_msg[0x5];
1074         u8 reserved_at_1c8[0x4];
1075         u8 max_tc[0x4];
1076         u8 temp_warn_event[0x1];
1077         u8 dcbx[0x1];
1078         u8 general_notification_event[0x1];
1079         u8 reserved_at_1d3[0x2];
1080         u8 fpga[0x1];
1081         u8 rol_s[0x1];
1082         u8 rol_g[0x1];
1083         u8 reserved_at_1d8[0x1];
1084         u8 wol_s[0x1];
1085         u8 wol_g[0x1];
1086         u8 wol_a[0x1];
1087         u8 wol_b[0x1];
1088         u8 wol_m[0x1];
1089         u8 wol_u[0x1];
1090         u8 wol_p[0x1];
1091         u8 stat_rate_support[0x10];
1092         u8 reserved_at_1f0[0xc];
1093         u8 cqe_version[0x4];
1094         u8 compact_address_vector[0x1];
1095         u8 striding_rq[0x1];
1096         u8 reserved_at_202[0x1];
1097         u8 ipoib_enhanced_offloads[0x1];
1098         u8 ipoib_basic_offloads[0x1];
1099         u8 reserved_at_205[0x1];
1100         u8 repeated_block_disabled[0x1];
1101         u8 umr_modify_entity_size_disabled[0x1];
1102         u8 umr_modify_atomic_disabled[0x1];
1103         u8 umr_indirect_mkey_disabled[0x1];
1104         u8 umr_fence[0x2];
1105         u8 reserved_at_20c[0x3];
1106         u8 drain_sigerr[0x1];
1107         u8 cmdif_checksum[0x2];
1108         u8 sigerr_cqe[0x1];
1109         u8 reserved_at_213[0x1];
1110         u8 wq_signature[0x1];
1111         u8 sctr_data_cqe[0x1];
1112         u8 reserved_at_216[0x1];
1113         u8 sho[0x1];
1114         u8 tph[0x1];
1115         u8 rf[0x1];
1116         u8 dct[0x1];
1117         u8 qos[0x1];
1118         u8 eth_net_offloads[0x1];
1119         u8 roce[0x1];
1120         u8 atomic[0x1];
1121         u8 reserved_at_21f[0x1];
1122         u8 cq_oi[0x1];
1123         u8 cq_resize[0x1];
1124         u8 cq_moderation[0x1];
1125         u8 reserved_at_223[0x3];
1126         u8 cq_eq_remap[0x1];
1127         u8 pg[0x1];
1128         u8 block_lb_mc[0x1];
1129         u8 reserved_at_229[0x1];
1130         u8 scqe_break_moderation[0x1];
1131         u8 cq_period_start_from_cqe[0x1];
1132         u8 cd[0x1];
1133         u8 reserved_at_22d[0x1];
1134         u8 apm[0x1];
1135         u8 vector_calc[0x1];
1136         u8 umr_ptr_rlky[0x1];
1137         u8 imaicl[0x1];
1138         u8 reserved_at_232[0x4];
1139         u8 qkv[0x1];
1140         u8 pkv[0x1];
1141         u8 set_deth_sqpn[0x1];
1142         u8 reserved_at_239[0x3];
1143         u8 xrc[0x1];
1144         u8 ud[0x1];
1145         u8 uc[0x1];
1146         u8 rc[0x1];
1147         u8 uar_4k[0x1];
1148         u8 reserved_at_241[0x9];
1149         u8 uar_sz[0x6];
1150         u8 reserved_at_250[0x8];
1151         u8 log_pg_sz[0x8];
1152         u8 bf[0x1];
1153         u8 driver_version[0x1];
1154         u8 pad_tx_eth_packet[0x1];
1155         u8 reserved_at_263[0x8];
1156         u8 log_bf_reg_size[0x5];
1157         u8 reserved_at_270[0xb];
1158         u8 lag_master[0x1];
1159         u8 num_lag_ports[0x4];
1160         u8 reserved_at_280[0x10];
1161         u8 max_wqe_sz_sq[0x10];
1162         u8 reserved_at_2a0[0x10];
1163         u8 max_wqe_sz_rq[0x10];
1164         u8 max_flow_counter_31_16[0x10];
1165         u8 max_wqe_sz_sq_dc[0x10];
1166         u8 reserved_at_2e0[0x7];
1167         u8 max_qp_mcg[0x19];
1168         u8 reserved_at_300[0x10];
1169         u8 flow_counter_bulk_alloc[0x08];
1170         u8 log_max_mcg[0x8];
1171         u8 reserved_at_320[0x3];
1172         u8 log_max_transport_domain[0x5];
1173         u8 reserved_at_328[0x3];
1174         u8 log_max_pd[0x5];
1175         u8 reserved_at_330[0xb];
1176         u8 log_max_xrcd[0x5];
1177         u8 nic_receive_steering_discard[0x1];
1178         u8 receive_discard_vport_down[0x1];
1179         u8 transmit_discard_vport_down[0x1];
1180         u8 reserved_at_343[0x5];
1181         u8 log_max_flow_counter_bulk[0x8];
1182         u8 max_flow_counter_15_0[0x10];
1183         u8 modify_tis[0x1];
1184         u8 flow_counters_dump[0x1];
1185         u8 reserved_at_360[0x1];
1186         u8 log_max_rq[0x5];
1187         u8 reserved_at_368[0x3];
1188         u8 log_max_sq[0x5];
1189         u8 reserved_at_370[0x3];
1190         u8 log_max_tir[0x5];
1191         u8 reserved_at_378[0x3];
1192         u8 log_max_tis[0x5];
1193         u8 basic_cyclic_rcv_wqe[0x1];
1194         u8 reserved_at_381[0x2];
1195         u8 log_max_rmp[0x5];
1196         u8 reserved_at_388[0x3];
1197         u8 log_max_rqt[0x5];
1198         u8 reserved_at_390[0x3];
1199         u8 log_max_rqt_size[0x5];
1200         u8 reserved_at_398[0x3];
1201         u8 log_max_tis_per_sq[0x5];
1202         u8 ext_stride_num_range[0x1];
1203         u8 reserved_at_3a1[0x2];
1204         u8 log_max_stride_sz_rq[0x5];
1205         u8 reserved_at_3a8[0x3];
1206         u8 log_min_stride_sz_rq[0x5];
1207         u8 reserved_at_3b0[0x3];
1208         u8 log_max_stride_sz_sq[0x5];
1209         u8 reserved_at_3b8[0x3];
1210         u8 log_min_stride_sz_sq[0x5];
1211         u8 hairpin[0x1];
1212         u8 reserved_at_3c1[0x2];
1213         u8 log_max_hairpin_queues[0x5];
1214         u8 reserved_at_3c8[0x3];
1215         u8 log_max_hairpin_wq_data_sz[0x5];
1216         u8 reserved_at_3d0[0x3];
1217         u8 log_max_hairpin_num_packets[0x5];
1218         u8 reserved_at_3d8[0x3];
1219         u8 log_max_wq_sz[0x5];
1220         u8 nic_vport_change_event[0x1];
1221         u8 disable_local_lb_uc[0x1];
1222         u8 disable_local_lb_mc[0x1];
1223         u8 log_min_hairpin_wq_data_sz[0x5];
1224         u8 reserved_at_3e8[0x3];
1225         u8 log_max_vlan_list[0x5];
1226         u8 reserved_at_3f0[0x3];
1227         u8 log_max_current_mc_list[0x5];
1228         u8 reserved_at_3f8[0x3];
1229         u8 log_max_current_uc_list[0x5];
1230         u8 general_obj_types[0x40];
1231         u8 reserved_at_440[0x20];
1232         u8 reserved_at_460[0x10];
1233         u8 max_num_eqs[0x10];
1234         u8 reserved_at_480[0x3];
1235         u8 log_max_l2_table[0x5];
1236         u8 reserved_at_488[0x8];
1237         u8 log_uar_page_sz[0x10];
1238         u8 reserved_at_4a0[0x20];
1239         u8 device_frequency_mhz[0x20];
1240         u8 device_frequency_khz[0x20];
1241         u8 reserved_at_500[0x20];
1242         u8 num_of_uars_per_page[0x20];
1243         u8 flex_parser_protocols[0x20];
1244         u8 reserved_at_560[0x20];
1245         u8 reserved_at_580[0x3c];
1246         u8 mini_cqe_resp_stride_index[0x1];
1247         u8 cqe_128_always[0x1];
1248         u8 cqe_compression_128[0x1];
1249         u8 cqe_compression[0x1];
1250         u8 cqe_compression_timeout[0x10];
1251         u8 cqe_compression_max_num[0x10];
1252         u8 reserved_at_5e0[0x10];
1253         u8 tag_matching[0x1];
1254         u8 rndv_offload_rc[0x1];
1255         u8 rndv_offload_dc[0x1];
1256         u8 log_tag_matching_list_sz[0x5];
1257         u8 reserved_at_5f8[0x3];
1258         u8 log_max_xrq[0x5];
1259         u8 affiliate_nic_vport_criteria[0x8];
1260         u8 native_port_num[0x8];
1261         u8 num_vhca_ports[0x8];
1262         u8 reserved_at_618[0x6];
1263         u8 sw_owner_id[0x1];
1264         u8 reserved_at_61f[0x1e1];
1265 };
1266
1267 struct mlx5_ifc_qos_cap_bits {
1268         u8 packet_pacing[0x1];
1269         u8 esw_scheduling[0x1];
1270         u8 esw_bw_share[0x1];
1271         u8 esw_rate_limit[0x1];
1272         u8 reserved_at_4[0x1];
1273         u8 packet_pacing_burst_bound[0x1];
1274         u8 packet_pacing_typical_size[0x1];
1275         u8 flow_meter_srtcm[0x1];
1276         u8 reserved_at_8[0x8];
1277         u8 log_max_flow_meter[0x8];
1278         u8 flow_meter_reg_id[0x8];
1279         u8 reserved_at_25[0x8];
1280         u8 flow_meter_reg_share[0x1];
1281         u8 reserved_at_2e[0x17];
1282         u8 packet_pacing_max_rate[0x20];
1283         u8 packet_pacing_min_rate[0x20];
1284         u8 reserved_at_80[0x10];
1285         u8 packet_pacing_rate_table_size[0x10];
1286         u8 esw_element_type[0x10];
1287         u8 esw_tsar_type[0x10];
1288         u8 reserved_at_c0[0x10];
1289         u8 max_qos_para_vport[0x10];
1290         u8 max_tsar_bw_share[0x20];
1291         u8 reserved_at_100[0x6e8];
1292 };
1293
1294 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1295         u8 csum_cap[0x1];
1296         u8 vlan_cap[0x1];
1297         u8 lro_cap[0x1];
1298         u8 lro_psh_flag[0x1];
1299         u8 lro_time_stamp[0x1];
1300         u8 lro_max_msg_sz_mode[0x2];
1301         u8 wqe_vlan_insert[0x1];
1302         u8 self_lb_en_modifiable[0x1];
1303         u8 self_lb_mc[0x1];
1304         u8 self_lb_uc[0x1];
1305         u8 max_lso_cap[0x5];
1306         u8 multi_pkt_send_wqe[0x2];
1307         u8 wqe_inline_mode[0x2];
1308         u8 rss_ind_tbl_cap[0x4];
1309         u8 reg_umr_sq[0x1];
1310         u8 scatter_fcs[0x1];
1311         u8 enhanced_multi_pkt_send_wqe[0x1];
1312         u8 tunnel_lso_const_out_ip_id[0x1];
1313         u8 tunnel_lro_gre[0x1];
1314         u8 tunnel_lro_vxlan[0x1];
1315         u8 tunnel_stateless_gre[0x1];
1316         u8 tunnel_stateless_vxlan[0x1];
1317         u8 swp[0x1];
1318         u8 swp_csum[0x1];
1319         u8 swp_lso[0x1];
1320         u8 reserved_at_23[0x8];
1321         u8 tunnel_stateless_gtp[0x1];
1322         u8 reserved_at_25[0x4];
1323         u8 max_vxlan_udp_ports[0x8];
1324         u8 reserved_at_38[0x6];
1325         u8 max_geneve_opt_len[0x1];
1326         u8 tunnel_stateless_geneve_rx[0x1];
1327         u8 reserved_at_40[0x10];
1328         u8 lro_min_mss_size[0x10];
1329         u8 reserved_at_60[0x120];
1330         u8 lro_timer_supported_periods[4][0x20];
1331         u8 reserved_at_200[0x600];
1332 };
1333
1334 enum {
1335         MLX5_VIRTQ_TYPE_SPLIT = 0,
1336         MLX5_VIRTQ_TYPE_PACKED = 1,
1337 };
1338
1339 enum {
1340         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1341         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1342         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1343 };
1344
1345 struct mlx5_ifc_virtio_emulation_cap_bits {
1346         u8 desc_tunnel_offload_type[0x1];
1347         u8 eth_frame_offload_type[0x1];
1348         u8 virtio_version_1_0[0x1];
1349         u8 tso_ipv4[0x1];
1350         u8 tso_ipv6[0x1];
1351         u8 tx_csum[0x1];
1352         u8 rx_csum[0x1];
1353         u8 reserved_at_7[0x1][0x9];
1354         u8 event_mode[0x8];
1355         u8 virtio_queue_type[0x8];
1356         u8 reserved_at_20[0x13];
1357         u8 log_doorbell_stride[0x5];
1358         u8 reserved_at_3b[0x3];
1359         u8 log_doorbell_bar_size[0x5];
1360         u8 doorbell_bar_offset[0x40];
1361         u8 reserved_at_80[0x8];
1362         u8 max_num_virtio_queues[0x18];
1363         u8 reserved_at_a0[0x60];
1364         u8 umem_1_buffer_param_a[0x20];
1365         u8 umem_1_buffer_param_b[0x20];
1366         u8 umem_2_buffer_param_a[0x20];
1367         u8 umem_2_buffer_param_b[0x20];
1368         u8 umem_3_buffer_param_a[0x20];
1369         u8 umem_3_buffer_param_b[0x20];
1370         u8 reserved_at_1c0[0x620];
1371 };
1372
1373 union mlx5_ifc_hca_cap_union_bits {
1374         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1375         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1376                per_protocol_networking_offload_caps;
1377         struct mlx5_ifc_qos_cap_bits qos_cap;
1378         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1379         u8 reserved_at_0[0x8000];
1380 };
1381
1382 struct mlx5_ifc_query_hca_cap_out_bits {
1383         u8 status[0x8];
1384         u8 reserved_at_8[0x18];
1385         u8 syndrome[0x20];
1386         u8 reserved_at_40[0x40];
1387         union mlx5_ifc_hca_cap_union_bits capability;
1388 };
1389
1390 struct mlx5_ifc_query_hca_cap_in_bits {
1391         u8 opcode[0x10];
1392         u8 reserved_at_10[0x10];
1393         u8 reserved_at_20[0x10];
1394         u8 op_mod[0x10];
1395         u8 reserved_at_40[0x40];
1396 };
1397
1398 struct mlx5_ifc_mac_address_layout_bits {
1399         u8 reserved_at_0[0x10];
1400         u8 mac_addr_47_32[0x10];
1401         u8 mac_addr_31_0[0x20];
1402 };
1403
1404 struct mlx5_ifc_nic_vport_context_bits {
1405         u8 reserved_at_0[0x5];
1406         u8 min_wqe_inline_mode[0x3];
1407         u8 reserved_at_8[0x15];
1408         u8 disable_mc_local_lb[0x1];
1409         u8 disable_uc_local_lb[0x1];
1410         u8 roce_en[0x1];
1411         u8 arm_change_event[0x1];
1412         u8 reserved_at_21[0x1a];
1413         u8 event_on_mtu[0x1];
1414         u8 event_on_promisc_change[0x1];
1415         u8 event_on_vlan_change[0x1];
1416         u8 event_on_mc_address_change[0x1];
1417         u8 event_on_uc_address_change[0x1];
1418         u8 reserved_at_40[0xc];
1419         u8 affiliation_criteria[0x4];
1420         u8 affiliated_vhca_id[0x10];
1421         u8 reserved_at_60[0xd0];
1422         u8 mtu[0x10];
1423         u8 system_image_guid[0x40];
1424         u8 port_guid[0x40];
1425         u8 node_guid[0x40];
1426         u8 reserved_at_200[0x140];
1427         u8 qkey_violation_counter[0x10];
1428         u8 reserved_at_350[0x430];
1429         u8 promisc_uc[0x1];
1430         u8 promisc_mc[0x1];
1431         u8 promisc_all[0x1];
1432         u8 reserved_at_783[0x2];
1433         u8 allowed_list_type[0x3];
1434         u8 reserved_at_788[0xc];
1435         u8 allowed_list_size[0xc];
1436         struct mlx5_ifc_mac_address_layout_bits permanent_address;
1437         u8 reserved_at_7e0[0x20];
1438 };
1439
1440 struct mlx5_ifc_query_nic_vport_context_out_bits {
1441         u8 status[0x8];
1442         u8 reserved_at_8[0x18];
1443         u8 syndrome[0x20];
1444         u8 reserved_at_40[0x40];
1445         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1446 };
1447
1448 struct mlx5_ifc_query_nic_vport_context_in_bits {
1449         u8 opcode[0x10];
1450         u8 reserved_at_10[0x10];
1451         u8 reserved_at_20[0x10];
1452         u8 op_mod[0x10];
1453         u8 other_vport[0x1];
1454         u8 reserved_at_41[0xf];
1455         u8 vport_number[0x10];
1456         u8 reserved_at_60[0x5];
1457         u8 allowed_list_type[0x3];
1458         u8 reserved_at_68[0x18];
1459 };
1460
1461 struct mlx5_ifc_tisc_bits {
1462         u8 strict_lag_tx_port_affinity[0x1];
1463         u8 reserved_at_1[0x3];
1464         u8 lag_tx_port_affinity[0x04];
1465         u8 reserved_at_8[0x4];
1466         u8 prio[0x4];
1467         u8 reserved_at_10[0x10];
1468         u8 reserved_at_20[0x100];
1469         u8 reserved_at_120[0x8];
1470         u8 transport_domain[0x18];
1471         u8 reserved_at_140[0x8];
1472         u8 underlay_qpn[0x18];
1473         u8 reserved_at_160[0x3a0];
1474 };
1475
1476 struct mlx5_ifc_query_tis_out_bits {
1477         u8 status[0x8];
1478         u8 reserved_at_8[0x18];
1479         u8 syndrome[0x20];
1480         u8 reserved_at_40[0x40];
1481         struct mlx5_ifc_tisc_bits tis_context;
1482 };
1483
1484 struct mlx5_ifc_query_tis_in_bits {
1485         u8 opcode[0x10];
1486         u8 reserved_at_10[0x10];
1487         u8 reserved_at_20[0x10];
1488         u8 op_mod[0x10];
1489         u8 reserved_at_40[0x8];
1490         u8 tisn[0x18];
1491         u8 reserved_at_60[0x20];
1492 };
1493
1494 struct mlx5_ifc_alloc_transport_domain_out_bits {
1495         u8 status[0x8];
1496         u8 reserved_at_8[0x18];
1497         u8 syndrome[0x20];
1498         u8 reserved_at_40[0x8];
1499         u8 transport_domain[0x18];
1500         u8 reserved_at_60[0x20];
1501 };
1502
1503 struct mlx5_ifc_alloc_transport_domain_in_bits {
1504         u8 opcode[0x10];
1505         u8 reserved_at_10[0x10];
1506         u8 reserved_at_20[0x10];
1507         u8 op_mod[0x10];
1508         u8 reserved_at_40[0x40];
1509 };
1510
1511 enum {
1512         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
1513         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
1514         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
1515         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
1516 };
1517
1518 enum {
1519         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
1520         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1521 };
1522
1523 struct mlx5_ifc_wq_bits {
1524         u8 wq_type[0x4];
1525         u8 wq_signature[0x1];
1526         u8 end_padding_mode[0x2];
1527         u8 cd_slave[0x1];
1528         u8 reserved_at_8[0x18];
1529         u8 hds_skip_first_sge[0x1];
1530         u8 log2_hds_buf_size[0x3];
1531         u8 reserved_at_24[0x7];
1532         u8 page_offset[0x5];
1533         u8 lwm[0x10];
1534         u8 reserved_at_40[0x8];
1535         u8 pd[0x18];
1536         u8 reserved_at_60[0x8];
1537         u8 uar_page[0x18];
1538         u8 dbr_addr[0x40];
1539         u8 hw_counter[0x20];
1540         u8 sw_counter[0x20];
1541         u8 reserved_at_100[0xc];
1542         u8 log_wq_stride[0x4];
1543         u8 reserved_at_110[0x3];
1544         u8 log_wq_pg_sz[0x5];
1545         u8 reserved_at_118[0x3];
1546         u8 log_wq_sz[0x5];
1547         u8 dbr_umem_valid[0x1];
1548         u8 wq_umem_valid[0x1];
1549         u8 reserved_at_122[0x1];
1550         u8 log_hairpin_num_packets[0x5];
1551         u8 reserved_at_128[0x3];
1552         u8 log_hairpin_data_sz[0x5];
1553         u8 reserved_at_130[0x4];
1554         u8 single_wqe_log_num_of_strides[0x4];
1555         u8 two_byte_shift_en[0x1];
1556         u8 reserved_at_139[0x4];
1557         u8 single_stride_log_num_of_bytes[0x3];
1558         u8 dbr_umem_id[0x20];
1559         u8 wq_umem_id[0x20];
1560         u8 wq_umem_offset[0x40];
1561         u8 reserved_at_1c0[0x440];
1562 };
1563
1564 enum {
1565         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
1566         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
1567 };
1568
1569 enum {
1570         MLX5_RQC_STATE_RST  = 0x0,
1571         MLX5_RQC_STATE_RDY  = 0x1,
1572         MLX5_RQC_STATE_ERR  = 0x3,
1573 };
1574
1575 struct mlx5_ifc_rqc_bits {
1576         u8 rlky[0x1];
1577         u8 delay_drop_en[0x1];
1578         u8 scatter_fcs[0x1];
1579         u8 vsd[0x1];
1580         u8 mem_rq_type[0x4];
1581         u8 state[0x4];
1582         u8 reserved_at_c[0x1];
1583         u8 flush_in_error_en[0x1];
1584         u8 hairpin[0x1];
1585         u8 reserved_at_f[0x11];
1586         u8 reserved_at_20[0x8];
1587         u8 user_index[0x18];
1588         u8 reserved_at_40[0x8];
1589         u8 cqn[0x18];
1590         u8 counter_set_id[0x8];
1591         u8 reserved_at_68[0x18];
1592         u8 reserved_at_80[0x8];
1593         u8 rmpn[0x18];
1594         u8 reserved_at_a0[0x8];
1595         u8 hairpin_peer_sq[0x18];
1596         u8 reserved_at_c0[0x10];
1597         u8 hairpin_peer_vhca[0x10];
1598         u8 reserved_at_e0[0xa0];
1599         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1600 };
1601
1602 struct mlx5_ifc_create_rq_out_bits {
1603         u8 status[0x8];
1604         u8 reserved_at_8[0x18];
1605         u8 syndrome[0x20];
1606         u8 reserved_at_40[0x8];
1607         u8 rqn[0x18];
1608         u8 reserved_at_60[0x20];
1609 };
1610
1611 struct mlx5_ifc_create_rq_in_bits {
1612         u8 opcode[0x10];
1613         u8 uid[0x10];
1614         u8 reserved_at_20[0x10];
1615         u8 op_mod[0x10];
1616         u8 reserved_at_40[0xc0];
1617         struct mlx5_ifc_rqc_bits ctx;
1618 };
1619
1620 struct mlx5_ifc_modify_rq_out_bits {
1621         u8 status[0x8];
1622         u8 reserved_at_8[0x18];
1623         u8 syndrome[0x20];
1624         u8 reserved_at_40[0x40];
1625 };
1626
1627 struct mlx5_ifc_create_tis_out_bits {
1628         u8 status[0x8];
1629         u8 reserved_at_8[0x18];
1630         u8 syndrome[0x20];
1631         u8 reserved_at_40[0x8];
1632         u8 tisn[0x18];
1633         u8 reserved_at_60[0x20];
1634 };
1635
1636 struct mlx5_ifc_create_tis_in_bits {
1637         u8 opcode[0x10];
1638         u8 uid[0x10];
1639         u8 reserved_at_20[0x10];
1640         u8 op_mod[0x10];
1641         u8 reserved_at_40[0xc0];
1642         struct mlx5_ifc_tisc_bits ctx;
1643 };
1644
1645 enum {
1646         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1647         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1648         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1649         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1650 };
1651
1652 struct mlx5_ifc_modify_rq_in_bits {
1653         u8 opcode[0x10];
1654         u8 uid[0x10];
1655         u8 reserved_at_20[0x10];
1656         u8 op_mod[0x10];
1657         u8 rq_state[0x4];
1658         u8 reserved_at_44[0x4];
1659         u8 rqn[0x18];
1660         u8 reserved_at_60[0x20];
1661         u8 modify_bitmask[0x40];
1662         u8 reserved_at_c0[0x40];
1663         struct mlx5_ifc_rqc_bits ctx;
1664 };
1665
1666 enum {
1667         MLX5_L3_PROT_TYPE_IPV4 = 0,
1668         MLX5_L3_PROT_TYPE_IPV6 = 1,
1669 };
1670
1671 enum {
1672         MLX5_L4_PROT_TYPE_TCP = 0,
1673         MLX5_L4_PROT_TYPE_UDP = 1,
1674 };
1675
1676 enum {
1677         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1678         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1679         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1680         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1681         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1682 };
1683
1684 struct mlx5_ifc_rx_hash_field_select_bits {
1685         u8 l3_prot_type[0x1];
1686         u8 l4_prot_type[0x1];
1687         u8 selected_fields[0x1e];
1688 };
1689
1690 enum {
1691         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1692         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1693 };
1694
1695 enum {
1696         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1697         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1698 };
1699
1700 enum {
1701         MLX5_RX_HASH_FN_NONE           = 0x0,
1702         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
1703         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
1704 };
1705
1706 enum {
1707         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
1708         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
1709 };
1710
1711 enum {
1712         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
1713         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
1714 };
1715
1716 struct mlx5_ifc_tirc_bits {
1717         u8 reserved_at_0[0x20];
1718         u8 disp_type[0x4];
1719         u8 reserved_at_24[0x1c];
1720         u8 reserved_at_40[0x40];
1721         u8 reserved_at_80[0x4];
1722         u8 lro_timeout_period_usecs[0x10];
1723         u8 lro_enable_mask[0x4];
1724         u8 lro_max_msg_sz[0x8];
1725         u8 reserved_at_a0[0x40];
1726         u8 reserved_at_e0[0x8];
1727         u8 inline_rqn[0x18];
1728         u8 rx_hash_symmetric[0x1];
1729         u8 reserved_at_101[0x1];
1730         u8 tunneled_offload_en[0x1];
1731         u8 reserved_at_103[0x5];
1732         u8 indirect_table[0x18];
1733         u8 rx_hash_fn[0x4];
1734         u8 reserved_at_124[0x2];
1735         u8 self_lb_block[0x2];
1736         u8 transport_domain[0x18];
1737         u8 rx_hash_toeplitz_key[10][0x20];
1738         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1739         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1740         u8 reserved_at_2c0[0x4c0];
1741 };
1742
1743 struct mlx5_ifc_create_tir_out_bits {
1744         u8 status[0x8];
1745         u8 reserved_at_8[0x18];
1746         u8 syndrome[0x20];
1747         u8 reserved_at_40[0x8];
1748         u8 tirn[0x18];
1749         u8 reserved_at_60[0x20];
1750 };
1751
1752 struct mlx5_ifc_create_tir_in_bits {
1753         u8 opcode[0x10];
1754         u8 uid[0x10];
1755         u8 reserved_at_20[0x10];
1756         u8 op_mod[0x10];
1757         u8 reserved_at_40[0xc0];
1758         struct mlx5_ifc_tirc_bits ctx;
1759 };
1760
1761 enum {
1762         MLX5_INLINE_Q_TYPE_RQ = 0x0,
1763         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
1764 };
1765
1766 struct mlx5_ifc_rq_num_bits {
1767         u8 reserved_at_0[0x8];
1768         u8 rq_num[0x18];
1769 };
1770
1771 struct mlx5_ifc_rqtc_bits {
1772         u8 reserved_at_0[0xa5];
1773         u8 list_q_type[0x3];
1774         u8 reserved_at_a8[0x8];
1775         u8 rqt_max_size[0x10];
1776         u8 reserved_at_c0[0x10];
1777         u8 rqt_actual_size[0x10];
1778         u8 reserved_at_e0[0x6a0];
1779         struct mlx5_ifc_rq_num_bits rq_num[];
1780 };
1781
1782 struct mlx5_ifc_create_rqt_out_bits {
1783         u8 status[0x8];
1784         u8 reserved_at_8[0x18];
1785         u8 syndrome[0x20];
1786         u8 reserved_at_40[0x8];
1787         u8 rqtn[0x18];
1788         u8 reserved_at_60[0x20];
1789 };
1790
1791 #ifdef PEDANTIC
1792 #pragma GCC diagnostic ignored "-Wpedantic"
1793 #endif
1794 struct mlx5_ifc_create_rqt_in_bits {
1795         u8 opcode[0x10];
1796         u8 uid[0x10];
1797         u8 reserved_at_20[0x10];
1798         u8 op_mod[0x10];
1799         u8 reserved_at_40[0xc0];
1800         struct mlx5_ifc_rqtc_bits rqt_context;
1801 };
1802
1803 struct mlx5_ifc_modify_rqt_in_bits {
1804         u8 opcode[0x10];
1805         u8 uid[0x10];
1806         u8 reserved_at_20[0x10];
1807         u8 op_mod[0x10];
1808         u8 reserved_at_40[0x8];
1809         u8 rqtn[0x18];
1810         u8 reserved_at_60[0x20];
1811         u8 modify_bitmask[0x40];
1812         u8 reserved_at_c0[0x40];
1813         struct mlx5_ifc_rqtc_bits rqt_context;
1814 };
1815 #ifdef PEDANTIC
1816 #pragma GCC diagnostic error "-Wpedantic"
1817 #endif
1818
1819 struct mlx5_ifc_modify_rqt_out_bits {
1820         u8 status[0x8];
1821         u8 reserved_at_8[0x18];
1822         u8 syndrome[0x20];
1823         u8 reserved_at_40[0x40];
1824 };
1825
1826 enum {
1827         MLX5_SQC_STATE_RST  = 0x0,
1828         MLX5_SQC_STATE_RDY  = 0x1,
1829         MLX5_SQC_STATE_ERR  = 0x3,
1830 };
1831
1832 struct mlx5_ifc_sqc_bits {
1833         u8 rlky[0x1];
1834         u8 cd_master[0x1];
1835         u8 fre[0x1];
1836         u8 flush_in_error_en[0x1];
1837         u8 allow_multi_pkt_send_wqe[0x1];
1838         u8 min_wqe_inline_mode[0x3];
1839         u8 state[0x4];
1840         u8 reg_umr[0x1];
1841         u8 allow_swp[0x1];
1842         u8 hairpin[0x1];
1843         u8 reserved_at_f[0x11];
1844         u8 reserved_at_20[0x8];
1845         u8 user_index[0x18];
1846         u8 reserved_at_40[0x8];
1847         u8 cqn[0x18];
1848         u8 reserved_at_60[0x8];
1849         u8 hairpin_peer_rq[0x18];
1850         u8 reserved_at_80[0x10];
1851         u8 hairpin_peer_vhca[0x10];
1852         u8 reserved_at_a0[0x50];
1853         u8 packet_pacing_rate_limit_index[0x10];
1854         u8 tis_lst_sz[0x10];
1855         u8 reserved_at_110[0x10];
1856         u8 reserved_at_120[0x40];
1857         u8 reserved_at_160[0x8];
1858         u8 tis_num_0[0x18];
1859         struct mlx5_ifc_wq_bits wq;
1860 };
1861
1862 struct mlx5_ifc_query_sq_in_bits {
1863         u8 opcode[0x10];
1864         u8 reserved_at_10[0x10];
1865         u8 reserved_at_20[0x10];
1866         u8 op_mod[0x10];
1867         u8 reserved_at_40[0x8];
1868         u8 sqn[0x18];
1869         u8 reserved_at_60[0x20];
1870 };
1871
1872 struct mlx5_ifc_modify_sq_out_bits {
1873         u8 status[0x8];
1874         u8 reserved_at_8[0x18];
1875         u8 syndrome[0x20];
1876         u8 reserved_at_40[0x40];
1877 };
1878
1879 struct mlx5_ifc_modify_sq_in_bits {
1880         u8 opcode[0x10];
1881         u8 uid[0x10];
1882         u8 reserved_at_20[0x10];
1883         u8 op_mod[0x10];
1884         u8 sq_state[0x4];
1885         u8 reserved_at_44[0x4];
1886         u8 sqn[0x18];
1887         u8 reserved_at_60[0x20];
1888         u8 modify_bitmask[0x40];
1889         u8 reserved_at_c0[0x40];
1890         struct mlx5_ifc_sqc_bits ctx;
1891 };
1892
1893 struct mlx5_ifc_create_sq_out_bits {
1894         u8 status[0x8];
1895         u8 reserved_at_8[0x18];
1896         u8 syndrome[0x20];
1897         u8 reserved_at_40[0x8];
1898         u8 sqn[0x18];
1899         u8 reserved_at_60[0x20];
1900 };
1901
1902 struct mlx5_ifc_create_sq_in_bits {
1903         u8 opcode[0x10];
1904         u8 uid[0x10];
1905         u8 reserved_at_20[0x10];
1906         u8 op_mod[0x10];
1907         u8 reserved_at_40[0xc0];
1908         struct mlx5_ifc_sqc_bits ctx;
1909 };
1910
1911 enum {
1912         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
1913         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
1914         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
1915         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
1916         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
1917 };
1918
1919 struct mlx5_ifc_flow_meter_parameters_bits {
1920         u8         valid[0x1];                  // 00h
1921         u8         bucket_overflow[0x1];
1922         u8         start_color[0x2];
1923         u8         both_buckets_on_green[0x1];
1924         u8         meter_mode[0x2];
1925         u8         reserved_at_1[0x19];
1926         u8         reserved_at_2[0x20]; //04h
1927         u8         reserved_at_3[0x3];
1928         u8         cbs_exponent[0x5];           // 08h
1929         u8         cbs_mantissa[0x8];
1930         u8         reserved_at_4[0x3];
1931         u8         cir_exponent[0x5];
1932         u8         cir_mantissa[0x8];
1933         u8         reserved_at_5[0x20];         // 0Ch
1934         u8         reserved_at_6[0x3];
1935         u8         ebs_exponent[0x5];           // 10h
1936         u8         ebs_mantissa[0x8];
1937         u8         reserved_at_7[0x3];
1938         u8         eir_exponent[0x5];
1939         u8         eir_mantissa[0x8];
1940         u8         reserved_at_8[0x60];         // 14h-1Ch
1941 };
1942
1943 struct mlx5_ifc_cqc_bits {
1944         u8 status[0x4];
1945         u8 as_notify[0x1];
1946         u8 initiator_src_dct[0x1];
1947         u8 dbr_umem_valid[0x1];
1948         u8 reserved_at_7[0x1];
1949         u8 cqe_sz[0x3];
1950         u8 cc[0x1];
1951         u8 reserved_at_c[0x1];
1952         u8 scqe_break_moderation_en[0x1];
1953         u8 oi[0x1];
1954         u8 cq_period_mode[0x2];
1955         u8 cqe_comp_en[0x1];
1956         u8 mini_cqe_res_format[0x2];
1957         u8 st[0x4];
1958         u8 reserved_at_18[0x8];
1959         u8 dbr_umem_id[0x20];
1960         u8 reserved_at_40[0x14];
1961         u8 page_offset[0x6];
1962         u8 reserved_at_5a[0x6];
1963         u8 reserved_at_60[0x3];
1964         u8 log_cq_size[0x5];
1965         u8 uar_page[0x18];
1966         u8 reserved_at_80[0x4];
1967         u8 cq_period[0xc];
1968         u8 cq_max_count[0x10];
1969         u8 reserved_at_a0[0x18];
1970         u8 c_eqn[0x8];
1971         u8 reserved_at_c0[0x3];
1972         u8 log_page_size[0x5];
1973         u8 reserved_at_c8[0x18];
1974         u8 reserved_at_e0[0x20];
1975         u8 reserved_at_100[0x8];
1976         u8 last_notified_index[0x18];
1977         u8 reserved_at_120[0x8];
1978         u8 last_solicit_index[0x18];
1979         u8 reserved_at_140[0x8];
1980         u8 consumer_counter[0x18];
1981         u8 reserved_at_160[0x8];
1982         u8 producer_counter[0x18];
1983         u8 local_partition_id[0xc];
1984         u8 process_id[0x14];
1985         u8 reserved_at_1A0[0x20];
1986         u8 dbr_addr[0x40];
1987 };
1988
1989 struct mlx5_ifc_create_cq_out_bits {
1990         u8 status[0x8];
1991         u8 reserved_at_8[0x18];
1992         u8 syndrome[0x20];
1993         u8 reserved_at_40[0x8];
1994         u8 cqn[0x18];
1995         u8 reserved_at_60[0x20];
1996 };
1997
1998 struct mlx5_ifc_create_cq_in_bits {
1999         u8 opcode[0x10];
2000         u8 uid[0x10];
2001         u8 reserved_at_20[0x10];
2002         u8 op_mod[0x10];
2003         u8 reserved_at_40[0x40];
2004         struct mlx5_ifc_cqc_bits cq_context;
2005         u8 cq_umem_offset[0x40];
2006         u8 cq_umem_id[0x20];
2007         u8 cq_umem_valid[0x1];
2008         u8 reserved_at_2e1[0x1f];
2009         u8 reserved_at_300[0x580];
2010         u8 pas[];
2011 };
2012
2013 enum {
2014         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2015         MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2016 };
2017
2018 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2019         u8 opcode[0x10];
2020         u8 reserved_at_10[0x20];
2021         u8 obj_type[0x10];
2022         u8 obj_id[0x20];
2023         u8 reserved_at_60[0x20];
2024 };
2025
2026 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2027         u8 status[0x8];
2028         u8 reserved_at_8[0x18];
2029         u8 syndrome[0x20];
2030         u8 obj_id[0x20];
2031         u8 reserved_at_60[0x20];
2032 };
2033
2034 struct mlx5_ifc_virtio_q_counters_bits {
2035         u8 modify_field_select[0x40];
2036         u8 reserved_at_40[0x40];
2037         u8 received_desc[0x40];
2038         u8 completed_desc[0x40];
2039         u8 error_cqes[0x20];
2040         u8 bad_desc_errors[0x20];
2041         u8 exceed_max_chain[0x20];
2042         u8 invalid_buffer[0x20];
2043         u8 reserved_at_180[0x50];
2044 };
2045
2046 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2047         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2048         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2049 };
2050
2051 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2052         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2053         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2054 };
2055 enum {
2056         MLX5_VIRTQ_STATE_INIT = 0,
2057         MLX5_VIRTQ_STATE_RDY = 1,
2058         MLX5_VIRTQ_STATE_SUSPEND = 2,
2059         MLX5_VIRTQ_STATE_ERROR = 3,
2060 };
2061
2062 enum {
2063         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2064         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2065         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2066 };
2067
2068 struct mlx5_ifc_virtio_q_bits {
2069         u8 virtio_q_type[0x8];
2070         u8 reserved_at_8[0x5];
2071         u8 event_mode[0x3];
2072         u8 queue_index[0x10];
2073         u8 full_emulation[0x1];
2074         u8 virtio_version_1_0[0x1];
2075         u8 reserved_at_22[0x2];
2076         u8 offload_type[0x4];
2077         u8 event_qpn_or_msix[0x18];
2078         u8 doorbell_stride_idx[0x10];
2079         u8 queue_size[0x10];
2080         u8 device_emulation_id[0x20];
2081         u8 desc_addr[0x40];
2082         u8 used_addr[0x40];
2083         u8 available_addr[0x40];
2084         u8 virtio_q_mkey[0x20];
2085         u8 reserved_at_160[0x20];
2086         u8 umem_1_id[0x20];
2087         u8 umem_1_size[0x20];
2088         u8 umem_1_offset[0x40];
2089         u8 umem_2_id[0x20];
2090         u8 umem_2_size[0x20];
2091         u8 umem_2_offset[0x40];
2092         u8 umem_3_id[0x20];
2093         u8 umem_3_size[0x20];
2094         u8 umem_3_offset[0x40];
2095         u8 counter_set_id[0x20];
2096         u8 reserved_at_320[0x8];
2097         u8 pd[0x18];
2098         u8 reserved_at_340[0xc0];
2099 };
2100
2101 struct mlx5_ifc_virtio_net_q_bits {
2102         u8 modify_field_select[0x40];
2103         u8 reserved_at_40[0x40];
2104         u8 tso_ipv4[0x1];
2105         u8 tso_ipv6[0x1];
2106         u8 tx_csum[0x1];
2107         u8 rx_csum[0x1];
2108         u8 reserved_at_84[0x6];
2109         u8 dirty_bitmap_dump_enable[0x1];
2110         u8 vhost_log_page[0x5];
2111         u8 reserved_at_90[0xc];
2112         u8 state[0x4];
2113         u8 error_type[0x8];
2114         u8 tisn_or_qpn[0x18];
2115         u8 dirty_bitmap_mkey[0x20];
2116         u8 dirty_bitmap_size[0x20];
2117         u8 dirty_bitmap_addr[0x40];
2118         u8 hw_available_index[0x10];
2119         u8 hw_used_index[0x10];
2120         u8 reserved_at_160[0xa0];
2121         struct mlx5_ifc_virtio_q_bits virtio_q_context;
2122 };
2123
2124 struct mlx5_ifc_create_virtq_in_bits {
2125         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2126         struct mlx5_ifc_virtio_net_q_bits virtq;
2127 };
2128
2129 struct mlx5_ifc_query_virtq_out_bits {
2130         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2131         struct mlx5_ifc_virtio_net_q_bits virtq;
2132 };
2133
2134 enum {
2135         MLX5_QP_ST_RC = 0x0,
2136 };
2137
2138 enum {
2139         MLX5_QP_PM_MIGRATED = 0x3,
2140 };
2141
2142 enum {
2143         MLX5_NON_ZERO_RQ = 0x0,
2144         MLX5_SRQ_RQ = 0x1,
2145         MLX5_CRQ_RQ = 0x2,
2146         MLX5_ZERO_LEN_RQ = 0x3,
2147 };
2148
2149 struct mlx5_ifc_ads_bits {
2150         u8 fl[0x1];
2151         u8 free_ar[0x1];
2152         u8 reserved_at_2[0xe];
2153         u8 pkey_index[0x10];
2154         u8 reserved_at_20[0x8];
2155         u8 grh[0x1];
2156         u8 mlid[0x7];
2157         u8 rlid[0x10];
2158         u8 ack_timeout[0x5];
2159         u8 reserved_at_45[0x3];
2160         u8 src_addr_index[0x8];
2161         u8 reserved_at_50[0x4];
2162         u8 stat_rate[0x4];
2163         u8 hop_limit[0x8];
2164         u8 reserved_at_60[0x4];
2165         u8 tclass[0x8];
2166         u8 flow_label[0x14];
2167         u8 rgid_rip[16][0x8];
2168         u8 reserved_at_100[0x4];
2169         u8 f_dscp[0x1];
2170         u8 f_ecn[0x1];
2171         u8 reserved_at_106[0x1];
2172         u8 f_eth_prio[0x1];
2173         u8 ecn[0x2];
2174         u8 dscp[0x6];
2175         u8 udp_sport[0x10];
2176         u8 dei_cfi[0x1];
2177         u8 eth_prio[0x3];
2178         u8 sl[0x4];
2179         u8 vhca_port_num[0x8];
2180         u8 rmac_47_32[0x10];
2181         u8 rmac_31_0[0x20];
2182 };
2183
2184 struct mlx5_ifc_qpc_bits {
2185         u8 state[0x4];
2186         u8 lag_tx_port_affinity[0x4];
2187         u8 st[0x8];
2188         u8 reserved_at_10[0x3];
2189         u8 pm_state[0x2];
2190         u8 reserved_at_15[0x1];
2191         u8 req_e2e_credit_mode[0x2];
2192         u8 offload_type[0x4];
2193         u8 end_padding_mode[0x2];
2194         u8 reserved_at_1e[0x2];
2195         u8 wq_signature[0x1];
2196         u8 block_lb_mc[0x1];
2197         u8 atomic_like_write_en[0x1];
2198         u8 latency_sensitive[0x1];
2199         u8 reserved_at_24[0x1];
2200         u8 drain_sigerr[0x1];
2201         u8 reserved_at_26[0x2];
2202         u8 pd[0x18];
2203         u8 mtu[0x3];
2204         u8 log_msg_max[0x5];
2205         u8 reserved_at_48[0x1];
2206         u8 log_rq_size[0x4];
2207         u8 log_rq_stride[0x3];
2208         u8 no_sq[0x1];
2209         u8 log_sq_size[0x4];
2210         u8 reserved_at_55[0x6];
2211         u8 rlky[0x1];
2212         u8 ulp_stateless_offload_mode[0x4];
2213         u8 counter_set_id[0x8];
2214         u8 uar_page[0x18];
2215         u8 reserved_at_80[0x8];
2216         u8 user_index[0x18];
2217         u8 reserved_at_a0[0x3];
2218         u8 log_page_size[0x5];
2219         u8 remote_qpn[0x18];
2220         struct mlx5_ifc_ads_bits primary_address_path;
2221         struct mlx5_ifc_ads_bits secondary_address_path;
2222         u8 log_ack_req_freq[0x4];
2223         u8 reserved_at_384[0x4];
2224         u8 log_sra_max[0x3];
2225         u8 reserved_at_38b[0x2];
2226         u8 retry_count[0x3];
2227         u8 rnr_retry[0x3];
2228         u8 reserved_at_393[0x1];
2229         u8 fre[0x1];
2230         u8 cur_rnr_retry[0x3];
2231         u8 cur_retry_count[0x3];
2232         u8 reserved_at_39b[0x5];
2233         u8 reserved_at_3a0[0x20];
2234         u8 reserved_at_3c0[0x8];
2235         u8 next_send_psn[0x18];
2236         u8 reserved_at_3e0[0x8];
2237         u8 cqn_snd[0x18];
2238         u8 reserved_at_400[0x8];
2239         u8 deth_sqpn[0x18];
2240         u8 reserved_at_420[0x20];
2241         u8 reserved_at_440[0x8];
2242         u8 last_acked_psn[0x18];
2243         u8 reserved_at_460[0x8];
2244         u8 ssn[0x18];
2245         u8 reserved_at_480[0x8];
2246         u8 log_rra_max[0x3];
2247         u8 reserved_at_48b[0x1];
2248         u8 atomic_mode[0x4];
2249         u8 rre[0x1];
2250         u8 rwe[0x1];
2251         u8 rae[0x1];
2252         u8 reserved_at_493[0x1];
2253         u8 page_offset[0x6];
2254         u8 reserved_at_49a[0x3];
2255         u8 cd_slave_receive[0x1];
2256         u8 cd_slave_send[0x1];
2257         u8 cd_master[0x1];
2258         u8 reserved_at_4a0[0x3];
2259         u8 min_rnr_nak[0x5];
2260         u8 next_rcv_psn[0x18];
2261         u8 reserved_at_4c0[0x8];
2262         u8 xrcd[0x18];
2263         u8 reserved_at_4e0[0x8];
2264         u8 cqn_rcv[0x18];
2265         u8 dbr_addr[0x40];
2266         u8 q_key[0x20];
2267         u8 reserved_at_560[0x5];
2268         u8 rq_type[0x3];
2269         u8 srqn_rmpn_xrqn[0x18];
2270         u8 reserved_at_580[0x8];
2271         u8 rmsn[0x18];
2272         u8 hw_sq_wqebb_counter[0x10];
2273         u8 sw_sq_wqebb_counter[0x10];
2274         u8 hw_rq_counter[0x20];
2275         u8 sw_rq_counter[0x20];
2276         u8 reserved_at_600[0x20];
2277         u8 reserved_at_620[0xf];
2278         u8 cgs[0x1];
2279         u8 cs_req[0x8];
2280         u8 cs_res[0x8];
2281         u8 dc_access_key[0x40];
2282         u8 reserved_at_680[0x3];
2283         u8 dbr_umem_valid[0x1];
2284         u8 reserved_at_684[0x9c];
2285         u8 dbr_umem_id[0x20];
2286 };
2287
2288 struct mlx5_ifc_create_qp_out_bits {
2289         u8 status[0x8];
2290         u8 reserved_at_8[0x18];
2291         u8 syndrome[0x20];
2292         u8 reserved_at_40[0x8];
2293         u8 qpn[0x18];
2294         u8 reserved_at_60[0x20];
2295 };
2296
2297 #ifdef PEDANTIC
2298 #pragma GCC diagnostic ignored "-Wpedantic"
2299 #endif
2300 struct mlx5_ifc_create_qp_in_bits {
2301         u8 opcode[0x10];
2302         u8 uid[0x10];
2303         u8 reserved_at_20[0x10];
2304         u8 op_mod[0x10];
2305         u8 reserved_at_40[0x40];
2306         u8 opt_param_mask[0x20];
2307         u8 reserved_at_a0[0x20];
2308         struct mlx5_ifc_qpc_bits qpc;
2309         u8 wq_umem_offset[0x40];
2310         u8 wq_umem_id[0x20];
2311         u8 wq_umem_valid[0x1];
2312         u8 reserved_at_861[0x1f];
2313         u8 pas[0][0x40];
2314 };
2315 #ifdef PEDANTIC
2316 #pragma GCC diagnostic error "-Wpedantic"
2317 #endif
2318
2319 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2320         u8 status[0x8];
2321         u8 reserved_at_8[0x18];
2322         u8 syndrome[0x20];
2323         u8 reserved_at_40[0x40];
2324 };
2325
2326 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2327         u8 opcode[0x10];
2328         u8 uid[0x10];
2329         u8 reserved_at_20[0x10];
2330         u8 op_mod[0x10];
2331         u8 reserved_at_40[0x8];
2332         u8 qpn[0x18];
2333         u8 reserved_at_60[0x20];
2334         u8 opt_param_mask[0x20];
2335         u8 reserved_at_a0[0x20];
2336         struct mlx5_ifc_qpc_bits qpc;
2337         u8 reserved_at_800[0x80];
2338 };
2339
2340 struct mlx5_ifc_sqd2rts_qp_out_bits {
2341         u8 status[0x8];
2342         u8 reserved_at_8[0x18];
2343         u8 syndrome[0x20];
2344         u8 reserved_at_40[0x40];
2345 };
2346
2347 struct mlx5_ifc_sqd2rts_qp_in_bits {
2348         u8 opcode[0x10];
2349         u8 uid[0x10];
2350         u8 reserved_at_20[0x10];
2351         u8 op_mod[0x10];
2352         u8 reserved_at_40[0x8];
2353         u8 qpn[0x18];
2354         u8 reserved_at_60[0x20];
2355         u8 opt_param_mask[0x20];
2356         u8 reserved_at_a0[0x20];
2357         struct mlx5_ifc_qpc_bits qpc;
2358         u8 reserved_at_800[0x80];
2359 };
2360
2361 struct mlx5_ifc_rts2rts_qp_out_bits {
2362         u8 status[0x8];
2363         u8 reserved_at_8[0x18];
2364         u8 syndrome[0x20];
2365         u8 reserved_at_40[0x40];
2366 };
2367
2368 struct mlx5_ifc_rts2rts_qp_in_bits {
2369         u8 opcode[0x10];
2370         u8 uid[0x10];
2371         u8 reserved_at_20[0x10];
2372         u8 op_mod[0x10];
2373         u8 reserved_at_40[0x8];
2374         u8 qpn[0x18];
2375         u8 reserved_at_60[0x20];
2376         u8 opt_param_mask[0x20];
2377         u8 reserved_at_a0[0x20];
2378         struct mlx5_ifc_qpc_bits qpc;
2379         u8 reserved_at_800[0x80];
2380 };
2381
2382 struct mlx5_ifc_rtr2rts_qp_out_bits {
2383         u8 status[0x8];
2384         u8 reserved_at_8[0x18];
2385         u8 syndrome[0x20];
2386         u8 reserved_at_40[0x40];
2387 };
2388
2389 struct mlx5_ifc_rtr2rts_qp_in_bits {
2390         u8 opcode[0x10];
2391         u8 uid[0x10];
2392         u8 reserved_at_20[0x10];
2393         u8 op_mod[0x10];
2394         u8 reserved_at_40[0x8];
2395         u8 qpn[0x18];
2396         u8 reserved_at_60[0x20];
2397         u8 opt_param_mask[0x20];
2398         u8 reserved_at_a0[0x20];
2399         struct mlx5_ifc_qpc_bits qpc;
2400         u8 reserved_at_800[0x80];
2401 };
2402
2403 struct mlx5_ifc_rst2init_qp_out_bits {
2404         u8 status[0x8];
2405         u8 reserved_at_8[0x18];
2406         u8 syndrome[0x20];
2407         u8 reserved_at_40[0x40];
2408 };
2409
2410 struct mlx5_ifc_rst2init_qp_in_bits {
2411         u8 opcode[0x10];
2412         u8 uid[0x10];
2413         u8 reserved_at_20[0x10];
2414         u8 op_mod[0x10];
2415         u8 reserved_at_40[0x8];
2416         u8 qpn[0x18];
2417         u8 reserved_at_60[0x20];
2418         u8 opt_param_mask[0x20];
2419         u8 reserved_at_a0[0x20];
2420         struct mlx5_ifc_qpc_bits qpc;
2421         u8 reserved_at_800[0x80];
2422 };
2423
2424 struct mlx5_ifc_init2rtr_qp_out_bits {
2425         u8 status[0x8];
2426         u8 reserved_at_8[0x18];
2427         u8 syndrome[0x20];
2428         u8 reserved_at_40[0x40];
2429 };
2430
2431 struct mlx5_ifc_init2rtr_qp_in_bits {
2432         u8 opcode[0x10];
2433         u8 uid[0x10];
2434         u8 reserved_at_20[0x10];
2435         u8 op_mod[0x10];
2436         u8 reserved_at_40[0x8];
2437         u8 qpn[0x18];
2438         u8 reserved_at_60[0x20];
2439         u8 opt_param_mask[0x20];
2440         u8 reserved_at_a0[0x20];
2441         struct mlx5_ifc_qpc_bits qpc;
2442         u8 reserved_at_800[0x80];
2443 };
2444
2445 struct mlx5_ifc_init2init_qp_out_bits {
2446         u8 status[0x8];
2447         u8 reserved_at_8[0x18];
2448         u8 syndrome[0x20];
2449         u8 reserved_at_40[0x40];
2450 };
2451
2452 struct mlx5_ifc_init2init_qp_in_bits {
2453         u8 opcode[0x10];
2454         u8 uid[0x10];
2455         u8 reserved_at_20[0x10];
2456         u8 op_mod[0x10];
2457         u8 reserved_at_40[0x8];
2458         u8 qpn[0x18];
2459         u8 reserved_at_60[0x20];
2460         u8 opt_param_mask[0x20];
2461         u8 reserved_at_a0[0x20];
2462         struct mlx5_ifc_qpc_bits qpc;
2463         u8 reserved_at_800[0x80];
2464 };
2465
2466 #ifdef PEDANTIC
2467 #pragma GCC diagnostic ignored "-Wpedantic"
2468 #endif
2469 struct mlx5_ifc_query_qp_out_bits {
2470         u8 status[0x8];
2471         u8 reserved_at_8[0x18];
2472         u8 syndrome[0x20];
2473         u8 reserved_at_40[0x40];
2474         u8 opt_param_mask[0x20];
2475         u8 reserved_at_a0[0x20];
2476         struct mlx5_ifc_qpc_bits qpc;
2477         u8 reserved_at_800[0x80];
2478         u8 pas[0][0x40];
2479 };
2480 #ifdef PEDANTIC
2481 #pragma GCC diagnostic error "-Wpedantic"
2482 #endif
2483
2484 struct mlx5_ifc_query_qp_in_bits {
2485         u8 opcode[0x10];
2486         u8 reserved_at_10[0x10];
2487         u8 reserved_at_20[0x10];
2488         u8 op_mod[0x10];
2489         u8 reserved_at_40[0x8];
2490         u8 qpn[0x18];
2491         u8 reserved_at_60[0x20];
2492 };
2493
2494 /* CQE format mask. */
2495 #define MLX5E_CQE_FORMAT_MASK 0xc
2496
2497 /* MPW opcode. */
2498 #define MLX5_OPC_MOD_MPW 0x01
2499
2500 /* Compressed Rx CQE structure. */
2501 struct mlx5_mini_cqe8 {
2502         union {
2503                 uint32_t rx_hash_result;
2504                 struct {
2505                         uint16_t checksum;
2506                         uint16_t stride_idx;
2507                 };
2508                 struct {
2509                         uint16_t wqe_counter;
2510                         uint8_t  s_wqe_opcode;
2511                         uint8_t  reserved;
2512                 } s_wqe_info;
2513         };
2514         uint32_t byte_cnt;
2515 };
2516
2517 /* srTCM PRM flow meter parameters. */
2518 enum {
2519         MLX5_FLOW_COLOR_RED = 0,
2520         MLX5_FLOW_COLOR_YELLOW,
2521         MLX5_FLOW_COLOR_GREEN,
2522         MLX5_FLOW_COLOR_UNDEFINED,
2523 };
2524
2525 /* Maximum value of srTCM metering parameters. */
2526 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
2527 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
2528 #define MLX5_SRTCM_EBS_MAX 0
2529
2530 /* The bits meter color use. */
2531 #define MLX5_MTR_COLOR_BITS 8
2532
2533 /**
2534  * Convert a user mark to flow mark.
2535  *
2536  * @param val
2537  *   Mark value to convert.
2538  *
2539  * @return
2540  *   Converted mark value.
2541  */
2542 static inline uint32_t
2543 mlx5_flow_mark_set(uint32_t val)
2544 {
2545         uint32_t ret;
2546
2547         /*
2548          * Add one to the user value to differentiate un-marked flows from
2549          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
2550          * remains untouched.
2551          */
2552         if (val != MLX5_FLOW_MARK_DEFAULT)
2553                 ++val;
2554 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2555         /*
2556          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
2557          * word, byte-swapped by the kernel on little-endian systems. In this
2558          * case, left-shifting the resulting big-endian value ensures the
2559          * least significant 24 bits are retained when converting it back.
2560          */
2561         ret = rte_cpu_to_be_32(val) >> 8;
2562 #else
2563         ret = val;
2564 #endif
2565         return ret;
2566 }
2567
2568 /**
2569  * Convert a mark to user mark.
2570  *
2571  * @param val
2572  *   Mark value to convert.
2573  *
2574  * @return
2575  *   Converted mark value.
2576  */
2577 static inline uint32_t
2578 mlx5_flow_mark_get(uint32_t val)
2579 {
2580         /*
2581          * Subtract one from the retrieved value. It was added by
2582          * mlx5_flow_mark_set() to distinguish unmarked flows.
2583          */
2584 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2585         return (val >> 8) - 1;
2586 #else
2587         return val - 1;
2588 #endif
2589 }
2590
2591 #endif /* RTE_PMD_MLX5_PRM_H_ */