drivers/common/mlx5/mlx5_prm.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #ifndef RTE_PMD_MLX5_PRM_H_
   7 #define RTE_PMD_MLX5_PRM_H_
   8
   9 #include <unistd.h>
  10
  11 #include <rte_vect.h>
  12 #include <rte_byteorder.h>
  13
  14 #include <mlx5_glue.h>
  15 #include "mlx5_autoconf.h"
  16
  17 /* RSS hash key size. */
  18 #define MLX5_RSS_HASH_KEY_LEN 40
  19
  20 /* Get CQE owner bit. */
  21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
  22
  23 /* Get CQE format. */
  24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
  25
  26 /* Get CQE opcode. */
  27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
  28
  29 /* Get CQE solicited event. */
  30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
  31
  32 /* Invalidate a CQE. */
  33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
  34
  35 /* Hardware index widths. */
  36 #define MLX5_CQ_INDEX_WIDTH 24
  37 #define MLX5_WQ_INDEX_WIDTH 16
  38
  39 /* WQE Segment sizes in bytes. */
  40 #define MLX5_WSEG_SIZE 16u
  41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
  42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
  43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
  44
  45 /* WQE/WQEBB size in bytes. */
  46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
  47
  48 /*
  49  * Max size of a WQE session.
  50  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
  51  * the WQE size field in Control Segment is 6 bits wide.
  52  */
  53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
  54
  55 /*
  56  * Default minimum number of Tx queues for inlining packets.
  57  * If there are less queues as specified we assume we have
  58  * no enough CPU resources (cycles) to perform inlining,
  59  * the PCIe throughput is not supposed as bottleneck and
  60  * inlining is disabled.
  61  */
  62 #define MLX5_INLINE_MAX_TXQS 8u
  63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
  64
  65 /*
  66  * Default packet length threshold to be inlined with
  67  * enhanced MPW. If packet length exceeds the threshold
  68  * the data are not inlined. Should be aligned in WQEBB
  69  * boundary with accounting the title Control and Ethernet
  70  * segments.
  71  */
  72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
  73                                   MLX5_DSEG_MIN_INLINE_SIZE)
  74 /*
  75  * Maximal inline data length sent with enhanced MPW.
  76  * Is based on maximal WQE size.
  77  */
  78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
  79                                   MLX5_WQE_CSEG_SIZE - \
  80                                   MLX5_WQE_ESEG_SIZE - \
  81                                   MLX5_WQE_DSEG_SIZE + \
  82                                   MLX5_DSEG_MIN_INLINE_SIZE)
  83 /*
  84  * Minimal amount of packets to be sent with EMPW.
  85  * This limits the minimal required size of sent EMPW.
  86  * If there are no enough resources to built minimal
  87  * EMPW the sending loop exits.
  88  */
  89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
  90 /*
  91  * Maximal amount of packets to be sent with EMPW.
  92  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
  93  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
  94  * without CQE generation request, being multiplied by
  95  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
  96  * in tx burst routine at the moment of freeing multiple mbufs.
  97  */
  98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
  99 #define MLX5_MPW_MAX_PACKETS 6
 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
 101
 102 /*
 103  * Default packet length threshold to be inlined with
 104  * ordinary SEND. Inlining saves the MR key search
 105  * and extra PCIe data fetch transaction, but eats the
 106  * CPU cycles.
 107  */
 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
 109                                   MLX5_ESEG_MIN_INLINE_SIZE - \
 110                                   MLX5_WQE_CSEG_SIZE - \
 111                                   MLX5_WQE_ESEG_SIZE - \
 112                                   MLX5_WQE_DSEG_SIZE)
 113 /*
 114  * Maximal inline data length sent with ordinary SEND.
 115  * Is based on maximal WQE size.
 116  */
 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
 118                                   MLX5_WQE_CSEG_SIZE - \
 119                                   MLX5_WQE_ESEG_SIZE - \
 120                                   MLX5_WQE_DSEG_SIZE + \
 121                                   MLX5_ESEG_MIN_INLINE_SIZE)
 122
 123 /* Missed in mlv5dv.h, should define here. */
 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 126 #endif
 127
 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
 129 #define MLX5_OPCODE_SEND_EN 0x17u
 130 #endif
 131
 132 #ifndef HAVE_MLX5_OPCODE_WAIT
 133 #define MLX5_OPCODE_WAIT 0x0fu
 134 #endif
 135
 136 /* CQE value to inform that VLAN is stripped. */
 137 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 138
 139 /* IPv4 options. */
 140 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
 141
 142 /* IPv6 packet. */
 143 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
 144
 145 /* IPv4 packet. */
 146 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
 147
 148 /* TCP packet. */
 149 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
 150
 151 /* UDP packet. */
 152 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
 153
 154 /* IP is fragmented. */
 155 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
 156
 157 /* L2 header is valid. */
 158 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
 159
 160 /* L3 header is valid. */
 161 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
 162
 163 /* L4 header is valid. */
 164 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
 165
 166 /* Outer packet, 0 IPv4, 1 IPv6. */
 167 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
 168
 169 /* Tunnel packet bit in the CQE. */
 170 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 171
 172 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
 173 #define MLX5_CQE_LRO_PUSH_MASK 0x40
 174
 175 /* Mask for L4 type in the CQE hdr_type_etc field. */
 176 #define MLX5_CQE_L4_TYPE_MASK 0x70
 177
 178 /* The bit index of L4 type in CQE hdr_type_etc field. */
 179 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
 180
 181 /* L4 type to indicate TCP packet without acknowledgment. */
 182 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
 183
 184 /* L4 type to indicate TCP packet with acknowledgment. */
 185 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
 186
 187 /* Inner L3 checksum offload (Tunneled packets only). */
 188 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 189
 190 /* Inner L4 checksum offload (Tunneled packets only). */
 191 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
 192
 193 /* Outer L4 type is TCP. */
 194 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
 195
 196 /* Outer L4 type is UDP. */
 197 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
 198
 199 /* Outer L3 type is IPV4. */
 200 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
 201
 202 /* Outer L3 type is IPV6. */
 203 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
 204
 205 /* Inner L4 type is TCP. */
 206 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
 207
 208 /* Inner L4 type is UDP. */
 209 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
 210
 211 /* Inner L3 type is IPV4. */
 212 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
 213
 214 /* Inner L3 type is IPV6. */
 215 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
 216
 217 /* VLAN insertion flag. */
 218 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
 219
 220 /* Data inline segment flag. */
 221 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
 222
 223 /* Is flow mark valid. */
 224 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 225 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
 226 #else
 227 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
 228 #endif
 229
 230 /* INVALID is used by packets matching no flow rules. */
 231 #define MLX5_FLOW_MARK_INVALID 0
 232
 233 /* Maximum allowed value to mark a packet. */
 234 #define MLX5_FLOW_MARK_MAX 0xfffff0
 235
 236 /* Default mark value used when none is provided. */
 237 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
 238
 239 /* Default mark mask for metadata legacy mode. */
 240 #define MLX5_FLOW_MARK_MASK 0xffffff
 241
 242 /* Byte length mask when mark is enable in miniCQE */
 243 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
 244
 245 /* Maximum number of DS in WQE. Limited by 6-bit field. */
 246 #define MLX5_DSEG_MAX 63
 247
 248 /* The completion mode offset in the WQE control segment line 2. */
 249 #define MLX5_COMP_MODE_OFFSET 2
 250
 251 /* Amount of data bytes in minimal inline data segment. */
 252 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
 253
 254 /* Amount of data bytes in minimal inline eth segment. */
 255 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
 256
 257 /* Amount of data bytes after eth data segment. */
 258 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 259
 260 /* The maximum log value of segments per RQ WQE. */
 261 #define MLX5_MAX_LOG_RQ_SEGS 5u
 262
 263 /* The alignment needed for WQ buffer. */
 264 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
 265
 266 /* The alignment needed for CQ buffer. */
 267 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
 268
 269 /* Completion mode. */
 270 enum mlx5_completion_mode {
 271         MLX5_COMP_ONLY_ERR = 0x0,
 272         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
 273         MLX5_COMP_ALWAYS = 0x2,
 274         MLX5_COMP_CQE_AND_EQE = 0x3,
 275 };
 276
 277 /* MPW mode. */
 278 enum mlx5_mpw_mode {
 279         MLX5_MPW_DISABLED,
 280         MLX5_MPW,
 281         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
 282 };
 283
 284 /* WQE Control segment. */
 285 struct mlx5_wqe_cseg {
 286         uint32_t opcode;
 287         uint32_t sq_ds;
 288         uint32_t flags;
 289         uint32_t misc;
 290 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 291
 292 /* Header of data segment. Minimal size Data Segment */
 293 struct mlx5_wqe_dseg {
 294         uint32_t bcount;
 295         union {
 296                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
 297                 struct {
 298                         uint32_t lkey;
 299                         uint64_t pbuf;
 300                 } __rte_packed;
 301         };
 302 } __rte_packed;
 303
 304 /* Subset of struct WQE Ethernet Segment. */
 305 struct mlx5_wqe_eseg {
 306         union {
 307                 struct {
 308                         uint32_t swp_offs;
 309                         uint8_t cs_flags;
 310                         uint8_t swp_flags;
 311                         uint16_t mss;
 312                         uint32_t metadata;
 313                         uint16_t inline_hdr_sz;
 314                         union {
 315                                 uint16_t inline_data;
 316                                 uint16_t vlan_tag;
 317                         };
 318                 } __rte_packed;
 319                 struct {
 320                         uint32_t offsets;
 321                         uint32_t flags;
 322                         uint32_t flow_metadata;
 323                         uint32_t inline_hdr;
 324                 } __rte_packed;
 325         };
 326 } __rte_packed;
 327
 328 struct mlx5_wqe_qseg {
 329         uint32_t reserved0;
 330         uint32_t reserved1;
 331         uint32_t max_index;
 332         uint32_t qpn_cqn;
 333 } __rte_packed;
 334
 335 /* The title WQEBB, header of WQE. */
 336 struct mlx5_wqe {
 337         union {
 338                 struct mlx5_wqe_cseg cseg;
 339                 uint32_t ctrl[4];
 340         };
 341         struct mlx5_wqe_eseg eseg;
 342         union {
 343                 struct mlx5_wqe_dseg dseg[2];
 344                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
 345         };
 346 } __rte_packed;
 347
 348 /* WQE for Multi-Packet RQ. */
 349 struct mlx5_wqe_mprq {
 350         struct mlx5_wqe_srq_next_seg next_seg;
 351         struct mlx5_wqe_data_seg dseg;
 352 };
 353
 354 #define MLX5_MPRQ_LEN_MASK 0x000ffff
 355 #define MLX5_MPRQ_LEN_SHIFT 0
 356 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
 357 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
 358 #define MLX5_MPRQ_FILLER_MASK 0x80000000
 359 #define MLX5_MPRQ_FILLER_SHIFT 31
 360
 361 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
 362
 363 /* CQ element structure - should be equal to the cache line size */
 364 struct mlx5_cqe {
 365 #if (RTE_CACHE_LINE_SIZE == 128)
 366         uint8_t padding[64];
 367 #endif
 368         uint8_t pkt_info;
 369         uint8_t rsvd0;
 370         uint16_t wqe_id;
 371         uint8_t lro_tcppsh_abort_dupack;
 372         uint8_t lro_min_ttl;
 373         uint16_t lro_tcp_win;
 374         uint32_t lro_ack_seq_num;
 375         uint32_t rx_hash_res;
 376         uint8_t rx_hash_type;
 377         uint8_t rsvd1[3];
 378         uint16_t csum;
 379         uint8_t rsvd2[6];
 380         uint16_t hdr_type_etc;
 381         uint16_t vlan_info;
 382         uint8_t lro_num_seg;
 383         uint8_t rsvd3[3];
 384         uint32_t flow_table_metadata;
 385         uint8_t rsvd4[4];
 386         uint32_t byte_cnt;
 387         uint64_t timestamp;
 388         uint32_t sop_drop_qpn;
 389         uint16_t wqe_counter;
 390         uint8_t rsvd5;
 391         uint8_t op_own;
 392 };
 393
 394 struct mlx5_cqe_ts {
 395         uint64_t timestamp;
 396         uint32_t sop_drop_qpn;
 397         uint16_t wqe_counter;
 398         uint8_t rsvd5;
 399         uint8_t op_own;
 400 };
 401
 402 /* MMO metadata segment */
 403
 404 #define MLX5_OPCODE_MMO 0x2f
 405 #define MLX5_OPC_MOD_MMO_REGEX 0x4
 406
 407 struct mlx5_wqe_metadata_seg {
 408         uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
 409         uint32_t lkey;
 410         uint64_t addr;
 411 };
 412
 413 struct mlx5_ifc_regexp_mmo_control_bits {
 414         uint8_t reserved_at_31[0x2];
 415         uint8_t le[0x1];
 416         uint8_t reserved_at_28[0x1];
 417         uint8_t subset_id_0[0xc];
 418         uint8_t reserved_at_16[0x4];
 419         uint8_t subset_id_1[0xc];
 420         uint8_t ctrl[0x4];
 421         uint8_t subset_id_2[0xc];
 422         uint8_t reserved_at_16_1[0x4];
 423         uint8_t subset_id_3[0xc];
 424 };
 425
 426 struct mlx5_ifc_regexp_metadata_bits {
 427         uint8_t rof_version[0x10];
 428         uint8_t latency_count[0x10];
 429         uint8_t instruction_count[0x10];
 430         uint8_t primary_thread_count[0x10];
 431         uint8_t match_count[0x8];
 432         uint8_t detected_match_count[0x8];
 433         uint8_t status[0x10];
 434         uint8_t job_id[0x20];
 435         uint8_t reserved[0x80];
 436 };
 437
 438 struct mlx5_ifc_regexp_match_tuple_bits {
 439         uint8_t length[0x10];
 440         uint8_t start_ptr[0x10];
 441         uint8_t rule_id[0x20];
 442 };
 443
 444 /* Adding direct verbs to data-path. */
 445
 446 /* CQ sequence number mask. */
 447 #define MLX5_CQ_SQN_MASK 0x3
 448
 449 /* CQ sequence number index. */
 450 #define MLX5_CQ_SQN_OFFSET 28
 451
 452 /* CQ doorbell index mask. */
 453 #define MLX5_CI_MASK 0xffffff
 454
 455 /* CQ doorbell offset. */
 456 #define MLX5_CQ_ARM_DB 1
 457
 458 /* CQ doorbell offset*/
 459 #define MLX5_CQ_DOORBELL 0x20
 460
 461 /* CQE format value. */
 462 #define MLX5_COMPRESSED 0x3
 463
 464 /* CQ doorbell cmd types. */
 465 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
 466 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
 467
 468 /* Action type of header modification. */
 469 enum {
 470         MLX5_MODIFICATION_TYPE_SET = 0x1,
 471         MLX5_MODIFICATION_TYPE_ADD = 0x2,
 472         MLX5_MODIFICATION_TYPE_COPY = 0x3,
 473 };
 474
 475 /* The field of packet to be modified. */
 476 enum mlx5_modification_field {
 477         MLX5_MODI_OUT_NONE = -1,
 478         MLX5_MODI_OUT_SMAC_47_16 = 1,
 479         MLX5_MODI_OUT_SMAC_15_0,
 480         MLX5_MODI_OUT_ETHERTYPE,
 481         MLX5_MODI_OUT_DMAC_47_16,
 482         MLX5_MODI_OUT_DMAC_15_0,
 483         MLX5_MODI_OUT_IP_DSCP,
 484         MLX5_MODI_OUT_TCP_FLAGS,
 485         MLX5_MODI_OUT_TCP_SPORT,
 486         MLX5_MODI_OUT_TCP_DPORT,
 487         MLX5_MODI_OUT_IPV4_TTL,
 488         MLX5_MODI_OUT_UDP_SPORT,
 489         MLX5_MODI_OUT_UDP_DPORT,
 490         MLX5_MODI_OUT_SIPV6_127_96,
 491         MLX5_MODI_OUT_SIPV6_95_64,
 492         MLX5_MODI_OUT_SIPV6_63_32,
 493         MLX5_MODI_OUT_SIPV6_31_0,
 494         MLX5_MODI_OUT_DIPV6_127_96,
 495         MLX5_MODI_OUT_DIPV6_95_64,
 496         MLX5_MODI_OUT_DIPV6_63_32,
 497         MLX5_MODI_OUT_DIPV6_31_0,
 498         MLX5_MODI_OUT_SIPV4,
 499         MLX5_MODI_OUT_DIPV4,
 500         MLX5_MODI_OUT_FIRST_VID,
 501         MLX5_MODI_IN_SMAC_47_16 = 0x31,
 502         MLX5_MODI_IN_SMAC_15_0,
 503         MLX5_MODI_IN_ETHERTYPE,
 504         MLX5_MODI_IN_DMAC_47_16,
 505         MLX5_MODI_IN_DMAC_15_0,
 506         MLX5_MODI_IN_IP_DSCP,
 507         MLX5_MODI_IN_TCP_FLAGS,
 508         MLX5_MODI_IN_TCP_SPORT,
 509         MLX5_MODI_IN_TCP_DPORT,
 510         MLX5_MODI_IN_IPV4_TTL,
 511         MLX5_MODI_IN_UDP_SPORT,
 512         MLX5_MODI_IN_UDP_DPORT,
 513         MLX5_MODI_IN_SIPV6_127_96,
 514         MLX5_MODI_IN_SIPV6_95_64,
 515         MLX5_MODI_IN_SIPV6_63_32,
 516         MLX5_MODI_IN_SIPV6_31_0,
 517         MLX5_MODI_IN_DIPV6_127_96,
 518         MLX5_MODI_IN_DIPV6_95_64,
 519         MLX5_MODI_IN_DIPV6_63_32,
 520         MLX5_MODI_IN_DIPV6_31_0,
 521         MLX5_MODI_IN_SIPV4,
 522         MLX5_MODI_IN_DIPV4,
 523         MLX5_MODI_OUT_IPV6_HOPLIMIT,
 524         MLX5_MODI_IN_IPV6_HOPLIMIT,
 525         MLX5_MODI_META_DATA_REG_A,
 526         MLX5_MODI_META_DATA_REG_B = 0x50,
 527         MLX5_MODI_META_REG_C_0,
 528         MLX5_MODI_META_REG_C_1,
 529         MLX5_MODI_META_REG_C_2,
 530         MLX5_MODI_META_REG_C_3,
 531         MLX5_MODI_META_REG_C_4,
 532         MLX5_MODI_META_REG_C_5,
 533         MLX5_MODI_META_REG_C_6,
 534         MLX5_MODI_META_REG_C_7,
 535         MLX5_MODI_OUT_TCP_SEQ_NUM,
 536         MLX5_MODI_IN_TCP_SEQ_NUM,
 537         MLX5_MODI_OUT_TCP_ACK_NUM,
 538         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 539 };
 540
 541 /* Total number of metadata reg_c's. */
 542 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
 543
 544 enum modify_reg {
 545         REG_NON = 0,
 546         REG_A,
 547         REG_B,
 548         REG_C_0,
 549         REG_C_1,
 550         REG_C_2,
 551         REG_C_3,
 552         REG_C_4,
 553         REG_C_5,
 554         REG_C_6,
 555         REG_C_7,
 556 };
 557
 558 /* Modification sub command. */
 559 struct mlx5_modification_cmd {
 560         union {
 561                 uint32_t data0;
 562                 struct {
 563                         unsigned int length:5;
 564                         unsigned int rsvd0:3;
 565                         unsigned int offset:5;
 566                         unsigned int rsvd1:3;
 567                         unsigned int field:12;
 568                         unsigned int action_type:4;
 569                 };
 570         };
 571         union {
 572                 uint32_t data1;
 573                 uint8_t data[4];
 574                 struct {
 575                         unsigned int rsvd2:8;
 576                         unsigned int dst_offset:5;
 577                         unsigned int rsvd3:3;
 578                         unsigned int dst_field:12;
 579                         unsigned int rsvd4:4;
 580                 };
 581         };
 582 };
 583
 584 typedef uint32_t u32;
 585 typedef uint16_t u16;
 586 typedef uint8_t u8;
 587
 588 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 589 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
 590 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
 591                                   (&(__mlx5_nullp(typ)->fld)))
 592 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 593                                     (__mlx5_bit_off(typ, fld) & 0x1f))
 594 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
 595 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
 596 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
 597                                   __mlx5_dw_bit_off(typ, fld))
 598 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 599 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
 600 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
 601                                     (__mlx5_bit_off(typ, fld) & 0xf))
 602 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 603 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
 604                                   __mlx5_16_bit_off(typ, fld))
 605 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 606 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
 607 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 608 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 609
 610 /* insert a value to a struct */
 611 #define MLX5_SET(typ, p, fld, v) \
 612         do { \
 613                 u32 _v = v; \
 614                 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
 615                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
 616                                   __mlx5_dw_off(typ, fld))) & \
 617                                   (~__mlx5_dw_mask(typ, fld))) | \
 618                                  (((_v) & __mlx5_mask(typ, fld)) << \
 619                                    __mlx5_dw_bit_off(typ, fld))); \
 620         } while (0)
 621
 622 #define MLX5_SET64(typ, p, fld, v) \
 623         do { \
 624                 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
 625                 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
 626                         rte_cpu_to_be_64(v); \
 627         } while (0)
 628
 629 #define MLX5_SET16(typ, p, fld, v) \
 630         do { \
 631                 u16 _v = v; \
 632                 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
 633                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 634                                   __mlx5_16_off(typ, fld))) & \
 635                                   (~__mlx5_16_mask(typ, fld))) | \
 636                                  (((_v) & __mlx5_mask16(typ, fld)) << \
 637                                   __mlx5_16_bit_off(typ, fld))); \
 638         } while (0)
 639
 640 #define MLX5_GET_VOLATILE(typ, p, fld) \
 641         ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
 642         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 643         __mlx5_mask(typ, fld))
 644 #define MLX5_GET(typ, p, fld) \
 645         ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
 646         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 647         __mlx5_mask(typ, fld))
 648 #define MLX5_GET16(typ, p, fld) \
 649         ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 650           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 651          __mlx5_mask16(typ, fld))
 652 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
 653                                                    __mlx5_64_off(typ, fld)))
 654 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 655
 656 struct mlx5_ifc_fte_match_set_misc_bits {
 657         u8 gre_c_present[0x1];
 658         u8 reserved_at_1[0x1];
 659         u8 gre_k_present[0x1];
 660         u8 gre_s_present[0x1];
 661         u8 source_vhci_port[0x4];
 662         u8 source_sqn[0x18];
 663         u8 reserved_at_20[0x10];
 664         u8 source_port[0x10];
 665         u8 outer_second_prio[0x3];
 666         u8 outer_second_cfi[0x1];
 667         u8 outer_second_vid[0xc];
 668         u8 inner_second_prio[0x3];
 669         u8 inner_second_cfi[0x1];
 670         u8 inner_second_vid[0xc];
 671         u8 outer_second_cvlan_tag[0x1];
 672         u8 inner_second_cvlan_tag[0x1];
 673         u8 outer_second_svlan_tag[0x1];
 674         u8 inner_second_svlan_tag[0x1];
 675         u8 reserved_at_64[0xc];
 676         u8 gre_protocol[0x10];
 677         u8 gre_key_h[0x18];
 678         u8 gre_key_l[0x8];
 679         u8 vxlan_vni[0x18];
 680         u8 reserved_at_b8[0x8];
 681         u8 geneve_vni[0x18];
 682         u8 reserved_at_e4[0x7];
 683         u8 geneve_oam[0x1];
 684         u8 reserved_at_e0[0xc];
 685         u8 outer_ipv6_flow_label[0x14];
 686         u8 reserved_at_100[0xc];
 687         u8 inner_ipv6_flow_label[0x14];
 688         u8 reserved_at_120[0xa];
 689         u8 geneve_opt_len[0x6];
 690         u8 geneve_protocol_type[0x10];
 691         u8 reserved_at_140[0xc0];
 692 };
 693
 694 struct mlx5_ifc_ipv4_layout_bits {
 695         u8 reserved_at_0[0x60];
 696         u8 ipv4[0x20];
 697 };
 698
 699 struct mlx5_ifc_ipv6_layout_bits {
 700         u8 ipv6[16][0x8];
 701 };
 702
 703 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 704         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 705         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 706         u8 reserved_at_0[0x80];
 707 };
 708
 709 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 710         u8 smac_47_16[0x20];
 711         u8 smac_15_0[0x10];
 712         u8 ethertype[0x10];
 713         u8 dmac_47_16[0x20];
 714         u8 dmac_15_0[0x10];
 715         u8 first_prio[0x3];
 716         u8 first_cfi[0x1];
 717         u8 first_vid[0xc];
 718         u8 ip_protocol[0x8];
 719         u8 ip_dscp[0x6];
 720         u8 ip_ecn[0x2];
 721         u8 cvlan_tag[0x1];
 722         u8 svlan_tag[0x1];
 723         u8 frag[0x1];
 724         u8 ip_version[0x4];
 725         u8 tcp_flags[0x9];
 726         u8 tcp_sport[0x10];
 727         u8 tcp_dport[0x10];
 728         u8 reserved_at_c0[0x18];
 729         u8 ip_ttl_hoplimit[0x8];
 730         u8 udp_sport[0x10];
 731         u8 udp_dport[0x10];
 732         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 733         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 734 };
 735
 736 struct mlx5_ifc_fte_match_mpls_bits {
 737         u8 mpls_label[0x14];
 738         u8 mpls_exp[0x3];
 739         u8 mpls_s_bos[0x1];
 740         u8 mpls_ttl[0x8];
 741 };
 742
 743 struct mlx5_ifc_fte_match_set_misc2_bits {
 744         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 745         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 746         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 747         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 748         u8 metadata_reg_c_7[0x20];
 749         u8 metadata_reg_c_6[0x20];
 750         u8 metadata_reg_c_5[0x20];
 751         u8 metadata_reg_c_4[0x20];
 752         u8 metadata_reg_c_3[0x20];
 753         u8 metadata_reg_c_2[0x20];
 754         u8 metadata_reg_c_1[0x20];
 755         u8 metadata_reg_c_0[0x20];
 756         u8 metadata_reg_a[0x20];
 757         u8 metadata_reg_b[0x20];
 758         u8 reserved_at_1c0[0x40];
 759 };
 760
 761 struct mlx5_ifc_fte_match_set_misc3_bits {
 762         u8 inner_tcp_seq_num[0x20];
 763         u8 outer_tcp_seq_num[0x20];
 764         u8 inner_tcp_ack_num[0x20];
 765         u8 outer_tcp_ack_num[0x20];
 766         u8 reserved_at_auto1[0x8];
 767         u8 outer_vxlan_gpe_vni[0x18];
 768         u8 outer_vxlan_gpe_next_protocol[0x8];
 769         u8 outer_vxlan_gpe_flags[0x8];
 770         u8 reserved_at_a8[0x10];
 771         u8 icmp_header_data[0x20];
 772         u8 icmpv6_header_data[0x20];
 773         u8 icmp_type[0x8];
 774         u8 icmp_code[0x8];
 775         u8 icmpv6_type[0x8];
 776         u8 icmpv6_code[0x8];
 777         u8 reserved_at_120[0x20];
 778         u8 gtpu_teid[0x20];
 779         u8 gtpu_msg_type[0x08];
 780         u8 gtpu_msg_flags[0x08];
 781         u8 reserved_at_170[0x90];
 782 };
 783
 784 struct mlx5_ifc_fte_match_set_misc4_bits {
 785         u8 prog_sample_field_value_0[0x20];
 786         u8 prog_sample_field_id_0[0x20];
 787         u8 prog_sample_field_value_1[0x20];
 788         u8 prog_sample_field_id_1[0x20];
 789         u8 prog_sample_field_value_2[0x20];
 790         u8 prog_sample_field_id_2[0x20];
 791         u8 prog_sample_field_value_3[0x20];
 792         u8 prog_sample_field_id_3[0x20];
 793         u8 reserved_at_100[0x100];
 794 };
 795
 796 /* Flow matcher. */
 797 struct mlx5_ifc_fte_match_param_bits {
 798         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 799         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 800         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 801         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
 802         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
 803         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
 804 };
 805
 806 enum {
 807         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
 808         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
 809         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
 810         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
 811         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
 812         MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
 813 };
 814
 815 enum {
 816         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
 817         MLX5_CMD_OP_CREATE_MKEY = 0x200,
 818         MLX5_CMD_OP_CREATE_CQ = 0x400,
 819         MLX5_CMD_OP_CREATE_QP = 0x500,
 820         MLX5_CMD_OP_RST2INIT_QP = 0x502,
 821         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
 822         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
 823         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
 824         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
 825         MLX5_CMD_OP_QP_2ERR = 0x507,
 826         MLX5_CMD_OP_QP_2RST = 0x50A,
 827         MLX5_CMD_OP_QUERY_QP = 0x50B,
 828         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
 829         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
 830         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
 831         MLX5_CMD_OP_RESUME_QP = 0x510,
 832         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
 833         MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
 834         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
 835         MLX5_CMD_OP_CREATE_TIR = 0x900,
 836         MLX5_CMD_OP_MODIFY_TIR = 0x901,
 837         MLX5_CMD_OP_CREATE_SQ = 0X904,
 838         MLX5_CMD_OP_MODIFY_SQ = 0X905,
 839         MLX5_CMD_OP_CREATE_RQ = 0x908,
 840         MLX5_CMD_OP_MODIFY_RQ = 0x909,
 841         MLX5_CMD_OP_CREATE_TIS = 0x912,
 842         MLX5_CMD_OP_QUERY_TIS = 0x915,
 843         MLX5_CMD_OP_CREATE_RQT = 0x916,
 844         MLX5_CMD_OP_MODIFY_RQT = 0x917,
 845         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
 846         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
 847         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
 848         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
 849         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
 850         MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
 851         MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
 852         MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
 853         MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
 854         MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
 855 };
 856
 857 enum {
 858         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
 859         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
 860         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
 861 };
 862
 863 #define MLX5_ADAPTER_PAGE_SHIFT 12
 864 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
 865 /**
 866  * The batch counter dcs id starts from 0x800000 and none batch counter
 867  * starts from 0. As currently, the counter is changed to be indexed by
 868  * pool index and the offset of the counter in the pool counters_raw array.
 869  * It means now the counter index is same for batch and none batch counter.
 870  * Add the 0x800000 batch counter offset to the batch counter index helps
 871  * indicate the counter index is from batch or none batch container pool.
 872  */
 873 #define MLX5_CNT_BATCH_OFFSET 0x800000
 874
 875 /* The counter batch query requires ID align with 4. */
 876 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
 877
 878 /* Flow counters. */
 879 struct mlx5_ifc_alloc_flow_counter_out_bits {
 880         u8         status[0x8];
 881         u8         reserved_at_8[0x18];
 882         u8         syndrome[0x20];
 883         u8         flow_counter_id[0x20];
 884         u8         reserved_at_60[0x20];
 885 };
 886
 887 struct mlx5_ifc_alloc_flow_counter_in_bits {
 888         u8         opcode[0x10];
 889         u8         reserved_at_10[0x10];
 890         u8         reserved_at_20[0x10];
 891         u8         op_mod[0x10];
 892         u8         flow_counter_id[0x20];
 893         u8         reserved_at_40[0x18];
 894         u8         flow_counter_bulk[0x8];
 895 };
 896
 897 struct mlx5_ifc_dealloc_flow_counter_out_bits {
 898         u8         status[0x8];
 899         u8         reserved_at_8[0x18];
 900         u8         syndrome[0x20];
 901         u8         reserved_at_40[0x40];
 902 };
 903
 904 struct mlx5_ifc_dealloc_flow_counter_in_bits {
 905         u8         opcode[0x10];
 906         u8         reserved_at_10[0x10];
 907         u8         reserved_at_20[0x10];
 908         u8         op_mod[0x10];
 909         u8         flow_counter_id[0x20];
 910         u8         reserved_at_60[0x20];
 911 };
 912
 913 struct mlx5_ifc_traffic_counter_bits {
 914         u8         packets[0x40];
 915         u8         octets[0x40];
 916 };
 917
 918 struct mlx5_ifc_query_flow_counter_out_bits {
 919         u8         status[0x8];
 920         u8         reserved_at_8[0x18];
 921         u8         syndrome[0x20];
 922         u8         reserved_at_40[0x40];
 923         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
 924 };
 925
 926 struct mlx5_ifc_query_flow_counter_in_bits {
 927         u8         opcode[0x10];
 928         u8         reserved_at_10[0x10];
 929         u8         reserved_at_20[0x10];
 930         u8         op_mod[0x10];
 931         u8         reserved_at_40[0x20];
 932         u8         mkey[0x20];
 933         u8         address[0x40];
 934         u8         clear[0x1];
 935         u8         dump_to_memory[0x1];
 936         u8         num_of_counters[0x1e];
 937         u8         flow_counter_id[0x20];
 938 };
 939
 940 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
 941 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
 942
 943
 944 struct mlx5_ifc_klm_bits {
 945         u8         byte_count[0x20];
 946         u8         mkey[0x20];
 947         u8         address[0x40];
 948 };
 949
 950 struct mlx5_ifc_mkc_bits {
 951         u8         reserved_at_0[0x1];
 952         u8         free[0x1];
 953         u8         reserved_at_2[0x1];
 954         u8         access_mode_4_2[0x3];
 955         u8         reserved_at_6[0x7];
 956         u8         relaxed_ordering_write[0x1];
 957         u8         reserved_at_e[0x1];
 958         u8         small_fence_on_rdma_read_response[0x1];
 959         u8         umr_en[0x1];
 960         u8         a[0x1];
 961         u8         rw[0x1];
 962         u8         rr[0x1];
 963         u8         lw[0x1];
 964         u8         lr[0x1];
 965         u8         access_mode_1_0[0x2];
 966         u8         reserved_at_18[0x8];
 967
 968         u8         qpn[0x18];
 969         u8         mkey_7_0[0x8];
 970
 971         u8         reserved_at_40[0x20];
 972
 973         u8         length64[0x1];
 974         u8         bsf_en[0x1];
 975         u8         sync_umr[0x1];
 976         u8         reserved_at_63[0x2];
 977         u8         expected_sigerr_count[0x1];
 978         u8         reserved_at_66[0x1];
 979         u8         en_rinval[0x1];
 980         u8         pd[0x18];
 981
 982         u8         start_addr[0x40];
 983
 984         u8         len[0x40];
 985
 986         u8         bsf_octword_size[0x20];
 987
 988         u8         reserved_at_120[0x80];
 989
 990         u8         translations_octword_size[0x20];
 991
 992         u8         reserved_at_1c0[0x19];
 993         u8                 relaxed_ordering_read[0x1];
 994         u8                 reserved_at_1da[0x1];
 995         u8         log_page_size[0x5];
 996
 997         u8         reserved_at_1e0[0x20];
 998 };
 999
1000 struct mlx5_ifc_create_mkey_out_bits {
1001         u8         status[0x8];
1002         u8         reserved_at_8[0x18];
1003
1004         u8         syndrome[0x20];
1005
1006         u8         reserved_at_40[0x8];
1007         u8         mkey_index[0x18];
1008
1009         u8         reserved_at_60[0x20];
1010 };
1011
1012 struct mlx5_ifc_create_mkey_in_bits {
1013         u8         opcode[0x10];
1014         u8         reserved_at_10[0x10];
1015
1016         u8         reserved_at_20[0x10];
1017         u8         op_mod[0x10];
1018
1019         u8         reserved_at_40[0x20];
1020
1021         u8         pg_access[0x1];
1022         u8         reserved_at_61[0x1f];
1023
1024         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1025
1026         u8         reserved_at_280[0x80];
1027
1028         u8         translations_octword_actual_size[0x20];
1029
1030         u8         mkey_umem_id[0x20];
1031
1032         u8         mkey_umem_offset[0x40];
1033
1034         u8         reserved_at_380[0x500];
1035
1036         u8         klm_pas_mtt[][0x20];
1037 };
1038
1039 enum {
1040         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1041         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1042         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1043         MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1044         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1045 };
1046
1047 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1048                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1049 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1050                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1051 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1052                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1053 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1054                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1055
1056 enum {
1057         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
1058         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
1059 };
1060
1061 enum {
1062         MLX5_CAP_INLINE_MODE_L2,
1063         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1064         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1065 };
1066
1067 enum {
1068         MLX5_INLINE_MODE_NONE,
1069         MLX5_INLINE_MODE_L2,
1070         MLX5_INLINE_MODE_IP,
1071         MLX5_INLINE_MODE_TCP_UDP,
1072         MLX5_INLINE_MODE_RESERVED4,
1073         MLX5_INLINE_MODE_INNER_L2,
1074         MLX5_INLINE_MODE_INNER_IP,
1075         MLX5_INLINE_MODE_INNER_TCP_UDP,
1076 };
1077
1078 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1079 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1080 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1081 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1082 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1083 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1084 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1085 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1086 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1087 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1088 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1089
1090 struct mlx5_ifc_cmd_hca_cap_bits {
1091         u8 reserved_at_0[0x30];
1092         u8 vhca_id[0x10];
1093         u8 reserved_at_40[0x40];
1094         u8 log_max_srq_sz[0x8];
1095         u8 log_max_qp_sz[0x8];
1096         u8 reserved_at_90[0x9];
1097         u8 wqe_index_ignore_cap[0x1];
1098         u8 dynamic_qp_allocation[0x1];
1099         u8 log_max_qp[0x5];
1100         u8 regexp[0x1];
1101         u8 reserved_at_a1[0x3];
1102         u8 regexp_num_of_engines[0x4];
1103         u8 reserved_at_a8[0x3];
1104         u8 log_max_srq[0x5];
1105         u8 reserved_at_b0[0x3];
1106         u8 regexp_log_crspace_size[0x5];
1107         u8 reserved_at_b8[0x3];
1108         u8 scatter_fcs_w_decap_disable[0x1];
1109         u8 reserved_at_bc[0x4];
1110         u8 reserved_at_c0[0x8];
1111         u8 log_max_cq_sz[0x8];
1112         u8 reserved_at_d0[0xb];
1113         u8 log_max_cq[0x5];
1114         u8 log_max_eq_sz[0x8];
1115         u8 relaxed_ordering_write[0x1];
1116         u8 relaxed_ordering_read[0x1];
1117         u8 access_register_user[0x1];
1118         u8 log_max_mkey[0x5];
1119         u8 reserved_at_f0[0x8];
1120         u8 dump_fill_mkey[0x1];
1121         u8 reserved_at_f9[0x3];
1122         u8 log_max_eq[0x4];
1123         u8 max_indirection[0x8];
1124         u8 fixed_buffer_size[0x1];
1125         u8 log_max_mrw_sz[0x7];
1126         u8 force_teardown[0x1];
1127         u8 reserved_at_111[0x1];
1128         u8 log_max_bsf_list_size[0x6];
1129         u8 umr_extended_translation_offset[0x1];
1130         u8 null_mkey[0x1];
1131         u8 log_max_klm_list_size[0x6];
1132         u8 non_wire_sq[0x1];
1133         u8 reserved_at_121[0x9];
1134         u8 log_max_ra_req_dc[0x6];
1135         u8 reserved_at_130[0x3];
1136         u8 log_max_static_sq_wq[0x5];
1137         u8 reserved_at_138[0x2];
1138         u8 log_max_ra_res_dc[0x6];
1139         u8 reserved_at_140[0xa];
1140         u8 log_max_ra_req_qp[0x6];
1141         u8 reserved_at_150[0xa];
1142         u8 log_max_ra_res_qp[0x6];
1143         u8 end_pad[0x1];
1144         u8 cc_query_allowed[0x1];
1145         u8 cc_modify_allowed[0x1];
1146         u8 start_pad[0x1];
1147         u8 cache_line_128byte[0x1];
1148         u8 reserved_at_165[0xa];
1149         u8 qcam_reg[0x1];
1150         u8 gid_table_size[0x10];
1151         u8 out_of_seq_cnt[0x1];
1152         u8 vport_counters[0x1];
1153         u8 retransmission_q_counters[0x1];
1154         u8 debug[0x1];
1155         u8 modify_rq_counter_set_id[0x1];
1156         u8 rq_delay_drop[0x1];
1157         u8 max_qp_cnt[0xa];
1158         u8 pkey_table_size[0x10];
1159         u8 vport_group_manager[0x1];
1160         u8 vhca_group_manager[0x1];
1161         u8 ib_virt[0x1];
1162         u8 eth_virt[0x1];
1163         u8 vnic_env_queue_counters[0x1];
1164         u8 ets[0x1];
1165         u8 nic_flow_table[0x1];
1166         u8 eswitch_manager[0x1];
1167         u8 device_memory[0x1];
1168         u8 mcam_reg[0x1];
1169         u8 pcam_reg[0x1];
1170         u8 local_ca_ack_delay[0x5];
1171         u8 port_module_event[0x1];
1172         u8 enhanced_error_q_counters[0x1];
1173         u8 ports_check[0x1];
1174         u8 reserved_at_1b3[0x1];
1175         u8 disable_link_up[0x1];
1176         u8 beacon_led[0x1];
1177         u8 port_type[0x2];
1178         u8 num_ports[0x8];
1179         u8 reserved_at_1c0[0x1];
1180         u8 pps[0x1];
1181         u8 pps_modify[0x1];
1182         u8 log_max_msg[0x5];
1183         u8 reserved_at_1c8[0x4];
1184         u8 max_tc[0x4];
1185         u8 temp_warn_event[0x1];
1186         u8 dcbx[0x1];
1187         u8 general_notification_event[0x1];
1188         u8 reserved_at_1d3[0x2];
1189         u8 fpga[0x1];
1190         u8 rol_s[0x1];
1191         u8 rol_g[0x1];
1192         u8 reserved_at_1d8[0x1];
1193         u8 wol_s[0x1];
1194         u8 wol_g[0x1];
1195         u8 wol_a[0x1];
1196         u8 wol_b[0x1];
1197         u8 wol_m[0x1];
1198         u8 wol_u[0x1];
1199         u8 wol_p[0x1];
1200         u8 stat_rate_support[0x10];
1201         u8 reserved_at_1f0[0xc];
1202         u8 cqe_version[0x4];
1203         u8 compact_address_vector[0x1];
1204         u8 striding_rq[0x1];
1205         u8 reserved_at_202[0x1];
1206         u8 ipoib_enhanced_offloads[0x1];
1207         u8 ipoib_basic_offloads[0x1];
1208         u8 reserved_at_205[0x1];
1209         u8 repeated_block_disabled[0x1];
1210         u8 umr_modify_entity_size_disabled[0x1];
1211         u8 umr_modify_atomic_disabled[0x1];
1212         u8 umr_indirect_mkey_disabled[0x1];
1213         u8 umr_fence[0x2];
1214         u8 reserved_at_20c[0x3];
1215         u8 drain_sigerr[0x1];
1216         u8 cmdif_checksum[0x2];
1217         u8 sigerr_cqe[0x1];
1218         u8 reserved_at_213[0x1];
1219         u8 wq_signature[0x1];
1220         u8 sctr_data_cqe[0x1];
1221         u8 reserved_at_216[0x1];
1222         u8 sho[0x1];
1223         u8 tph[0x1];
1224         u8 rf[0x1];
1225         u8 dct[0x1];
1226         u8 qos[0x1];
1227         u8 eth_net_offloads[0x1];
1228         u8 roce[0x1];
1229         u8 atomic[0x1];
1230         u8 reserved_at_21f[0x1];
1231         u8 cq_oi[0x1];
1232         u8 cq_resize[0x1];
1233         u8 cq_moderation[0x1];
1234         u8 reserved_at_223[0x3];
1235         u8 cq_eq_remap[0x1];
1236         u8 pg[0x1];
1237         u8 block_lb_mc[0x1];
1238         u8 reserved_at_229[0x1];
1239         u8 scqe_break_moderation[0x1];
1240         u8 cq_period_start_from_cqe[0x1];
1241         u8 cd[0x1];
1242         u8 reserved_at_22d[0x1];
1243         u8 apm[0x1];
1244         u8 vector_calc[0x1];
1245         u8 umr_ptr_rlky[0x1];
1246         u8 imaicl[0x1];
1247         u8 reserved_at_232[0x4];
1248         u8 qkv[0x1];
1249         u8 pkv[0x1];
1250         u8 set_deth_sqpn[0x1];
1251         u8 reserved_at_239[0x3];
1252         u8 xrc[0x1];
1253         u8 ud[0x1];
1254         u8 uc[0x1];
1255         u8 rc[0x1];
1256         u8 uar_4k[0x1];
1257         u8 reserved_at_241[0x9];
1258         u8 uar_sz[0x6];
1259         u8 reserved_at_250[0x8];
1260         u8 log_pg_sz[0x8];
1261         u8 bf[0x1];
1262         u8 driver_version[0x1];
1263         u8 pad_tx_eth_packet[0x1];
1264         u8 reserved_at_263[0x8];
1265         u8 log_bf_reg_size[0x5];
1266         u8 reserved_at_270[0xb];
1267         u8 lag_master[0x1];
1268         u8 num_lag_ports[0x4];
1269         u8 reserved_at_280[0x10];
1270         u8 max_wqe_sz_sq[0x10];
1271         u8 reserved_at_2a0[0x10];
1272         u8 max_wqe_sz_rq[0x10];
1273         u8 max_flow_counter_31_16[0x10];
1274         u8 max_wqe_sz_sq_dc[0x10];
1275         u8 reserved_at_2e0[0x7];
1276         u8 max_qp_mcg[0x19];
1277         u8 reserved_at_300[0x10];
1278         u8 flow_counter_bulk_alloc[0x08];
1279         u8 log_max_mcg[0x8];
1280         u8 reserved_at_320[0x3];
1281         u8 log_max_transport_domain[0x5];
1282         u8 reserved_at_328[0x3];
1283         u8 log_max_pd[0x5];
1284         u8 reserved_at_330[0xb];
1285         u8 log_max_xrcd[0x5];
1286         u8 nic_receive_steering_discard[0x1];
1287         u8 receive_discard_vport_down[0x1];
1288         u8 transmit_discard_vport_down[0x1];
1289         u8 reserved_at_343[0x5];
1290         u8 log_max_flow_counter_bulk[0x8];
1291         u8 max_flow_counter_15_0[0x10];
1292         u8 modify_tis[0x1];
1293         u8 flow_counters_dump[0x1];
1294         u8 reserved_at_360[0x1];
1295         u8 log_max_rq[0x5];
1296         u8 reserved_at_368[0x3];
1297         u8 log_max_sq[0x5];
1298         u8 reserved_at_370[0x3];
1299         u8 log_max_tir[0x5];
1300         u8 reserved_at_378[0x3];
1301         u8 log_max_tis[0x5];
1302         u8 basic_cyclic_rcv_wqe[0x1];
1303         u8 reserved_at_381[0x2];
1304         u8 log_max_rmp[0x5];
1305         u8 reserved_at_388[0x3];
1306         u8 log_max_rqt[0x5];
1307         u8 reserved_at_390[0x3];
1308         u8 log_max_rqt_size[0x5];
1309         u8 reserved_at_398[0x3];
1310         u8 log_max_tis_per_sq[0x5];
1311         u8 ext_stride_num_range[0x1];
1312         u8 reserved_at_3a1[0x2];
1313         u8 log_max_stride_sz_rq[0x5];
1314         u8 reserved_at_3a8[0x3];
1315         u8 log_min_stride_sz_rq[0x5];
1316         u8 reserved_at_3b0[0x3];
1317         u8 log_max_stride_sz_sq[0x5];
1318         u8 reserved_at_3b8[0x3];
1319         u8 log_min_stride_sz_sq[0x5];
1320         u8 hairpin[0x1];
1321         u8 reserved_at_3c1[0x2];
1322         u8 log_max_hairpin_queues[0x5];
1323         u8 reserved_at_3c8[0x3];
1324         u8 log_max_hairpin_wq_data_sz[0x5];
1325         u8 reserved_at_3d0[0x3];
1326         u8 log_max_hairpin_num_packets[0x5];
1327         u8 reserved_at_3d8[0x3];
1328         u8 log_max_wq_sz[0x5];
1329         u8 nic_vport_change_event[0x1];
1330         u8 disable_local_lb_uc[0x1];
1331         u8 disable_local_lb_mc[0x1];
1332         u8 log_min_hairpin_wq_data_sz[0x5];
1333         u8 reserved_at_3e8[0x3];
1334         u8 log_max_vlan_list[0x5];
1335         u8 reserved_at_3f0[0x3];
1336         u8 log_max_current_mc_list[0x5];
1337         u8 reserved_at_3f8[0x3];
1338         u8 log_max_current_uc_list[0x5];
1339         u8 general_obj_types[0x40];
1340         u8 reserved_at_440[0x20];
1341         u8 reserved_at_460[0x10];
1342         u8 max_num_eqs[0x10];
1343         u8 reserved_at_480[0x3];
1344         u8 log_max_l2_table[0x5];
1345         u8 reserved_at_488[0x8];
1346         u8 log_uar_page_sz[0x10];
1347         u8 reserved_at_4a0[0x20];
1348         u8 device_frequency_mhz[0x20];
1349         u8 device_frequency_khz[0x20];
1350         u8 reserved_at_500[0x20];
1351         u8 num_of_uars_per_page[0x20];
1352         u8 flex_parser_protocols[0x20];
1353         u8 reserved_at_560[0x20];
1354         u8 reserved_at_580[0x3c];
1355         u8 mini_cqe_resp_stride_index[0x1];
1356         u8 cqe_128_always[0x1];
1357         u8 cqe_compression_128[0x1];
1358         u8 cqe_compression[0x1];
1359         u8 cqe_compression_timeout[0x10];
1360         u8 cqe_compression_max_num[0x10];
1361         u8 reserved_at_5e0[0x10];
1362         u8 tag_matching[0x1];
1363         u8 rndv_offload_rc[0x1];
1364         u8 rndv_offload_dc[0x1];
1365         u8 log_tag_matching_list_sz[0x5];
1366         u8 reserved_at_5f8[0x3];
1367         u8 log_max_xrq[0x5];
1368         u8 affiliate_nic_vport_criteria[0x8];
1369         u8 native_port_num[0x8];
1370         u8 num_vhca_ports[0x8];
1371         u8 reserved_at_618[0x6];
1372         u8 sw_owner_id[0x1];
1373         u8 reserved_at_61f[0x1e1];
1374 };
1375
1376 struct mlx5_ifc_qos_cap_bits {
1377         u8 packet_pacing[0x1];
1378         u8 esw_scheduling[0x1];
1379         u8 esw_bw_share[0x1];
1380         u8 esw_rate_limit[0x1];
1381         u8 reserved_at_4[0x1];
1382         u8 packet_pacing_burst_bound[0x1];
1383         u8 packet_pacing_typical_size[0x1];
1384         u8 flow_meter_srtcm[0x1];
1385         u8 reserved_at_8[0x8];
1386         u8 log_max_flow_meter[0x8];
1387         u8 flow_meter_reg_id[0x8];
1388         u8 wqe_rate_pp[0x1];
1389         u8 reserved_at_25[0x7];
1390         u8 flow_meter_reg_share[0x1];
1391         u8 reserved_at_2e[0x17];
1392         u8 packet_pacing_max_rate[0x20];
1393         u8 packet_pacing_min_rate[0x20];
1394         u8 reserved_at_80[0x10];
1395         u8 packet_pacing_rate_table_size[0x10];
1396         u8 esw_element_type[0x10];
1397         u8 esw_tsar_type[0x10];
1398         u8 reserved_at_c0[0x10];
1399         u8 max_qos_para_vport[0x10];
1400         u8 max_tsar_bw_share[0x20];
1401         u8 reserved_at_100[0x6e8];
1402 };
1403
1404 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1405         u8 csum_cap[0x1];
1406         u8 vlan_cap[0x1];
1407         u8 lro_cap[0x1];
1408         u8 lro_psh_flag[0x1];
1409         u8 lro_time_stamp[0x1];
1410         u8 lro_max_msg_sz_mode[0x2];
1411         u8 wqe_vlan_insert[0x1];
1412         u8 self_lb_en_modifiable[0x1];
1413         u8 self_lb_mc[0x1];
1414         u8 self_lb_uc[0x1];
1415         u8 max_lso_cap[0x5];
1416         u8 multi_pkt_send_wqe[0x2];
1417         u8 wqe_inline_mode[0x2];
1418         u8 rss_ind_tbl_cap[0x4];
1419         u8 reg_umr_sq[0x1];
1420         u8 scatter_fcs[0x1];
1421         u8 enhanced_multi_pkt_send_wqe[0x1];
1422         u8 tunnel_lso_const_out_ip_id[0x1];
1423         u8 tunnel_lro_gre[0x1];
1424         u8 tunnel_lro_vxlan[0x1];
1425         u8 tunnel_stateless_gre[0x1];
1426         u8 tunnel_stateless_vxlan[0x1];
1427         u8 swp[0x1];
1428         u8 swp_csum[0x1];
1429         u8 swp_lso[0x1];
1430         u8 reserved_at_23[0x8];
1431         u8 tunnel_stateless_gtp[0x1];
1432         u8 reserved_at_25[0x4];
1433         u8 max_vxlan_udp_ports[0x8];
1434         u8 reserved_at_38[0x6];
1435         u8 max_geneve_opt_len[0x1];
1436         u8 tunnel_stateless_geneve_rx[0x1];
1437         u8 reserved_at_40[0x10];
1438         u8 lro_min_mss_size[0x10];
1439         u8 reserved_at_60[0x120];
1440         u8 lro_timer_supported_periods[4][0x20];
1441         u8 reserved_at_200[0x600];
1442 };
1443
1444 enum {
1445         MLX5_VIRTQ_TYPE_SPLIT = 0,
1446         MLX5_VIRTQ_TYPE_PACKED = 1,
1447 };
1448
1449 enum {
1450         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1451         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1452         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1453 };
1454
1455 struct mlx5_ifc_virtio_emulation_cap_bits {
1456         u8 desc_tunnel_offload_type[0x1];
1457         u8 eth_frame_offload_type[0x1];
1458         u8 virtio_version_1_0[0x1];
1459         u8 tso_ipv4[0x1];
1460         u8 tso_ipv6[0x1];
1461         u8 tx_csum[0x1];
1462         u8 rx_csum[0x1];
1463         u8 reserved_at_7[0x1][0x9];
1464         u8 event_mode[0x8];
1465         u8 virtio_queue_type[0x8];
1466         u8 reserved_at_20[0x13];
1467         u8 log_doorbell_stride[0x5];
1468         u8 reserved_at_3b[0x3];
1469         u8 log_doorbell_bar_size[0x5];
1470         u8 doorbell_bar_offset[0x40];
1471         u8 reserved_at_80[0x8];
1472         u8 max_num_virtio_queues[0x18];
1473         u8 reserved_at_a0[0x60];
1474         u8 umem_1_buffer_param_a[0x20];
1475         u8 umem_1_buffer_param_b[0x20];
1476         u8 umem_2_buffer_param_a[0x20];
1477         u8 umem_2_buffer_param_b[0x20];
1478         u8 umem_3_buffer_param_a[0x20];
1479         u8 umem_3_buffer_param_b[0x20];
1480         u8 reserved_at_1c0[0x620];
1481 };
1482
1483 struct mlx5_ifc_flow_table_prop_layout_bits {
1484         u8 ft_support[0x1];
1485         u8 flow_tag[0x1];
1486         u8 flow_counter[0x1];
1487         u8 flow_modify_en[0x1];
1488         u8 modify_root[0x1];
1489         u8 identified_miss_table[0x1];
1490         u8 flow_table_modify[0x1];
1491         u8 reformat[0x1];
1492         u8 decap[0x1];
1493         u8 reset_root_to_default[0x1];
1494         u8 pop_vlan[0x1];
1495         u8 push_vlan[0x1];
1496         u8 fpga_vendor_acceleration[0x1];
1497         u8 pop_vlan_2[0x1];
1498         u8 push_vlan_2[0x1];
1499         u8 reformat_and_vlan_action[0x1];
1500         u8 modify_and_vlan_action[0x1];
1501         u8 sw_owner[0x1];
1502         u8 reformat_l3_tunnel_to_l2[0x1];
1503         u8 reformat_l2_to_l3_tunnel[0x1];
1504         u8 reformat_and_modify_action[0x1];
1505         u8 reserved_at_15[0x9];
1506         u8 sw_owner_v2[0x1];
1507         u8 reserved_at_1f[0x1];
1508         u8 reserved_at_20[0x2];
1509         u8 log_max_ft_size[0x6];
1510         u8 log_max_modify_header_context[0x8];
1511         u8 max_modify_header_actions[0x8];
1512         u8 max_ft_level[0x8];
1513         u8 reserved_at_40[0x8];
1514         u8 log_max_ft_sampler_num[8];
1515         u8 metadata_reg_b_width[0x8];
1516         u8 metadata_reg_a_width[0x8];
1517         u8 reserved_at_60[0x18];
1518         u8 log_max_ft_num[0x8];
1519         u8 reserved_at_80[0x10];
1520         u8 log_max_flow_counter[0x8];
1521         u8 log_max_destination[0x8];
1522         u8 reserved_at_a0[0x18];
1523         u8 log_max_flow[0x8];
1524         u8 reserved_at_c0[0x140];
1525 };
1526
1527 struct mlx5_ifc_flow_table_nic_cap_bits {
1528         u8         reserved_at_0[0x200];
1529         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
1530 };
1531
1532 union mlx5_ifc_hca_cap_union_bits {
1533         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1534         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1535                per_protocol_networking_offload_caps;
1536         struct mlx5_ifc_qos_cap_bits qos_cap;
1537         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1538         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1539         u8 reserved_at_0[0x8000];
1540 };
1541
1542 struct mlx5_ifc_set_action_in_bits {
1543         u8 action_type[0x4];
1544         u8 field[0xc];
1545         u8 reserved_at_10[0x3];
1546         u8 offset[0x5];
1547         u8 reserved_at_18[0x3];
1548         u8 length[0x5];
1549         u8 data[0x20];
1550 };
1551
1552 struct mlx5_ifc_query_hca_cap_out_bits {
1553         u8 status[0x8];
1554         u8 reserved_at_8[0x18];
1555         u8 syndrome[0x20];
1556         u8 reserved_at_40[0x40];
1557         union mlx5_ifc_hca_cap_union_bits capability;
1558 };
1559
1560 struct mlx5_ifc_query_hca_cap_in_bits {
1561         u8 opcode[0x10];
1562         u8 reserved_at_10[0x10];
1563         u8 reserved_at_20[0x10];
1564         u8 op_mod[0x10];
1565         u8 reserved_at_40[0x40];
1566 };
1567
1568 struct mlx5_ifc_mac_address_layout_bits {
1569         u8 reserved_at_0[0x10];
1570         u8 mac_addr_47_32[0x10];
1571         u8 mac_addr_31_0[0x20];
1572 };
1573
1574 struct mlx5_ifc_nic_vport_context_bits {
1575         u8 reserved_at_0[0x5];
1576         u8 min_wqe_inline_mode[0x3];
1577         u8 reserved_at_8[0x15];
1578         u8 disable_mc_local_lb[0x1];
1579         u8 disable_uc_local_lb[0x1];
1580         u8 roce_en[0x1];
1581         u8 arm_change_event[0x1];
1582         u8 reserved_at_21[0x1a];
1583         u8 event_on_mtu[0x1];
1584         u8 event_on_promisc_change[0x1];
1585         u8 event_on_vlan_change[0x1];
1586         u8 event_on_mc_address_change[0x1];
1587         u8 event_on_uc_address_change[0x1];
1588         u8 reserved_at_40[0xc];
1589         u8 affiliation_criteria[0x4];
1590         u8 affiliated_vhca_id[0x10];
1591         u8 reserved_at_60[0xd0];
1592         u8 mtu[0x10];
1593         u8 system_image_guid[0x40];
1594         u8 port_guid[0x40];
1595         u8 node_guid[0x40];
1596         u8 reserved_at_200[0x140];
1597         u8 qkey_violation_counter[0x10];
1598         u8 reserved_at_350[0x430];
1599         u8 promisc_uc[0x1];
1600         u8 promisc_mc[0x1];
1601         u8 promisc_all[0x1];
1602         u8 reserved_at_783[0x2];
1603         u8 allowed_list_type[0x3];
1604         u8 reserved_at_788[0xc];
1605         u8 allowed_list_size[0xc];
1606         struct mlx5_ifc_mac_address_layout_bits permanent_address;
1607         u8 reserved_at_7e0[0x20];
1608 };
1609
1610 struct mlx5_ifc_query_nic_vport_context_out_bits {
1611         u8 status[0x8];
1612         u8 reserved_at_8[0x18];
1613         u8 syndrome[0x20];
1614         u8 reserved_at_40[0x40];
1615         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1616 };
1617
1618 struct mlx5_ifc_query_nic_vport_context_in_bits {
1619         u8 opcode[0x10];
1620         u8 reserved_at_10[0x10];
1621         u8 reserved_at_20[0x10];
1622         u8 op_mod[0x10];
1623         u8 other_vport[0x1];
1624         u8 reserved_at_41[0xf];
1625         u8 vport_number[0x10];
1626         u8 reserved_at_60[0x5];
1627         u8 allowed_list_type[0x3];
1628         u8 reserved_at_68[0x18];
1629 };
1630
1631 struct mlx5_ifc_tisc_bits {
1632         u8 strict_lag_tx_port_affinity[0x1];
1633         u8 reserved_at_1[0x3];
1634         u8 lag_tx_port_affinity[0x04];
1635         u8 reserved_at_8[0x4];
1636         u8 prio[0x4];
1637         u8 reserved_at_10[0x10];
1638         u8 reserved_at_20[0x100];
1639         u8 reserved_at_120[0x8];
1640         u8 transport_domain[0x18];
1641         u8 reserved_at_140[0x8];
1642         u8 underlay_qpn[0x18];
1643         u8 reserved_at_160[0x3a0];
1644 };
1645
1646 struct mlx5_ifc_query_tis_out_bits {
1647         u8 status[0x8];
1648         u8 reserved_at_8[0x18];
1649         u8 syndrome[0x20];
1650         u8 reserved_at_40[0x40];
1651         struct mlx5_ifc_tisc_bits tis_context;
1652 };
1653
1654 struct mlx5_ifc_query_tis_in_bits {
1655         u8 opcode[0x10];
1656         u8 reserved_at_10[0x10];
1657         u8 reserved_at_20[0x10];
1658         u8 op_mod[0x10];
1659         u8 reserved_at_40[0x8];
1660         u8 tisn[0x18];
1661         u8 reserved_at_60[0x20];
1662 };
1663
1664 struct mlx5_ifc_alloc_transport_domain_out_bits {
1665         u8 status[0x8];
1666         u8 reserved_at_8[0x18];
1667         u8 syndrome[0x20];
1668         u8 reserved_at_40[0x8];
1669         u8 transport_domain[0x18];
1670         u8 reserved_at_60[0x20];
1671 };
1672
1673 struct mlx5_ifc_alloc_transport_domain_in_bits {
1674         u8 opcode[0x10];
1675         u8 reserved_at_10[0x10];
1676         u8 reserved_at_20[0x10];
1677         u8 op_mod[0x10];
1678         u8 reserved_at_40[0x40];
1679 };
1680
1681 enum {
1682         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
1683         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
1684         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
1685         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
1686 };
1687
1688 enum {
1689         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
1690         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1691 };
1692
1693 struct mlx5_ifc_wq_bits {
1694         u8 wq_type[0x4];
1695         u8 wq_signature[0x1];
1696         u8 end_padding_mode[0x2];
1697         u8 cd_slave[0x1];
1698         u8 reserved_at_8[0x18];
1699         u8 hds_skip_first_sge[0x1];
1700         u8 log2_hds_buf_size[0x3];
1701         u8 reserved_at_24[0x7];
1702         u8 page_offset[0x5];
1703         u8 lwm[0x10];
1704         u8 reserved_at_40[0x8];
1705         u8 pd[0x18];
1706         u8 reserved_at_60[0x8];
1707         u8 uar_page[0x18];
1708         u8 dbr_addr[0x40];
1709         u8 hw_counter[0x20];
1710         u8 sw_counter[0x20];
1711         u8 reserved_at_100[0xc];
1712         u8 log_wq_stride[0x4];
1713         u8 reserved_at_110[0x3];
1714         u8 log_wq_pg_sz[0x5];
1715         u8 reserved_at_118[0x3];
1716         u8 log_wq_sz[0x5];
1717         u8 dbr_umem_valid[0x1];
1718         u8 wq_umem_valid[0x1];
1719         u8 reserved_at_122[0x1];
1720         u8 log_hairpin_num_packets[0x5];
1721         u8 reserved_at_128[0x3];
1722         u8 log_hairpin_data_sz[0x5];
1723         u8 reserved_at_130[0x4];
1724         u8 single_wqe_log_num_of_strides[0x4];
1725         u8 two_byte_shift_en[0x1];
1726         u8 reserved_at_139[0x4];
1727         u8 single_stride_log_num_of_bytes[0x3];
1728         u8 dbr_umem_id[0x20];
1729         u8 wq_umem_id[0x20];
1730         u8 wq_umem_offset[0x40];
1731         u8 reserved_at_1c0[0x440];
1732 };
1733
1734 enum {
1735         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
1736         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
1737 };
1738
1739 enum {
1740         MLX5_RQC_STATE_RST  = 0x0,
1741         MLX5_RQC_STATE_RDY  = 0x1,
1742         MLX5_RQC_STATE_ERR  = 0x3,
1743 };
1744
1745 struct mlx5_ifc_rqc_bits {
1746         u8 rlky[0x1];
1747         u8 delay_drop_en[0x1];
1748         u8 scatter_fcs[0x1];
1749         u8 vsd[0x1];
1750         u8 mem_rq_type[0x4];
1751         u8 state[0x4];
1752         u8 reserved_at_c[0x1];
1753         u8 flush_in_error_en[0x1];
1754         u8 hairpin[0x1];
1755         u8 reserved_at_f[0x11];
1756         u8 reserved_at_20[0x8];
1757         u8 user_index[0x18];
1758         u8 reserved_at_40[0x8];
1759         u8 cqn[0x18];
1760         u8 counter_set_id[0x8];
1761         u8 reserved_at_68[0x18];
1762         u8 reserved_at_80[0x8];
1763         u8 rmpn[0x18];
1764         u8 reserved_at_a0[0x8];
1765         u8 hairpin_peer_sq[0x18];
1766         u8 reserved_at_c0[0x10];
1767         u8 hairpin_peer_vhca[0x10];
1768         u8 reserved_at_e0[0xa0];
1769         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1770 };
1771
1772 struct mlx5_ifc_create_rq_out_bits {
1773         u8 status[0x8];
1774         u8 reserved_at_8[0x18];
1775         u8 syndrome[0x20];
1776         u8 reserved_at_40[0x8];
1777         u8 rqn[0x18];
1778         u8 reserved_at_60[0x20];
1779 };
1780
1781 struct mlx5_ifc_create_rq_in_bits {
1782         u8 opcode[0x10];
1783         u8 uid[0x10];
1784         u8 reserved_at_20[0x10];
1785         u8 op_mod[0x10];
1786         u8 reserved_at_40[0xc0];
1787         struct mlx5_ifc_rqc_bits ctx;
1788 };
1789
1790 struct mlx5_ifc_modify_rq_out_bits {
1791         u8 status[0x8];
1792         u8 reserved_at_8[0x18];
1793         u8 syndrome[0x20];
1794         u8 reserved_at_40[0x40];
1795 };
1796
1797 struct mlx5_ifc_create_tis_out_bits {
1798         u8 status[0x8];
1799         u8 reserved_at_8[0x18];
1800         u8 syndrome[0x20];
1801         u8 reserved_at_40[0x8];
1802         u8 tisn[0x18];
1803         u8 reserved_at_60[0x20];
1804 };
1805
1806 struct mlx5_ifc_create_tis_in_bits {
1807         u8 opcode[0x10];
1808         u8 uid[0x10];
1809         u8 reserved_at_20[0x10];
1810         u8 op_mod[0x10];
1811         u8 reserved_at_40[0xc0];
1812         struct mlx5_ifc_tisc_bits ctx;
1813 };
1814
1815 enum {
1816         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1817         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1818         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1819         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1820 };
1821
1822 struct mlx5_ifc_modify_rq_in_bits {
1823         u8 opcode[0x10];
1824         u8 uid[0x10];
1825         u8 reserved_at_20[0x10];
1826         u8 op_mod[0x10];
1827         u8 rq_state[0x4];
1828         u8 reserved_at_44[0x4];
1829         u8 rqn[0x18];
1830         u8 reserved_at_60[0x20];
1831         u8 modify_bitmask[0x40];
1832         u8 reserved_at_c0[0x40];
1833         struct mlx5_ifc_rqc_bits ctx;
1834 };
1835
1836 enum {
1837         MLX5_L3_PROT_TYPE_IPV4 = 0,
1838         MLX5_L3_PROT_TYPE_IPV6 = 1,
1839 };
1840
1841 enum {
1842         MLX5_L4_PROT_TYPE_TCP = 0,
1843         MLX5_L4_PROT_TYPE_UDP = 1,
1844 };
1845
1846 enum {
1847         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1848         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1849         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1850         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1851         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1852 };
1853
1854 struct mlx5_ifc_rx_hash_field_select_bits {
1855         u8 l3_prot_type[0x1];
1856         u8 l4_prot_type[0x1];
1857         u8 selected_fields[0x1e];
1858 };
1859
1860 enum {
1861         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1862         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1863 };
1864
1865 enum {
1866         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1867         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1868 };
1869
1870 enum {
1871         MLX5_RX_HASH_FN_NONE           = 0x0,
1872         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
1873         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
1874 };
1875
1876 enum {
1877         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
1878         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
1879 };
1880
1881 enum {
1882         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
1883         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
1884 };
1885
1886 struct mlx5_ifc_tirc_bits {
1887         u8 reserved_at_0[0x20];
1888         u8 disp_type[0x4];
1889         u8 reserved_at_24[0x1c];
1890         u8 reserved_at_40[0x40];
1891         u8 reserved_at_80[0x4];
1892         u8 lro_timeout_period_usecs[0x10];
1893         u8 lro_enable_mask[0x4];
1894         u8 lro_max_msg_sz[0x8];
1895         u8 reserved_at_a0[0x40];
1896         u8 reserved_at_e0[0x8];
1897         u8 inline_rqn[0x18];
1898         u8 rx_hash_symmetric[0x1];
1899         u8 reserved_at_101[0x1];
1900         u8 tunneled_offload_en[0x1];
1901         u8 reserved_at_103[0x5];
1902         u8 indirect_table[0x18];
1903         u8 rx_hash_fn[0x4];
1904         u8 reserved_at_124[0x2];
1905         u8 self_lb_block[0x2];
1906         u8 transport_domain[0x18];
1907         u8 rx_hash_toeplitz_key[10][0x20];
1908         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1909         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1910         u8 reserved_at_2c0[0x4c0];
1911 };
1912
1913 struct mlx5_ifc_create_tir_out_bits {
1914         u8 status[0x8];
1915         u8 reserved_at_8[0x18];
1916         u8 syndrome[0x20];
1917         u8 reserved_at_40[0x8];
1918         u8 tirn[0x18];
1919         u8 reserved_at_60[0x20];
1920 };
1921
1922 struct mlx5_ifc_create_tir_in_bits {
1923         u8 opcode[0x10];
1924         u8 uid[0x10];
1925         u8 reserved_at_20[0x10];
1926         u8 op_mod[0x10];
1927         u8 reserved_at_40[0xc0];
1928         struct mlx5_ifc_tirc_bits ctx;
1929 };
1930
1931 enum {
1932         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
1933         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
1934         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
1935         /* bit 3 - tunneled_offload_en modify not supported. */
1936         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
1937 };
1938
1939 struct mlx5_ifc_modify_tir_out_bits {
1940         u8 status[0x8];
1941         u8 reserved_at_8[0x18];
1942         u8 syndrome[0x20];
1943         u8 reserved_at_40[0x40];
1944 };
1945
1946 struct mlx5_ifc_modify_tir_in_bits {
1947         u8 opcode[0x10];
1948         u8 uid[0x10];
1949         u8 reserved_at_20[0x10];
1950         u8 op_mod[0x10];
1951         u8 reserved_at_40[0x8];
1952         u8 tirn[0x18];
1953         u8 reserved_at_60[0x20];
1954         u8 modify_bitmask[0x40];
1955         u8 reserved_at_c0[0x40];
1956         struct mlx5_ifc_tirc_bits ctx;
1957 };
1958
1959 enum {
1960         MLX5_INLINE_Q_TYPE_RQ = 0x0,
1961         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
1962 };
1963
1964 struct mlx5_ifc_rq_num_bits {
1965         u8 reserved_at_0[0x8];
1966         u8 rq_num[0x18];
1967 };
1968
1969 struct mlx5_ifc_rqtc_bits {
1970         u8 reserved_at_0[0xa5];
1971         u8 list_q_type[0x3];
1972         u8 reserved_at_a8[0x8];
1973         u8 rqt_max_size[0x10];
1974         u8 reserved_at_c0[0x10];
1975         u8 rqt_actual_size[0x10];
1976         u8 reserved_at_e0[0x6a0];
1977         struct mlx5_ifc_rq_num_bits rq_num[];
1978 };
1979
1980 struct mlx5_ifc_create_rqt_out_bits {
1981         u8 status[0x8];
1982         u8 reserved_at_8[0x18];
1983         u8 syndrome[0x20];
1984         u8 reserved_at_40[0x8];
1985         u8 rqtn[0x18];
1986         u8 reserved_at_60[0x20];
1987 };
1988
1989 #ifdef PEDANTIC
1990 #pragma GCC diagnostic ignored "-Wpedantic"
1991 #endif
1992 struct mlx5_ifc_create_rqt_in_bits {
1993         u8 opcode[0x10];
1994         u8 uid[0x10];
1995         u8 reserved_at_20[0x10];
1996         u8 op_mod[0x10];
1997         u8 reserved_at_40[0xc0];
1998         struct mlx5_ifc_rqtc_bits rqt_context;
1999 };
2000
2001 struct mlx5_ifc_modify_rqt_in_bits {
2002         u8 opcode[0x10];
2003         u8 uid[0x10];
2004         u8 reserved_at_20[0x10];
2005         u8 op_mod[0x10];
2006         u8 reserved_at_40[0x8];
2007         u8 rqtn[0x18];
2008         u8 reserved_at_60[0x20];
2009         u8 modify_bitmask[0x40];
2010         u8 reserved_at_c0[0x40];
2011         struct mlx5_ifc_rqtc_bits rqt_context;
2012 };
2013 #ifdef PEDANTIC
2014 #pragma GCC diagnostic error "-Wpedantic"
2015 #endif
2016
2017 struct mlx5_ifc_modify_rqt_out_bits {
2018         u8 status[0x8];
2019         u8 reserved_at_8[0x18];
2020         u8 syndrome[0x20];
2021         u8 reserved_at_40[0x40];
2022 };
2023
2024 enum {
2025         MLX5_SQC_STATE_RST  = 0x0,
2026         MLX5_SQC_STATE_RDY  = 0x1,
2027         MLX5_SQC_STATE_ERR  = 0x3,
2028 };
2029
2030 struct mlx5_ifc_sqc_bits {
2031         u8 rlky[0x1];
2032         u8 cd_master[0x1];
2033         u8 fre[0x1];
2034         u8 flush_in_error_en[0x1];
2035         u8 allow_multi_pkt_send_wqe[0x1];
2036         u8 min_wqe_inline_mode[0x3];
2037         u8 state[0x4];
2038         u8 reg_umr[0x1];
2039         u8 allow_swp[0x1];
2040         u8 hairpin[0x1];
2041         u8 non_wire[0x1];
2042         u8 static_sq_wq[0x1];
2043         u8 reserved_at_11[0xf];
2044         u8 reserved_at_20[0x8];
2045         u8 user_index[0x18];
2046         u8 reserved_at_40[0x8];
2047         u8 cqn[0x18];
2048         u8 reserved_at_60[0x8];
2049         u8 hairpin_peer_rq[0x18];
2050         u8 reserved_at_80[0x10];
2051         u8 hairpin_peer_vhca[0x10];
2052         u8 reserved_at_a0[0x50];
2053         u8 packet_pacing_rate_limit_index[0x10];
2054         u8 tis_lst_sz[0x10];
2055         u8 reserved_at_110[0x10];
2056         u8 reserved_at_120[0x40];
2057         u8 reserved_at_160[0x8];
2058         u8 tis_num_0[0x18];
2059         struct mlx5_ifc_wq_bits wq;
2060 };
2061
2062 struct mlx5_ifc_query_sq_in_bits {
2063         u8 opcode[0x10];
2064         u8 reserved_at_10[0x10];
2065         u8 reserved_at_20[0x10];
2066         u8 op_mod[0x10];
2067         u8 reserved_at_40[0x8];
2068         u8 sqn[0x18];
2069         u8 reserved_at_60[0x20];
2070 };
2071
2072 struct mlx5_ifc_modify_sq_out_bits {
2073         u8 status[0x8];
2074         u8 reserved_at_8[0x18];
2075         u8 syndrome[0x20];
2076         u8 reserved_at_40[0x40];
2077 };
2078
2079 struct mlx5_ifc_modify_sq_in_bits {
2080         u8 opcode[0x10];
2081         u8 uid[0x10];
2082         u8 reserved_at_20[0x10];
2083         u8 op_mod[0x10];
2084         u8 sq_state[0x4];
2085         u8 reserved_at_44[0x4];
2086         u8 sqn[0x18];
2087         u8 reserved_at_60[0x20];
2088         u8 modify_bitmask[0x40];
2089         u8 reserved_at_c0[0x40];
2090         struct mlx5_ifc_sqc_bits ctx;
2091 };
2092
2093 struct mlx5_ifc_create_sq_out_bits {
2094         u8 status[0x8];
2095         u8 reserved_at_8[0x18];
2096         u8 syndrome[0x20];
2097         u8 reserved_at_40[0x8];
2098         u8 sqn[0x18];
2099         u8 reserved_at_60[0x20];
2100 };
2101
2102 struct mlx5_ifc_create_sq_in_bits {
2103         u8 opcode[0x10];
2104         u8 uid[0x10];
2105         u8 reserved_at_20[0x10];
2106         u8 op_mod[0x10];
2107         u8 reserved_at_40[0xc0];
2108         struct mlx5_ifc_sqc_bits ctx;
2109 };
2110
2111 enum {
2112         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2113         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2114         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2115         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2116         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2117 };
2118
2119 struct mlx5_ifc_flow_meter_parameters_bits {
2120         u8         valid[0x1];                  // 00h
2121         u8         bucket_overflow[0x1];
2122         u8         start_color[0x2];
2123         u8         both_buckets_on_green[0x1];
2124         u8         meter_mode[0x2];
2125         u8         reserved_at_1[0x19];
2126         u8         reserved_at_2[0x20]; //04h
2127         u8         reserved_at_3[0x3];
2128         u8         cbs_exponent[0x5];           // 08h
2129         u8         cbs_mantissa[0x8];
2130         u8         reserved_at_4[0x3];
2131         u8         cir_exponent[0x5];
2132         u8         cir_mantissa[0x8];
2133         u8         reserved_at_5[0x20];         // 0Ch
2134         u8         reserved_at_6[0x3];
2135         u8         ebs_exponent[0x5];           // 10h
2136         u8         ebs_mantissa[0x8];
2137         u8         reserved_at_7[0x3];
2138         u8         eir_exponent[0x5];
2139         u8         eir_mantissa[0x8];
2140         u8         reserved_at_8[0x60];         // 14h-1Ch
2141 };
2142
2143 enum {
2144         MLX5_CQE_SIZE_64B = 0x0,
2145         MLX5_CQE_SIZE_128B = 0x1,
2146 };
2147
2148 struct mlx5_ifc_cqc_bits {
2149         u8 status[0x4];
2150         u8 as_notify[0x1];
2151         u8 initiator_src_dct[0x1];
2152         u8 dbr_umem_valid[0x1];
2153         u8 reserved_at_7[0x1];
2154         u8 cqe_sz[0x3];
2155         u8 cc[0x1];
2156         u8 reserved_at_c[0x1];
2157         u8 scqe_break_moderation_en[0x1];
2158         u8 oi[0x1];
2159         u8 cq_period_mode[0x2];
2160         u8 cqe_comp_en[0x1];
2161         u8 mini_cqe_res_format[0x2];
2162         u8 st[0x4];
2163         u8 reserved_at_18[0x1];
2164         u8 cqe_comp_layout[0x7];
2165         u8 dbr_umem_id[0x20];
2166         u8 reserved_at_40[0x14];
2167         u8 page_offset[0x6];
2168         u8 reserved_at_5a[0x2];
2169         u8 mini_cqe_res_format_ext[0x2];
2170         u8 cq_timestamp_format[0x2];
2171         u8 reserved_at_60[0x3];
2172         u8 log_cq_size[0x5];
2173         u8 uar_page[0x18];
2174         u8 reserved_at_80[0x4];
2175         u8 cq_period[0xc];
2176         u8 cq_max_count[0x10];
2177         u8 reserved_at_a0[0x18];
2178         u8 c_eqn[0x8];
2179         u8 reserved_at_c0[0x3];
2180         u8 log_page_size[0x5];
2181         u8 reserved_at_c8[0x18];
2182         u8 reserved_at_e0[0x20];
2183         u8 reserved_at_100[0x8];
2184         u8 last_notified_index[0x18];
2185         u8 reserved_at_120[0x8];
2186         u8 last_solicit_index[0x18];
2187         u8 reserved_at_140[0x8];
2188         u8 consumer_counter[0x18];
2189         u8 reserved_at_160[0x8];
2190         u8 producer_counter[0x18];
2191         u8 local_partition_id[0xc];
2192         u8 process_id[0x14];
2193         u8 reserved_at_1A0[0x20];
2194         u8 dbr_addr[0x40];
2195 };
2196
2197 struct mlx5_ifc_create_cq_out_bits {
2198         u8 status[0x8];
2199         u8 reserved_at_8[0x18];
2200         u8 syndrome[0x20];
2201         u8 reserved_at_40[0x8];
2202         u8 cqn[0x18];
2203         u8 reserved_at_60[0x20];
2204 };
2205
2206 struct mlx5_ifc_create_cq_in_bits {
2207         u8 opcode[0x10];
2208         u8 uid[0x10];
2209         u8 reserved_at_20[0x10];
2210         u8 op_mod[0x10];
2211         u8 reserved_at_40[0x40];
2212         struct mlx5_ifc_cqc_bits cq_context;
2213         u8 cq_umem_offset[0x40];
2214         u8 cq_umem_id[0x20];
2215         u8 cq_umem_valid[0x1];
2216         u8 reserved_at_2e1[0x1f];
2217         u8 reserved_at_300[0x580];
2218         u8 pas[];
2219 };
2220
2221 enum {
2222         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2223         MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2224         MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2225         MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2226 };
2227
2228 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2229         u8 opcode[0x10];
2230         u8 reserved_at_10[0x20];
2231         u8 obj_type[0x10];
2232         u8 obj_id[0x20];
2233         u8 reserved_at_60[0x20];
2234 };
2235
2236 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2237         u8 status[0x8];
2238         u8 reserved_at_8[0x18];
2239         u8 syndrome[0x20];
2240         u8 obj_id[0x20];
2241         u8 reserved_at_60[0x20];
2242 };
2243
2244 struct mlx5_ifc_virtio_q_counters_bits {
2245         u8 modify_field_select[0x40];
2246         u8 reserved_at_40[0x40];
2247         u8 received_desc[0x40];
2248         u8 completed_desc[0x40];
2249         u8 error_cqes[0x20];
2250         u8 bad_desc_errors[0x20];
2251         u8 exceed_max_chain[0x20];
2252         u8 invalid_buffer[0x20];
2253         u8 reserved_at_180[0x50];
2254 };
2255
2256 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2257         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2258         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2259 };
2260
2261 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2262         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2263         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2264 };
2265 enum {
2266         MLX5_VIRTQ_STATE_INIT = 0,
2267         MLX5_VIRTQ_STATE_RDY = 1,
2268         MLX5_VIRTQ_STATE_SUSPEND = 2,
2269         MLX5_VIRTQ_STATE_ERROR = 3,
2270 };
2271
2272 enum {
2273         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2274         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2275         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2276 };
2277
2278 struct mlx5_ifc_virtio_q_bits {
2279         u8 virtio_q_type[0x8];
2280         u8 reserved_at_8[0x5];
2281         u8 event_mode[0x3];
2282         u8 queue_index[0x10];
2283         u8 full_emulation[0x1];
2284         u8 virtio_version_1_0[0x1];
2285         u8 reserved_at_22[0x2];
2286         u8 offload_type[0x4];
2287         u8 event_qpn_or_msix[0x18];
2288         u8 doorbell_stride_idx[0x10];
2289         u8 queue_size[0x10];
2290         u8 device_emulation_id[0x20];
2291         u8 desc_addr[0x40];
2292         u8 used_addr[0x40];
2293         u8 available_addr[0x40];
2294         u8 virtio_q_mkey[0x20];
2295         u8 reserved_at_160[0x18];
2296         u8 error_type[0x8];
2297         u8 umem_1_id[0x20];
2298         u8 umem_1_size[0x20];
2299         u8 umem_1_offset[0x40];
2300         u8 umem_2_id[0x20];
2301         u8 umem_2_size[0x20];
2302         u8 umem_2_offset[0x40];
2303         u8 umem_3_id[0x20];
2304         u8 umem_3_size[0x20];
2305         u8 umem_3_offset[0x40];
2306         u8 counter_set_id[0x20];
2307         u8 reserved_at_320[0x8];
2308         u8 pd[0x18];
2309         u8 reserved_at_340[0xc0];
2310 };
2311
2312 struct mlx5_ifc_virtio_net_q_bits {
2313         u8 modify_field_select[0x40];
2314         u8 reserved_at_40[0x40];
2315         u8 tso_ipv4[0x1];
2316         u8 tso_ipv6[0x1];
2317         u8 tx_csum[0x1];
2318         u8 rx_csum[0x1];
2319         u8 reserved_at_84[0x6];
2320         u8 dirty_bitmap_dump_enable[0x1];
2321         u8 vhost_log_page[0x5];
2322         u8 reserved_at_90[0xc];
2323         u8 state[0x4];
2324         u8 reserved_at_a0[0x8];
2325         u8 tisn_or_qpn[0x18];
2326         u8 dirty_bitmap_mkey[0x20];
2327         u8 dirty_bitmap_size[0x20];
2328         u8 dirty_bitmap_addr[0x40];
2329         u8 hw_available_index[0x10];
2330         u8 hw_used_index[0x10];
2331         u8 reserved_at_160[0xa0];
2332         struct mlx5_ifc_virtio_q_bits virtio_q_context;
2333 };
2334
2335 struct mlx5_ifc_create_virtq_in_bits {
2336         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2337         struct mlx5_ifc_virtio_net_q_bits virtq;
2338 };
2339
2340 struct mlx5_ifc_query_virtq_out_bits {
2341         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2342         struct mlx5_ifc_virtio_net_q_bits virtq;
2343 };
2344
2345 struct mlx5_ifc_flow_hit_aso_bits {
2346         u8 modify_field_select[0x40];
2347         u8 reserved_at_40[0x48];
2348         u8 access_pd[0x18];
2349         u8 reserved_at_a0[0x160];
2350         u8 flag[0x200];
2351 };
2352
2353 struct mlx5_ifc_create_flow_hit_aso_in_bits {
2354         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2355         struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
2356 };
2357
2358 enum {
2359         MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
2360 };
2361
2362 enum {
2363         MLX5_QP_ST_RC = 0x0,
2364 };
2365
2366 enum {
2367         MLX5_QP_PM_MIGRATED = 0x3,
2368 };
2369
2370 enum {
2371         MLX5_NON_ZERO_RQ = 0x0,
2372         MLX5_SRQ_RQ = 0x1,
2373         MLX5_CRQ_RQ = 0x2,
2374         MLX5_ZERO_LEN_RQ = 0x3,
2375 };
2376
2377 struct mlx5_ifc_ads_bits {
2378         u8 fl[0x1];
2379         u8 free_ar[0x1];
2380         u8 reserved_at_2[0xe];
2381         u8 pkey_index[0x10];
2382         u8 reserved_at_20[0x8];
2383         u8 grh[0x1];
2384         u8 mlid[0x7];
2385         u8 rlid[0x10];
2386         u8 ack_timeout[0x5];
2387         u8 reserved_at_45[0x3];
2388         u8 src_addr_index[0x8];
2389         u8 reserved_at_50[0x4];
2390         u8 stat_rate[0x4];
2391         u8 hop_limit[0x8];
2392         u8 reserved_at_60[0x4];
2393         u8 tclass[0x8];
2394         u8 flow_label[0x14];
2395         u8 rgid_rip[16][0x8];
2396         u8 reserved_at_100[0x4];
2397         u8 f_dscp[0x1];
2398         u8 f_ecn[0x1];
2399         u8 reserved_at_106[0x1];
2400         u8 f_eth_prio[0x1];
2401         u8 ecn[0x2];
2402         u8 dscp[0x6];
2403         u8 udp_sport[0x10];
2404         u8 dei_cfi[0x1];
2405         u8 eth_prio[0x3];
2406         u8 sl[0x4];
2407         u8 vhca_port_num[0x8];
2408         u8 rmac_47_32[0x10];
2409         u8 rmac_31_0[0x20];
2410 };
2411
2412 struct mlx5_ifc_qpc_bits {
2413         u8 state[0x4];
2414         u8 lag_tx_port_affinity[0x4];
2415         u8 st[0x8];
2416         u8 reserved_at_10[0x3];
2417         u8 pm_state[0x2];
2418         u8 reserved_at_15[0x1];
2419         u8 req_e2e_credit_mode[0x2];
2420         u8 offload_type[0x4];
2421         u8 end_padding_mode[0x2];
2422         u8 reserved_at_1e[0x2];
2423         u8 wq_signature[0x1];
2424         u8 block_lb_mc[0x1];
2425         u8 atomic_like_write_en[0x1];
2426         u8 latency_sensitive[0x1];
2427         u8 reserved_at_24[0x1];
2428         u8 drain_sigerr[0x1];
2429         u8 reserved_at_26[0x2];
2430         u8 pd[0x18];
2431         u8 mtu[0x3];
2432         u8 log_msg_max[0x5];
2433         u8 reserved_at_48[0x1];
2434         u8 log_rq_size[0x4];
2435         u8 log_rq_stride[0x3];
2436         u8 no_sq[0x1];
2437         u8 log_sq_size[0x4];
2438         u8 reserved_at_55[0x6];
2439         u8 rlky[0x1];
2440         u8 ulp_stateless_offload_mode[0x4];
2441         u8 counter_set_id[0x8];
2442         u8 uar_page[0x18];
2443         u8 reserved_at_80[0x8];
2444         u8 user_index[0x18];
2445         u8 reserved_at_a0[0x3];
2446         u8 log_page_size[0x5];
2447         u8 remote_qpn[0x18];
2448         struct mlx5_ifc_ads_bits primary_address_path;
2449         struct mlx5_ifc_ads_bits secondary_address_path;
2450         u8 log_ack_req_freq[0x4];
2451         u8 reserved_at_384[0x4];
2452         u8 log_sra_max[0x3];
2453         u8 reserved_at_38b[0x2];
2454         u8 retry_count[0x3];
2455         u8 rnr_retry[0x3];
2456         u8 reserved_at_393[0x1];
2457         u8 fre[0x1];
2458         u8 cur_rnr_retry[0x3];
2459         u8 cur_retry_count[0x3];
2460         u8 reserved_at_39b[0x5];
2461         u8 reserved_at_3a0[0x20];
2462         u8 reserved_at_3c0[0x8];
2463         u8 next_send_psn[0x18];
2464         u8 reserved_at_3e0[0x8];
2465         u8 cqn_snd[0x18];
2466         u8 reserved_at_400[0x8];
2467         u8 deth_sqpn[0x18];
2468         u8 reserved_at_420[0x20];
2469         u8 reserved_at_440[0x8];
2470         u8 last_acked_psn[0x18];
2471         u8 reserved_at_460[0x8];
2472         u8 ssn[0x18];
2473         u8 reserved_at_480[0x8];
2474         u8 log_rra_max[0x3];
2475         u8 reserved_at_48b[0x1];
2476         u8 atomic_mode[0x4];
2477         u8 rre[0x1];
2478         u8 rwe[0x1];
2479         u8 rae[0x1];
2480         u8 reserved_at_493[0x1];
2481         u8 page_offset[0x6];
2482         u8 reserved_at_49a[0x3];
2483         u8 cd_slave_receive[0x1];
2484         u8 cd_slave_send[0x1];
2485         u8 cd_master[0x1];
2486         u8 reserved_at_4a0[0x3];
2487         u8 min_rnr_nak[0x5];
2488         u8 next_rcv_psn[0x18];
2489         u8 reserved_at_4c0[0x8];
2490         u8 xrcd[0x18];
2491         u8 reserved_at_4e0[0x8];
2492         u8 cqn_rcv[0x18];
2493         u8 dbr_addr[0x40];
2494         u8 q_key[0x20];
2495         u8 reserved_at_560[0x5];
2496         u8 rq_type[0x3];
2497         u8 srqn_rmpn_xrqn[0x18];
2498         u8 reserved_at_580[0x8];
2499         u8 rmsn[0x18];
2500         u8 hw_sq_wqebb_counter[0x10];
2501         u8 sw_sq_wqebb_counter[0x10];
2502         u8 hw_rq_counter[0x20];
2503         u8 sw_rq_counter[0x20];
2504         u8 reserved_at_600[0x20];
2505         u8 reserved_at_620[0xf];
2506         u8 cgs[0x1];
2507         u8 cs_req[0x8];
2508         u8 cs_res[0x8];
2509         u8 dc_access_key[0x40];
2510         u8 reserved_at_680[0x3];
2511         u8 dbr_umem_valid[0x1];
2512         u8 reserved_at_684[0x9c];
2513         u8 dbr_umem_id[0x20];
2514 };
2515
2516 struct mlx5_ifc_create_qp_out_bits {
2517         u8 status[0x8];
2518         u8 reserved_at_8[0x18];
2519         u8 syndrome[0x20];
2520         u8 reserved_at_40[0x8];
2521         u8 qpn[0x18];
2522         u8 reserved_at_60[0x20];
2523 };
2524
2525 #ifdef PEDANTIC
2526 #pragma GCC diagnostic ignored "-Wpedantic"
2527 #endif
2528 struct mlx5_ifc_create_qp_in_bits {
2529         u8 opcode[0x10];
2530         u8 uid[0x10];
2531         u8 reserved_at_20[0x10];
2532         u8 op_mod[0x10];
2533         u8 reserved_at_40[0x40];
2534         u8 opt_param_mask[0x20];
2535         u8 reserved_at_a0[0x20];
2536         struct mlx5_ifc_qpc_bits qpc;
2537         u8 wq_umem_offset[0x40];
2538         u8 wq_umem_id[0x20];
2539         u8 wq_umem_valid[0x1];
2540         u8 reserved_at_861[0x1f];
2541         u8 pas[0][0x40];
2542 };
2543 #ifdef PEDANTIC
2544 #pragma GCC diagnostic error "-Wpedantic"
2545 #endif
2546
2547 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2548         u8 status[0x8];
2549         u8 reserved_at_8[0x18];
2550         u8 syndrome[0x20];
2551         u8 reserved_at_40[0x40];
2552 };
2553
2554 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2555         u8 opcode[0x10];
2556         u8 uid[0x10];
2557         u8 reserved_at_20[0x10];
2558         u8 op_mod[0x10];
2559         u8 reserved_at_40[0x8];
2560         u8 qpn[0x18];
2561         u8 reserved_at_60[0x20];
2562         u8 opt_param_mask[0x20];
2563         u8 reserved_at_a0[0x20];
2564         struct mlx5_ifc_qpc_bits qpc;
2565         u8 reserved_at_800[0x80];
2566 };
2567
2568 struct mlx5_ifc_sqd2rts_qp_out_bits {
2569         u8 status[0x8];
2570         u8 reserved_at_8[0x18];
2571         u8 syndrome[0x20];
2572         u8 reserved_at_40[0x40];
2573 };
2574
2575 struct mlx5_ifc_sqd2rts_qp_in_bits {
2576         u8 opcode[0x10];
2577         u8 uid[0x10];
2578         u8 reserved_at_20[0x10];
2579         u8 op_mod[0x10];
2580         u8 reserved_at_40[0x8];
2581         u8 qpn[0x18];
2582         u8 reserved_at_60[0x20];
2583         u8 opt_param_mask[0x20];
2584         u8 reserved_at_a0[0x20];
2585         struct mlx5_ifc_qpc_bits qpc;
2586         u8 reserved_at_800[0x80];
2587 };
2588
2589 struct mlx5_ifc_rts2rts_qp_out_bits {
2590         u8 status[0x8];
2591         u8 reserved_at_8[0x18];
2592         u8 syndrome[0x20];
2593         u8 reserved_at_40[0x40];
2594 };
2595
2596 struct mlx5_ifc_rts2rts_qp_in_bits {
2597         u8 opcode[0x10];
2598         u8 uid[0x10];
2599         u8 reserved_at_20[0x10];
2600         u8 op_mod[0x10];
2601         u8 reserved_at_40[0x8];
2602         u8 qpn[0x18];
2603         u8 reserved_at_60[0x20];
2604         u8 opt_param_mask[0x20];
2605         u8 reserved_at_a0[0x20];
2606         struct mlx5_ifc_qpc_bits qpc;
2607         u8 reserved_at_800[0x80];
2608 };
2609
2610 struct mlx5_ifc_rtr2rts_qp_out_bits {
2611         u8 status[0x8];
2612         u8 reserved_at_8[0x18];
2613         u8 syndrome[0x20];
2614         u8 reserved_at_40[0x40];
2615 };
2616
2617 struct mlx5_ifc_rtr2rts_qp_in_bits {
2618         u8 opcode[0x10];
2619         u8 uid[0x10];
2620         u8 reserved_at_20[0x10];
2621         u8 op_mod[0x10];
2622         u8 reserved_at_40[0x8];
2623         u8 qpn[0x18];
2624         u8 reserved_at_60[0x20];
2625         u8 opt_param_mask[0x20];
2626         u8 reserved_at_a0[0x20];
2627         struct mlx5_ifc_qpc_bits qpc;
2628         u8 reserved_at_800[0x80];
2629 };
2630
2631 struct mlx5_ifc_rst2init_qp_out_bits {
2632         u8 status[0x8];
2633         u8 reserved_at_8[0x18];
2634         u8 syndrome[0x20];
2635         u8 reserved_at_40[0x40];
2636 };
2637
2638 struct mlx5_ifc_rst2init_qp_in_bits {
2639         u8 opcode[0x10];
2640         u8 uid[0x10];
2641         u8 reserved_at_20[0x10];
2642         u8 op_mod[0x10];
2643         u8 reserved_at_40[0x8];
2644         u8 qpn[0x18];
2645         u8 reserved_at_60[0x20];
2646         u8 opt_param_mask[0x20];
2647         u8 reserved_at_a0[0x20];
2648         struct mlx5_ifc_qpc_bits qpc;
2649         u8 reserved_at_800[0x80];
2650 };
2651
2652 struct mlx5_ifc_init2rtr_qp_out_bits {
2653         u8 status[0x8];
2654         u8 reserved_at_8[0x18];
2655         u8 syndrome[0x20];
2656         u8 reserved_at_40[0x40];
2657 };
2658
2659 struct mlx5_ifc_init2rtr_qp_in_bits {
2660         u8 opcode[0x10];
2661         u8 uid[0x10];
2662         u8 reserved_at_20[0x10];
2663         u8 op_mod[0x10];
2664         u8 reserved_at_40[0x8];
2665         u8 qpn[0x18];
2666         u8 reserved_at_60[0x20];
2667         u8 opt_param_mask[0x20];
2668         u8 reserved_at_a0[0x20];
2669         struct mlx5_ifc_qpc_bits qpc;
2670         u8 reserved_at_800[0x80];
2671 };
2672
2673 struct mlx5_ifc_init2init_qp_out_bits {
2674         u8 status[0x8];
2675         u8 reserved_at_8[0x18];
2676         u8 syndrome[0x20];
2677         u8 reserved_at_40[0x40];
2678 };
2679
2680 struct mlx5_ifc_init2init_qp_in_bits {
2681         u8 opcode[0x10];
2682         u8 uid[0x10];
2683         u8 reserved_at_20[0x10];
2684         u8 op_mod[0x10];
2685         u8 reserved_at_40[0x8];
2686         u8 qpn[0x18];
2687         u8 reserved_at_60[0x20];
2688         u8 opt_param_mask[0x20];
2689         u8 reserved_at_a0[0x20];
2690         struct mlx5_ifc_qpc_bits qpc;
2691         u8 reserved_at_800[0x80];
2692 };
2693
2694 #ifdef PEDANTIC
2695 #pragma GCC diagnostic ignored "-Wpedantic"
2696 #endif
2697 struct mlx5_ifc_query_qp_out_bits {
2698         u8 status[0x8];
2699         u8 reserved_at_8[0x18];
2700         u8 syndrome[0x20];
2701         u8 reserved_at_40[0x40];
2702         u8 opt_param_mask[0x20];
2703         u8 reserved_at_a0[0x20];
2704         struct mlx5_ifc_qpc_bits qpc;
2705         u8 reserved_at_800[0x80];
2706         u8 pas[0][0x40];
2707 };
2708 #ifdef PEDANTIC
2709 #pragma GCC diagnostic error "-Wpedantic"
2710 #endif
2711
2712 struct mlx5_ifc_query_qp_in_bits {
2713         u8 opcode[0x10];
2714         u8 reserved_at_10[0x10];
2715         u8 reserved_at_20[0x10];
2716         u8 op_mod[0x10];
2717         u8 reserved_at_40[0x8];
2718         u8 qpn[0x18];
2719         u8 reserved_at_60[0x20];
2720 };
2721
2722 enum {
2723         MLX5_DATA_RATE = 0x0,
2724         MLX5_WQE_RATE = 0x1,
2725 };
2726
2727 struct mlx5_ifc_set_pp_rate_limit_context_bits {
2728         u8 rate_limit[0x20];
2729         u8 burst_upper_bound[0x20];
2730         u8 reserved_at_40[0xC];
2731         u8 rate_mode[0x4];
2732         u8 typical_packet_size[0x10];
2733         u8 reserved_at_60[0x120];
2734 };
2735
2736 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
2737
2738 #ifdef PEDANTIC
2739 #pragma GCC diagnostic ignored "-Wpedantic"
2740 #endif
2741 struct mlx5_ifc_access_register_out_bits {
2742         u8 status[0x8];
2743         u8 reserved_at_8[0x18];
2744         u8 syndrome[0x20];
2745         u8 reserved_at_40[0x40];
2746         u8 register_data[0][0x20];
2747 };
2748
2749 struct mlx5_ifc_access_register_in_bits {
2750         u8 opcode[0x10];
2751         u8 reserved_at_10[0x10];
2752         u8 reserved_at_20[0x10];
2753         u8 op_mod[0x10];
2754         u8 reserved_at_40[0x10];
2755         u8 register_id[0x10];
2756         u8 argument[0x20];
2757         u8 register_data[0][0x20];
2758 };
2759 #ifdef PEDANTIC
2760 #pragma GCC diagnostic error "-Wpedantic"
2761 #endif
2762
2763 enum {
2764         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
2765         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
2766 };
2767
2768 enum {
2769         MLX5_REGISTER_ID_MTUTC  = 0x9055,
2770 };
2771
2772 struct mlx5_ifc_register_mtutc_bits {
2773         u8 time_stamp_mode[0x2];
2774         u8 time_stamp_state[0x2];
2775         u8 reserved_at_4[0x18];
2776         u8 operation[0x4];
2777         u8 freq_adjustment[0x20];
2778         u8 reserved_at_40[0x40];
2779         u8 utc_sec[0x20];
2780         u8 utc_nsec[0x20];
2781         u8 time_adjustment[0x20];
2782 };
2783
2784 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
2785 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
2786
2787 struct mlx5_ifc_parse_graph_arc_bits {
2788         u8 start_inner_tunnel[0x1];
2789         u8 reserved_at_1[0x7];
2790         u8 arc_parse_graph_node[0x8];
2791         u8 compare_condition_value[0x10];
2792         u8 parse_graph_node_handle[0x20];
2793         u8 reserved_at_40[0x40];
2794 };
2795
2796 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
2797         u8 flow_match_sample_en[0x1];
2798         u8 reserved_at_1[0x3];
2799         u8 flow_match_sample_offset_mode[0x4];
2800         u8 reserved_at_5[0x8];
2801         u8 flow_match_sample_field_offset[0x10];
2802         u8 reserved_at_32[0x4];
2803         u8 flow_match_sample_field_offset_shift[0x4];
2804         u8 flow_match_sample_field_base_offset[0x8];
2805         u8 reserved_at_48[0xd];
2806         u8 flow_match_sample_tunnel_mode[0x3];
2807         u8 flow_match_sample_field_offset_mask[0x20];
2808         u8 flow_match_sample_field_id[0x20];
2809 };
2810
2811 struct mlx5_ifc_parse_graph_flex_bits {
2812         u8 modify_field_select[0x40];
2813         u8 reserved_at_64[0x20];
2814         u8 header_length_base_value[0x10];
2815         u8 reserved_at_112[0x4];
2816         u8 header_length_field_shift[0x4];
2817         u8 reserved_at_120[0x4];
2818         u8 header_length_mode[0x4];
2819         u8 header_length_field_offset[0x10];
2820         u8 next_header_field_offset[0x10];
2821         u8 reserved_at_160[0x1b];
2822         u8 next_header_field_size[0x5];
2823         u8 header_length_field_mask[0x20];
2824         u8 reserved_at_224[0x20];
2825         struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
2826         struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
2827         struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
2828 };
2829
2830 struct mlx5_ifc_create_flex_parser_in_bits {
2831         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2832         struct mlx5_ifc_parse_graph_flex_bits flex;
2833 };
2834
2835 struct mlx5_ifc_create_flex_parser_out_bits {
2836         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2837         struct mlx5_ifc_parse_graph_flex_bits flex;
2838 };
2839
2840 struct mlx5_ifc_parse_graph_flex_out_bits {
2841         u8 status[0x8];
2842         u8 reserved_at_8[0x18];
2843         u8 syndrome[0x20];
2844         u8 reserved_at_40[0x40];
2845         struct mlx5_ifc_parse_graph_flex_bits capability;
2846 };
2847
2848 struct regexp_params_field_select_bits {
2849         u8 reserved_at_0[0x1e];
2850         u8 stop_engine[0x1];
2851         u8 db_umem_id[0x1];
2852 };
2853
2854 struct mlx5_ifc_regexp_params_bits {
2855         u8 reserved_at_0[0x1f];
2856         u8 stop_engine[0x1];
2857         u8 db_umem_id[0x20];
2858         u8 db_umem_offset[0x40];
2859         u8 reserved_at_80[0x100];
2860 };
2861
2862 struct mlx5_ifc_set_regexp_params_in_bits {
2863         u8 opcode[0x10];
2864         u8 uid[0x10];
2865         u8 reserved_at_20[0x10];
2866         u8 op_mod[0x10];
2867         u8 reserved_at_40[0x18];
2868         u8 engine_id[0x8];
2869         struct regexp_params_field_select_bits field_select;
2870         struct mlx5_ifc_regexp_params_bits regexp_params;
2871 };
2872
2873 struct mlx5_ifc_set_regexp_params_out_bits {
2874         u8 status[0x8];
2875         u8 reserved_at_8[0x18];
2876         u8 syndrome[0x20];
2877         u8 reserved_at_18[0x40];
2878 };
2879
2880 struct mlx5_ifc_query_regexp_params_in_bits {
2881         u8 opcode[0x10];
2882         u8 uid[0x10];
2883         u8 reserved_at_20[0x10];
2884         u8 op_mod[0x10];
2885         u8 reserved_at_40[0x18];
2886         u8 engine_id[0x8];
2887         u8 reserved[0x20];
2888 };
2889
2890 struct mlx5_ifc_query_regexp_params_out_bits {
2891         u8 status[0x8];
2892         u8 reserved_at_8[0x18];
2893         u8 syndrome[0x20];
2894         u8 reserved[0x40];
2895         struct mlx5_ifc_regexp_params_bits regexp_params;
2896 };
2897
2898 struct mlx5_ifc_set_regexp_register_in_bits {
2899         u8 opcode[0x10];
2900         u8 uid[0x10];
2901         u8 reserved_at_20[0x10];
2902         u8 op_mod[0x10];
2903         u8 reserved_at_40[0x18];
2904         u8 engine_id[0x8];
2905         u8 register_address[0x20];
2906         u8 register_data[0x20];
2907         u8 reserved[0x60];
2908 };
2909
2910 struct mlx5_ifc_set_regexp_register_out_bits {
2911         u8 status[0x8];
2912         u8 reserved_at_8[0x18];
2913         u8 syndrome[0x20];
2914         u8 reserved[0x40];
2915 };
2916
2917 struct mlx5_ifc_query_regexp_register_in_bits {
2918         u8 opcode[0x10];
2919         u8 uid[0x10];
2920         u8 reserved_at_20[0x10];
2921         u8 op_mod[0x10];
2922         u8 reserved_at_40[0x18];
2923         u8 engine_id[0x8];
2924         u8 register_address[0x20];
2925 };
2926
2927 struct mlx5_ifc_query_regexp_register_out_bits {
2928         u8 status[0x8];
2929         u8 reserved_at_8[0x18];
2930         u8 syndrome[0x20];
2931         u8 reserved[0x20];
2932         u8 register_data[0x20];
2933 };
2934
2935 /* CQE format mask. */
2936 #define MLX5E_CQE_FORMAT_MASK 0xc
2937
2938 /* MPW opcode. */
2939 #define MLX5_OPC_MOD_MPW 0x01
2940
2941 /* Compressed Rx CQE structure. */
2942 struct mlx5_mini_cqe8 {
2943         union {
2944                 uint32_t rx_hash_result;
2945                 struct {
2946                         union {
2947                                 uint16_t checksum;
2948                                 uint16_t flow_tag_high;
2949                                 struct {
2950                                         uint8_t reserved;
2951                                         uint8_t hdr_type;
2952                                 };
2953                         };
2954                         uint16_t stride_idx;
2955                 };
2956                 struct {
2957                         uint16_t wqe_counter;
2958                         uint8_t  s_wqe_opcode;
2959                         uint8_t  reserved;
2960                 } s_wqe_info;
2961         };
2962         union {
2963                 uint32_t byte_cnt_flow;
2964                 uint32_t byte_cnt;
2965         };
2966 };
2967
2968 /* Mini CQE responder format. */
2969 enum {
2970         MLX5_CQE_RESP_FORMAT_HASH = 0x0,
2971         MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
2972         MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
2973         MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
2974         MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
2975 };
2976
2977 /* srTCM PRM flow meter parameters. */
2978 enum {
2979         MLX5_FLOW_COLOR_RED = 0,
2980         MLX5_FLOW_COLOR_YELLOW,
2981         MLX5_FLOW_COLOR_GREEN,
2982         MLX5_FLOW_COLOR_UNDEFINED,
2983 };
2984
2985 /* Maximum value of srTCM metering parameters. */
2986 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
2987 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
2988 #define MLX5_SRTCM_EBS_MAX 0
2989
2990 /* The bits meter color use. */
2991 #define MLX5_MTR_COLOR_BITS 8
2992
2993 /* Length mode of dynamic flex parser graph node. */
2994 enum mlx5_parse_graph_node_len_mode {
2995         MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
2996         MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
2997         MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
2998 };
2999
3000 /* Offset mode of the samples of flex parser. */
3001 enum mlx5_parse_graph_flow_match_sample_offset_mode {
3002         MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
3003         MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
3004         MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
3005 };
3006
3007 /* Node index for an input / output arc of the flex parser graph. */
3008 enum mlx5_parse_graph_arc_node_index {
3009         MLX5_GRAPH_ARC_NODE_NULL = 0x0,
3010         MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
3011         MLX5_GRAPH_ARC_NODE_MAC = 0x2,
3012         MLX5_GRAPH_ARC_NODE_IP = 0x3,
3013         MLX5_GRAPH_ARC_NODE_GRE = 0x4,
3014         MLX5_GRAPH_ARC_NODE_UDP = 0x5,
3015         MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
3016         MLX5_GRAPH_ARC_NODE_TCP = 0x7,
3017         MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
3018         MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
3019         MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
3020         MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
3021 };
3022
3023 /**
3024  * Convert a user mark to flow mark.
3025  *
3026  * @param val
3027  *   Mark value to convert.
3028  *
3029  * @return
3030  *   Converted mark value.
3031  */
3032 static inline uint32_t
3033 mlx5_flow_mark_set(uint32_t val)
3034 {
3035         uint32_t ret;
3036
3037         /*
3038          * Add one to the user value to differentiate un-marked flows from
3039          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
3040          * remains untouched.
3041          */
3042         if (val != MLX5_FLOW_MARK_DEFAULT)
3043                 ++val;
3044 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3045         /*
3046          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
3047          * word, byte-swapped by the kernel on little-endian systems. In this
3048          * case, left-shifting the resulting big-endian value ensures the
3049          * least significant 24 bits are retained when converting it back.
3050          */
3051         ret = rte_cpu_to_be_32(val) >> 8;
3052 #else
3053         ret = val;
3054 #endif
3055         return ret;
3056 }
3057
3058 /**
3059  * Convert a mark to user mark.
3060  *
3061  * @param val
3062  *   Mark value to convert.
3063  *
3064  * @return
3065  *   Converted mark value.
3066  */
3067 static inline uint32_t
3068 mlx5_flow_mark_get(uint32_t val)
3069 {
3070         /*
3071          * Subtract one from the retrieved value. It was added by
3072          * mlx5_flow_mark_set() to distinguish unmarked flows.
3073          */
3074 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3075         return (val >> 8) - 1;
3076 #else
3077         return val - 1;
3078 #endif
3079 }
3080
3081 #endif /* RTE_PMD_MLX5_PRM_H_ */