drivers/common/mlx5/mlx5_prm.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #ifndef RTE_PMD_MLX5_PRM_H_
   7 #define RTE_PMD_MLX5_PRM_H_
   8
   9 /* Verbs header. */
  10 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
  11 #ifdef PEDANTIC
  12 #pragma GCC diagnostic ignored "-Wpedantic"
  13 #endif
  14 #include <infiniband/mlx5dv.h>
  15 #ifdef PEDANTIC
  16 #pragma GCC diagnostic error "-Wpedantic"
  17 #endif
  18
  19 #include <rte_vect.h>
  20 #include <rte_byteorder.h>
  21
  22 #include "mlx5_autoconf.h"
  23
  24 /* RSS hash key size. */
  25 #define MLX5_RSS_HASH_KEY_LEN 40
  26
  27 /* Get CQE owner bit. */
  28 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
  29
  30 /* Get CQE format. */
  31 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
  32
  33 /* Get CQE opcode. */
  34 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
  35
  36 /* Get CQE solicited event. */
  37 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
  38
  39 /* Invalidate a CQE. */
  40 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
  41
  42 /* WQE Segment sizes in bytes. */
  43 #define MLX5_WSEG_SIZE 16u
  44 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
  45 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
  46 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
  47
  48 /* WQE/WQEBB size in bytes. */
  49 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
  50
  51 /*
  52  * Max size of a WQE session.
  53  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
  54  * the WQE size field in Control Segment is 6 bits wide.
  55  */
  56 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
  57
  58 /*
  59  * Default minimum number of Tx queues for inlining packets.
  60  * If there are less queues as specified we assume we have
  61  * no enough CPU resources (cycles) to perform inlining,
  62  * the PCIe throughput is not supposed as bottleneck and
  63  * inlining is disabled.
  64  */
  65 #define MLX5_INLINE_MAX_TXQS 8u
  66 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
  67
  68 /*
  69  * Default packet length threshold to be inlined with
  70  * enhanced MPW. If packet length exceeds the threshold
  71  * the data are not inlined. Should be aligned in WQEBB
  72  * boundary with accounting the title Control and Ethernet
  73  * segments.
  74  */
  75 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
  76                                   MLX5_DSEG_MIN_INLINE_SIZE)
  77 /*
  78  * Maximal inline data length sent with enhanced MPW.
  79  * Is based on maximal WQE size.
  80  */
  81 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
  82                                   MLX5_WQE_CSEG_SIZE - \
  83                                   MLX5_WQE_ESEG_SIZE - \
  84                                   MLX5_WQE_DSEG_SIZE + \
  85                                   MLX5_DSEG_MIN_INLINE_SIZE)
  86 /*
  87  * Minimal amount of packets to be sent with EMPW.
  88  * This limits the minimal required size of sent EMPW.
  89  * If there are no enough resources to built minimal
  90  * EMPW the sending loop exits.
  91  */
  92 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
  93 /*
  94  * Maximal amount of packets to be sent with EMPW.
  95  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
  96  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
  97  * without CQE generation request, being multiplied by
  98  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
  99  * in tx burst routine at the moment of freeing multiple mbufs.
 100  */
 101 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
 102 #define MLX5_MPW_MAX_PACKETS 6
 103 #define MLX5_MPW_INLINE_MAX_PACKETS 6
 104
 105 /*
 106  * Default packet length threshold to be inlined with
 107  * ordinary SEND. Inlining saves the MR key search
 108  * and extra PCIe data fetch transaction, but eats the
 109  * CPU cycles.
 110  */
 111 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
 112                                   MLX5_ESEG_MIN_INLINE_SIZE - \
 113                                   MLX5_WQE_CSEG_SIZE - \
 114                                   MLX5_WQE_ESEG_SIZE - \
 115                                   MLX5_WQE_DSEG_SIZE)
 116 /*
 117  * Maximal inline data length sent with ordinary SEND.
 118  * Is based on maximal WQE size.
 119  */
 120 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
 121                                   MLX5_WQE_CSEG_SIZE - \
 122                                   MLX5_WQE_ESEG_SIZE - \
 123                                   MLX5_WQE_DSEG_SIZE + \
 124                                   MLX5_ESEG_MIN_INLINE_SIZE)
 125
 126 /* Missed in mlv5dv.h, should define here. */
 127 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 128
 129 /* CQE value to inform that VLAN is stripped. */
 130 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 131
 132 /* IPv4 options. */
 133 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
 134
 135 /* IPv6 packet. */
 136 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
 137
 138 /* IPv4 packet. */
 139 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
 140
 141 /* TCP packet. */
 142 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
 143
 144 /* UDP packet. */
 145 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
 146
 147 /* IP is fragmented. */
 148 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
 149
 150 /* L2 header is valid. */
 151 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
 152
 153 /* L3 header is valid. */
 154 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
 155
 156 /* L4 header is valid. */
 157 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
 158
 159 /* Outer packet, 0 IPv4, 1 IPv6. */
 160 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
 161
 162 /* Tunnel packet bit in the CQE. */
 163 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 164
 165 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
 166 #define MLX5_CQE_LRO_PUSH_MASK 0x40
 167
 168 /* Mask for L4 type in the CQE hdr_type_etc field. */
 169 #define MLX5_CQE_L4_TYPE_MASK 0x70
 170
 171 /* The bit index of L4 type in CQE hdr_type_etc field. */
 172 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
 173
 174 /* L4 type to indicate TCP packet without acknowledgment. */
 175 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
 176
 177 /* L4 type to indicate TCP packet with acknowledgment. */
 178 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
 179
 180 /* Inner L3 checksum offload (Tunneled packets only). */
 181 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 182
 183 /* Inner L4 checksum offload (Tunneled packets only). */
 184 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
 185
 186 /* Outer L4 type is TCP. */
 187 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
 188
 189 /* Outer L4 type is UDP. */
 190 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
 191
 192 /* Outer L3 type is IPV4. */
 193 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
 194
 195 /* Outer L3 type is IPV6. */
 196 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
 197
 198 /* Inner L4 type is TCP. */
 199 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
 200
 201 /* Inner L4 type is UDP. */
 202 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
 203
 204 /* Inner L3 type is IPV4. */
 205 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
 206
 207 /* Inner L3 type is IPV6. */
 208 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
 209
 210 /* VLAN insertion flag. */
 211 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
 212
 213 /* Data inline segment flag. */
 214 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
 215
 216 /* Is flow mark valid. */
 217 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 218 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
 219 #else
 220 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
 221 #endif
 222
 223 /* INVALID is used by packets matching no flow rules. */
 224 #define MLX5_FLOW_MARK_INVALID 0
 225
 226 /* Maximum allowed value to mark a packet. */
 227 #define MLX5_FLOW_MARK_MAX 0xfffff0
 228
 229 /* Default mark value used when none is provided. */
 230 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
 231
 232 /* Default mark mask for metadata legacy mode. */
 233 #define MLX5_FLOW_MARK_MASK 0xffffff
 234
 235 /* Maximum number of DS in WQE. Limited by 6-bit field. */
 236 #define MLX5_DSEG_MAX 63
 237
 238 /* The completion mode offset in the WQE control segment line 2. */
 239 #define MLX5_COMP_MODE_OFFSET 2
 240
 241 /* Amount of data bytes in minimal inline data segment. */
 242 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
 243
 244 /* Amount of data bytes in minimal inline eth segment. */
 245 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
 246
 247 /* Amount of data bytes after eth data segment. */
 248 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 249
 250 /* The maximum log value of segments per RQ WQE. */
 251 #define MLX5_MAX_LOG_RQ_SEGS 5u
 252
 253 /* The alignment needed for WQ buffer. */
 254 #define MLX5_WQE_BUF_ALIGNMENT 512
 255
 256 /* Completion mode. */
 257 enum mlx5_completion_mode {
 258         MLX5_COMP_ONLY_ERR = 0x0,
 259         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
 260         MLX5_COMP_ALWAYS = 0x2,
 261         MLX5_COMP_CQE_AND_EQE = 0x3,
 262 };
 263
 264 /* MPW mode. */
 265 enum mlx5_mpw_mode {
 266         MLX5_MPW_DISABLED,
 267         MLX5_MPW,
 268         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
 269 };
 270
 271 /* WQE Control segment. */
 272 struct mlx5_wqe_cseg {
 273         uint32_t opcode;
 274         uint32_t sq_ds;
 275         uint32_t flags;
 276         uint32_t misc;
 277 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 278
 279 /* Header of data segment. Minimal size Data Segment */
 280 struct mlx5_wqe_dseg {
 281         uint32_t bcount;
 282         union {
 283                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
 284                 struct {
 285                         uint32_t lkey;
 286                         uint64_t pbuf;
 287                 } __rte_packed;
 288         };
 289 } __rte_packed;
 290
 291 /* Subset of struct WQE Ethernet Segment. */
 292 struct mlx5_wqe_eseg {
 293         union {
 294                 struct {
 295                         uint32_t swp_offs;
 296                         uint8_t cs_flags;
 297                         uint8_t swp_flags;
 298                         uint16_t mss;
 299                         uint32_t metadata;
 300                         uint16_t inline_hdr_sz;
 301                         union {
 302                                 uint16_t inline_data;
 303                                 uint16_t vlan_tag;
 304                         };
 305                 } __rte_packed;
 306                 struct {
 307                         uint32_t offsets;
 308                         uint32_t flags;
 309                         uint32_t flow_metadata;
 310                         uint32_t inline_hdr;
 311                 } __rte_packed;
 312         };
 313 } __rte_packed;
 314
 315 /* The title WQEBB, header of WQE. */
 316 struct mlx5_wqe {
 317         union {
 318                 struct mlx5_wqe_cseg cseg;
 319                 uint32_t ctrl[4];
 320         };
 321         struct mlx5_wqe_eseg eseg;
 322         union {
 323                 struct mlx5_wqe_dseg dseg[2];
 324                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
 325         };
 326 } __rte_packed;
 327
 328 /* WQE for Multi-Packet RQ. */
 329 struct mlx5_wqe_mprq {
 330         struct mlx5_wqe_srq_next_seg next_seg;
 331         struct mlx5_wqe_data_seg dseg;
 332 };
 333
 334 #define MLX5_MPRQ_LEN_MASK 0x000ffff
 335 #define MLX5_MPRQ_LEN_SHIFT 0
 336 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
 337 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
 338 #define MLX5_MPRQ_FILLER_MASK 0x80000000
 339 #define MLX5_MPRQ_FILLER_SHIFT 31
 340
 341 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
 342
 343 /* CQ element structure - should be equal to the cache line size */
 344 struct mlx5_cqe {
 345 #if (RTE_CACHE_LINE_SIZE == 128)
 346         uint8_t padding[64];
 347 #endif
 348         uint8_t pkt_info;
 349         uint8_t rsvd0;
 350         uint16_t wqe_id;
 351         uint8_t lro_tcppsh_abort_dupack;
 352         uint8_t lro_min_ttl;
 353         uint16_t lro_tcp_win;
 354         uint32_t lro_ack_seq_num;
 355         uint32_t rx_hash_res;
 356         uint8_t rx_hash_type;
 357         uint8_t rsvd1[3];
 358         uint16_t csum;
 359         uint8_t rsvd2[6];
 360         uint16_t hdr_type_etc;
 361         uint16_t vlan_info;
 362         uint8_t lro_num_seg;
 363         uint8_t rsvd3[3];
 364         uint32_t flow_table_metadata;
 365         uint8_t rsvd4[4];
 366         uint32_t byte_cnt;
 367         uint64_t timestamp;
 368         uint32_t sop_drop_qpn;
 369         uint16_t wqe_counter;
 370         uint8_t rsvd5;
 371         uint8_t op_own;
 372 };
 373
 374 /* Adding direct verbs to data-path. */
 375
 376 /* CQ sequence number mask. */
 377 #define MLX5_CQ_SQN_MASK 0x3
 378
 379 /* CQ sequence number index. */
 380 #define MLX5_CQ_SQN_OFFSET 28
 381
 382 /* CQ doorbell index mask. */
 383 #define MLX5_CI_MASK 0xffffff
 384
 385 /* CQ doorbell offset. */
 386 #define MLX5_CQ_ARM_DB 1
 387
 388 /* CQ doorbell offset*/
 389 #define MLX5_CQ_DOORBELL 0x20
 390
 391 /* CQE format value. */
 392 #define MLX5_COMPRESSED 0x3
 393
 394 /* CQ doorbell cmd types. */
 395 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
 396 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
 397
 398 /* Action type of header modification. */
 399 enum {
 400         MLX5_MODIFICATION_TYPE_SET = 0x1,
 401         MLX5_MODIFICATION_TYPE_ADD = 0x2,
 402         MLX5_MODIFICATION_TYPE_COPY = 0x3,
 403 };
 404
 405 /* The field of packet to be modified. */
 406 enum mlx5_modification_field {
 407         MLX5_MODI_OUT_NONE = -1,
 408         MLX5_MODI_OUT_SMAC_47_16 = 1,
 409         MLX5_MODI_OUT_SMAC_15_0,
 410         MLX5_MODI_OUT_ETHERTYPE,
 411         MLX5_MODI_OUT_DMAC_47_16,
 412         MLX5_MODI_OUT_DMAC_15_0,
 413         MLX5_MODI_OUT_IP_DSCP,
 414         MLX5_MODI_OUT_TCP_FLAGS,
 415         MLX5_MODI_OUT_TCP_SPORT,
 416         MLX5_MODI_OUT_TCP_DPORT,
 417         MLX5_MODI_OUT_IPV4_TTL,
 418         MLX5_MODI_OUT_UDP_SPORT,
 419         MLX5_MODI_OUT_UDP_DPORT,
 420         MLX5_MODI_OUT_SIPV6_127_96,
 421         MLX5_MODI_OUT_SIPV6_95_64,
 422         MLX5_MODI_OUT_SIPV6_63_32,
 423         MLX5_MODI_OUT_SIPV6_31_0,
 424         MLX5_MODI_OUT_DIPV6_127_96,
 425         MLX5_MODI_OUT_DIPV6_95_64,
 426         MLX5_MODI_OUT_DIPV6_63_32,
 427         MLX5_MODI_OUT_DIPV6_31_0,
 428         MLX5_MODI_OUT_SIPV4,
 429         MLX5_MODI_OUT_DIPV4,
 430         MLX5_MODI_OUT_FIRST_VID,
 431         MLX5_MODI_IN_SMAC_47_16 = 0x31,
 432         MLX5_MODI_IN_SMAC_15_0,
 433         MLX5_MODI_IN_ETHERTYPE,
 434         MLX5_MODI_IN_DMAC_47_16,
 435         MLX5_MODI_IN_DMAC_15_0,
 436         MLX5_MODI_IN_IP_DSCP,
 437         MLX5_MODI_IN_TCP_FLAGS,
 438         MLX5_MODI_IN_TCP_SPORT,
 439         MLX5_MODI_IN_TCP_DPORT,
 440         MLX5_MODI_IN_IPV4_TTL,
 441         MLX5_MODI_IN_UDP_SPORT,
 442         MLX5_MODI_IN_UDP_DPORT,
 443         MLX5_MODI_IN_SIPV6_127_96,
 444         MLX5_MODI_IN_SIPV6_95_64,
 445         MLX5_MODI_IN_SIPV6_63_32,
 446         MLX5_MODI_IN_SIPV6_31_0,
 447         MLX5_MODI_IN_DIPV6_127_96,
 448         MLX5_MODI_IN_DIPV6_95_64,
 449         MLX5_MODI_IN_DIPV6_63_32,
 450         MLX5_MODI_IN_DIPV6_31_0,
 451         MLX5_MODI_IN_SIPV4,
 452         MLX5_MODI_IN_DIPV4,
 453         MLX5_MODI_OUT_IPV6_HOPLIMIT,
 454         MLX5_MODI_IN_IPV6_HOPLIMIT,
 455         MLX5_MODI_META_DATA_REG_A,
 456         MLX5_MODI_META_DATA_REG_B = 0x50,
 457         MLX5_MODI_META_REG_C_0,
 458         MLX5_MODI_META_REG_C_1,
 459         MLX5_MODI_META_REG_C_2,
 460         MLX5_MODI_META_REG_C_3,
 461         MLX5_MODI_META_REG_C_4,
 462         MLX5_MODI_META_REG_C_5,
 463         MLX5_MODI_META_REG_C_6,
 464         MLX5_MODI_META_REG_C_7,
 465         MLX5_MODI_OUT_TCP_SEQ_NUM,
 466         MLX5_MODI_IN_TCP_SEQ_NUM,
 467         MLX5_MODI_OUT_TCP_ACK_NUM,
 468         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 469 };
 470
 471 /* Total number of metadata reg_c's. */
 472 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
 473
 474 enum modify_reg {
 475         REG_NONE = 0,
 476         REG_A,
 477         REG_B,
 478         REG_C_0,
 479         REG_C_1,
 480         REG_C_2,
 481         REG_C_3,
 482         REG_C_4,
 483         REG_C_5,
 484         REG_C_6,
 485         REG_C_7,
 486 };
 487
 488 /* Modification sub command. */
 489 struct mlx5_modification_cmd {
 490         union {
 491                 uint32_t data0;
 492                 struct {
 493                         unsigned int length:5;
 494                         unsigned int rsvd0:3;
 495                         unsigned int offset:5;
 496                         unsigned int rsvd1:3;
 497                         unsigned int field:12;
 498                         unsigned int action_type:4;
 499                 };
 500         };
 501         union {
 502                 uint32_t data1;
 503                 uint8_t data[4];
 504                 struct {
 505                         unsigned int rsvd2:8;
 506                         unsigned int dst_offset:5;
 507                         unsigned int rsvd3:3;
 508                         unsigned int dst_field:12;
 509                         unsigned int rsvd4:4;
 510                 };
 511         };
 512 };
 513
 514 typedef uint32_t u32;
 515 typedef uint16_t u16;
 516 typedef uint8_t u8;
 517
 518 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 519 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
 520 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
 521                                   (&(__mlx5_nullp(typ)->fld)))
 522 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 523                                     (__mlx5_bit_off(typ, fld) & 0x1f))
 524 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
 525 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
 526 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
 527                                   __mlx5_dw_bit_off(typ, fld))
 528 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 529 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
 530 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
 531                                     (__mlx5_bit_off(typ, fld) & 0xf))
 532 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 533 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
 534                                   __mlx5_16_bit_off(typ, fld))
 535 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 536 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
 537 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 538 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 539
 540 /* insert a value to a struct */
 541 #define MLX5_SET(typ, p, fld, v) \
 542         do { \
 543                 u32 _v = v; \
 544                 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
 545                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
 546                                   __mlx5_dw_off(typ, fld))) & \
 547                                   (~__mlx5_dw_mask(typ, fld))) | \
 548                                  (((_v) & __mlx5_mask(typ, fld)) << \
 549                                    __mlx5_dw_bit_off(typ, fld))); \
 550         } while (0)
 551
 552 #define MLX5_SET64(typ, p, fld, v) \
 553         do { \
 554                 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
 555                 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
 556                         rte_cpu_to_be_64(v); \
 557         } while (0)
 558
 559 #define MLX5_SET16(typ, p, fld, v) \
 560         do { \
 561                 u16 _v = v; \
 562                 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
 563                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((__be16 *)(p) + \
 564                                   __mlx5_16_off(typ, fld))) & \
 565                                   (~__mlx5_16_mask(typ, fld))) | \
 566                                  (((_v) & __mlx5_mask16(typ, fld)) << \
 567                                   __mlx5_16_bit_off(typ, fld))); \
 568         } while (0)
 569
 570 #define MLX5_GET(typ, p, fld) \
 571         ((rte_be_to_cpu_32(*((__be32 *)(p) +\
 572         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 573         __mlx5_mask(typ, fld))
 574 #define MLX5_GET16(typ, p, fld) \
 575         ((rte_be_to_cpu_16(*((__be16 *)(p) + \
 576           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 577          __mlx5_mask16(typ, fld))
 578 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
 579                                                    __mlx5_64_off(typ, fld)))
 580 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 581
 582 struct mlx5_ifc_fte_match_set_misc_bits {
 583         u8 gre_c_present[0x1];
 584         u8 reserved_at_1[0x1];
 585         u8 gre_k_present[0x1];
 586         u8 gre_s_present[0x1];
 587         u8 source_vhci_port[0x4];
 588         u8 source_sqn[0x18];
 589         u8 reserved_at_20[0x10];
 590         u8 source_port[0x10];
 591         u8 outer_second_prio[0x3];
 592         u8 outer_second_cfi[0x1];
 593         u8 outer_second_vid[0xc];
 594         u8 inner_second_prio[0x3];
 595         u8 inner_second_cfi[0x1];
 596         u8 inner_second_vid[0xc];
 597         u8 outer_second_cvlan_tag[0x1];
 598         u8 inner_second_cvlan_tag[0x1];
 599         u8 outer_second_svlan_tag[0x1];
 600         u8 inner_second_svlan_tag[0x1];
 601         u8 reserved_at_64[0xc];
 602         u8 gre_protocol[0x10];
 603         u8 gre_key_h[0x18];
 604         u8 gre_key_l[0x8];
 605         u8 vxlan_vni[0x18];
 606         u8 reserved_at_b8[0x8];
 607         u8 geneve_vni[0x18];
 608         u8 reserved_at_e4[0x7];
 609         u8 geneve_oam[0x1];
 610         u8 reserved_at_e0[0xc];
 611         u8 outer_ipv6_flow_label[0x14];
 612         u8 reserved_at_100[0xc];
 613         u8 inner_ipv6_flow_label[0x14];
 614         u8 reserved_at_120[0xa];
 615         u8 geneve_opt_len[0x6];
 616         u8 geneve_protocol_type[0x10];
 617         u8 reserved_at_140[0xc0];
 618 };
 619
 620 struct mlx5_ifc_ipv4_layout_bits {
 621         u8 reserved_at_0[0x60];
 622         u8 ipv4[0x20];
 623 };
 624
 625 struct mlx5_ifc_ipv6_layout_bits {
 626         u8 ipv6[16][0x8];
 627 };
 628
 629 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 630         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 631         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 632         u8 reserved_at_0[0x80];
 633 };
 634
 635 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 636         u8 smac_47_16[0x20];
 637         u8 smac_15_0[0x10];
 638         u8 ethertype[0x10];
 639         u8 dmac_47_16[0x20];
 640         u8 dmac_15_0[0x10];
 641         u8 first_prio[0x3];
 642         u8 first_cfi[0x1];
 643         u8 first_vid[0xc];
 644         u8 ip_protocol[0x8];
 645         u8 ip_dscp[0x6];
 646         u8 ip_ecn[0x2];
 647         u8 cvlan_tag[0x1];
 648         u8 svlan_tag[0x1];
 649         u8 frag[0x1];
 650         u8 ip_version[0x4];
 651         u8 tcp_flags[0x9];
 652         u8 tcp_sport[0x10];
 653         u8 tcp_dport[0x10];
 654         u8 reserved_at_c0[0x18];
 655         u8 ip_ttl_hoplimit[0x8];
 656         u8 udp_sport[0x10];
 657         u8 udp_dport[0x10];
 658         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 659         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 660 };
 661
 662 struct mlx5_ifc_fte_match_mpls_bits {
 663         u8 mpls_label[0x14];
 664         u8 mpls_exp[0x3];
 665         u8 mpls_s_bos[0x1];
 666         u8 mpls_ttl[0x8];
 667 };
 668
 669 struct mlx5_ifc_fte_match_set_misc2_bits {
 670         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 671         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 672         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 673         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 674         u8 metadata_reg_c_7[0x20];
 675         u8 metadata_reg_c_6[0x20];
 676         u8 metadata_reg_c_5[0x20];
 677         u8 metadata_reg_c_4[0x20];
 678         u8 metadata_reg_c_3[0x20];
 679         u8 metadata_reg_c_2[0x20];
 680         u8 metadata_reg_c_1[0x20];
 681         u8 metadata_reg_c_0[0x20];
 682         u8 metadata_reg_a[0x20];
 683         u8 metadata_reg_b[0x20];
 684         u8 reserved_at_1c0[0x40];
 685 };
 686
 687 struct mlx5_ifc_fte_match_set_misc3_bits {
 688         u8 inner_tcp_seq_num[0x20];
 689         u8 outer_tcp_seq_num[0x20];
 690         u8 inner_tcp_ack_num[0x20];
 691         u8 outer_tcp_ack_num[0x20];
 692         u8 reserved_at_auto1[0x8];
 693         u8 outer_vxlan_gpe_vni[0x18];
 694         u8 outer_vxlan_gpe_next_protocol[0x8];
 695         u8 outer_vxlan_gpe_flags[0x8];
 696         u8 reserved_at_a8[0x10];
 697         u8 icmp_header_data[0x20];
 698         u8 icmpv6_header_data[0x20];
 699         u8 icmp_type[0x8];
 700         u8 icmp_code[0x8];
 701         u8 icmpv6_type[0x8];
 702         u8 icmpv6_code[0x8];
 703         u8 reserved_at_120[0x20];
 704         u8 gtpu_teid[0x20];
 705         u8 gtpu_msg_type[0x08];
 706         u8 gtpu_msg_flags[0x08];
 707         u8 reserved_at_170[0x90];
 708 };
 709
 710 /* Flow matcher. */
 711 struct mlx5_ifc_fte_match_param_bits {
 712         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 713         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 714         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 715         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
 716         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
 717 };
 718
 719 enum {
 720         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
 721         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
 722         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
 723         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
 724         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
 725 };
 726
 727 enum {
 728         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
 729         MLX5_CMD_OP_CREATE_MKEY = 0x200,
 730         MLX5_CMD_OP_CREATE_CQ = 0x400,
 731         MLX5_CMD_OP_CREATE_QP = 0x500,
 732         MLX5_CMD_OP_RST2INIT_QP = 0x502,
 733         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
 734         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
 735         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
 736         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
 737         MLX5_CMD_OP_QP_2ERR = 0x507,
 738         MLX5_CMD_OP_QP_2RST = 0x50A,
 739         MLX5_CMD_OP_QUERY_QP = 0x50B,
 740         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
 741         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
 742         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
 743         MLX5_CMD_OP_RESUME_QP = 0x510,
 744         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
 745         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
 746         MLX5_CMD_OP_CREATE_TIR = 0x900,
 747         MLX5_CMD_OP_CREATE_SQ = 0X904,
 748         MLX5_CMD_OP_MODIFY_SQ = 0X905,
 749         MLX5_CMD_OP_CREATE_RQ = 0x908,
 750         MLX5_CMD_OP_MODIFY_RQ = 0x909,
 751         MLX5_CMD_OP_CREATE_TIS = 0x912,
 752         MLX5_CMD_OP_QUERY_TIS = 0x915,
 753         MLX5_CMD_OP_CREATE_RQT = 0x916,
 754         MLX5_CMD_OP_MODIFY_RQT = 0x917,
 755         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
 756         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
 757         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
 758         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
 759         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
 760 };
 761
 762 enum {
 763         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
 764         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
 765         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
 766 };
 767
 768 #define MLX5_ADAPTER_PAGE_SHIFT 12
 769 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
 770 /**
 771  * The batch counter dcs id starts from 0x800000 and none batch counter
 772  * starts from 0. As currently, the counter is changed to be indexed by
 773  * pool index and the offset of the counter in the pool counters_raw array.
 774  * It means now the counter index is same for batch and none batch counter.
 775  * Add the 0x800000 batch counter offset to the batch counter index helps
 776  * indicate the counter index is from batch or none batch container pool.
 777  */
 778 #define MLX5_CNT_BATCH_OFFSET 0x800000
 779
 780 /* Flow counters. */
 781 struct mlx5_ifc_alloc_flow_counter_out_bits {
 782         u8         status[0x8];
 783         u8         reserved_at_8[0x18];
 784         u8         syndrome[0x20];
 785         u8         flow_counter_id[0x20];
 786         u8         reserved_at_60[0x20];
 787 };
 788
 789 struct mlx5_ifc_alloc_flow_counter_in_bits {
 790         u8         opcode[0x10];
 791         u8         reserved_at_10[0x10];
 792         u8         reserved_at_20[0x10];
 793         u8         op_mod[0x10];
 794         u8         flow_counter_id[0x20];
 795         u8         reserved_at_40[0x18];
 796         u8         flow_counter_bulk[0x8];
 797 };
 798
 799 struct mlx5_ifc_dealloc_flow_counter_out_bits {
 800         u8         status[0x8];
 801         u8         reserved_at_8[0x18];
 802         u8         syndrome[0x20];
 803         u8         reserved_at_40[0x40];
 804 };
 805
 806 struct mlx5_ifc_dealloc_flow_counter_in_bits {
 807         u8         opcode[0x10];
 808         u8         reserved_at_10[0x10];
 809         u8         reserved_at_20[0x10];
 810         u8         op_mod[0x10];
 811         u8         flow_counter_id[0x20];
 812         u8         reserved_at_60[0x20];
 813 };
 814
 815 struct mlx5_ifc_traffic_counter_bits {
 816         u8         packets[0x40];
 817         u8         octets[0x40];
 818 };
 819
 820 struct mlx5_ifc_query_flow_counter_out_bits {
 821         u8         status[0x8];
 822         u8         reserved_at_8[0x18];
 823         u8         syndrome[0x20];
 824         u8         reserved_at_40[0x40];
 825         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
 826 };
 827
 828 struct mlx5_ifc_query_flow_counter_in_bits {
 829         u8         opcode[0x10];
 830         u8         reserved_at_10[0x10];
 831         u8         reserved_at_20[0x10];
 832         u8         op_mod[0x10];
 833         u8         reserved_at_40[0x20];
 834         u8         mkey[0x20];
 835         u8         address[0x40];
 836         u8         clear[0x1];
 837         u8         dump_to_memory[0x1];
 838         u8         num_of_counters[0x1e];
 839         u8         flow_counter_id[0x20];
 840 };
 841
 842 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
 843 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
 844
 845
 846 struct mlx5_ifc_klm_bits {
 847         u8         byte_count[0x20];
 848         u8         mkey[0x20];
 849         u8         address[0x40];
 850 };
 851
 852 struct mlx5_ifc_mkc_bits {
 853         u8         reserved_at_0[0x1];
 854         u8         free[0x1];
 855         u8         reserved_at_2[0x1];
 856         u8         access_mode_4_2[0x3];
 857         u8         reserved_at_6[0x7];
 858         u8         relaxed_ordering_write[0x1];
 859         u8         reserved_at_e[0x1];
 860         u8         small_fence_on_rdma_read_response[0x1];
 861         u8         umr_en[0x1];
 862         u8         a[0x1];
 863         u8         rw[0x1];
 864         u8         rr[0x1];
 865         u8         lw[0x1];
 866         u8         lr[0x1];
 867         u8         access_mode_1_0[0x2];
 868         u8         reserved_at_18[0x8];
 869
 870         u8         qpn[0x18];
 871         u8         mkey_7_0[0x8];
 872
 873         u8         reserved_at_40[0x20];
 874
 875         u8         length64[0x1];
 876         u8         bsf_en[0x1];
 877         u8         sync_umr[0x1];
 878         u8         reserved_at_63[0x2];
 879         u8         expected_sigerr_count[0x1];
 880         u8         reserved_at_66[0x1];
 881         u8         en_rinval[0x1];
 882         u8         pd[0x18];
 883
 884         u8         start_addr[0x40];
 885
 886         u8         len[0x40];
 887
 888         u8         bsf_octword_size[0x20];
 889
 890         u8         reserved_at_120[0x80];
 891
 892         u8         translations_octword_size[0x20];
 893
 894         u8         reserved_at_1c0[0x19];
 895         u8                 relaxed_ordering_read[0x1];
 896         u8                 reserved_at_1da[0x1];
 897         u8         log_page_size[0x5];
 898
 899         u8         reserved_at_1e0[0x20];
 900 };
 901
 902 struct mlx5_ifc_create_mkey_out_bits {
 903         u8         status[0x8];
 904         u8         reserved_at_8[0x18];
 905
 906         u8         syndrome[0x20];
 907
 908         u8         reserved_at_40[0x8];
 909         u8         mkey_index[0x18];
 910
 911         u8         reserved_at_60[0x20];
 912 };
 913
 914 struct mlx5_ifc_create_mkey_in_bits {
 915         u8         opcode[0x10];
 916         u8         reserved_at_10[0x10];
 917
 918         u8         reserved_at_20[0x10];
 919         u8         op_mod[0x10];
 920
 921         u8         reserved_at_40[0x20];
 922
 923         u8         pg_access[0x1];
 924         u8         reserved_at_61[0x1f];
 925
 926         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
 927
 928         u8         reserved_at_280[0x80];
 929
 930         u8         translations_octword_actual_size[0x20];
 931
 932         u8         mkey_umem_id[0x20];
 933
 934         u8         mkey_umem_offset[0x40];
 935
 936         u8         reserved_at_380[0x500];
 937
 938         u8         klm_pas_mtt[][0x20];
 939 };
 940
 941 enum {
 942         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
 943         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
 944         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
 945         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
 946 };
 947
 948 enum {
 949         MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),
 950 };
 951
 952 enum {
 953         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
 954         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
 955 };
 956
 957 enum {
 958         MLX5_CAP_INLINE_MODE_L2,
 959         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
 960         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
 961 };
 962
 963 enum {
 964         MLX5_INLINE_MODE_NONE,
 965         MLX5_INLINE_MODE_L2,
 966         MLX5_INLINE_MODE_IP,
 967         MLX5_INLINE_MODE_TCP_UDP,
 968         MLX5_INLINE_MODE_RESERVED4,
 969         MLX5_INLINE_MODE_INNER_L2,
 970         MLX5_INLINE_MODE_INNER_IP,
 971         MLX5_INLINE_MODE_INNER_TCP_UDP,
 972 };
 973
 974 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
 975 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
 976 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
 977 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
 978 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
 979 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
 980 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
 981 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
 982 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
 983 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
 984 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
 985
 986 struct mlx5_ifc_cmd_hca_cap_bits {
 987         u8 reserved_at_0[0x30];
 988         u8 vhca_id[0x10];
 989         u8 reserved_at_40[0x40];
 990         u8 log_max_srq_sz[0x8];
 991         u8 log_max_qp_sz[0x8];
 992         u8 reserved_at_90[0xb];
 993         u8 log_max_qp[0x5];
 994         u8 reserved_at_a0[0xb];
 995         u8 log_max_srq[0x5];
 996         u8 reserved_at_b0[0x10];
 997         u8 reserved_at_c0[0x8];
 998         u8 log_max_cq_sz[0x8];
 999         u8 reserved_at_d0[0xb];
1000         u8 log_max_cq[0x5];
1001         u8 log_max_eq_sz[0x8];
1002         u8 reserved_at_e8[0x2];
1003         u8 log_max_mkey[0x6];
1004         u8 reserved_at_f0[0x8];
1005         u8 dump_fill_mkey[0x1];
1006         u8 reserved_at_f9[0x3];
1007         u8 log_max_eq[0x4];
1008         u8 max_indirection[0x8];
1009         u8 fixed_buffer_size[0x1];
1010         u8 log_max_mrw_sz[0x7];
1011         u8 force_teardown[0x1];
1012         u8 reserved_at_111[0x1];
1013         u8 log_max_bsf_list_size[0x6];
1014         u8 umr_extended_translation_offset[0x1];
1015         u8 null_mkey[0x1];
1016         u8 log_max_klm_list_size[0x6];
1017         u8 reserved_at_120[0xa];
1018         u8 log_max_ra_req_dc[0x6];
1019         u8 reserved_at_130[0xa];
1020         u8 log_max_ra_res_dc[0x6];
1021         u8 reserved_at_140[0xa];
1022         u8 log_max_ra_req_qp[0x6];
1023         u8 reserved_at_150[0xa];
1024         u8 log_max_ra_res_qp[0x6];
1025         u8 end_pad[0x1];
1026         u8 cc_query_allowed[0x1];
1027         u8 cc_modify_allowed[0x1];
1028         u8 start_pad[0x1];
1029         u8 cache_line_128byte[0x1];
1030         u8 reserved_at_165[0xa];
1031         u8 qcam_reg[0x1];
1032         u8 gid_table_size[0x10];
1033         u8 out_of_seq_cnt[0x1];
1034         u8 vport_counters[0x1];
1035         u8 retransmission_q_counters[0x1];
1036         u8 debug[0x1];
1037         u8 modify_rq_counter_set_id[0x1];
1038         u8 rq_delay_drop[0x1];
1039         u8 max_qp_cnt[0xa];
1040         u8 pkey_table_size[0x10];
1041         u8 vport_group_manager[0x1];
1042         u8 vhca_group_manager[0x1];
1043         u8 ib_virt[0x1];
1044         u8 eth_virt[0x1];
1045         u8 vnic_env_queue_counters[0x1];
1046         u8 ets[0x1];
1047         u8 nic_flow_table[0x1];
1048         u8 eswitch_manager[0x1];
1049         u8 device_memory[0x1];
1050         u8 mcam_reg[0x1];
1051         u8 pcam_reg[0x1];
1052         u8 local_ca_ack_delay[0x5];
1053         u8 port_module_event[0x1];
1054         u8 enhanced_error_q_counters[0x1];
1055         u8 ports_check[0x1];
1056         u8 reserved_at_1b3[0x1];
1057         u8 disable_link_up[0x1];
1058         u8 beacon_led[0x1];
1059         u8 port_type[0x2];
1060         u8 num_ports[0x8];
1061         u8 reserved_at_1c0[0x1];
1062         u8 pps[0x1];
1063         u8 pps_modify[0x1];
1064         u8 log_max_msg[0x5];
1065         u8 reserved_at_1c8[0x4];
1066         u8 max_tc[0x4];
1067         u8 temp_warn_event[0x1];
1068         u8 dcbx[0x1];
1069         u8 general_notification_event[0x1];
1070         u8 reserved_at_1d3[0x2];
1071         u8 fpga[0x1];
1072         u8 rol_s[0x1];
1073         u8 rol_g[0x1];
1074         u8 reserved_at_1d8[0x1];
1075         u8 wol_s[0x1];
1076         u8 wol_g[0x1];
1077         u8 wol_a[0x1];
1078         u8 wol_b[0x1];
1079         u8 wol_m[0x1];
1080         u8 wol_u[0x1];
1081         u8 wol_p[0x1];
1082         u8 stat_rate_support[0x10];
1083         u8 reserved_at_1f0[0xc];
1084         u8 cqe_version[0x4];
1085         u8 compact_address_vector[0x1];
1086         u8 striding_rq[0x1];
1087         u8 reserved_at_202[0x1];
1088         u8 ipoib_enhanced_offloads[0x1];
1089         u8 ipoib_basic_offloads[0x1];
1090         u8 reserved_at_205[0x1];
1091         u8 repeated_block_disabled[0x1];
1092         u8 umr_modify_entity_size_disabled[0x1];
1093         u8 umr_modify_atomic_disabled[0x1];
1094         u8 umr_indirect_mkey_disabled[0x1];
1095         u8 umr_fence[0x2];
1096         u8 reserved_at_20c[0x3];
1097         u8 drain_sigerr[0x1];
1098         u8 cmdif_checksum[0x2];
1099         u8 sigerr_cqe[0x1];
1100         u8 reserved_at_213[0x1];
1101         u8 wq_signature[0x1];
1102         u8 sctr_data_cqe[0x1];
1103         u8 reserved_at_216[0x1];
1104         u8 sho[0x1];
1105         u8 tph[0x1];
1106         u8 rf[0x1];
1107         u8 dct[0x1];
1108         u8 qos[0x1];
1109         u8 eth_net_offloads[0x1];
1110         u8 roce[0x1];
1111         u8 atomic[0x1];
1112         u8 reserved_at_21f[0x1];
1113         u8 cq_oi[0x1];
1114         u8 cq_resize[0x1];
1115         u8 cq_moderation[0x1];
1116         u8 reserved_at_223[0x3];
1117         u8 cq_eq_remap[0x1];
1118         u8 pg[0x1];
1119         u8 block_lb_mc[0x1];
1120         u8 reserved_at_229[0x1];
1121         u8 scqe_break_moderation[0x1];
1122         u8 cq_period_start_from_cqe[0x1];
1123         u8 cd[0x1];
1124         u8 reserved_at_22d[0x1];
1125         u8 apm[0x1];
1126         u8 vector_calc[0x1];
1127         u8 umr_ptr_rlky[0x1];
1128         u8 imaicl[0x1];
1129         u8 reserved_at_232[0x4];
1130         u8 qkv[0x1];
1131         u8 pkv[0x1];
1132         u8 set_deth_sqpn[0x1];
1133         u8 reserved_at_239[0x3];
1134         u8 xrc[0x1];
1135         u8 ud[0x1];
1136         u8 uc[0x1];
1137         u8 rc[0x1];
1138         u8 uar_4k[0x1];
1139         u8 reserved_at_241[0x9];
1140         u8 uar_sz[0x6];
1141         u8 reserved_at_250[0x8];
1142         u8 log_pg_sz[0x8];
1143         u8 bf[0x1];
1144         u8 driver_version[0x1];
1145         u8 pad_tx_eth_packet[0x1];
1146         u8 reserved_at_263[0x8];
1147         u8 log_bf_reg_size[0x5];
1148         u8 reserved_at_270[0xb];
1149         u8 lag_master[0x1];
1150         u8 num_lag_ports[0x4];
1151         u8 reserved_at_280[0x10];
1152         u8 max_wqe_sz_sq[0x10];
1153         u8 reserved_at_2a0[0x10];
1154         u8 max_wqe_sz_rq[0x10];
1155         u8 max_flow_counter_31_16[0x10];
1156         u8 max_wqe_sz_sq_dc[0x10];
1157         u8 reserved_at_2e0[0x7];
1158         u8 max_qp_mcg[0x19];
1159         u8 reserved_at_300[0x10];
1160         u8 flow_counter_bulk_alloc[0x08];
1161         u8 log_max_mcg[0x8];
1162         u8 reserved_at_320[0x3];
1163         u8 log_max_transport_domain[0x5];
1164         u8 reserved_at_328[0x3];
1165         u8 log_max_pd[0x5];
1166         u8 reserved_at_330[0xb];
1167         u8 log_max_xrcd[0x5];
1168         u8 nic_receive_steering_discard[0x1];
1169         u8 receive_discard_vport_down[0x1];
1170         u8 transmit_discard_vport_down[0x1];
1171         u8 reserved_at_343[0x5];
1172         u8 log_max_flow_counter_bulk[0x8];
1173         u8 max_flow_counter_15_0[0x10];
1174         u8 modify_tis[0x1];
1175         u8 flow_counters_dump[0x1];
1176         u8 reserved_at_360[0x1];
1177         u8 log_max_rq[0x5];
1178         u8 reserved_at_368[0x3];
1179         u8 log_max_sq[0x5];
1180         u8 reserved_at_370[0x3];
1181         u8 log_max_tir[0x5];
1182         u8 reserved_at_378[0x3];
1183         u8 log_max_tis[0x5];
1184         u8 basic_cyclic_rcv_wqe[0x1];
1185         u8 reserved_at_381[0x2];
1186         u8 log_max_rmp[0x5];
1187         u8 reserved_at_388[0x3];
1188         u8 log_max_rqt[0x5];
1189         u8 reserved_at_390[0x3];
1190         u8 log_max_rqt_size[0x5];
1191         u8 reserved_at_398[0x3];
1192         u8 log_max_tis_per_sq[0x5];
1193         u8 ext_stride_num_range[0x1];
1194         u8 reserved_at_3a1[0x2];
1195         u8 log_max_stride_sz_rq[0x5];
1196         u8 reserved_at_3a8[0x3];
1197         u8 log_min_stride_sz_rq[0x5];
1198         u8 reserved_at_3b0[0x3];
1199         u8 log_max_stride_sz_sq[0x5];
1200         u8 reserved_at_3b8[0x3];
1201         u8 log_min_stride_sz_sq[0x5];
1202         u8 hairpin[0x1];
1203         u8 reserved_at_3c1[0x2];
1204         u8 log_max_hairpin_queues[0x5];
1205         u8 reserved_at_3c8[0x3];
1206         u8 log_max_hairpin_wq_data_sz[0x5];
1207         u8 reserved_at_3d0[0x3];
1208         u8 log_max_hairpin_num_packets[0x5];
1209         u8 reserved_at_3d8[0x3];
1210         u8 log_max_wq_sz[0x5];
1211         u8 nic_vport_change_event[0x1];
1212         u8 disable_local_lb_uc[0x1];
1213         u8 disable_local_lb_mc[0x1];
1214         u8 log_min_hairpin_wq_data_sz[0x5];
1215         u8 reserved_at_3e8[0x3];
1216         u8 log_max_vlan_list[0x5];
1217         u8 reserved_at_3f0[0x3];
1218         u8 log_max_current_mc_list[0x5];
1219         u8 reserved_at_3f8[0x3];
1220         u8 log_max_current_uc_list[0x5];
1221         u8 general_obj_types[0x40];
1222         u8 reserved_at_440[0x20];
1223         u8 reserved_at_460[0x10];
1224         u8 max_num_eqs[0x10];
1225         u8 reserved_at_480[0x3];
1226         u8 log_max_l2_table[0x5];
1227         u8 reserved_at_488[0x8];
1228         u8 log_uar_page_sz[0x10];
1229         u8 reserved_at_4a0[0x20];
1230         u8 device_frequency_mhz[0x20];
1231         u8 device_frequency_khz[0x20];
1232         u8 reserved_at_500[0x20];
1233         u8 num_of_uars_per_page[0x20];
1234         u8 flex_parser_protocols[0x20];
1235         u8 reserved_at_560[0x20];
1236         u8 reserved_at_580[0x3c];
1237         u8 mini_cqe_resp_stride_index[0x1];
1238         u8 cqe_128_always[0x1];
1239         u8 cqe_compression_128[0x1];
1240         u8 cqe_compression[0x1];
1241         u8 cqe_compression_timeout[0x10];
1242         u8 cqe_compression_max_num[0x10];
1243         u8 reserved_at_5e0[0x10];
1244         u8 tag_matching[0x1];
1245         u8 rndv_offload_rc[0x1];
1246         u8 rndv_offload_dc[0x1];
1247         u8 log_tag_matching_list_sz[0x5];
1248         u8 reserved_at_5f8[0x3];
1249         u8 log_max_xrq[0x5];
1250         u8 affiliate_nic_vport_criteria[0x8];
1251         u8 native_port_num[0x8];
1252         u8 num_vhca_ports[0x8];
1253         u8 reserved_at_618[0x6];
1254         u8 sw_owner_id[0x1];
1255         u8 reserved_at_61f[0x1e1];
1256 };
1257
1258 struct mlx5_ifc_qos_cap_bits {
1259         u8 packet_pacing[0x1];
1260         u8 esw_scheduling[0x1];
1261         u8 esw_bw_share[0x1];
1262         u8 esw_rate_limit[0x1];
1263         u8 reserved_at_4[0x1];
1264         u8 packet_pacing_burst_bound[0x1];
1265         u8 packet_pacing_typical_size[0x1];
1266         u8 flow_meter_srtcm[0x1];
1267         u8 reserved_at_8[0x8];
1268         u8 log_max_flow_meter[0x8];
1269         u8 flow_meter_reg_id[0x8];
1270         u8 reserved_at_25[0x8];
1271         u8 flow_meter_reg_share[0x1];
1272         u8 reserved_at_2e[0x17];
1273         u8 packet_pacing_max_rate[0x20];
1274         u8 packet_pacing_min_rate[0x20];
1275         u8 reserved_at_80[0x10];
1276         u8 packet_pacing_rate_table_size[0x10];
1277         u8 esw_element_type[0x10];
1278         u8 esw_tsar_type[0x10];
1279         u8 reserved_at_c0[0x10];
1280         u8 max_qos_para_vport[0x10];
1281         u8 max_tsar_bw_share[0x20];
1282         u8 reserved_at_100[0x6e8];
1283 };
1284
1285 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1286         u8 csum_cap[0x1];
1287         u8 vlan_cap[0x1];
1288         u8 lro_cap[0x1];
1289         u8 lro_psh_flag[0x1];
1290         u8 lro_time_stamp[0x1];
1291         u8 lro_max_msg_sz_mode[0x2];
1292         u8 wqe_vlan_insert[0x1];
1293         u8 self_lb_en_modifiable[0x1];
1294         u8 self_lb_mc[0x1];
1295         u8 self_lb_uc[0x1];
1296         u8 max_lso_cap[0x5];
1297         u8 multi_pkt_send_wqe[0x2];
1298         u8 wqe_inline_mode[0x2];
1299         u8 rss_ind_tbl_cap[0x4];
1300         u8 reg_umr_sq[0x1];
1301         u8 scatter_fcs[0x1];
1302         u8 enhanced_multi_pkt_send_wqe[0x1];
1303         u8 tunnel_lso_const_out_ip_id[0x1];
1304         u8 tunnel_lro_gre[0x1];
1305         u8 tunnel_lro_vxlan[0x1];
1306         u8 tunnel_stateless_gre[0x1];
1307         u8 tunnel_stateless_vxlan[0x1];
1308         u8 swp[0x1];
1309         u8 swp_csum[0x1];
1310         u8 swp_lso[0x1];
1311         u8 reserved_at_23[0x8];
1312         u8 tunnel_stateless_gtp[0x1];
1313         u8 reserved_at_25[0x4];
1314         u8 max_vxlan_udp_ports[0x8];
1315         u8 reserved_at_38[0x6];
1316         u8 max_geneve_opt_len[0x1];
1317         u8 tunnel_stateless_geneve_rx[0x1];
1318         u8 reserved_at_40[0x10];
1319         u8 lro_min_mss_size[0x10];
1320         u8 reserved_at_60[0x120];
1321         u8 lro_timer_supported_periods[4][0x20];
1322         u8 reserved_at_200[0x600];
1323 };
1324
1325 enum {
1326         MLX5_VIRTQ_TYPE_SPLIT = 0,
1327         MLX5_VIRTQ_TYPE_PACKED = 1,
1328 };
1329
1330 enum {
1331         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1332         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1333         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1334 };
1335
1336 struct mlx5_ifc_virtio_emulation_cap_bits {
1337         u8 desc_tunnel_offload_type[0x1];
1338         u8 eth_frame_offload_type[0x1];
1339         u8 virtio_version_1_0[0x1];
1340         u8 tso_ipv4[0x1];
1341         u8 tso_ipv6[0x1];
1342         u8 tx_csum[0x1];
1343         u8 rx_csum[0x1];
1344         u8 reserved_at_7[0x1][0x9];
1345         u8 event_mode[0x8];
1346         u8 virtio_queue_type[0x8];
1347         u8 reserved_at_20[0x13];
1348         u8 log_doorbell_stride[0x5];
1349         u8 reserved_at_3b[0x3];
1350         u8 log_doorbell_bar_size[0x5];
1351         u8 doorbell_bar_offset[0x40];
1352         u8 reserved_at_80[0x8];
1353         u8 max_num_virtio_queues[0x18];
1354         u8 reserved_at_a0[0x60];
1355         u8 umem_1_buffer_param_a[0x20];
1356         u8 umem_1_buffer_param_b[0x20];
1357         u8 umem_2_buffer_param_a[0x20];
1358         u8 umem_2_buffer_param_b[0x20];
1359         u8 umem_3_buffer_param_a[0x20];
1360         u8 umem_3_buffer_param_b[0x20];
1361         u8 reserved_at_1c0[0x620];
1362 };
1363
1364 union mlx5_ifc_hca_cap_union_bits {
1365         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1366         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1367                per_protocol_networking_offload_caps;
1368         struct mlx5_ifc_qos_cap_bits qos_cap;
1369         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1370         u8 reserved_at_0[0x8000];
1371 };
1372
1373 struct mlx5_ifc_query_hca_cap_out_bits {
1374         u8 status[0x8];
1375         u8 reserved_at_8[0x18];
1376         u8 syndrome[0x20];
1377         u8 reserved_at_40[0x40];
1378         union mlx5_ifc_hca_cap_union_bits capability;
1379 };
1380
1381 struct mlx5_ifc_query_hca_cap_in_bits {
1382         u8 opcode[0x10];
1383         u8 reserved_at_10[0x10];
1384         u8 reserved_at_20[0x10];
1385         u8 op_mod[0x10];
1386         u8 reserved_at_40[0x40];
1387 };
1388
1389 struct mlx5_ifc_mac_address_layout_bits {
1390         u8 reserved_at_0[0x10];
1391         u8 mac_addr_47_32[0x10];
1392         u8 mac_addr_31_0[0x20];
1393 };
1394
1395 struct mlx5_ifc_nic_vport_context_bits {
1396         u8 reserved_at_0[0x5];
1397         u8 min_wqe_inline_mode[0x3];
1398         u8 reserved_at_8[0x15];
1399         u8 disable_mc_local_lb[0x1];
1400         u8 disable_uc_local_lb[0x1];
1401         u8 roce_en[0x1];
1402         u8 arm_change_event[0x1];
1403         u8 reserved_at_21[0x1a];
1404         u8 event_on_mtu[0x1];
1405         u8 event_on_promisc_change[0x1];
1406         u8 event_on_vlan_change[0x1];
1407         u8 event_on_mc_address_change[0x1];
1408         u8 event_on_uc_address_change[0x1];
1409         u8 reserved_at_40[0xc];
1410         u8 affiliation_criteria[0x4];
1411         u8 affiliated_vhca_id[0x10];
1412         u8 reserved_at_60[0xd0];
1413         u8 mtu[0x10];
1414         u8 system_image_guid[0x40];
1415         u8 port_guid[0x40];
1416         u8 node_guid[0x40];
1417         u8 reserved_at_200[0x140];
1418         u8 qkey_violation_counter[0x10];
1419         u8 reserved_at_350[0x430];
1420         u8 promisc_uc[0x1];
1421         u8 promisc_mc[0x1];
1422         u8 promisc_all[0x1];
1423         u8 reserved_at_783[0x2];
1424         u8 allowed_list_type[0x3];
1425         u8 reserved_at_788[0xc];
1426         u8 allowed_list_size[0xc];
1427         struct mlx5_ifc_mac_address_layout_bits permanent_address;
1428         u8 reserved_at_7e0[0x20];
1429 };
1430
1431 struct mlx5_ifc_query_nic_vport_context_out_bits {
1432         u8 status[0x8];
1433         u8 reserved_at_8[0x18];
1434         u8 syndrome[0x20];
1435         u8 reserved_at_40[0x40];
1436         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1437 };
1438
1439 struct mlx5_ifc_query_nic_vport_context_in_bits {
1440         u8 opcode[0x10];
1441         u8 reserved_at_10[0x10];
1442         u8 reserved_at_20[0x10];
1443         u8 op_mod[0x10];
1444         u8 other_vport[0x1];
1445         u8 reserved_at_41[0xf];
1446         u8 vport_number[0x10];
1447         u8 reserved_at_60[0x5];
1448         u8 allowed_list_type[0x3];
1449         u8 reserved_at_68[0x18];
1450 };
1451
1452 struct mlx5_ifc_tisc_bits {
1453         u8 strict_lag_tx_port_affinity[0x1];
1454         u8 reserved_at_1[0x3];
1455         u8 lag_tx_port_affinity[0x04];
1456         u8 reserved_at_8[0x4];
1457         u8 prio[0x4];
1458         u8 reserved_at_10[0x10];
1459         u8 reserved_at_20[0x100];
1460         u8 reserved_at_120[0x8];
1461         u8 transport_domain[0x18];
1462         u8 reserved_at_140[0x8];
1463         u8 underlay_qpn[0x18];
1464         u8 reserved_at_160[0x3a0];
1465 };
1466
1467 struct mlx5_ifc_query_tis_out_bits {
1468         u8 status[0x8];
1469         u8 reserved_at_8[0x18];
1470         u8 syndrome[0x20];
1471         u8 reserved_at_40[0x40];
1472         struct mlx5_ifc_tisc_bits tis_context;
1473 };
1474
1475 struct mlx5_ifc_query_tis_in_bits {
1476         u8 opcode[0x10];
1477         u8 reserved_at_10[0x10];
1478         u8 reserved_at_20[0x10];
1479         u8 op_mod[0x10];
1480         u8 reserved_at_40[0x8];
1481         u8 tisn[0x18];
1482         u8 reserved_at_60[0x20];
1483 };
1484
1485 struct mlx5_ifc_alloc_transport_domain_out_bits {
1486         u8 status[0x8];
1487         u8 reserved_at_8[0x18];
1488         u8 syndrome[0x20];
1489         u8 reserved_at_40[0x8];
1490         u8 transport_domain[0x18];
1491         u8 reserved_at_60[0x20];
1492 };
1493
1494 struct mlx5_ifc_alloc_transport_domain_in_bits {
1495         u8 opcode[0x10];
1496         u8 reserved_at_10[0x10];
1497         u8 reserved_at_20[0x10];
1498         u8 op_mod[0x10];
1499         u8 reserved_at_40[0x40];
1500 };
1501
1502 enum {
1503         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
1504         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
1505         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
1506         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
1507 };
1508
1509 enum {
1510         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
1511         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1512 };
1513
1514 struct mlx5_ifc_wq_bits {
1515         u8 wq_type[0x4];
1516         u8 wq_signature[0x1];
1517         u8 end_padding_mode[0x2];
1518         u8 cd_slave[0x1];
1519         u8 reserved_at_8[0x18];
1520         u8 hds_skip_first_sge[0x1];
1521         u8 log2_hds_buf_size[0x3];
1522         u8 reserved_at_24[0x7];
1523         u8 page_offset[0x5];
1524         u8 lwm[0x10];
1525         u8 reserved_at_40[0x8];
1526         u8 pd[0x18];
1527         u8 reserved_at_60[0x8];
1528         u8 uar_page[0x18];
1529         u8 dbr_addr[0x40];
1530         u8 hw_counter[0x20];
1531         u8 sw_counter[0x20];
1532         u8 reserved_at_100[0xc];
1533         u8 log_wq_stride[0x4];
1534         u8 reserved_at_110[0x3];
1535         u8 log_wq_pg_sz[0x5];
1536         u8 reserved_at_118[0x3];
1537         u8 log_wq_sz[0x5];
1538         u8 dbr_umem_valid[0x1];
1539         u8 wq_umem_valid[0x1];
1540         u8 reserved_at_122[0x1];
1541         u8 log_hairpin_num_packets[0x5];
1542         u8 reserved_at_128[0x3];
1543         u8 log_hairpin_data_sz[0x5];
1544         u8 reserved_at_130[0x4];
1545         u8 single_wqe_log_num_of_strides[0x4];
1546         u8 two_byte_shift_en[0x1];
1547         u8 reserved_at_139[0x4];
1548         u8 single_stride_log_num_of_bytes[0x3];
1549         u8 dbr_umem_id[0x20];
1550         u8 wq_umem_id[0x20];
1551         u8 wq_umem_offset[0x40];
1552         u8 reserved_at_1c0[0x440];
1553 };
1554
1555 enum {
1556         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
1557         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
1558 };
1559
1560 enum {
1561         MLX5_RQC_STATE_RST  = 0x0,
1562         MLX5_RQC_STATE_RDY  = 0x1,
1563         MLX5_RQC_STATE_ERR  = 0x3,
1564 };
1565
1566 struct mlx5_ifc_rqc_bits {
1567         u8 rlky[0x1];
1568         u8 delay_drop_en[0x1];
1569         u8 scatter_fcs[0x1];
1570         u8 vsd[0x1];
1571         u8 mem_rq_type[0x4];
1572         u8 state[0x4];
1573         u8 reserved_at_c[0x1];
1574         u8 flush_in_error_en[0x1];
1575         u8 hairpin[0x1];
1576         u8 reserved_at_f[0x11];
1577         u8 reserved_at_20[0x8];
1578         u8 user_index[0x18];
1579         u8 reserved_at_40[0x8];
1580         u8 cqn[0x18];
1581         u8 counter_set_id[0x8];
1582         u8 reserved_at_68[0x18];
1583         u8 reserved_at_80[0x8];
1584         u8 rmpn[0x18];
1585         u8 reserved_at_a0[0x8];
1586         u8 hairpin_peer_sq[0x18];
1587         u8 reserved_at_c0[0x10];
1588         u8 hairpin_peer_vhca[0x10];
1589         u8 reserved_at_e0[0xa0];
1590         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1591 };
1592
1593 struct mlx5_ifc_create_rq_out_bits {
1594         u8 status[0x8];
1595         u8 reserved_at_8[0x18];
1596         u8 syndrome[0x20];
1597         u8 reserved_at_40[0x8];
1598         u8 rqn[0x18];
1599         u8 reserved_at_60[0x20];
1600 };
1601
1602 struct mlx5_ifc_create_rq_in_bits {
1603         u8 opcode[0x10];
1604         u8 uid[0x10];
1605         u8 reserved_at_20[0x10];
1606         u8 op_mod[0x10];
1607         u8 reserved_at_40[0xc0];
1608         struct mlx5_ifc_rqc_bits ctx;
1609 };
1610
1611 struct mlx5_ifc_modify_rq_out_bits {
1612         u8 status[0x8];
1613         u8 reserved_at_8[0x18];
1614         u8 syndrome[0x20];
1615         u8 reserved_at_40[0x40];
1616 };
1617
1618 struct mlx5_ifc_create_tis_out_bits {
1619         u8 status[0x8];
1620         u8 reserved_at_8[0x18];
1621         u8 syndrome[0x20];
1622         u8 reserved_at_40[0x8];
1623         u8 tisn[0x18];
1624         u8 reserved_at_60[0x20];
1625 };
1626
1627 struct mlx5_ifc_create_tis_in_bits {
1628         u8 opcode[0x10];
1629         u8 uid[0x10];
1630         u8 reserved_at_20[0x10];
1631         u8 op_mod[0x10];
1632         u8 reserved_at_40[0xc0];
1633         struct mlx5_ifc_tisc_bits ctx;
1634 };
1635
1636 enum {
1637         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1638         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1639         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1640         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1641 };
1642
1643 struct mlx5_ifc_modify_rq_in_bits {
1644         u8 opcode[0x10];
1645         u8 uid[0x10];
1646         u8 reserved_at_20[0x10];
1647         u8 op_mod[0x10];
1648         u8 rq_state[0x4];
1649         u8 reserved_at_44[0x4];
1650         u8 rqn[0x18];
1651         u8 reserved_at_60[0x20];
1652         u8 modify_bitmask[0x40];
1653         u8 reserved_at_c0[0x40];
1654         struct mlx5_ifc_rqc_bits ctx;
1655 };
1656
1657 enum {
1658         MLX5_L3_PROT_TYPE_IPV4 = 0,
1659         MLX5_L3_PROT_TYPE_IPV6 = 1,
1660 };
1661
1662 enum {
1663         MLX5_L4_PROT_TYPE_TCP = 0,
1664         MLX5_L4_PROT_TYPE_UDP = 1,
1665 };
1666
1667 enum {
1668         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
1669         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
1670         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
1671         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
1672         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
1673 };
1674
1675 struct mlx5_ifc_rx_hash_field_select_bits {
1676         u8 l3_prot_type[0x1];
1677         u8 l4_prot_type[0x1];
1678         u8 selected_fields[0x1e];
1679 };
1680
1681 enum {
1682         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
1683         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
1684 };
1685
1686 enum {
1687         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
1688         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
1689 };
1690
1691 enum {
1692         MLX5_RX_HASH_FN_NONE           = 0x0,
1693         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
1694         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
1695 };
1696
1697 enum {
1698         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
1699         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
1700 };
1701
1702 enum {
1703         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
1704         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
1705 };
1706
1707 struct mlx5_ifc_tirc_bits {
1708         u8 reserved_at_0[0x20];
1709         u8 disp_type[0x4];
1710         u8 reserved_at_24[0x1c];
1711         u8 reserved_at_40[0x40];
1712         u8 reserved_at_80[0x4];
1713         u8 lro_timeout_period_usecs[0x10];
1714         u8 lro_enable_mask[0x4];
1715         u8 lro_max_msg_sz[0x8];
1716         u8 reserved_at_a0[0x40];
1717         u8 reserved_at_e0[0x8];
1718         u8 inline_rqn[0x18];
1719         u8 rx_hash_symmetric[0x1];
1720         u8 reserved_at_101[0x1];
1721         u8 tunneled_offload_en[0x1];
1722         u8 reserved_at_103[0x5];
1723         u8 indirect_table[0x18];
1724         u8 rx_hash_fn[0x4];
1725         u8 reserved_at_124[0x2];
1726         u8 self_lb_block[0x2];
1727         u8 transport_domain[0x18];
1728         u8 rx_hash_toeplitz_key[10][0x20];
1729         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1730         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1731         u8 reserved_at_2c0[0x4c0];
1732 };
1733
1734 struct mlx5_ifc_create_tir_out_bits {
1735         u8 status[0x8];
1736         u8 reserved_at_8[0x18];
1737         u8 syndrome[0x20];
1738         u8 reserved_at_40[0x8];
1739         u8 tirn[0x18];
1740         u8 reserved_at_60[0x20];
1741 };
1742
1743 struct mlx5_ifc_create_tir_in_bits {
1744         u8 opcode[0x10];
1745         u8 uid[0x10];
1746         u8 reserved_at_20[0x10];
1747         u8 op_mod[0x10];
1748         u8 reserved_at_40[0xc0];
1749         struct mlx5_ifc_tirc_bits ctx;
1750 };
1751
1752 enum {
1753         MLX5_INLINE_Q_TYPE_RQ = 0x0,
1754         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
1755 };
1756
1757 struct mlx5_ifc_rq_num_bits {
1758         u8 reserved_at_0[0x8];
1759         u8 rq_num[0x18];
1760 };
1761
1762 struct mlx5_ifc_rqtc_bits {
1763         u8 reserved_at_0[0xa5];
1764         u8 list_q_type[0x3];
1765         u8 reserved_at_a8[0x8];
1766         u8 rqt_max_size[0x10];
1767         u8 reserved_at_c0[0x10];
1768         u8 rqt_actual_size[0x10];
1769         u8 reserved_at_e0[0x6a0];
1770         struct mlx5_ifc_rq_num_bits rq_num[];
1771 };
1772
1773 struct mlx5_ifc_create_rqt_out_bits {
1774         u8 status[0x8];
1775         u8 reserved_at_8[0x18];
1776         u8 syndrome[0x20];
1777         u8 reserved_at_40[0x8];
1778         u8 rqtn[0x18];
1779         u8 reserved_at_60[0x20];
1780 };
1781
1782 #ifdef PEDANTIC
1783 #pragma GCC diagnostic ignored "-Wpedantic"
1784 #endif
1785 struct mlx5_ifc_create_rqt_in_bits {
1786         u8 opcode[0x10];
1787         u8 uid[0x10];
1788         u8 reserved_at_20[0x10];
1789         u8 op_mod[0x10];
1790         u8 reserved_at_40[0xc0];
1791         struct mlx5_ifc_rqtc_bits rqt_context;
1792 };
1793
1794 struct mlx5_ifc_modify_rqt_in_bits {
1795         u8 opcode[0x10];
1796         u8 uid[0x10];
1797         u8 reserved_at_20[0x10];
1798         u8 op_mod[0x10];
1799         u8 reserved_at_40[0x8];
1800         u8 rqtn[0x18];
1801         u8 reserved_at_60[0x20];
1802         u8 modify_bitmask[0x40];
1803         u8 reserved_at_c0[0x40];
1804         struct mlx5_ifc_rqtc_bits rqt_context;
1805 };
1806 #ifdef PEDANTIC
1807 #pragma GCC diagnostic error "-Wpedantic"
1808 #endif
1809
1810 struct mlx5_ifc_modify_rqt_out_bits {
1811         u8 status[0x8];
1812         u8 reserved_at_8[0x18];
1813         u8 syndrome[0x20];
1814         u8 reserved_at_40[0x40];
1815 };
1816
1817 enum {
1818         MLX5_SQC_STATE_RST  = 0x0,
1819         MLX5_SQC_STATE_RDY  = 0x1,
1820         MLX5_SQC_STATE_ERR  = 0x3,
1821 };
1822
1823 struct mlx5_ifc_sqc_bits {
1824         u8 rlky[0x1];
1825         u8 cd_master[0x1];
1826         u8 fre[0x1];
1827         u8 flush_in_error_en[0x1];
1828         u8 allow_multi_pkt_send_wqe[0x1];
1829         u8 min_wqe_inline_mode[0x3];
1830         u8 state[0x4];
1831         u8 reg_umr[0x1];
1832         u8 allow_swp[0x1];
1833         u8 hairpin[0x1];
1834         u8 reserved_at_f[0x11];
1835         u8 reserved_at_20[0x8];
1836         u8 user_index[0x18];
1837         u8 reserved_at_40[0x8];
1838         u8 cqn[0x18];
1839         u8 reserved_at_60[0x8];
1840         u8 hairpin_peer_rq[0x18];
1841         u8 reserved_at_80[0x10];
1842         u8 hairpin_peer_vhca[0x10];
1843         u8 reserved_at_a0[0x50];
1844         u8 packet_pacing_rate_limit_index[0x10];
1845         u8 tis_lst_sz[0x10];
1846         u8 reserved_at_110[0x10];
1847         u8 reserved_at_120[0x40];
1848         u8 reserved_at_160[0x8];
1849         u8 tis_num_0[0x18];
1850         struct mlx5_ifc_wq_bits wq;
1851 };
1852
1853 struct mlx5_ifc_query_sq_in_bits {
1854         u8 opcode[0x10];
1855         u8 reserved_at_10[0x10];
1856         u8 reserved_at_20[0x10];
1857         u8 op_mod[0x10];
1858         u8 reserved_at_40[0x8];
1859         u8 sqn[0x18];
1860         u8 reserved_at_60[0x20];
1861 };
1862
1863 struct mlx5_ifc_modify_sq_out_bits {
1864         u8 status[0x8];
1865         u8 reserved_at_8[0x18];
1866         u8 syndrome[0x20];
1867         u8 reserved_at_40[0x40];
1868 };
1869
1870 struct mlx5_ifc_modify_sq_in_bits {
1871         u8 opcode[0x10];
1872         u8 uid[0x10];
1873         u8 reserved_at_20[0x10];
1874         u8 op_mod[0x10];
1875         u8 sq_state[0x4];
1876         u8 reserved_at_44[0x4];
1877         u8 sqn[0x18];
1878         u8 reserved_at_60[0x20];
1879         u8 modify_bitmask[0x40];
1880         u8 reserved_at_c0[0x40];
1881         struct mlx5_ifc_sqc_bits ctx;
1882 };
1883
1884 struct mlx5_ifc_create_sq_out_bits {
1885         u8 status[0x8];
1886         u8 reserved_at_8[0x18];
1887         u8 syndrome[0x20];
1888         u8 reserved_at_40[0x8];
1889         u8 sqn[0x18];
1890         u8 reserved_at_60[0x20];
1891 };
1892
1893 struct mlx5_ifc_create_sq_in_bits {
1894         u8 opcode[0x10];
1895         u8 uid[0x10];
1896         u8 reserved_at_20[0x10];
1897         u8 op_mod[0x10];
1898         u8 reserved_at_40[0xc0];
1899         struct mlx5_ifc_sqc_bits ctx;
1900 };
1901
1902 enum {
1903         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
1904         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
1905         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
1906         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
1907         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
1908 };
1909
1910 struct mlx5_ifc_flow_meter_parameters_bits {
1911         u8         valid[0x1];                  // 00h
1912         u8         bucket_overflow[0x1];
1913         u8         start_color[0x2];
1914         u8         both_buckets_on_green[0x1];
1915         u8         meter_mode[0x2];
1916         u8         reserved_at_1[0x19];
1917         u8         reserved_at_2[0x20]; //04h
1918         u8         reserved_at_3[0x3];
1919         u8         cbs_exponent[0x5];           // 08h
1920         u8         cbs_mantissa[0x8];
1921         u8         reserved_at_4[0x3];
1922         u8         cir_exponent[0x5];
1923         u8         cir_mantissa[0x8];
1924         u8         reserved_at_5[0x20];         // 0Ch
1925         u8         reserved_at_6[0x3];
1926         u8         ebs_exponent[0x5];           // 10h
1927         u8         ebs_mantissa[0x8];
1928         u8         reserved_at_7[0x3];
1929         u8         eir_exponent[0x5];
1930         u8         eir_mantissa[0x8];
1931         u8         reserved_at_8[0x60];         // 14h-1Ch
1932 };
1933
1934 struct mlx5_ifc_cqc_bits {
1935         u8 status[0x4];
1936         u8 as_notify[0x1];
1937         u8 initiator_src_dct[0x1];
1938         u8 dbr_umem_valid[0x1];
1939         u8 reserved_at_7[0x1];
1940         u8 cqe_sz[0x3];
1941         u8 cc[0x1];
1942         u8 reserved_at_c[0x1];
1943         u8 scqe_break_moderation_en[0x1];
1944         u8 oi[0x1];
1945         u8 cq_period_mode[0x2];
1946         u8 cqe_comp_en[0x1];
1947         u8 mini_cqe_res_format[0x2];
1948         u8 st[0x4];
1949         u8 reserved_at_18[0x8];
1950         u8 dbr_umem_id[0x20];
1951         u8 reserved_at_40[0x14];
1952         u8 page_offset[0x6];
1953         u8 reserved_at_5a[0x6];
1954         u8 reserved_at_60[0x3];
1955         u8 log_cq_size[0x5];
1956         u8 uar_page[0x18];
1957         u8 reserved_at_80[0x4];
1958         u8 cq_period[0xc];
1959         u8 cq_max_count[0x10];
1960         u8 reserved_at_a0[0x18];
1961         u8 c_eqn[0x8];
1962         u8 reserved_at_c0[0x3];
1963         u8 log_page_size[0x5];
1964         u8 reserved_at_c8[0x18];
1965         u8 reserved_at_e0[0x20];
1966         u8 reserved_at_100[0x8];
1967         u8 last_notified_index[0x18];
1968         u8 reserved_at_120[0x8];
1969         u8 last_solicit_index[0x18];
1970         u8 reserved_at_140[0x8];
1971         u8 consumer_counter[0x18];
1972         u8 reserved_at_160[0x8];
1973         u8 producer_counter[0x18];
1974         u8 local_partition_id[0xc];
1975         u8 process_id[0x14];
1976         u8 reserved_at_1A0[0x20];
1977         u8 dbr_addr[0x40];
1978 };
1979
1980 struct mlx5_ifc_create_cq_out_bits {
1981         u8 status[0x8];
1982         u8 reserved_at_8[0x18];
1983         u8 syndrome[0x20];
1984         u8 reserved_at_40[0x8];
1985         u8 cqn[0x18];
1986         u8 reserved_at_60[0x20];
1987 };
1988
1989 struct mlx5_ifc_create_cq_in_bits {
1990         u8 opcode[0x10];
1991         u8 uid[0x10];
1992         u8 reserved_at_20[0x10];
1993         u8 op_mod[0x10];
1994         u8 reserved_at_40[0x40];
1995         struct mlx5_ifc_cqc_bits cq_context;
1996         u8 cq_umem_offset[0x40];
1997         u8 cq_umem_id[0x20];
1998         u8 cq_umem_valid[0x1];
1999         u8 reserved_at_2e1[0x1f];
2000         u8 reserved_at_300[0x580];
2001         u8 pas[];
2002 };
2003
2004 enum {
2005         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2006 };
2007
2008 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2009         u8 opcode[0x10];
2010         u8 reserved_at_10[0x20];
2011         u8 obj_type[0x10];
2012         u8 obj_id[0x20];
2013         u8 reserved_at_60[0x20];
2014 };
2015
2016 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2017         u8 status[0x8];
2018         u8 reserved_at_8[0x18];
2019         u8 syndrome[0x20];
2020         u8 obj_id[0x20];
2021         u8 reserved_at_60[0x20];
2022 };
2023
2024 enum {
2025         MLX5_VIRTQ_STATE_INIT = 0,
2026         MLX5_VIRTQ_STATE_RDY = 1,
2027         MLX5_VIRTQ_STATE_SUSPEND = 2,
2028         MLX5_VIRTQ_STATE_ERROR = 3,
2029 };
2030
2031 enum {
2032         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2033         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2034         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2035 };
2036
2037 struct mlx5_ifc_virtio_q_bits {
2038         u8 virtio_q_type[0x8];
2039         u8 reserved_at_8[0x5];
2040         u8 event_mode[0x3];
2041         u8 queue_index[0x10];
2042         u8 full_emulation[0x1];
2043         u8 virtio_version_1_0[0x1];
2044         u8 reserved_at_22[0x2];
2045         u8 offload_type[0x4];
2046         u8 event_qpn_or_msix[0x18];
2047         u8 doorbell_stride_idx[0x10];
2048         u8 queue_size[0x10];
2049         u8 device_emulation_id[0x20];
2050         u8 desc_addr[0x40];
2051         u8 used_addr[0x40];
2052         u8 available_addr[0x40];
2053         u8 virtio_q_mkey[0x20];
2054         u8 reserved_at_160[0x20];
2055         u8 umem_1_id[0x20];
2056         u8 umem_1_size[0x20];
2057         u8 umem_1_offset[0x40];
2058         u8 umem_2_id[0x20];
2059         u8 umem_2_size[0x20];
2060         u8 umem_2_offset[0x40];
2061         u8 umem_3_id[0x20];
2062         u8 umem_3_size[0x20];
2063         u8 umem_3_offset[0x40];
2064         u8 reserved_at_300[0x100];
2065 };
2066
2067 struct mlx5_ifc_virtio_net_q_bits {
2068         u8 modify_field_select[0x40];
2069         u8 reserved_at_40[0x40];
2070         u8 tso_ipv4[0x1];
2071         u8 tso_ipv6[0x1];
2072         u8 tx_csum[0x1];
2073         u8 rx_csum[0x1];
2074         u8 reserved_at_84[0x6];
2075         u8 dirty_bitmap_dump_enable[0x1];
2076         u8 vhost_log_page[0x5];
2077         u8 reserved_at_90[0xc];
2078         u8 state[0x4];
2079         u8 error_type[0x8];
2080         u8 tisn_or_qpn[0x18];
2081         u8 dirty_bitmap_mkey[0x20];
2082         u8 dirty_bitmap_size[0x20];
2083         u8 dirty_bitmap_addr[0x40];
2084         u8 hw_available_index[0x10];
2085         u8 hw_used_index[0x10];
2086         u8 reserved_at_160[0xa0];
2087         struct mlx5_ifc_virtio_q_bits virtio_q_context;
2088 };
2089
2090 struct mlx5_ifc_create_virtq_in_bits {
2091         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2092         struct mlx5_ifc_virtio_net_q_bits virtq;
2093 };
2094
2095 struct mlx5_ifc_query_virtq_out_bits {
2096         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2097         struct mlx5_ifc_virtio_net_q_bits virtq;
2098 };
2099
2100 enum {
2101         MLX5_QP_ST_RC = 0x0,
2102 };
2103
2104 enum {
2105         MLX5_QP_PM_MIGRATED = 0x3,
2106 };
2107
2108 enum {
2109         MLX5_NON_ZERO_RQ = 0x0,
2110         MLX5_SRQ_RQ = 0x1,
2111         MLX5_CRQ_RQ = 0x2,
2112         MLX5_ZERO_LEN_RQ = 0x3,
2113 };
2114
2115 struct mlx5_ifc_ads_bits {
2116         u8 fl[0x1];
2117         u8 free_ar[0x1];
2118         u8 reserved_at_2[0xe];
2119         u8 pkey_index[0x10];
2120         u8 reserved_at_20[0x8];
2121         u8 grh[0x1];
2122         u8 mlid[0x7];
2123         u8 rlid[0x10];
2124         u8 ack_timeout[0x5];
2125         u8 reserved_at_45[0x3];
2126         u8 src_addr_index[0x8];
2127         u8 reserved_at_50[0x4];
2128         u8 stat_rate[0x4];
2129         u8 hop_limit[0x8];
2130         u8 reserved_at_60[0x4];
2131         u8 tclass[0x8];
2132         u8 flow_label[0x14];
2133         u8 rgid_rip[16][0x8];
2134         u8 reserved_at_100[0x4];
2135         u8 f_dscp[0x1];
2136         u8 f_ecn[0x1];
2137         u8 reserved_at_106[0x1];
2138         u8 f_eth_prio[0x1];
2139         u8 ecn[0x2];
2140         u8 dscp[0x6];
2141         u8 udp_sport[0x10];
2142         u8 dei_cfi[0x1];
2143         u8 eth_prio[0x3];
2144         u8 sl[0x4];
2145         u8 vhca_port_num[0x8];
2146         u8 rmac_47_32[0x10];
2147         u8 rmac_31_0[0x20];
2148 };
2149
2150 struct mlx5_ifc_qpc_bits {
2151         u8 state[0x4];
2152         u8 lag_tx_port_affinity[0x4];
2153         u8 st[0x8];
2154         u8 reserved_at_10[0x3];
2155         u8 pm_state[0x2];
2156         u8 reserved_at_15[0x1];
2157         u8 req_e2e_credit_mode[0x2];
2158         u8 offload_type[0x4];
2159         u8 end_padding_mode[0x2];
2160         u8 reserved_at_1e[0x2];
2161         u8 wq_signature[0x1];
2162         u8 block_lb_mc[0x1];
2163         u8 atomic_like_write_en[0x1];
2164         u8 latency_sensitive[0x1];
2165         u8 reserved_at_24[0x1];
2166         u8 drain_sigerr[0x1];
2167         u8 reserved_at_26[0x2];
2168         u8 pd[0x18];
2169         u8 mtu[0x3];
2170         u8 log_msg_max[0x5];
2171         u8 reserved_at_48[0x1];
2172         u8 log_rq_size[0x4];
2173         u8 log_rq_stride[0x3];
2174         u8 no_sq[0x1];
2175         u8 log_sq_size[0x4];
2176         u8 reserved_at_55[0x6];
2177         u8 rlky[0x1];
2178         u8 ulp_stateless_offload_mode[0x4];
2179         u8 counter_set_id[0x8];
2180         u8 uar_page[0x18];
2181         u8 reserved_at_80[0x8];
2182         u8 user_index[0x18];
2183         u8 reserved_at_a0[0x3];
2184         u8 log_page_size[0x5];
2185         u8 remote_qpn[0x18];
2186         struct mlx5_ifc_ads_bits primary_address_path;
2187         struct mlx5_ifc_ads_bits secondary_address_path;
2188         u8 log_ack_req_freq[0x4];
2189         u8 reserved_at_384[0x4];
2190         u8 log_sra_max[0x3];
2191         u8 reserved_at_38b[0x2];
2192         u8 retry_count[0x3];
2193         u8 rnr_retry[0x3];
2194         u8 reserved_at_393[0x1];
2195         u8 fre[0x1];
2196         u8 cur_rnr_retry[0x3];
2197         u8 cur_retry_count[0x3];
2198         u8 reserved_at_39b[0x5];
2199         u8 reserved_at_3a0[0x20];
2200         u8 reserved_at_3c0[0x8];
2201         u8 next_send_psn[0x18];
2202         u8 reserved_at_3e0[0x8];
2203         u8 cqn_snd[0x18];
2204         u8 reserved_at_400[0x8];
2205         u8 deth_sqpn[0x18];
2206         u8 reserved_at_420[0x20];
2207         u8 reserved_at_440[0x8];
2208         u8 last_acked_psn[0x18];
2209         u8 reserved_at_460[0x8];
2210         u8 ssn[0x18];
2211         u8 reserved_at_480[0x8];
2212         u8 log_rra_max[0x3];
2213         u8 reserved_at_48b[0x1];
2214         u8 atomic_mode[0x4];
2215         u8 rre[0x1];
2216         u8 rwe[0x1];
2217         u8 rae[0x1];
2218         u8 reserved_at_493[0x1];
2219         u8 page_offset[0x6];
2220         u8 reserved_at_49a[0x3];
2221         u8 cd_slave_receive[0x1];
2222         u8 cd_slave_send[0x1];
2223         u8 cd_master[0x1];
2224         u8 reserved_at_4a0[0x3];
2225         u8 min_rnr_nak[0x5];
2226         u8 next_rcv_psn[0x18];
2227         u8 reserved_at_4c0[0x8];
2228         u8 xrcd[0x18];
2229         u8 reserved_at_4e0[0x8];
2230         u8 cqn_rcv[0x18];
2231         u8 dbr_addr[0x40];
2232         u8 q_key[0x20];
2233         u8 reserved_at_560[0x5];
2234         u8 rq_type[0x3];
2235         u8 srqn_rmpn_xrqn[0x18];
2236         u8 reserved_at_580[0x8];
2237         u8 rmsn[0x18];
2238         u8 hw_sq_wqebb_counter[0x10];
2239         u8 sw_sq_wqebb_counter[0x10];
2240         u8 hw_rq_counter[0x20];
2241         u8 sw_rq_counter[0x20];
2242         u8 reserved_at_600[0x20];
2243         u8 reserved_at_620[0xf];
2244         u8 cgs[0x1];
2245         u8 cs_req[0x8];
2246         u8 cs_res[0x8];
2247         u8 dc_access_key[0x40];
2248         u8 reserved_at_680[0x3];
2249         u8 dbr_umem_valid[0x1];
2250         u8 reserved_at_684[0x9c];
2251         u8 dbr_umem_id[0x20];
2252 };
2253
2254 struct mlx5_ifc_create_qp_out_bits {
2255         u8 status[0x8];
2256         u8 reserved_at_8[0x18];
2257         u8 syndrome[0x20];
2258         u8 reserved_at_40[0x8];
2259         u8 qpn[0x18];
2260         u8 reserved_at_60[0x20];
2261 };
2262
2263 #ifdef PEDANTIC
2264 #pragma GCC diagnostic ignored "-Wpedantic"
2265 #endif
2266 struct mlx5_ifc_create_qp_in_bits {
2267         u8 opcode[0x10];
2268         u8 uid[0x10];
2269         u8 reserved_at_20[0x10];
2270         u8 op_mod[0x10];
2271         u8 reserved_at_40[0x40];
2272         u8 opt_param_mask[0x20];
2273         u8 reserved_at_a0[0x20];
2274         struct mlx5_ifc_qpc_bits qpc;
2275         u8 wq_umem_offset[0x40];
2276         u8 wq_umem_id[0x20];
2277         u8 wq_umem_valid[0x1];
2278         u8 reserved_at_861[0x1f];
2279         u8 pas[0][0x40];
2280 };
2281 #ifdef PEDANTIC
2282 #pragma GCC diagnostic error "-Wpedantic"
2283 #endif
2284
2285 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2286         u8 status[0x8];
2287         u8 reserved_at_8[0x18];
2288         u8 syndrome[0x20];
2289         u8 reserved_at_40[0x40];
2290 };
2291
2292 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2293         u8 opcode[0x10];
2294         u8 uid[0x10];
2295         u8 reserved_at_20[0x10];
2296         u8 op_mod[0x10];
2297         u8 reserved_at_40[0x8];
2298         u8 qpn[0x18];
2299         u8 reserved_at_60[0x20];
2300         u8 opt_param_mask[0x20];
2301         u8 reserved_at_a0[0x20];
2302         struct mlx5_ifc_qpc_bits qpc;
2303         u8 reserved_at_800[0x80];
2304 };
2305
2306 struct mlx5_ifc_sqd2rts_qp_out_bits {
2307         u8 status[0x8];
2308         u8 reserved_at_8[0x18];
2309         u8 syndrome[0x20];
2310         u8 reserved_at_40[0x40];
2311 };
2312
2313 struct mlx5_ifc_sqd2rts_qp_in_bits {
2314         u8 opcode[0x10];
2315         u8 uid[0x10];
2316         u8 reserved_at_20[0x10];
2317         u8 op_mod[0x10];
2318         u8 reserved_at_40[0x8];
2319         u8 qpn[0x18];
2320         u8 reserved_at_60[0x20];
2321         u8 opt_param_mask[0x20];
2322         u8 reserved_at_a0[0x20];
2323         struct mlx5_ifc_qpc_bits qpc;
2324         u8 reserved_at_800[0x80];
2325 };
2326
2327 struct mlx5_ifc_rts2rts_qp_out_bits {
2328         u8 status[0x8];
2329         u8 reserved_at_8[0x18];
2330         u8 syndrome[0x20];
2331         u8 reserved_at_40[0x40];
2332 };
2333
2334 struct mlx5_ifc_rts2rts_qp_in_bits {
2335         u8 opcode[0x10];
2336         u8 uid[0x10];
2337         u8 reserved_at_20[0x10];
2338         u8 op_mod[0x10];
2339         u8 reserved_at_40[0x8];
2340         u8 qpn[0x18];
2341         u8 reserved_at_60[0x20];
2342         u8 opt_param_mask[0x20];
2343         u8 reserved_at_a0[0x20];
2344         struct mlx5_ifc_qpc_bits qpc;
2345         u8 reserved_at_800[0x80];
2346 };
2347
2348 struct mlx5_ifc_rtr2rts_qp_out_bits {
2349         u8 status[0x8];
2350         u8 reserved_at_8[0x18];
2351         u8 syndrome[0x20];
2352         u8 reserved_at_40[0x40];
2353 };
2354
2355 struct mlx5_ifc_rtr2rts_qp_in_bits {
2356         u8 opcode[0x10];
2357         u8 uid[0x10];
2358         u8 reserved_at_20[0x10];
2359         u8 op_mod[0x10];
2360         u8 reserved_at_40[0x8];
2361         u8 qpn[0x18];
2362         u8 reserved_at_60[0x20];
2363         u8 opt_param_mask[0x20];
2364         u8 reserved_at_a0[0x20];
2365         struct mlx5_ifc_qpc_bits qpc;
2366         u8 reserved_at_800[0x80];
2367 };
2368
2369 struct mlx5_ifc_rst2init_qp_out_bits {
2370         u8 status[0x8];
2371         u8 reserved_at_8[0x18];
2372         u8 syndrome[0x20];
2373         u8 reserved_at_40[0x40];
2374 };
2375
2376 struct mlx5_ifc_rst2init_qp_in_bits {
2377         u8 opcode[0x10];
2378         u8 uid[0x10];
2379         u8 reserved_at_20[0x10];
2380         u8 op_mod[0x10];
2381         u8 reserved_at_40[0x8];
2382         u8 qpn[0x18];
2383         u8 reserved_at_60[0x20];
2384         u8 opt_param_mask[0x20];
2385         u8 reserved_at_a0[0x20];
2386         struct mlx5_ifc_qpc_bits qpc;
2387         u8 reserved_at_800[0x80];
2388 };
2389
2390 struct mlx5_ifc_init2rtr_qp_out_bits {
2391         u8 status[0x8];
2392         u8 reserved_at_8[0x18];
2393         u8 syndrome[0x20];
2394         u8 reserved_at_40[0x40];
2395 };
2396
2397 struct mlx5_ifc_init2rtr_qp_in_bits {
2398         u8 opcode[0x10];
2399         u8 uid[0x10];
2400         u8 reserved_at_20[0x10];
2401         u8 op_mod[0x10];
2402         u8 reserved_at_40[0x8];
2403         u8 qpn[0x18];
2404         u8 reserved_at_60[0x20];
2405         u8 opt_param_mask[0x20];
2406         u8 reserved_at_a0[0x20];
2407         struct mlx5_ifc_qpc_bits qpc;
2408         u8 reserved_at_800[0x80];
2409 };
2410
2411 struct mlx5_ifc_init2init_qp_out_bits {
2412         u8 status[0x8];
2413         u8 reserved_at_8[0x18];
2414         u8 syndrome[0x20];
2415         u8 reserved_at_40[0x40];
2416 };
2417
2418 struct mlx5_ifc_init2init_qp_in_bits {
2419         u8 opcode[0x10];
2420         u8 uid[0x10];
2421         u8 reserved_at_20[0x10];
2422         u8 op_mod[0x10];
2423         u8 reserved_at_40[0x8];
2424         u8 qpn[0x18];
2425         u8 reserved_at_60[0x20];
2426         u8 opt_param_mask[0x20];
2427         u8 reserved_at_a0[0x20];
2428         struct mlx5_ifc_qpc_bits qpc;
2429         u8 reserved_at_800[0x80];
2430 };
2431
2432 #ifdef PEDANTIC
2433 #pragma GCC diagnostic ignored "-Wpedantic"
2434 #endif
2435 struct mlx5_ifc_query_qp_out_bits {
2436         u8 status[0x8];
2437         u8 reserved_at_8[0x18];
2438         u8 syndrome[0x20];
2439         u8 reserved_at_40[0x40];
2440         u8 opt_param_mask[0x20];
2441         u8 reserved_at_a0[0x20];
2442         struct mlx5_ifc_qpc_bits qpc;
2443         u8 reserved_at_800[0x80];
2444         u8 pas[0][0x40];
2445 };
2446 #ifdef PEDANTIC
2447 #pragma GCC diagnostic error "-Wpedantic"
2448 #endif
2449
2450 struct mlx5_ifc_query_qp_in_bits {
2451         u8 opcode[0x10];
2452         u8 reserved_at_10[0x10];
2453         u8 reserved_at_20[0x10];
2454         u8 op_mod[0x10];
2455         u8 reserved_at_40[0x8];
2456         u8 qpn[0x18];
2457         u8 reserved_at_60[0x20];
2458 };
2459
2460 /* CQE format mask. */
2461 #define MLX5E_CQE_FORMAT_MASK 0xc
2462
2463 /* MPW opcode. */
2464 #define MLX5_OPC_MOD_MPW 0x01
2465
2466 /* Compressed Rx CQE structure. */
2467 struct mlx5_mini_cqe8 {
2468         union {
2469                 uint32_t rx_hash_result;
2470                 struct {
2471                         uint16_t checksum;
2472                         uint16_t stride_idx;
2473                 };
2474                 struct {
2475                         uint16_t wqe_counter;
2476                         uint8_t  s_wqe_opcode;
2477                         uint8_t  reserved;
2478                 } s_wqe_info;
2479         };
2480         uint32_t byte_cnt;
2481 };
2482
2483 /* srTCM PRM flow meter parameters. */
2484 enum {
2485         MLX5_FLOW_COLOR_RED = 0,
2486         MLX5_FLOW_COLOR_YELLOW,
2487         MLX5_FLOW_COLOR_GREEN,
2488         MLX5_FLOW_COLOR_UNDEFINED,
2489 };
2490
2491 /* Maximum value of srTCM metering parameters. */
2492 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
2493 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
2494 #define MLX5_SRTCM_EBS_MAX 0
2495
2496 /* The bits meter color use. */
2497 #define MLX5_MTR_COLOR_BITS 8
2498
2499 /**
2500  * Convert a user mark to flow mark.
2501  *
2502  * @param val
2503  *   Mark value to convert.
2504  *
2505  * @return
2506  *   Converted mark value.
2507  */
2508 static inline uint32_t
2509 mlx5_flow_mark_set(uint32_t val)
2510 {
2511         uint32_t ret;
2512
2513         /*
2514          * Add one to the user value to differentiate un-marked flows from
2515          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
2516          * remains untouched.
2517          */
2518         if (val != MLX5_FLOW_MARK_DEFAULT)
2519                 ++val;
2520 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2521         /*
2522          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
2523          * word, byte-swapped by the kernel on little-endian systems. In this
2524          * case, left-shifting the resulting big-endian value ensures the
2525          * least significant 24 bits are retained when converting it back.
2526          */
2527         ret = rte_cpu_to_be_32(val) >> 8;
2528 #else
2529         ret = val;
2530 #endif
2531         return ret;
2532 }
2533
2534 /**
2535  * Convert a mark to user mark.
2536  *
2537  * @param val
2538  *   Mark value to convert.
2539  *
2540  * @return
2541  *   Converted mark value.
2542  */
2543 static inline uint32_t
2544 mlx5_flow_mark_get(uint32_t val)
2545 {
2546         /*
2547          * Subtract one from the retrieved value. It was added by
2548          * mlx5_flow_mark_set() to distinguish unmarked flows.
2549          */
2550 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2551         return (val >> 8) - 1;
2552 #else
2553         return val - 1;
2554 #endif
2555 }
2556
2557 #endif /* RTE_PMD_MLX5_PRM_H_ */