1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright 2016 6WIND S.A.
3 * Copyright 2016 Mellanox Technologies, Ltd
6 #ifndef RTE_PMD_MLX5_PRM_H_
7 #define RTE_PMD_MLX5_PRM_H_
10 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
12 #pragma GCC diagnostic ignored "-Wpedantic"
14 #include <infiniband/mlx5dv.h>
16 #pragma GCC diagnostic error "-Wpedantic"
22 #include <rte_byteorder.h>
24 #include "mlx5_autoconf.h"
26 /* RSS hash key size. */
27 #define MLX5_RSS_HASH_KEY_LEN 40
29 /* Get CQE owner bit. */
30 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
33 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
36 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
38 /* Get CQE solicited event. */
39 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
41 /* Invalidate a CQE. */
42 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
44 /* Hardware index widths. */
45 #define MLX5_CQ_INDEX_WIDTH 24
46 #define MLX5_WQ_INDEX_WIDTH 16
48 /* WQE Segment sizes in bytes. */
49 #define MLX5_WSEG_SIZE 16u
50 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
51 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
52 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
54 /* WQE/WQEBB size in bytes. */
55 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
58 * Max size of a WQE session.
59 * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
60 * the WQE size field in Control Segment is 6 bits wide.
62 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
65 * Default minimum number of Tx queues for inlining packets.
66 * If there are less queues as specified we assume we have
67 * no enough CPU resources (cycles) to perform inlining,
68 * the PCIe throughput is not supposed as bottleneck and
69 * inlining is disabled.
71 #define MLX5_INLINE_MAX_TXQS 8u
72 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
75 * Default packet length threshold to be inlined with
76 * enhanced MPW. If packet length exceeds the threshold
77 * the data are not inlined. Should be aligned in WQEBB
78 * boundary with accounting the title Control and Ethernet
81 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
82 MLX5_DSEG_MIN_INLINE_SIZE)
84 * Maximal inline data length sent with enhanced MPW.
85 * Is based on maximal WQE size.
87 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
88 MLX5_WQE_CSEG_SIZE - \
89 MLX5_WQE_ESEG_SIZE - \
90 MLX5_WQE_DSEG_SIZE + \
91 MLX5_DSEG_MIN_INLINE_SIZE)
93 * Minimal amount of packets to be sent with EMPW.
94 * This limits the minimal required size of sent EMPW.
95 * If there are no enough resources to built minimal
96 * EMPW the sending loop exits.
98 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
100 * Maximal amount of packets to be sent with EMPW.
101 * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
102 * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
103 * without CQE generation request, being multiplied by
104 * MLX5_TX_COMP_MAX_CQE it may cause significant latency
105 * in tx burst routine at the moment of freeing multiple mbufs.
107 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
108 #define MLX5_MPW_MAX_PACKETS 6
109 #define MLX5_MPW_INLINE_MAX_PACKETS 6
112 * Default packet length threshold to be inlined with
113 * ordinary SEND. Inlining saves the MR key search
114 * and extra PCIe data fetch transaction, but eats the
117 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
118 MLX5_ESEG_MIN_INLINE_SIZE - \
119 MLX5_WQE_CSEG_SIZE - \
120 MLX5_WQE_ESEG_SIZE - \
123 * Maximal inline data length sent with ordinary SEND.
124 * Is based on maximal WQE size.
126 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
127 MLX5_WQE_CSEG_SIZE - \
128 MLX5_WQE_ESEG_SIZE - \
129 MLX5_WQE_DSEG_SIZE + \
130 MLX5_ESEG_MIN_INLINE_SIZE)
132 /* Missed in mlv5dv.h, should define here. */
133 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
134 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
137 #ifndef HAVE_MLX5_OPCODE_SEND_EN
138 #define MLX5_OPCODE_SEND_EN 0x17u
141 #ifndef HAVE_MLX5_OPCODE_WAIT
142 #define MLX5_OPCODE_WAIT 0x0fu
145 /* CQE value to inform that VLAN is stripped. */
146 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
149 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
152 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
155 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
158 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
161 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
163 /* IP is fragmented. */
164 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
166 /* L2 header is valid. */
167 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
169 /* L3 header is valid. */
170 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
172 /* L4 header is valid. */
173 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
175 /* Outer packet, 0 IPv4, 1 IPv6. */
176 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
178 /* Tunnel packet bit in the CQE. */
179 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
181 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
182 #define MLX5_CQE_LRO_PUSH_MASK 0x40
184 /* Mask for L4 type in the CQE hdr_type_etc field. */
185 #define MLX5_CQE_L4_TYPE_MASK 0x70
187 /* The bit index of L4 type in CQE hdr_type_etc field. */
188 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
190 /* L4 type to indicate TCP packet without acknowledgment. */
191 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
193 /* L4 type to indicate TCP packet with acknowledgment. */
194 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
196 /* Inner L3 checksum offload (Tunneled packets only). */
197 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
199 /* Inner L4 checksum offload (Tunneled packets only). */
200 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
202 /* Outer L4 type is TCP. */
203 #define MLX5_ETH_WQE_L4_OUTER_TCP (0u << 5)
205 /* Outer L4 type is UDP. */
206 #define MLX5_ETH_WQE_L4_OUTER_UDP (1u << 5)
208 /* Outer L3 type is IPV4. */
209 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
211 /* Outer L3 type is IPV6. */
212 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
214 /* Inner L4 type is TCP. */
215 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
217 /* Inner L4 type is UDP. */
218 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
220 /* Inner L3 type is IPV4. */
221 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
223 /* Inner L3 type is IPV6. */
224 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
226 /* VLAN insertion flag. */
227 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
229 /* Data inline segment flag. */
230 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
232 /* Is flow mark valid. */
233 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
234 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
236 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
239 /* INVALID is used by packets matching no flow rules. */
240 #define MLX5_FLOW_MARK_INVALID 0
242 /* Maximum allowed value to mark a packet. */
243 #define MLX5_FLOW_MARK_MAX 0xfffff0
245 /* Default mark value used when none is provided. */
246 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
248 /* Default mark mask for metadata legacy mode. */
249 #define MLX5_FLOW_MARK_MASK 0xffffff
251 /* Maximum number of DS in WQE. Limited by 6-bit field. */
252 #define MLX5_DSEG_MAX 63
254 /* The completion mode offset in the WQE control segment line 2. */
255 #define MLX5_COMP_MODE_OFFSET 2
257 /* Amount of data bytes in minimal inline data segment. */
258 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
260 /* Amount of data bytes in minimal inline eth segment. */
261 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
263 /* Amount of data bytes after eth data segment. */
264 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
266 /* The maximum log value of segments per RQ WQE. */
267 #define MLX5_MAX_LOG_RQ_SEGS 5u
269 /* The alignment needed for WQ buffer. */
270 #define MLX5_WQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)
272 /* The alignment needed for CQ buffer. */
273 #define MLX5_CQE_BUF_ALIGNMENT sysconf(_SC_PAGESIZE)
275 /* Completion mode. */
276 enum mlx5_completion_mode {
277 MLX5_COMP_ONLY_ERR = 0x0,
278 MLX5_COMP_ONLY_FIRST_ERR = 0x1,
279 MLX5_COMP_ALWAYS = 0x2,
280 MLX5_COMP_CQE_AND_EQE = 0x3,
287 MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
290 /* WQE Control segment. */
291 struct mlx5_wqe_cseg {
296 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
298 /* Header of data segment. Minimal size Data Segment */
299 struct mlx5_wqe_dseg {
302 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
310 /* Subset of struct WQE Ethernet Segment. */
311 struct mlx5_wqe_eseg {
319 uint16_t inline_hdr_sz;
321 uint16_t inline_data;
328 uint32_t flow_metadata;
334 struct mlx5_wqe_qseg {
341 /* The title WQEBB, header of WQE. */
344 struct mlx5_wqe_cseg cseg;
347 struct mlx5_wqe_eseg eseg;
349 struct mlx5_wqe_dseg dseg[2];
350 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
354 /* WQE for Multi-Packet RQ. */
355 struct mlx5_wqe_mprq {
356 struct mlx5_wqe_srq_next_seg next_seg;
357 struct mlx5_wqe_data_seg dseg;
360 #define MLX5_MPRQ_LEN_MASK 0x000ffff
361 #define MLX5_MPRQ_LEN_SHIFT 0
362 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
363 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
364 #define MLX5_MPRQ_FILLER_MASK 0x80000000
365 #define MLX5_MPRQ_FILLER_SHIFT 31
367 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
369 /* CQ element structure - should be equal to the cache line size */
371 #if (RTE_CACHE_LINE_SIZE == 128)
377 uint8_t lro_tcppsh_abort_dupack;
379 uint16_t lro_tcp_win;
380 uint32_t lro_ack_seq_num;
381 uint32_t rx_hash_res;
382 uint8_t rx_hash_type;
386 uint16_t hdr_type_etc;
390 uint32_t flow_table_metadata;
394 uint32_t sop_drop_qpn;
395 uint16_t wqe_counter;
402 uint32_t sop_drop_qpn;
403 uint16_t wqe_counter;
408 /* MMO metadata segment */
410 #define MLX5_OPCODE_MMO 0x2f
411 #define MLX5_OPC_MOD_MMO_REGEX 0x4
413 struct mlx5_wqe_metadata_seg {
414 uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
419 struct mlx5_ifc_regexp_mmo_control_bits {
420 uint8_t reserved_at_31[0x2];
422 uint8_t reserved_at_28[0x1];
423 uint8_t subset_id_0[0xc];
424 uint8_t reserved_at_16[0x4];
425 uint8_t subset_id_1[0xc];
427 uint8_t subset_id_2[0xc];
428 uint8_t reserved_at_16_1[0x4];
429 uint8_t subset_id_3[0xc];
432 struct mlx5_ifc_regexp_metadata_bits {
433 uint8_t rof_version[0x10];
434 uint8_t latency_count[0x10];
435 uint8_t instruction_count[0x10];
436 uint8_t primary_thread_count[0x10];
437 uint8_t match_count[0x8];
438 uint8_t detected_match_count[0x8];
439 uint8_t status[0x10];
440 uint8_t job_id[0x20];
441 uint8_t reserved[0x80];
444 struct mlx5_ifc_regexp_match_tuple_bits {
445 uint8_t length[0x10];
446 uint8_t start_ptr[0x10];
447 uint8_t rule_id[0x20];
450 /* Adding direct verbs to data-path. */
452 /* CQ sequence number mask. */
453 #define MLX5_CQ_SQN_MASK 0x3
455 /* CQ sequence number index. */
456 #define MLX5_CQ_SQN_OFFSET 28
458 /* CQ doorbell index mask. */
459 #define MLX5_CI_MASK 0xffffff
461 /* CQ doorbell offset. */
462 #define MLX5_CQ_ARM_DB 1
464 /* CQ doorbell offset*/
465 #define MLX5_CQ_DOORBELL 0x20
467 /* CQE format value. */
468 #define MLX5_COMPRESSED 0x3
470 /* CQ doorbell cmd types. */
471 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
472 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
474 /* Action type of header modification. */
476 MLX5_MODIFICATION_TYPE_SET = 0x1,
477 MLX5_MODIFICATION_TYPE_ADD = 0x2,
478 MLX5_MODIFICATION_TYPE_COPY = 0x3,
481 /* The field of packet to be modified. */
482 enum mlx5_modification_field {
483 MLX5_MODI_OUT_NONE = -1,
484 MLX5_MODI_OUT_SMAC_47_16 = 1,
485 MLX5_MODI_OUT_SMAC_15_0,
486 MLX5_MODI_OUT_ETHERTYPE,
487 MLX5_MODI_OUT_DMAC_47_16,
488 MLX5_MODI_OUT_DMAC_15_0,
489 MLX5_MODI_OUT_IP_DSCP,
490 MLX5_MODI_OUT_TCP_FLAGS,
491 MLX5_MODI_OUT_TCP_SPORT,
492 MLX5_MODI_OUT_TCP_DPORT,
493 MLX5_MODI_OUT_IPV4_TTL,
494 MLX5_MODI_OUT_UDP_SPORT,
495 MLX5_MODI_OUT_UDP_DPORT,
496 MLX5_MODI_OUT_SIPV6_127_96,
497 MLX5_MODI_OUT_SIPV6_95_64,
498 MLX5_MODI_OUT_SIPV6_63_32,
499 MLX5_MODI_OUT_SIPV6_31_0,
500 MLX5_MODI_OUT_DIPV6_127_96,
501 MLX5_MODI_OUT_DIPV6_95_64,
502 MLX5_MODI_OUT_DIPV6_63_32,
503 MLX5_MODI_OUT_DIPV6_31_0,
506 MLX5_MODI_OUT_FIRST_VID,
507 MLX5_MODI_IN_SMAC_47_16 = 0x31,
508 MLX5_MODI_IN_SMAC_15_0,
509 MLX5_MODI_IN_ETHERTYPE,
510 MLX5_MODI_IN_DMAC_47_16,
511 MLX5_MODI_IN_DMAC_15_0,
512 MLX5_MODI_IN_IP_DSCP,
513 MLX5_MODI_IN_TCP_FLAGS,
514 MLX5_MODI_IN_TCP_SPORT,
515 MLX5_MODI_IN_TCP_DPORT,
516 MLX5_MODI_IN_IPV4_TTL,
517 MLX5_MODI_IN_UDP_SPORT,
518 MLX5_MODI_IN_UDP_DPORT,
519 MLX5_MODI_IN_SIPV6_127_96,
520 MLX5_MODI_IN_SIPV6_95_64,
521 MLX5_MODI_IN_SIPV6_63_32,
522 MLX5_MODI_IN_SIPV6_31_0,
523 MLX5_MODI_IN_DIPV6_127_96,
524 MLX5_MODI_IN_DIPV6_95_64,
525 MLX5_MODI_IN_DIPV6_63_32,
526 MLX5_MODI_IN_DIPV6_31_0,
529 MLX5_MODI_OUT_IPV6_HOPLIMIT,
530 MLX5_MODI_IN_IPV6_HOPLIMIT,
531 MLX5_MODI_META_DATA_REG_A,
532 MLX5_MODI_META_DATA_REG_B = 0x50,
533 MLX5_MODI_META_REG_C_0,
534 MLX5_MODI_META_REG_C_1,
535 MLX5_MODI_META_REG_C_2,
536 MLX5_MODI_META_REG_C_3,
537 MLX5_MODI_META_REG_C_4,
538 MLX5_MODI_META_REG_C_5,
539 MLX5_MODI_META_REG_C_6,
540 MLX5_MODI_META_REG_C_7,
541 MLX5_MODI_OUT_TCP_SEQ_NUM,
542 MLX5_MODI_IN_TCP_SEQ_NUM,
543 MLX5_MODI_OUT_TCP_ACK_NUM,
544 MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
547 /* Total number of metadata reg_c's. */
548 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
564 /* Modification sub command. */
565 struct mlx5_modification_cmd {
569 unsigned int length:5;
570 unsigned int rsvd0:3;
571 unsigned int offset:5;
572 unsigned int rsvd1:3;
573 unsigned int field:12;
574 unsigned int action_type:4;
581 unsigned int rsvd2:8;
582 unsigned int dst_offset:5;
583 unsigned int rsvd3:3;
584 unsigned int dst_field:12;
585 unsigned int rsvd4:4;
590 typedef uint32_t u32;
591 typedef uint16_t u16;
594 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
595 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
596 #define __mlx5_bit_off(typ, fld) ((unsigned int)(unsigned long) \
597 (&(__mlx5_nullp(typ)->fld)))
598 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
599 (__mlx5_bit_off(typ, fld) & 0x1f))
600 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
601 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
602 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
603 __mlx5_dw_bit_off(typ, fld))
604 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
605 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
606 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
607 (__mlx5_bit_off(typ, fld) & 0xf))
608 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
609 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
610 __mlx5_16_bit_off(typ, fld))
611 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
612 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
613 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
614 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
616 /* insert a value to a struct */
617 #define MLX5_SET(typ, p, fld, v) \
620 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
621 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
622 __mlx5_dw_off(typ, fld))) & \
623 (~__mlx5_dw_mask(typ, fld))) | \
624 (((_v) & __mlx5_mask(typ, fld)) << \
625 __mlx5_dw_bit_off(typ, fld))); \
628 #define MLX5_SET64(typ, p, fld, v) \
630 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
631 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = \
632 rte_cpu_to_be_64(v); \
635 #define MLX5_SET16(typ, p, fld, v) \
638 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
639 rte_cpu_to_be_16((rte_be_to_cpu_16(*((__be16 *)(p) + \
640 __mlx5_16_off(typ, fld))) & \
641 (~__mlx5_16_mask(typ, fld))) | \
642 (((_v) & __mlx5_mask16(typ, fld)) << \
643 __mlx5_16_bit_off(typ, fld))); \
646 #define MLX5_GET_VOLATILE(typ, p, fld) \
647 ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
648 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
649 __mlx5_mask(typ, fld))
650 #define MLX5_GET(typ, p, fld) \
651 ((rte_be_to_cpu_32(*((__be32 *)(p) +\
652 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
653 __mlx5_mask(typ, fld))
654 #define MLX5_GET16(typ, p, fld) \
655 ((rte_be_to_cpu_16(*((__be16 *)(p) + \
656 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
657 __mlx5_mask16(typ, fld))
658 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((__be64 *)(p) + \
659 __mlx5_64_off(typ, fld)))
660 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
662 struct mlx5_ifc_fte_match_set_misc_bits {
663 u8 gre_c_present[0x1];
664 u8 reserved_at_1[0x1];
665 u8 gre_k_present[0x1];
666 u8 gre_s_present[0x1];
667 u8 source_vhci_port[0x4];
669 u8 reserved_at_20[0x10];
670 u8 source_port[0x10];
671 u8 outer_second_prio[0x3];
672 u8 outer_second_cfi[0x1];
673 u8 outer_second_vid[0xc];
674 u8 inner_second_prio[0x3];
675 u8 inner_second_cfi[0x1];
676 u8 inner_second_vid[0xc];
677 u8 outer_second_cvlan_tag[0x1];
678 u8 inner_second_cvlan_tag[0x1];
679 u8 outer_second_svlan_tag[0x1];
680 u8 inner_second_svlan_tag[0x1];
681 u8 reserved_at_64[0xc];
682 u8 gre_protocol[0x10];
686 u8 reserved_at_b8[0x8];
688 u8 reserved_at_e4[0x7];
690 u8 reserved_at_e0[0xc];
691 u8 outer_ipv6_flow_label[0x14];
692 u8 reserved_at_100[0xc];
693 u8 inner_ipv6_flow_label[0x14];
694 u8 reserved_at_120[0xa];
695 u8 geneve_opt_len[0x6];
696 u8 geneve_protocol_type[0x10];
697 u8 reserved_at_140[0xc0];
700 struct mlx5_ifc_ipv4_layout_bits {
701 u8 reserved_at_0[0x60];
705 struct mlx5_ifc_ipv6_layout_bits {
709 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
710 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
711 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
712 u8 reserved_at_0[0x80];
715 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
734 u8 reserved_at_c0[0x18];
735 u8 ip_ttl_hoplimit[0x8];
738 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
739 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
742 struct mlx5_ifc_fte_match_mpls_bits {
749 struct mlx5_ifc_fte_match_set_misc2_bits {
750 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
751 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
752 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
753 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
754 u8 metadata_reg_c_7[0x20];
755 u8 metadata_reg_c_6[0x20];
756 u8 metadata_reg_c_5[0x20];
757 u8 metadata_reg_c_4[0x20];
758 u8 metadata_reg_c_3[0x20];
759 u8 metadata_reg_c_2[0x20];
760 u8 metadata_reg_c_1[0x20];
761 u8 metadata_reg_c_0[0x20];
762 u8 metadata_reg_a[0x20];
763 u8 metadata_reg_b[0x20];
764 u8 reserved_at_1c0[0x40];
767 struct mlx5_ifc_fte_match_set_misc3_bits {
768 u8 inner_tcp_seq_num[0x20];
769 u8 outer_tcp_seq_num[0x20];
770 u8 inner_tcp_ack_num[0x20];
771 u8 outer_tcp_ack_num[0x20];
772 u8 reserved_at_auto1[0x8];
773 u8 outer_vxlan_gpe_vni[0x18];
774 u8 outer_vxlan_gpe_next_protocol[0x8];
775 u8 outer_vxlan_gpe_flags[0x8];
776 u8 reserved_at_a8[0x10];
777 u8 icmp_header_data[0x20];
778 u8 icmpv6_header_data[0x20];
783 u8 reserved_at_120[0x20];
785 u8 gtpu_msg_type[0x08];
786 u8 gtpu_msg_flags[0x08];
787 u8 reserved_at_170[0x90];
791 struct mlx5_ifc_fte_match_param_bits {
792 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
793 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
794 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
795 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
796 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
800 MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
801 MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
802 MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
803 MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
804 MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT
808 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
809 MLX5_CMD_OP_CREATE_MKEY = 0x200,
810 MLX5_CMD_OP_CREATE_CQ = 0x400,
811 MLX5_CMD_OP_CREATE_QP = 0x500,
812 MLX5_CMD_OP_RST2INIT_QP = 0x502,
813 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
814 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
815 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
816 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
817 MLX5_CMD_OP_QP_2ERR = 0x507,
818 MLX5_CMD_OP_QP_2RST = 0x50A,
819 MLX5_CMD_OP_QUERY_QP = 0x50B,
820 MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
821 MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
822 MLX5_CMD_OP_SUSPEND_QP = 0x50F,
823 MLX5_CMD_OP_RESUME_QP = 0x510,
824 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
825 MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
826 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
827 MLX5_CMD_OP_CREATE_TIR = 0x900,
828 MLX5_CMD_OP_CREATE_SQ = 0X904,
829 MLX5_CMD_OP_MODIFY_SQ = 0X905,
830 MLX5_CMD_OP_CREATE_RQ = 0x908,
831 MLX5_CMD_OP_MODIFY_RQ = 0x909,
832 MLX5_CMD_OP_CREATE_TIS = 0x912,
833 MLX5_CMD_OP_QUERY_TIS = 0x915,
834 MLX5_CMD_OP_CREATE_RQT = 0x916,
835 MLX5_CMD_OP_MODIFY_RQT = 0x917,
836 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
837 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
838 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
839 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
840 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
841 MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
842 MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
843 MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
844 MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
845 MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
849 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
850 MLX5_MKC_ACCESS_MODE_KLM = 0x2,
851 MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
854 #define MLX5_ADAPTER_PAGE_SHIFT 12
855 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
857 * The batch counter dcs id starts from 0x800000 and none batch counter
858 * starts from 0. As currently, the counter is changed to be indexed by
859 * pool index and the offset of the counter in the pool counters_raw array.
860 * It means now the counter index is same for batch and none batch counter.
861 * Add the 0x800000 batch counter offset to the batch counter index helps
862 * indicate the counter index is from batch or none batch container pool.
864 #define MLX5_CNT_BATCH_OFFSET 0x800000
867 struct mlx5_ifc_alloc_flow_counter_out_bits {
869 u8 reserved_at_8[0x18];
871 u8 flow_counter_id[0x20];
872 u8 reserved_at_60[0x20];
875 struct mlx5_ifc_alloc_flow_counter_in_bits {
877 u8 reserved_at_10[0x10];
878 u8 reserved_at_20[0x10];
880 u8 flow_counter_id[0x20];
881 u8 reserved_at_40[0x18];
882 u8 flow_counter_bulk[0x8];
885 struct mlx5_ifc_dealloc_flow_counter_out_bits {
887 u8 reserved_at_8[0x18];
889 u8 reserved_at_40[0x40];
892 struct mlx5_ifc_dealloc_flow_counter_in_bits {
894 u8 reserved_at_10[0x10];
895 u8 reserved_at_20[0x10];
897 u8 flow_counter_id[0x20];
898 u8 reserved_at_60[0x20];
901 struct mlx5_ifc_traffic_counter_bits {
906 struct mlx5_ifc_query_flow_counter_out_bits {
908 u8 reserved_at_8[0x18];
910 u8 reserved_at_40[0x40];
911 struct mlx5_ifc_traffic_counter_bits flow_statistics[];
914 struct mlx5_ifc_query_flow_counter_in_bits {
916 u8 reserved_at_10[0x10];
917 u8 reserved_at_20[0x10];
919 u8 reserved_at_40[0x20];
923 u8 dump_to_memory[0x1];
924 u8 num_of_counters[0x1e];
925 u8 flow_counter_id[0x20];
928 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
929 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
932 struct mlx5_ifc_klm_bits {
938 struct mlx5_ifc_mkc_bits {
939 u8 reserved_at_0[0x1];
941 u8 reserved_at_2[0x1];
942 u8 access_mode_4_2[0x3];
943 u8 reserved_at_6[0x7];
944 u8 relaxed_ordering_write[0x1];
945 u8 reserved_at_e[0x1];
946 u8 small_fence_on_rdma_read_response[0x1];
953 u8 access_mode_1_0[0x2];
954 u8 reserved_at_18[0x8];
959 u8 reserved_at_40[0x20];
964 u8 reserved_at_63[0x2];
965 u8 expected_sigerr_count[0x1];
966 u8 reserved_at_66[0x1];
974 u8 bsf_octword_size[0x20];
976 u8 reserved_at_120[0x80];
978 u8 translations_octword_size[0x20];
980 u8 reserved_at_1c0[0x19];
981 u8 relaxed_ordering_read[0x1];
982 u8 reserved_at_1da[0x1];
983 u8 log_page_size[0x5];
985 u8 reserved_at_1e0[0x20];
988 struct mlx5_ifc_create_mkey_out_bits {
990 u8 reserved_at_8[0x18];
994 u8 reserved_at_40[0x8];
997 u8 reserved_at_60[0x20];
1000 struct mlx5_ifc_create_mkey_in_bits {
1002 u8 reserved_at_10[0x10];
1004 u8 reserved_at_20[0x10];
1007 u8 reserved_at_40[0x20];
1010 u8 reserved_at_61[0x1f];
1012 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1014 u8 reserved_at_280[0x80];
1016 u8 translations_octword_actual_size[0x20];
1018 u8 mkey_umem_id[0x20];
1020 u8 mkey_umem_offset[0x40];
1022 u8 reserved_at_380[0x500];
1024 u8 klm_pas_mtt[][0x20];
1028 MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1029 MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1030 MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1031 MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1035 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q = (1ULL << 0xd),
1036 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS = (1ULL << 0x1c),
1040 MLX5_HCA_CAP_OPMOD_GET_MAX = 0,
1041 MLX5_HCA_CAP_OPMOD_GET_CUR = 1,
1045 MLX5_CAP_INLINE_MODE_L2,
1046 MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1047 MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1051 MLX5_INLINE_MODE_NONE,
1052 MLX5_INLINE_MODE_L2,
1053 MLX5_INLINE_MODE_IP,
1054 MLX5_INLINE_MODE_TCP_UDP,
1055 MLX5_INLINE_MODE_RESERVED4,
1056 MLX5_INLINE_MODE_INNER_L2,
1057 MLX5_INLINE_MODE_INNER_IP,
1058 MLX5_INLINE_MODE_INNER_TCP_UDP,
1061 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1062 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1063 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1064 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1065 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1066 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1067 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1068 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1069 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1070 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1071 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1073 struct mlx5_ifc_cmd_hca_cap_bits {
1074 u8 reserved_at_0[0x30];
1076 u8 reserved_at_40[0x40];
1077 u8 log_max_srq_sz[0x8];
1078 u8 log_max_qp_sz[0x8];
1079 u8 reserved_at_90[0x9];
1080 u8 wqe_index_ignore_cap[0x1];
1081 u8 dynamic_qp_allocation[0x1];
1084 u8 reserved_at_a1[0x3];
1085 u8 regexp_num_of_engines[0x4];
1086 u8 reserved_at_a8[0x3];
1087 u8 log_max_srq[0x5];
1088 u8 reserved_at_b0[0x3];
1089 u8 regexp_log_crspace_size[0x5];
1090 u8 reserved_at_b8[0x8];
1091 u8 reserved_at_c0[0x8];
1092 u8 log_max_cq_sz[0x8];
1093 u8 reserved_at_d0[0xb];
1095 u8 log_max_eq_sz[0x8];
1096 u8 relaxed_ordering_write[0x1];
1097 u8 relaxed_ordering_read[0x1];
1098 u8 log_max_mkey[0x6];
1099 u8 reserved_at_f0[0x8];
1100 u8 dump_fill_mkey[0x1];
1101 u8 reserved_at_f9[0x3];
1103 u8 max_indirection[0x8];
1104 u8 fixed_buffer_size[0x1];
1105 u8 log_max_mrw_sz[0x7];
1106 u8 force_teardown[0x1];
1107 u8 reserved_at_111[0x1];
1108 u8 log_max_bsf_list_size[0x6];
1109 u8 umr_extended_translation_offset[0x1];
1111 u8 log_max_klm_list_size[0x6];
1112 u8 non_wire_sq[0x1];
1113 u8 reserved_at_121[0x9];
1114 u8 log_max_ra_req_dc[0x6];
1115 u8 reserved_at_130[0x3];
1116 u8 log_max_static_sq_wq[0x5];
1117 u8 reserved_at_138[0x2];
1118 u8 log_max_ra_res_dc[0x6];
1119 u8 reserved_at_140[0xa];
1120 u8 log_max_ra_req_qp[0x6];
1121 u8 reserved_at_150[0xa];
1122 u8 log_max_ra_res_qp[0x6];
1124 u8 cc_query_allowed[0x1];
1125 u8 cc_modify_allowed[0x1];
1127 u8 cache_line_128byte[0x1];
1128 u8 reserved_at_165[0xa];
1130 u8 gid_table_size[0x10];
1131 u8 out_of_seq_cnt[0x1];
1132 u8 vport_counters[0x1];
1133 u8 retransmission_q_counters[0x1];
1135 u8 modify_rq_counter_set_id[0x1];
1136 u8 rq_delay_drop[0x1];
1138 u8 pkey_table_size[0x10];
1139 u8 vport_group_manager[0x1];
1140 u8 vhca_group_manager[0x1];
1143 u8 vnic_env_queue_counters[0x1];
1145 u8 nic_flow_table[0x1];
1146 u8 eswitch_manager[0x1];
1147 u8 device_memory[0x1];
1150 u8 local_ca_ack_delay[0x5];
1151 u8 port_module_event[0x1];
1152 u8 enhanced_error_q_counters[0x1];
1153 u8 ports_check[0x1];
1154 u8 reserved_at_1b3[0x1];
1155 u8 disable_link_up[0x1];
1159 u8 reserved_at_1c0[0x1];
1162 u8 log_max_msg[0x5];
1163 u8 reserved_at_1c8[0x4];
1165 u8 temp_warn_event[0x1];
1167 u8 general_notification_event[0x1];
1168 u8 reserved_at_1d3[0x2];
1172 u8 reserved_at_1d8[0x1];
1180 u8 stat_rate_support[0x10];
1181 u8 reserved_at_1f0[0xc];
1182 u8 cqe_version[0x4];
1183 u8 compact_address_vector[0x1];
1184 u8 striding_rq[0x1];
1185 u8 reserved_at_202[0x1];
1186 u8 ipoib_enhanced_offloads[0x1];
1187 u8 ipoib_basic_offloads[0x1];
1188 u8 reserved_at_205[0x1];
1189 u8 repeated_block_disabled[0x1];
1190 u8 umr_modify_entity_size_disabled[0x1];
1191 u8 umr_modify_atomic_disabled[0x1];
1192 u8 umr_indirect_mkey_disabled[0x1];
1194 u8 reserved_at_20c[0x3];
1195 u8 drain_sigerr[0x1];
1196 u8 cmdif_checksum[0x2];
1198 u8 reserved_at_213[0x1];
1199 u8 wq_signature[0x1];
1200 u8 sctr_data_cqe[0x1];
1201 u8 reserved_at_216[0x1];
1207 u8 eth_net_offloads[0x1];
1210 u8 reserved_at_21f[0x1];
1213 u8 cq_moderation[0x1];
1214 u8 reserved_at_223[0x3];
1215 u8 cq_eq_remap[0x1];
1217 u8 block_lb_mc[0x1];
1218 u8 reserved_at_229[0x1];
1219 u8 scqe_break_moderation[0x1];
1220 u8 cq_period_start_from_cqe[0x1];
1222 u8 reserved_at_22d[0x1];
1224 u8 vector_calc[0x1];
1225 u8 umr_ptr_rlky[0x1];
1227 u8 reserved_at_232[0x4];
1230 u8 set_deth_sqpn[0x1];
1231 u8 reserved_at_239[0x3];
1237 u8 reserved_at_241[0x9];
1239 u8 reserved_at_250[0x8];
1242 u8 driver_version[0x1];
1243 u8 pad_tx_eth_packet[0x1];
1244 u8 reserved_at_263[0x8];
1245 u8 log_bf_reg_size[0x5];
1246 u8 reserved_at_270[0xb];
1248 u8 num_lag_ports[0x4];
1249 u8 reserved_at_280[0x10];
1250 u8 max_wqe_sz_sq[0x10];
1251 u8 reserved_at_2a0[0x10];
1252 u8 max_wqe_sz_rq[0x10];
1253 u8 max_flow_counter_31_16[0x10];
1254 u8 max_wqe_sz_sq_dc[0x10];
1255 u8 reserved_at_2e0[0x7];
1256 u8 max_qp_mcg[0x19];
1257 u8 reserved_at_300[0x10];
1258 u8 flow_counter_bulk_alloc[0x08];
1259 u8 log_max_mcg[0x8];
1260 u8 reserved_at_320[0x3];
1261 u8 log_max_transport_domain[0x5];
1262 u8 reserved_at_328[0x3];
1264 u8 reserved_at_330[0xb];
1265 u8 log_max_xrcd[0x5];
1266 u8 nic_receive_steering_discard[0x1];
1267 u8 receive_discard_vport_down[0x1];
1268 u8 transmit_discard_vport_down[0x1];
1269 u8 reserved_at_343[0x5];
1270 u8 log_max_flow_counter_bulk[0x8];
1271 u8 max_flow_counter_15_0[0x10];
1273 u8 flow_counters_dump[0x1];
1274 u8 reserved_at_360[0x1];
1276 u8 reserved_at_368[0x3];
1278 u8 reserved_at_370[0x3];
1279 u8 log_max_tir[0x5];
1280 u8 reserved_at_378[0x3];
1281 u8 log_max_tis[0x5];
1282 u8 basic_cyclic_rcv_wqe[0x1];
1283 u8 reserved_at_381[0x2];
1284 u8 log_max_rmp[0x5];
1285 u8 reserved_at_388[0x3];
1286 u8 log_max_rqt[0x5];
1287 u8 reserved_at_390[0x3];
1288 u8 log_max_rqt_size[0x5];
1289 u8 reserved_at_398[0x3];
1290 u8 log_max_tis_per_sq[0x5];
1291 u8 ext_stride_num_range[0x1];
1292 u8 reserved_at_3a1[0x2];
1293 u8 log_max_stride_sz_rq[0x5];
1294 u8 reserved_at_3a8[0x3];
1295 u8 log_min_stride_sz_rq[0x5];
1296 u8 reserved_at_3b0[0x3];
1297 u8 log_max_stride_sz_sq[0x5];
1298 u8 reserved_at_3b8[0x3];
1299 u8 log_min_stride_sz_sq[0x5];
1301 u8 reserved_at_3c1[0x2];
1302 u8 log_max_hairpin_queues[0x5];
1303 u8 reserved_at_3c8[0x3];
1304 u8 log_max_hairpin_wq_data_sz[0x5];
1305 u8 reserved_at_3d0[0x3];
1306 u8 log_max_hairpin_num_packets[0x5];
1307 u8 reserved_at_3d8[0x3];
1308 u8 log_max_wq_sz[0x5];
1309 u8 nic_vport_change_event[0x1];
1310 u8 disable_local_lb_uc[0x1];
1311 u8 disable_local_lb_mc[0x1];
1312 u8 log_min_hairpin_wq_data_sz[0x5];
1313 u8 reserved_at_3e8[0x3];
1314 u8 log_max_vlan_list[0x5];
1315 u8 reserved_at_3f0[0x3];
1316 u8 log_max_current_mc_list[0x5];
1317 u8 reserved_at_3f8[0x3];
1318 u8 log_max_current_uc_list[0x5];
1319 u8 general_obj_types[0x40];
1320 u8 reserved_at_440[0x20];
1321 u8 reserved_at_460[0x10];
1322 u8 max_num_eqs[0x10];
1323 u8 reserved_at_480[0x3];
1324 u8 log_max_l2_table[0x5];
1325 u8 reserved_at_488[0x8];
1326 u8 log_uar_page_sz[0x10];
1327 u8 reserved_at_4a0[0x20];
1328 u8 device_frequency_mhz[0x20];
1329 u8 device_frequency_khz[0x20];
1330 u8 reserved_at_500[0x20];
1331 u8 num_of_uars_per_page[0x20];
1332 u8 flex_parser_protocols[0x20];
1333 u8 reserved_at_560[0x20];
1334 u8 reserved_at_580[0x3c];
1335 u8 mini_cqe_resp_stride_index[0x1];
1336 u8 cqe_128_always[0x1];
1337 u8 cqe_compression_128[0x1];
1338 u8 cqe_compression[0x1];
1339 u8 cqe_compression_timeout[0x10];
1340 u8 cqe_compression_max_num[0x10];
1341 u8 reserved_at_5e0[0x10];
1342 u8 tag_matching[0x1];
1343 u8 rndv_offload_rc[0x1];
1344 u8 rndv_offload_dc[0x1];
1345 u8 log_tag_matching_list_sz[0x5];
1346 u8 reserved_at_5f8[0x3];
1347 u8 log_max_xrq[0x5];
1348 u8 affiliate_nic_vport_criteria[0x8];
1349 u8 native_port_num[0x8];
1350 u8 num_vhca_ports[0x8];
1351 u8 reserved_at_618[0x6];
1352 u8 sw_owner_id[0x1];
1353 u8 reserved_at_61f[0x1e1];
1356 struct mlx5_ifc_qos_cap_bits {
1357 u8 packet_pacing[0x1];
1358 u8 esw_scheduling[0x1];
1359 u8 esw_bw_share[0x1];
1360 u8 esw_rate_limit[0x1];
1361 u8 reserved_at_4[0x1];
1362 u8 packet_pacing_burst_bound[0x1];
1363 u8 packet_pacing_typical_size[0x1];
1364 u8 flow_meter_srtcm[0x1];
1365 u8 reserved_at_8[0x8];
1366 u8 log_max_flow_meter[0x8];
1367 u8 flow_meter_reg_id[0x8];
1368 u8 wqe_rate_pp[0x1];
1369 u8 reserved_at_25[0x7];
1370 u8 flow_meter_reg_share[0x1];
1371 u8 reserved_at_2e[0x17];
1372 u8 packet_pacing_max_rate[0x20];
1373 u8 packet_pacing_min_rate[0x20];
1374 u8 reserved_at_80[0x10];
1375 u8 packet_pacing_rate_table_size[0x10];
1376 u8 esw_element_type[0x10];
1377 u8 esw_tsar_type[0x10];
1378 u8 reserved_at_c0[0x10];
1379 u8 max_qos_para_vport[0x10];
1380 u8 max_tsar_bw_share[0x20];
1381 u8 reserved_at_100[0x6e8];
1384 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1388 u8 lro_psh_flag[0x1];
1389 u8 lro_time_stamp[0x1];
1390 u8 lro_max_msg_sz_mode[0x2];
1391 u8 wqe_vlan_insert[0x1];
1392 u8 self_lb_en_modifiable[0x1];
1395 u8 max_lso_cap[0x5];
1396 u8 multi_pkt_send_wqe[0x2];
1397 u8 wqe_inline_mode[0x2];
1398 u8 rss_ind_tbl_cap[0x4];
1400 u8 scatter_fcs[0x1];
1401 u8 enhanced_multi_pkt_send_wqe[0x1];
1402 u8 tunnel_lso_const_out_ip_id[0x1];
1403 u8 tunnel_lro_gre[0x1];
1404 u8 tunnel_lro_vxlan[0x1];
1405 u8 tunnel_stateless_gre[0x1];
1406 u8 tunnel_stateless_vxlan[0x1];
1410 u8 reserved_at_23[0x8];
1411 u8 tunnel_stateless_gtp[0x1];
1412 u8 reserved_at_25[0x4];
1413 u8 max_vxlan_udp_ports[0x8];
1414 u8 reserved_at_38[0x6];
1415 u8 max_geneve_opt_len[0x1];
1416 u8 tunnel_stateless_geneve_rx[0x1];
1417 u8 reserved_at_40[0x10];
1418 u8 lro_min_mss_size[0x10];
1419 u8 reserved_at_60[0x120];
1420 u8 lro_timer_supported_periods[4][0x20];
1421 u8 reserved_at_200[0x600];
1425 MLX5_VIRTQ_TYPE_SPLIT = 0,
1426 MLX5_VIRTQ_TYPE_PACKED = 1,
1430 MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1431 MLX5_VIRTQ_EVENT_MODE_QP = 1,
1432 MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1435 struct mlx5_ifc_virtio_emulation_cap_bits {
1436 u8 desc_tunnel_offload_type[0x1];
1437 u8 eth_frame_offload_type[0x1];
1438 u8 virtio_version_1_0[0x1];
1443 u8 reserved_at_7[0x1][0x9];
1445 u8 virtio_queue_type[0x8];
1446 u8 reserved_at_20[0x13];
1447 u8 log_doorbell_stride[0x5];
1448 u8 reserved_at_3b[0x3];
1449 u8 log_doorbell_bar_size[0x5];
1450 u8 doorbell_bar_offset[0x40];
1451 u8 reserved_at_80[0x8];
1452 u8 max_num_virtio_queues[0x18];
1453 u8 reserved_at_a0[0x60];
1454 u8 umem_1_buffer_param_a[0x20];
1455 u8 umem_1_buffer_param_b[0x20];
1456 u8 umem_2_buffer_param_a[0x20];
1457 u8 umem_2_buffer_param_b[0x20];
1458 u8 umem_3_buffer_param_a[0x20];
1459 u8 umem_3_buffer_param_b[0x20];
1460 u8 reserved_at_1c0[0x620];
1463 union mlx5_ifc_hca_cap_union_bits {
1464 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1465 struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1466 per_protocol_networking_offload_caps;
1467 struct mlx5_ifc_qos_cap_bits qos_cap;
1468 struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1469 u8 reserved_at_0[0x8000];
1472 struct mlx5_ifc_query_hca_cap_out_bits {
1474 u8 reserved_at_8[0x18];
1476 u8 reserved_at_40[0x40];
1477 union mlx5_ifc_hca_cap_union_bits capability;
1480 struct mlx5_ifc_query_hca_cap_in_bits {
1482 u8 reserved_at_10[0x10];
1483 u8 reserved_at_20[0x10];
1485 u8 reserved_at_40[0x40];
1488 struct mlx5_ifc_mac_address_layout_bits {
1489 u8 reserved_at_0[0x10];
1490 u8 mac_addr_47_32[0x10];
1491 u8 mac_addr_31_0[0x20];
1494 struct mlx5_ifc_nic_vport_context_bits {
1495 u8 reserved_at_0[0x5];
1496 u8 min_wqe_inline_mode[0x3];
1497 u8 reserved_at_8[0x15];
1498 u8 disable_mc_local_lb[0x1];
1499 u8 disable_uc_local_lb[0x1];
1501 u8 arm_change_event[0x1];
1502 u8 reserved_at_21[0x1a];
1503 u8 event_on_mtu[0x1];
1504 u8 event_on_promisc_change[0x1];
1505 u8 event_on_vlan_change[0x1];
1506 u8 event_on_mc_address_change[0x1];
1507 u8 event_on_uc_address_change[0x1];
1508 u8 reserved_at_40[0xc];
1509 u8 affiliation_criteria[0x4];
1510 u8 affiliated_vhca_id[0x10];
1511 u8 reserved_at_60[0xd0];
1513 u8 system_image_guid[0x40];
1516 u8 reserved_at_200[0x140];
1517 u8 qkey_violation_counter[0x10];
1518 u8 reserved_at_350[0x430];
1521 u8 promisc_all[0x1];
1522 u8 reserved_at_783[0x2];
1523 u8 allowed_list_type[0x3];
1524 u8 reserved_at_788[0xc];
1525 u8 allowed_list_size[0xc];
1526 struct mlx5_ifc_mac_address_layout_bits permanent_address;
1527 u8 reserved_at_7e0[0x20];
1530 struct mlx5_ifc_query_nic_vport_context_out_bits {
1532 u8 reserved_at_8[0x18];
1534 u8 reserved_at_40[0x40];
1535 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1538 struct mlx5_ifc_query_nic_vport_context_in_bits {
1540 u8 reserved_at_10[0x10];
1541 u8 reserved_at_20[0x10];
1543 u8 other_vport[0x1];
1544 u8 reserved_at_41[0xf];
1545 u8 vport_number[0x10];
1546 u8 reserved_at_60[0x5];
1547 u8 allowed_list_type[0x3];
1548 u8 reserved_at_68[0x18];
1551 struct mlx5_ifc_tisc_bits {
1552 u8 strict_lag_tx_port_affinity[0x1];
1553 u8 reserved_at_1[0x3];
1554 u8 lag_tx_port_affinity[0x04];
1555 u8 reserved_at_8[0x4];
1557 u8 reserved_at_10[0x10];
1558 u8 reserved_at_20[0x100];
1559 u8 reserved_at_120[0x8];
1560 u8 transport_domain[0x18];
1561 u8 reserved_at_140[0x8];
1562 u8 underlay_qpn[0x18];
1563 u8 reserved_at_160[0x3a0];
1566 struct mlx5_ifc_query_tis_out_bits {
1568 u8 reserved_at_8[0x18];
1570 u8 reserved_at_40[0x40];
1571 struct mlx5_ifc_tisc_bits tis_context;
1574 struct mlx5_ifc_query_tis_in_bits {
1576 u8 reserved_at_10[0x10];
1577 u8 reserved_at_20[0x10];
1579 u8 reserved_at_40[0x8];
1581 u8 reserved_at_60[0x20];
1584 struct mlx5_ifc_alloc_transport_domain_out_bits {
1586 u8 reserved_at_8[0x18];
1588 u8 reserved_at_40[0x8];
1589 u8 transport_domain[0x18];
1590 u8 reserved_at_60[0x20];
1593 struct mlx5_ifc_alloc_transport_domain_in_bits {
1595 u8 reserved_at_10[0x10];
1596 u8 reserved_at_20[0x10];
1598 u8 reserved_at_40[0x40];
1602 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
1603 MLX5_WQ_TYPE_CYCLIC = 0x1,
1604 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
1605 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,
1609 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
1610 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1613 struct mlx5_ifc_wq_bits {
1615 u8 wq_signature[0x1];
1616 u8 end_padding_mode[0x2];
1618 u8 reserved_at_8[0x18];
1619 u8 hds_skip_first_sge[0x1];
1620 u8 log2_hds_buf_size[0x3];
1621 u8 reserved_at_24[0x7];
1622 u8 page_offset[0x5];
1624 u8 reserved_at_40[0x8];
1626 u8 reserved_at_60[0x8];
1629 u8 hw_counter[0x20];
1630 u8 sw_counter[0x20];
1631 u8 reserved_at_100[0xc];
1632 u8 log_wq_stride[0x4];
1633 u8 reserved_at_110[0x3];
1634 u8 log_wq_pg_sz[0x5];
1635 u8 reserved_at_118[0x3];
1637 u8 dbr_umem_valid[0x1];
1638 u8 wq_umem_valid[0x1];
1639 u8 reserved_at_122[0x1];
1640 u8 log_hairpin_num_packets[0x5];
1641 u8 reserved_at_128[0x3];
1642 u8 log_hairpin_data_sz[0x5];
1643 u8 reserved_at_130[0x4];
1644 u8 single_wqe_log_num_of_strides[0x4];
1645 u8 two_byte_shift_en[0x1];
1646 u8 reserved_at_139[0x4];
1647 u8 single_stride_log_num_of_bytes[0x3];
1648 u8 dbr_umem_id[0x20];
1649 u8 wq_umem_id[0x20];
1650 u8 wq_umem_offset[0x40];
1651 u8 reserved_at_1c0[0x440];
1655 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
1656 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
1660 MLX5_RQC_STATE_RST = 0x0,
1661 MLX5_RQC_STATE_RDY = 0x1,
1662 MLX5_RQC_STATE_ERR = 0x3,
1665 struct mlx5_ifc_rqc_bits {
1667 u8 delay_drop_en[0x1];
1668 u8 scatter_fcs[0x1];
1670 u8 mem_rq_type[0x4];
1672 u8 reserved_at_c[0x1];
1673 u8 flush_in_error_en[0x1];
1675 u8 reserved_at_f[0x11];
1676 u8 reserved_at_20[0x8];
1677 u8 user_index[0x18];
1678 u8 reserved_at_40[0x8];
1680 u8 counter_set_id[0x8];
1681 u8 reserved_at_68[0x18];
1682 u8 reserved_at_80[0x8];
1684 u8 reserved_at_a0[0x8];
1685 u8 hairpin_peer_sq[0x18];
1686 u8 reserved_at_c0[0x10];
1687 u8 hairpin_peer_vhca[0x10];
1688 u8 reserved_at_e0[0xa0];
1689 struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1692 struct mlx5_ifc_create_rq_out_bits {
1694 u8 reserved_at_8[0x18];
1696 u8 reserved_at_40[0x8];
1698 u8 reserved_at_60[0x20];
1701 struct mlx5_ifc_create_rq_in_bits {
1704 u8 reserved_at_20[0x10];
1706 u8 reserved_at_40[0xc0];
1707 struct mlx5_ifc_rqc_bits ctx;
1710 struct mlx5_ifc_modify_rq_out_bits {
1712 u8 reserved_at_8[0x18];
1714 u8 reserved_at_40[0x40];
1717 struct mlx5_ifc_create_tis_out_bits {
1719 u8 reserved_at_8[0x18];
1721 u8 reserved_at_40[0x8];
1723 u8 reserved_at_60[0x20];
1726 struct mlx5_ifc_create_tis_in_bits {
1729 u8 reserved_at_20[0x10];
1731 u8 reserved_at_40[0xc0];
1732 struct mlx5_ifc_tisc_bits ctx;
1736 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
1737 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
1738 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
1739 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
1742 struct mlx5_ifc_modify_rq_in_bits {
1745 u8 reserved_at_20[0x10];
1748 u8 reserved_at_44[0x4];
1750 u8 reserved_at_60[0x20];
1751 u8 modify_bitmask[0x40];
1752 u8 reserved_at_c0[0x40];
1753 struct mlx5_ifc_rqc_bits ctx;
1757 MLX5_L3_PROT_TYPE_IPV4 = 0,
1758 MLX5_L3_PROT_TYPE_IPV6 = 1,
1762 MLX5_L4_PROT_TYPE_TCP = 0,
1763 MLX5_L4_PROT_TYPE_UDP = 1,
1767 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1768 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1769 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1770 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1771 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1774 struct mlx5_ifc_rx_hash_field_select_bits {
1775 u8 l3_prot_type[0x1];
1776 u8 l4_prot_type[0x1];
1777 u8 selected_fields[0x1e];
1781 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1782 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1786 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1787 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1791 MLX5_RX_HASH_FN_NONE = 0x0,
1792 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1793 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
1797 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1,
1798 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2,
1802 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4 = 0x0,
1803 MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2 = 0x1,
1806 struct mlx5_ifc_tirc_bits {
1807 u8 reserved_at_0[0x20];
1809 u8 reserved_at_24[0x1c];
1810 u8 reserved_at_40[0x40];
1811 u8 reserved_at_80[0x4];
1812 u8 lro_timeout_period_usecs[0x10];
1813 u8 lro_enable_mask[0x4];
1814 u8 lro_max_msg_sz[0x8];
1815 u8 reserved_at_a0[0x40];
1816 u8 reserved_at_e0[0x8];
1817 u8 inline_rqn[0x18];
1818 u8 rx_hash_symmetric[0x1];
1819 u8 reserved_at_101[0x1];
1820 u8 tunneled_offload_en[0x1];
1821 u8 reserved_at_103[0x5];
1822 u8 indirect_table[0x18];
1824 u8 reserved_at_124[0x2];
1825 u8 self_lb_block[0x2];
1826 u8 transport_domain[0x18];
1827 u8 rx_hash_toeplitz_key[10][0x20];
1828 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1829 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1830 u8 reserved_at_2c0[0x4c0];
1833 struct mlx5_ifc_create_tir_out_bits {
1835 u8 reserved_at_8[0x18];
1837 u8 reserved_at_40[0x8];
1839 u8 reserved_at_60[0x20];
1842 struct mlx5_ifc_create_tir_in_bits {
1845 u8 reserved_at_20[0x10];
1847 u8 reserved_at_40[0xc0];
1848 struct mlx5_ifc_tirc_bits ctx;
1852 MLX5_INLINE_Q_TYPE_RQ = 0x0,
1853 MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
1856 struct mlx5_ifc_rq_num_bits {
1857 u8 reserved_at_0[0x8];
1861 struct mlx5_ifc_rqtc_bits {
1862 u8 reserved_at_0[0xa5];
1863 u8 list_q_type[0x3];
1864 u8 reserved_at_a8[0x8];
1865 u8 rqt_max_size[0x10];
1866 u8 reserved_at_c0[0x10];
1867 u8 rqt_actual_size[0x10];
1868 u8 reserved_at_e0[0x6a0];
1869 struct mlx5_ifc_rq_num_bits rq_num[];
1872 struct mlx5_ifc_create_rqt_out_bits {
1874 u8 reserved_at_8[0x18];
1876 u8 reserved_at_40[0x8];
1878 u8 reserved_at_60[0x20];
1882 #pragma GCC diagnostic ignored "-Wpedantic"
1884 struct mlx5_ifc_create_rqt_in_bits {
1887 u8 reserved_at_20[0x10];
1889 u8 reserved_at_40[0xc0];
1890 struct mlx5_ifc_rqtc_bits rqt_context;
1893 struct mlx5_ifc_modify_rqt_in_bits {
1896 u8 reserved_at_20[0x10];
1898 u8 reserved_at_40[0x8];
1900 u8 reserved_at_60[0x20];
1901 u8 modify_bitmask[0x40];
1902 u8 reserved_at_c0[0x40];
1903 struct mlx5_ifc_rqtc_bits rqt_context;
1906 #pragma GCC diagnostic error "-Wpedantic"
1909 struct mlx5_ifc_modify_rqt_out_bits {
1911 u8 reserved_at_8[0x18];
1913 u8 reserved_at_40[0x40];
1917 MLX5_SQC_STATE_RST = 0x0,
1918 MLX5_SQC_STATE_RDY = 0x1,
1919 MLX5_SQC_STATE_ERR = 0x3,
1922 struct mlx5_ifc_sqc_bits {
1926 u8 flush_in_error_en[0x1];
1927 u8 allow_multi_pkt_send_wqe[0x1];
1928 u8 min_wqe_inline_mode[0x3];
1934 u8 static_sq_wq[0x1];
1935 u8 reserved_at_11[0xf];
1936 u8 reserved_at_20[0x8];
1937 u8 user_index[0x18];
1938 u8 reserved_at_40[0x8];
1940 u8 reserved_at_60[0x8];
1941 u8 hairpin_peer_rq[0x18];
1942 u8 reserved_at_80[0x10];
1943 u8 hairpin_peer_vhca[0x10];
1944 u8 reserved_at_a0[0x50];
1945 u8 packet_pacing_rate_limit_index[0x10];
1946 u8 tis_lst_sz[0x10];
1947 u8 reserved_at_110[0x10];
1948 u8 reserved_at_120[0x40];
1949 u8 reserved_at_160[0x8];
1951 struct mlx5_ifc_wq_bits wq;
1954 struct mlx5_ifc_query_sq_in_bits {
1956 u8 reserved_at_10[0x10];
1957 u8 reserved_at_20[0x10];
1959 u8 reserved_at_40[0x8];
1961 u8 reserved_at_60[0x20];
1964 struct mlx5_ifc_modify_sq_out_bits {
1966 u8 reserved_at_8[0x18];
1968 u8 reserved_at_40[0x40];
1971 struct mlx5_ifc_modify_sq_in_bits {
1974 u8 reserved_at_20[0x10];
1977 u8 reserved_at_44[0x4];
1979 u8 reserved_at_60[0x20];
1980 u8 modify_bitmask[0x40];
1981 u8 reserved_at_c0[0x40];
1982 struct mlx5_ifc_sqc_bits ctx;
1985 struct mlx5_ifc_create_sq_out_bits {
1987 u8 reserved_at_8[0x18];
1989 u8 reserved_at_40[0x8];
1991 u8 reserved_at_60[0x20];
1994 struct mlx5_ifc_create_sq_in_bits {
1997 u8 reserved_at_20[0x10];
1999 u8 reserved_at_40[0xc0];
2000 struct mlx5_ifc_sqc_bits ctx;
2004 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2005 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2006 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2007 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2008 MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2011 struct mlx5_ifc_flow_meter_parameters_bits {
2012 u8 valid[0x1]; // 00h
2013 u8 bucket_overflow[0x1];
2014 u8 start_color[0x2];
2015 u8 both_buckets_on_green[0x1];
2017 u8 reserved_at_1[0x19];
2018 u8 reserved_at_2[0x20]; //04h
2019 u8 reserved_at_3[0x3];
2020 u8 cbs_exponent[0x5]; // 08h
2021 u8 cbs_mantissa[0x8];
2022 u8 reserved_at_4[0x3];
2023 u8 cir_exponent[0x5];
2024 u8 cir_mantissa[0x8];
2025 u8 reserved_at_5[0x20]; // 0Ch
2026 u8 reserved_at_6[0x3];
2027 u8 ebs_exponent[0x5]; // 10h
2028 u8 ebs_mantissa[0x8];
2029 u8 reserved_at_7[0x3];
2030 u8 eir_exponent[0x5];
2031 u8 eir_mantissa[0x8];
2032 u8 reserved_at_8[0x60]; // 14h-1Ch
2036 MLX5_CQE_SIZE_64B = 0x0,
2037 MLX5_CQE_SIZE_128B = 0x1,
2040 struct mlx5_ifc_cqc_bits {
2043 u8 initiator_src_dct[0x1];
2044 u8 dbr_umem_valid[0x1];
2045 u8 reserved_at_7[0x1];
2048 u8 reserved_at_c[0x1];
2049 u8 scqe_break_moderation_en[0x1];
2051 u8 cq_period_mode[0x2];
2052 u8 cqe_comp_en[0x1];
2053 u8 mini_cqe_res_format[0x2];
2055 u8 reserved_at_18[0x8];
2056 u8 dbr_umem_id[0x20];
2057 u8 reserved_at_40[0x14];
2058 u8 page_offset[0x6];
2059 u8 reserved_at_5a[0x6];
2060 u8 reserved_at_60[0x3];
2061 u8 log_cq_size[0x5];
2063 u8 reserved_at_80[0x4];
2065 u8 cq_max_count[0x10];
2066 u8 reserved_at_a0[0x18];
2068 u8 reserved_at_c0[0x3];
2069 u8 log_page_size[0x5];
2070 u8 reserved_at_c8[0x18];
2071 u8 reserved_at_e0[0x20];
2072 u8 reserved_at_100[0x8];
2073 u8 last_notified_index[0x18];
2074 u8 reserved_at_120[0x8];
2075 u8 last_solicit_index[0x18];
2076 u8 reserved_at_140[0x8];
2077 u8 consumer_counter[0x18];
2078 u8 reserved_at_160[0x8];
2079 u8 producer_counter[0x18];
2080 u8 local_partition_id[0xc];
2081 u8 process_id[0x14];
2082 u8 reserved_at_1A0[0x20];
2086 struct mlx5_ifc_create_cq_out_bits {
2088 u8 reserved_at_8[0x18];
2090 u8 reserved_at_40[0x8];
2092 u8 reserved_at_60[0x20];
2095 struct mlx5_ifc_create_cq_in_bits {
2098 u8 reserved_at_20[0x10];
2100 u8 reserved_at_40[0x40];
2101 struct mlx5_ifc_cqc_bits cq_context;
2102 u8 cq_umem_offset[0x40];
2103 u8 cq_umem_id[0x20];
2104 u8 cq_umem_valid[0x1];
2105 u8 reserved_at_2e1[0x1f];
2106 u8 reserved_at_300[0x580];
2111 MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2112 MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2115 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2117 u8 reserved_at_10[0x20];
2120 u8 reserved_at_60[0x20];
2123 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2125 u8 reserved_at_8[0x18];
2128 u8 reserved_at_60[0x20];
2131 struct mlx5_ifc_virtio_q_counters_bits {
2132 u8 modify_field_select[0x40];
2133 u8 reserved_at_40[0x40];
2134 u8 received_desc[0x40];
2135 u8 completed_desc[0x40];
2136 u8 error_cqes[0x20];
2137 u8 bad_desc_errors[0x20];
2138 u8 exceed_max_chain[0x20];
2139 u8 invalid_buffer[0x20];
2140 u8 reserved_at_180[0x50];
2143 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2144 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2145 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2148 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2149 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2150 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2153 MLX5_VIRTQ_STATE_INIT = 0,
2154 MLX5_VIRTQ_STATE_RDY = 1,
2155 MLX5_VIRTQ_STATE_SUSPEND = 2,
2156 MLX5_VIRTQ_STATE_ERROR = 3,
2160 MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2161 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2162 MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2165 struct mlx5_ifc_virtio_q_bits {
2166 u8 virtio_q_type[0x8];
2167 u8 reserved_at_8[0x5];
2169 u8 queue_index[0x10];
2170 u8 full_emulation[0x1];
2171 u8 virtio_version_1_0[0x1];
2172 u8 reserved_at_22[0x2];
2173 u8 offload_type[0x4];
2174 u8 event_qpn_or_msix[0x18];
2175 u8 doorbell_stride_idx[0x10];
2176 u8 queue_size[0x10];
2177 u8 device_emulation_id[0x20];
2180 u8 available_addr[0x40];
2181 u8 virtio_q_mkey[0x20];
2182 u8 reserved_at_160[0x20];
2184 u8 umem_1_size[0x20];
2185 u8 umem_1_offset[0x40];
2187 u8 umem_2_size[0x20];
2188 u8 umem_2_offset[0x40];
2190 u8 umem_3_size[0x20];
2191 u8 umem_3_offset[0x40];
2192 u8 counter_set_id[0x20];
2193 u8 reserved_at_320[0x8];
2195 u8 reserved_at_340[0xc0];
2198 struct mlx5_ifc_virtio_net_q_bits {
2199 u8 modify_field_select[0x40];
2200 u8 reserved_at_40[0x40];
2205 u8 reserved_at_84[0x6];
2206 u8 dirty_bitmap_dump_enable[0x1];
2207 u8 vhost_log_page[0x5];
2208 u8 reserved_at_90[0xc];
2211 u8 tisn_or_qpn[0x18];
2212 u8 dirty_bitmap_mkey[0x20];
2213 u8 dirty_bitmap_size[0x20];
2214 u8 dirty_bitmap_addr[0x40];
2215 u8 hw_available_index[0x10];
2216 u8 hw_used_index[0x10];
2217 u8 reserved_at_160[0xa0];
2218 struct mlx5_ifc_virtio_q_bits virtio_q_context;
2221 struct mlx5_ifc_create_virtq_in_bits {
2222 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2223 struct mlx5_ifc_virtio_net_q_bits virtq;
2226 struct mlx5_ifc_query_virtq_out_bits {
2227 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2228 struct mlx5_ifc_virtio_net_q_bits virtq;
2232 MLX5_QP_ST_RC = 0x0,
2236 MLX5_QP_PM_MIGRATED = 0x3,
2240 MLX5_NON_ZERO_RQ = 0x0,
2243 MLX5_ZERO_LEN_RQ = 0x3,
2246 struct mlx5_ifc_ads_bits {
2249 u8 reserved_at_2[0xe];
2250 u8 pkey_index[0x10];
2251 u8 reserved_at_20[0x8];
2255 u8 ack_timeout[0x5];
2256 u8 reserved_at_45[0x3];
2257 u8 src_addr_index[0x8];
2258 u8 reserved_at_50[0x4];
2261 u8 reserved_at_60[0x4];
2263 u8 flow_label[0x14];
2264 u8 rgid_rip[16][0x8];
2265 u8 reserved_at_100[0x4];
2268 u8 reserved_at_106[0x1];
2276 u8 vhca_port_num[0x8];
2277 u8 rmac_47_32[0x10];
2281 struct mlx5_ifc_qpc_bits {
2283 u8 lag_tx_port_affinity[0x4];
2285 u8 reserved_at_10[0x3];
2287 u8 reserved_at_15[0x1];
2288 u8 req_e2e_credit_mode[0x2];
2289 u8 offload_type[0x4];
2290 u8 end_padding_mode[0x2];
2291 u8 reserved_at_1e[0x2];
2292 u8 wq_signature[0x1];
2293 u8 block_lb_mc[0x1];
2294 u8 atomic_like_write_en[0x1];
2295 u8 latency_sensitive[0x1];
2296 u8 reserved_at_24[0x1];
2297 u8 drain_sigerr[0x1];
2298 u8 reserved_at_26[0x2];
2301 u8 log_msg_max[0x5];
2302 u8 reserved_at_48[0x1];
2303 u8 log_rq_size[0x4];
2304 u8 log_rq_stride[0x3];
2306 u8 log_sq_size[0x4];
2307 u8 reserved_at_55[0x6];
2309 u8 ulp_stateless_offload_mode[0x4];
2310 u8 counter_set_id[0x8];
2312 u8 reserved_at_80[0x8];
2313 u8 user_index[0x18];
2314 u8 reserved_at_a0[0x3];
2315 u8 log_page_size[0x5];
2316 u8 remote_qpn[0x18];
2317 struct mlx5_ifc_ads_bits primary_address_path;
2318 struct mlx5_ifc_ads_bits secondary_address_path;
2319 u8 log_ack_req_freq[0x4];
2320 u8 reserved_at_384[0x4];
2321 u8 log_sra_max[0x3];
2322 u8 reserved_at_38b[0x2];
2323 u8 retry_count[0x3];
2325 u8 reserved_at_393[0x1];
2327 u8 cur_rnr_retry[0x3];
2328 u8 cur_retry_count[0x3];
2329 u8 reserved_at_39b[0x5];
2330 u8 reserved_at_3a0[0x20];
2331 u8 reserved_at_3c0[0x8];
2332 u8 next_send_psn[0x18];
2333 u8 reserved_at_3e0[0x8];
2335 u8 reserved_at_400[0x8];
2337 u8 reserved_at_420[0x20];
2338 u8 reserved_at_440[0x8];
2339 u8 last_acked_psn[0x18];
2340 u8 reserved_at_460[0x8];
2342 u8 reserved_at_480[0x8];
2343 u8 log_rra_max[0x3];
2344 u8 reserved_at_48b[0x1];
2345 u8 atomic_mode[0x4];
2349 u8 reserved_at_493[0x1];
2350 u8 page_offset[0x6];
2351 u8 reserved_at_49a[0x3];
2352 u8 cd_slave_receive[0x1];
2353 u8 cd_slave_send[0x1];
2355 u8 reserved_at_4a0[0x3];
2356 u8 min_rnr_nak[0x5];
2357 u8 next_rcv_psn[0x18];
2358 u8 reserved_at_4c0[0x8];
2360 u8 reserved_at_4e0[0x8];
2364 u8 reserved_at_560[0x5];
2366 u8 srqn_rmpn_xrqn[0x18];
2367 u8 reserved_at_580[0x8];
2369 u8 hw_sq_wqebb_counter[0x10];
2370 u8 sw_sq_wqebb_counter[0x10];
2371 u8 hw_rq_counter[0x20];
2372 u8 sw_rq_counter[0x20];
2373 u8 reserved_at_600[0x20];
2374 u8 reserved_at_620[0xf];
2378 u8 dc_access_key[0x40];
2379 u8 reserved_at_680[0x3];
2380 u8 dbr_umem_valid[0x1];
2381 u8 reserved_at_684[0x9c];
2382 u8 dbr_umem_id[0x20];
2385 struct mlx5_ifc_create_qp_out_bits {
2387 u8 reserved_at_8[0x18];
2389 u8 reserved_at_40[0x8];
2391 u8 reserved_at_60[0x20];
2395 #pragma GCC diagnostic ignored "-Wpedantic"
2397 struct mlx5_ifc_create_qp_in_bits {
2400 u8 reserved_at_20[0x10];
2402 u8 reserved_at_40[0x40];
2403 u8 opt_param_mask[0x20];
2404 u8 reserved_at_a0[0x20];
2405 struct mlx5_ifc_qpc_bits qpc;
2406 u8 wq_umem_offset[0x40];
2407 u8 wq_umem_id[0x20];
2408 u8 wq_umem_valid[0x1];
2409 u8 reserved_at_861[0x1f];
2413 #pragma GCC diagnostic error "-Wpedantic"
2416 struct mlx5_ifc_sqerr2rts_qp_out_bits {
2418 u8 reserved_at_8[0x18];
2420 u8 reserved_at_40[0x40];
2423 struct mlx5_ifc_sqerr2rts_qp_in_bits {
2426 u8 reserved_at_20[0x10];
2428 u8 reserved_at_40[0x8];
2430 u8 reserved_at_60[0x20];
2431 u8 opt_param_mask[0x20];
2432 u8 reserved_at_a0[0x20];
2433 struct mlx5_ifc_qpc_bits qpc;
2434 u8 reserved_at_800[0x80];
2437 struct mlx5_ifc_sqd2rts_qp_out_bits {
2439 u8 reserved_at_8[0x18];
2441 u8 reserved_at_40[0x40];
2444 struct mlx5_ifc_sqd2rts_qp_in_bits {
2447 u8 reserved_at_20[0x10];
2449 u8 reserved_at_40[0x8];
2451 u8 reserved_at_60[0x20];
2452 u8 opt_param_mask[0x20];
2453 u8 reserved_at_a0[0x20];
2454 struct mlx5_ifc_qpc_bits qpc;
2455 u8 reserved_at_800[0x80];
2458 struct mlx5_ifc_rts2rts_qp_out_bits {
2460 u8 reserved_at_8[0x18];
2462 u8 reserved_at_40[0x40];
2465 struct mlx5_ifc_rts2rts_qp_in_bits {
2468 u8 reserved_at_20[0x10];
2470 u8 reserved_at_40[0x8];
2472 u8 reserved_at_60[0x20];
2473 u8 opt_param_mask[0x20];
2474 u8 reserved_at_a0[0x20];
2475 struct mlx5_ifc_qpc_bits qpc;
2476 u8 reserved_at_800[0x80];
2479 struct mlx5_ifc_rtr2rts_qp_out_bits {
2481 u8 reserved_at_8[0x18];
2483 u8 reserved_at_40[0x40];
2486 struct mlx5_ifc_rtr2rts_qp_in_bits {
2489 u8 reserved_at_20[0x10];
2491 u8 reserved_at_40[0x8];
2493 u8 reserved_at_60[0x20];
2494 u8 opt_param_mask[0x20];
2495 u8 reserved_at_a0[0x20];
2496 struct mlx5_ifc_qpc_bits qpc;
2497 u8 reserved_at_800[0x80];
2500 struct mlx5_ifc_rst2init_qp_out_bits {
2502 u8 reserved_at_8[0x18];
2504 u8 reserved_at_40[0x40];
2507 struct mlx5_ifc_rst2init_qp_in_bits {
2510 u8 reserved_at_20[0x10];
2512 u8 reserved_at_40[0x8];
2514 u8 reserved_at_60[0x20];
2515 u8 opt_param_mask[0x20];
2516 u8 reserved_at_a0[0x20];
2517 struct mlx5_ifc_qpc_bits qpc;
2518 u8 reserved_at_800[0x80];
2521 struct mlx5_ifc_init2rtr_qp_out_bits {
2523 u8 reserved_at_8[0x18];
2525 u8 reserved_at_40[0x40];
2528 struct mlx5_ifc_init2rtr_qp_in_bits {
2531 u8 reserved_at_20[0x10];
2533 u8 reserved_at_40[0x8];
2535 u8 reserved_at_60[0x20];
2536 u8 opt_param_mask[0x20];
2537 u8 reserved_at_a0[0x20];
2538 struct mlx5_ifc_qpc_bits qpc;
2539 u8 reserved_at_800[0x80];
2542 struct mlx5_ifc_init2init_qp_out_bits {
2544 u8 reserved_at_8[0x18];
2546 u8 reserved_at_40[0x40];
2549 struct mlx5_ifc_init2init_qp_in_bits {
2552 u8 reserved_at_20[0x10];
2554 u8 reserved_at_40[0x8];
2556 u8 reserved_at_60[0x20];
2557 u8 opt_param_mask[0x20];
2558 u8 reserved_at_a0[0x20];
2559 struct mlx5_ifc_qpc_bits qpc;
2560 u8 reserved_at_800[0x80];
2564 #pragma GCC diagnostic ignored "-Wpedantic"
2566 struct mlx5_ifc_query_qp_out_bits {
2568 u8 reserved_at_8[0x18];
2570 u8 reserved_at_40[0x40];
2571 u8 opt_param_mask[0x20];
2572 u8 reserved_at_a0[0x20];
2573 struct mlx5_ifc_qpc_bits qpc;
2574 u8 reserved_at_800[0x80];
2578 #pragma GCC diagnostic error "-Wpedantic"
2581 struct mlx5_ifc_query_qp_in_bits {
2583 u8 reserved_at_10[0x10];
2584 u8 reserved_at_20[0x10];
2586 u8 reserved_at_40[0x8];
2588 u8 reserved_at_60[0x20];
2592 MLX5_DATA_RATE = 0x0,
2593 MLX5_WQE_RATE = 0x1,
2596 struct mlx5_ifc_set_pp_rate_limit_context_bits {
2597 u8 rate_limit[0x20];
2598 u8 burst_upper_bound[0x20];
2599 u8 reserved_at_40[0xC];
2601 u8 typical_packet_size[0x10];
2602 u8 reserved_at_60[0x120];
2605 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
2608 #pragma GCC diagnostic ignored "-Wpedantic"
2610 struct mlx5_ifc_access_register_out_bits {
2612 u8 reserved_at_8[0x18];
2614 u8 reserved_at_40[0x40];
2615 u8 register_data[0][0x20];
2618 struct mlx5_ifc_access_register_in_bits {
2620 u8 reserved_at_10[0x10];
2621 u8 reserved_at_20[0x10];
2623 u8 reserved_at_40[0x10];
2624 u8 register_id[0x10];
2626 u8 register_data[0][0x20];
2629 #pragma GCC diagnostic error "-Wpedantic"
2633 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
2634 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
2638 MLX5_REGISTER_ID_MTUTC = 0x9055,
2641 struct mlx5_ifc_register_mtutc_bits {
2642 u8 time_stamp_mode[0x2];
2643 u8 time_stamp_state[0x2];
2644 u8 reserved_at_4[0x18];
2646 u8 freq_adjustment[0x20];
2647 u8 reserved_at_40[0x40];
2650 u8 time_adjustment[0x20];
2653 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
2654 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
2656 struct regexp_params_field_select_bits {
2657 u8 reserved_at_0[0x1e];
2658 u8 stop_engine[0x1];
2662 struct mlx5_ifc_regexp_params_bits {
2663 u8 reserved_at_0[0x1f];
2664 u8 stop_engine[0x1];
2665 u8 db_umem_id[0x20];
2666 u8 db_umem_offset[0x40];
2667 u8 reserved_at_80[0x100];
2670 struct mlx5_ifc_set_regexp_params_in_bits {
2673 u8 reserved_at_20[0x10];
2675 u8 reserved_at_40[0x18];
2677 struct regexp_params_field_select_bits field_select;
2678 struct mlx5_ifc_regexp_params_bits regexp_params;
2681 struct mlx5_ifc_set_regexp_params_out_bits {
2683 u8 reserved_at_8[0x18];
2685 u8 reserved_at_18[0x40];
2688 struct mlx5_ifc_query_regexp_params_in_bits {
2691 u8 reserved_at_20[0x10];
2693 u8 reserved_at_40[0x18];
2698 struct mlx5_ifc_query_regexp_params_out_bits {
2700 u8 reserved_at_8[0x18];
2703 struct mlx5_ifc_regexp_params_bits regexp_params;
2706 struct mlx5_ifc_set_regexp_register_in_bits {
2709 u8 reserved_at_20[0x10];
2711 u8 reserved_at_40[0x18];
2713 u8 register_address[0x20];
2714 u8 register_data[0x20];
2718 struct mlx5_ifc_set_regexp_register_out_bits {
2720 u8 reserved_at_8[0x18];
2725 struct mlx5_ifc_query_regexp_register_in_bits {
2728 u8 reserved_at_20[0x10];
2730 u8 reserved_at_40[0x18];
2732 u8 register_address[0x20];
2735 struct mlx5_ifc_query_regexp_register_out_bits {
2737 u8 reserved_at_8[0x18];
2740 u8 register_data[0x20];
2743 /* CQE format mask. */
2744 #define MLX5E_CQE_FORMAT_MASK 0xc
2747 #define MLX5_OPC_MOD_MPW 0x01
2749 /* Compressed Rx CQE structure. */
2750 struct mlx5_mini_cqe8 {
2752 uint32_t rx_hash_result;
2755 uint16_t stride_idx;
2758 uint16_t wqe_counter;
2759 uint8_t s_wqe_opcode;
2766 /* srTCM PRM flow meter parameters. */
2768 MLX5_FLOW_COLOR_RED = 0,
2769 MLX5_FLOW_COLOR_YELLOW,
2770 MLX5_FLOW_COLOR_GREEN,
2771 MLX5_FLOW_COLOR_UNDEFINED,
2774 /* Maximum value of srTCM metering parameters. */
2775 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
2776 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
2777 #define MLX5_SRTCM_EBS_MAX 0
2779 /* The bits meter color use. */
2780 #define MLX5_MTR_COLOR_BITS 8
2783 * Convert a user mark to flow mark.
2786 * Mark value to convert.
2789 * Converted mark value.
2791 static inline uint32_t
2792 mlx5_flow_mark_set(uint32_t val)
2797 * Add one to the user value to differentiate un-marked flows from
2798 * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
2799 * remains untouched.
2801 if (val != MLX5_FLOW_MARK_DEFAULT)
2803 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2805 * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
2806 * word, byte-swapped by the kernel on little-endian systems. In this
2807 * case, left-shifting the resulting big-endian value ensures the
2808 * least significant 24 bits are retained when converting it back.
2810 ret = rte_cpu_to_be_32(val) >> 8;
2818 * Convert a mark to user mark.
2821 * Mark value to convert.
2824 * Converted mark value.
2826 static inline uint32_t
2827 mlx5_flow_mark_get(uint32_t val)
2830 * Subtract one from the retrieved value. It was added by
2831 * mlx5_flow_mark_set() to distinguish unmarked flows.
2833 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
2834 return (val >> 8) - 1;
2840 #endif /* RTE_PMD_MLX5_PRM_H_ */