drivers/common/mlx5/mlx5_prm.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2016 6WIND S.A.
   3  * Copyright 2016 Mellanox Technologies, Ltd
   4  */
   5
   6 #ifndef RTE_PMD_MLX5_PRM_H_
   7 #define RTE_PMD_MLX5_PRM_H_
   8
   9 #include <unistd.h>
  10
  11 #include <rte_vect.h>
  12 #include <rte_byteorder.h>
  13
  14 #include <mlx5_glue.h>
  15 #include "mlx5_autoconf.h"
  16
  17 /* RSS hash key size. */
  18 #define MLX5_RSS_HASH_KEY_LEN 40
  19
  20 /* Get CQE owner bit. */
  21 #define MLX5_CQE_OWNER(op_own) ((op_own) & MLX5_CQE_OWNER_MASK)
  22
  23 /* Get CQE format. */
  24 #define MLX5_CQE_FORMAT(op_own) (((op_own) & MLX5E_CQE_FORMAT_MASK) >> 2)
  25
  26 /* Get CQE opcode. */
  27 #define MLX5_CQE_OPCODE(op_own) (((op_own) & 0xf0) >> 4)
  28
  29 /* Get CQE solicited event. */
  30 #define MLX5_CQE_SE(op_own) (((op_own) >> 1) & 1)
  31
  32 /* Invalidate a CQE. */
  33 #define MLX5_CQE_INVALIDATE (MLX5_CQE_INVALID << 4)
  34
  35 /* Hardware index widths. */
  36 #define MLX5_CQ_INDEX_WIDTH 24
  37 #define MLX5_WQ_INDEX_WIDTH 16
  38
  39 /* WQE Segment sizes in bytes. */
  40 #define MLX5_WSEG_SIZE 16u
  41 #define MLX5_WQE_CSEG_SIZE sizeof(struct mlx5_wqe_cseg)
  42 #define MLX5_WQE_DSEG_SIZE sizeof(struct mlx5_wqe_dseg)
  43 #define MLX5_WQE_ESEG_SIZE sizeof(struct mlx5_wqe_eseg)
  44
  45 /* WQE/WQEBB size in bytes. */
  46 #define MLX5_WQE_SIZE sizeof(struct mlx5_wqe)
  47
  48 /*
  49  * Max size of a WQE session.
  50  * Absolute maximum size is 63 (MLX5_DSEG_MAX) segments,
  51  * the WQE size field in Control Segment is 6 bits wide.
  52  */
  53 #define MLX5_WQE_SIZE_MAX (60 * MLX5_WSEG_SIZE)
  54
  55 /*
  56  * Default minimum number of Tx queues for inlining packets.
  57  * If there are less queues as specified we assume we have
  58  * no enough CPU resources (cycles) to perform inlining,
  59  * the PCIe throughput is not supposed as bottleneck and
  60  * inlining is disabled.
  61  */
  62 #define MLX5_INLINE_MAX_TXQS 8u
  63 #define MLX5_INLINE_MAX_TXQS_BLUEFIELD 16u
  64
  65 /*
  66  * Default packet length threshold to be inlined with
  67  * enhanced MPW. If packet length exceeds the threshold
  68  * the data are not inlined. Should be aligned in WQEBB
  69  * boundary with accounting the title Control and Ethernet
  70  * segments.
  71  */
  72 #define MLX5_EMPW_DEF_INLINE_LEN (4u * MLX5_WQE_SIZE + \
  73                                   MLX5_DSEG_MIN_INLINE_SIZE)
  74 /*
  75  * Maximal inline data length sent with enhanced MPW.
  76  * Is based on maximal WQE size.
  77  */
  78 #define MLX5_EMPW_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
  79                                   MLX5_WQE_CSEG_SIZE - \
  80                                   MLX5_WQE_ESEG_SIZE - \
  81                                   MLX5_WQE_DSEG_SIZE + \
  82                                   MLX5_DSEG_MIN_INLINE_SIZE)
  83 /*
  84  * Minimal amount of packets to be sent with EMPW.
  85  * This limits the minimal required size of sent EMPW.
  86  * If there are no enough resources to built minimal
  87  * EMPW the sending loop exits.
  88  */
  89 #define MLX5_EMPW_MIN_PACKETS (2u + 3u * 4u)
  90 /*
  91  * Maximal amount of packets to be sent with EMPW.
  92  * This value is not recommended to exceed MLX5_TX_COMP_THRESH,
  93  * otherwise there might be up to MLX5_EMPW_MAX_PACKETS mbufs
  94  * without CQE generation request, being multiplied by
  95  * MLX5_TX_COMP_MAX_CQE it may cause significant latency
  96  * in tx burst routine at the moment of freeing multiple mbufs.
  97  */
  98 #define MLX5_EMPW_MAX_PACKETS MLX5_TX_COMP_THRESH
  99 #define MLX5_MPW_MAX_PACKETS 6
 100 #define MLX5_MPW_INLINE_MAX_PACKETS 6
 101
 102 /*
 103  * Default packet length threshold to be inlined with
 104  * ordinary SEND. Inlining saves the MR key search
 105  * and extra PCIe data fetch transaction, but eats the
 106  * CPU cycles.
 107  */
 108 #define MLX5_SEND_DEF_INLINE_LEN (5U * MLX5_WQE_SIZE + \
 109                                   MLX5_ESEG_MIN_INLINE_SIZE - \
 110                                   MLX5_WQE_CSEG_SIZE - \
 111                                   MLX5_WQE_ESEG_SIZE - \
 112                                   MLX5_WQE_DSEG_SIZE)
 113 /*
 114  * Maximal inline data length sent with ordinary SEND.
 115  * Is based on maximal WQE size.
 116  */
 117 #define MLX5_SEND_MAX_INLINE_LEN (MLX5_WQE_SIZE_MAX - \
 118                                   MLX5_WQE_CSEG_SIZE - \
 119                                   MLX5_WQE_ESEG_SIZE - \
 120                                   MLX5_WQE_DSEG_SIZE + \
 121                                   MLX5_ESEG_MIN_INLINE_SIZE)
 122
 123 /* Missed in mlx5dv.h, should define here. */
 124 #ifndef HAVE_MLX5_OPCODE_ENHANCED_MPSW
 125 #define MLX5_OPCODE_ENHANCED_MPSW 0x29u
 126 #endif
 127
 128 #ifndef HAVE_MLX5_OPCODE_SEND_EN
 129 #define MLX5_OPCODE_SEND_EN 0x17u
 130 #endif
 131
 132 #ifndef HAVE_MLX5_OPCODE_WAIT
 133 #define MLX5_OPCODE_WAIT 0x0fu
 134 #endif
 135
 136 #ifndef HAVE_MLX5_OPCODE_ACCESS_ASO
 137 #define MLX5_OPCODE_ACCESS_ASO 0x2du
 138 #endif
 139
 140 /* CQE value to inform that VLAN is stripped. */
 141 #define MLX5_CQE_VLAN_STRIPPED (1u << 0)
 142
 143 /* IPv4 options. */
 144 #define MLX5_CQE_RX_IP_EXT_OPTS_PACKET (1u << 1)
 145
 146 /* IPv6 packet. */
 147 #define MLX5_CQE_RX_IPV6_PACKET (1u << 2)
 148
 149 /* IPv4 packet. */
 150 #define MLX5_CQE_RX_IPV4_PACKET (1u << 3)
 151
 152 /* TCP packet. */
 153 #define MLX5_CQE_RX_TCP_PACKET (1u << 4)
 154
 155 /* UDP packet. */
 156 #define MLX5_CQE_RX_UDP_PACKET (1u << 5)
 157
 158 /* IP is fragmented. */
 159 #define MLX5_CQE_RX_IP_FRAG_PACKET (1u << 7)
 160
 161 /* L2 header is valid. */
 162 #define MLX5_CQE_RX_L2_HDR_VALID (1u << 8)
 163
 164 /* L3 header is valid. */
 165 #define MLX5_CQE_RX_L3_HDR_VALID (1u << 9)
 166
 167 /* L4 header is valid. */
 168 #define MLX5_CQE_RX_L4_HDR_VALID (1u << 10)
 169
 170 /* Outer packet, 0 IPv4, 1 IPv6. */
 171 #define MLX5_CQE_RX_OUTER_PACKET (1u << 1)
 172
 173 /* Tunnel packet bit in the CQE. */
 174 #define MLX5_CQE_RX_TUNNEL_PACKET (1u << 0)
 175
 176 /* Mask for LRO push flag in the CQE lro_tcppsh_abort_dupack field. */
 177 #define MLX5_CQE_LRO_PUSH_MASK 0x40
 178
 179 /* Mask for L4 type in the CQE hdr_type_etc field. */
 180 #define MLX5_CQE_L4_TYPE_MASK 0x70
 181
 182 /* The bit index of L4 type in CQE hdr_type_etc field. */
 183 #define MLX5_CQE_L4_TYPE_SHIFT 0x4
 184
 185 /* L4 type to indicate TCP packet without acknowledgment. */
 186 #define MLX5_L4_HDR_TYPE_TCP_EMPTY_ACK 0x3
 187
 188 /* L4 type to indicate TCP packet with acknowledgment. */
 189 #define MLX5_L4_HDR_TYPE_TCP_WITH_ACL 0x4
 190
 191 /* Inner L3 checksum offload (Tunneled packets only). */
 192 #define MLX5_ETH_WQE_L3_INNER_CSUM (1u << 4)
 193
 194 /* Inner L4 checksum offload (Tunneled packets only). */
 195 #define MLX5_ETH_WQE_L4_INNER_CSUM (1u << 5)
 196
 197 /* Outer L4 type is TCP. */
 198 #define MLX5_ETH_WQE_L4_OUTER_TCP  (0u << 5)
 199
 200 /* Outer L4 type is UDP. */
 201 #define MLX5_ETH_WQE_L4_OUTER_UDP  (1u << 5)
 202
 203 /* Outer L3 type is IPV4. */
 204 #define MLX5_ETH_WQE_L3_OUTER_IPV4 (0u << 4)
 205
 206 /* Outer L3 type is IPV6. */
 207 #define MLX5_ETH_WQE_L3_OUTER_IPV6 (1u << 4)
 208
 209 /* Inner L4 type is TCP. */
 210 #define MLX5_ETH_WQE_L4_INNER_TCP (0u << 1)
 211
 212 /* Inner L4 type is UDP. */
 213 #define MLX5_ETH_WQE_L4_INNER_UDP (1u << 1)
 214
 215 /* Inner L3 type is IPV4. */
 216 #define MLX5_ETH_WQE_L3_INNER_IPV4 (0u << 0)
 217
 218 /* Inner L3 type is IPV6. */
 219 #define MLX5_ETH_WQE_L3_INNER_IPV6 (1u << 0)
 220
 221 /* VLAN insertion flag. */
 222 #define MLX5_ETH_WQE_VLAN_INSERT (1u << 31)
 223
 224 /* Data inline segment flag. */
 225 #define MLX5_ETH_WQE_DATA_INLINE (1u << 31)
 226
 227 /* Is flow mark valid. */
 228 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
 229 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff00)
 230 #else
 231 #define MLX5_FLOW_MARK_IS_VALID(val) ((val) & 0xffffff)
 232 #endif
 233
 234 /* INVALID is used by packets matching no flow rules. */
 235 #define MLX5_FLOW_MARK_INVALID 0
 236
 237 /* Maximum allowed value to mark a packet. */
 238 #define MLX5_FLOW_MARK_MAX 0xfffff0
 239
 240 /* Default mark value used when none is provided. */
 241 #define MLX5_FLOW_MARK_DEFAULT 0xffffff
 242
 243 /* Default mark mask for metadata legacy mode. */
 244 #define MLX5_FLOW_MARK_MASK 0xffffff
 245
 246 /* Byte length mask when mark is enable in miniCQE */
 247 #define MLX5_LEN_WITH_MARK_MASK 0xffffff00
 248
 249 /* Maximum number of DS in WQE. Limited by 6-bit field. */
 250 #define MLX5_DSEG_MAX 63
 251
 252 /* The completion mode offset in the WQE control segment line 2. */
 253 #define MLX5_COMP_MODE_OFFSET 2
 254
 255 /* Amount of data bytes in minimal inline data segment. */
 256 #define MLX5_DSEG_MIN_INLINE_SIZE 12u
 257
 258 /* Amount of data bytes in minimal inline eth segment. */
 259 #define MLX5_ESEG_MIN_INLINE_SIZE 18u
 260
 261 /* Amount of data bytes after eth data segment. */
 262 #define MLX5_ESEG_EXTRA_DATA_SIZE 32u
 263
 264 /* The maximum log value of segments per RQ WQE. */
 265 #define MLX5_MAX_LOG_RQ_SEGS 5u
 266
 267 /* The alignment needed for WQ buffer. */
 268 #define MLX5_WQE_BUF_ALIGNMENT rte_mem_page_size()
 269
 270 /* The alignment needed for CQ buffer. */
 271 #define MLX5_CQE_BUF_ALIGNMENT rte_mem_page_size()
 272
 273 /* Completion mode. */
 274 enum mlx5_completion_mode {
 275         MLX5_COMP_ONLY_ERR = 0x0,
 276         MLX5_COMP_ONLY_FIRST_ERR = 0x1,
 277         MLX5_COMP_ALWAYS = 0x2,
 278         MLX5_COMP_CQE_AND_EQE = 0x3,
 279 };
 280
 281 /* MPW mode. */
 282 enum mlx5_mpw_mode {
 283         MLX5_MPW_DISABLED,
 284         MLX5_MPW,
 285         MLX5_MPW_ENHANCED, /* Enhanced Multi-Packet Send WQE, a.k.a MPWv2. */
 286 };
 287
 288 /* WQE Control segment. */
 289 struct mlx5_wqe_cseg {
 290         uint32_t opcode;
 291         uint32_t sq_ds;
 292         uint32_t flags;
 293         uint32_t misc;
 294 } __rte_packed __rte_aligned(MLX5_WSEG_SIZE);
 295
 296 /*
 297  * WQE CSEG opcode field size is 32 bits, divided:
 298  * Bits 31:24 OPC_MOD
 299  * Bits 23:8 wqe_index
 300  * Bits 7:0 OPCODE
 301  */
 302 #define WQE_CSEG_OPC_MOD_OFFSET         24
 303 #define WQE_CSEG_WQE_INDEX_OFFSET        8
 304
 305 /* Header of data segment. Minimal size Data Segment */
 306 struct mlx5_wqe_dseg {
 307         uint32_t bcount;
 308         union {
 309                 uint8_t inline_data[MLX5_DSEG_MIN_INLINE_SIZE];
 310                 struct {
 311                         uint32_t lkey;
 312                         uint64_t pbuf;
 313                 } __rte_packed;
 314         };
 315 } __rte_packed;
 316
 317 /* Subset of struct WQE Ethernet Segment. */
 318 struct mlx5_wqe_eseg {
 319         union {
 320                 struct {
 321                         uint32_t swp_offs;
 322                         uint8_t cs_flags;
 323                         uint8_t swp_flags;
 324                         uint16_t mss;
 325                         uint32_t metadata;
 326                         uint16_t inline_hdr_sz;
 327                         union {
 328                                 uint16_t inline_data;
 329                                 uint16_t vlan_tag;
 330                         };
 331                 } __rte_packed;
 332                 struct {
 333                         uint32_t offsets;
 334                         uint32_t flags;
 335                         uint32_t flow_metadata;
 336                         uint32_t inline_hdr;
 337                 } __rte_packed;
 338         };
 339 } __rte_packed;
 340
 341 struct mlx5_wqe_qseg {
 342         uint32_t reserved0;
 343         uint32_t reserved1;
 344         uint32_t max_index;
 345         uint32_t qpn_cqn;
 346 } __rte_packed;
 347
 348 /* The title WQEBB, header of WQE. */
 349 struct mlx5_wqe {
 350         union {
 351                 struct mlx5_wqe_cseg cseg;
 352                 uint32_t ctrl[4];
 353         };
 354         struct mlx5_wqe_eseg eseg;
 355         union {
 356                 struct mlx5_wqe_dseg dseg[2];
 357                 uint8_t data[MLX5_ESEG_EXTRA_DATA_SIZE];
 358         };
 359 } __rte_packed;
 360
 361 /* WQE for Multi-Packet RQ. */
 362 struct mlx5_wqe_mprq {
 363         struct mlx5_wqe_srq_next_seg next_seg;
 364         struct mlx5_wqe_data_seg dseg;
 365 };
 366
 367 #define MLX5_MPRQ_LEN_MASK 0x000ffff
 368 #define MLX5_MPRQ_LEN_SHIFT 0
 369 #define MLX5_MPRQ_STRIDE_NUM_MASK 0x3fff0000
 370 #define MLX5_MPRQ_STRIDE_NUM_SHIFT 16
 371 #define MLX5_MPRQ_FILLER_MASK 0x80000000
 372 #define MLX5_MPRQ_FILLER_SHIFT 31
 373
 374 #define MLX5_MPRQ_STRIDE_SHIFT_BYTE 2
 375
 376 /* CQ element structure - should be equal to the cache line size */
 377 struct mlx5_cqe {
 378 #if (RTE_CACHE_LINE_SIZE == 128)
 379         uint8_t padding[64];
 380 #endif
 381         uint8_t pkt_info;
 382         uint8_t rsvd0;
 383         uint16_t wqe_id;
 384         uint8_t lro_tcppsh_abort_dupack;
 385         uint8_t lro_min_ttl;
 386         uint16_t lro_tcp_win;
 387         uint32_t lro_ack_seq_num;
 388         uint32_t rx_hash_res;
 389         uint8_t rx_hash_type;
 390         uint8_t rsvd1[3];
 391         uint16_t csum;
 392         uint8_t rsvd2[6];
 393         uint16_t hdr_type_etc;
 394         uint16_t vlan_info;
 395         uint8_t lro_num_seg;
 396         uint8_t rsvd3[3];
 397         uint32_t flow_table_metadata;
 398         uint8_t rsvd4[4];
 399         uint32_t byte_cnt;
 400         uint64_t timestamp;
 401         uint32_t sop_drop_qpn;
 402         uint16_t wqe_counter;
 403         uint8_t rsvd5;
 404         uint8_t op_own;
 405 };
 406
 407 struct mlx5_cqe_ts {
 408         uint64_t timestamp;
 409         uint32_t sop_drop_qpn;
 410         uint16_t wqe_counter;
 411         uint8_t rsvd5;
 412         uint8_t op_own;
 413 };
 414
 415 enum {
 416         MLX5_BSF_SIZE_16B = 0x0,
 417         MLX5_BSF_SIZE_32B = 0x1,
 418         MLX5_BSF_SIZE_64B = 0x2,
 419         MLX5_BSF_SIZE_128B = 0x3,
 420 };
 421
 422 enum {
 423         MLX5_BSF_P_TYPE_SIGNATURE = 0x0,
 424         MLX5_BSF_P_TYPE_CRYPTO = 0x1,
 425 };
 426
 427 enum {
 428         MLX5_ENCRYPTION_ORDER_ENCRYPTED_WIRE_SIGNATURE = 0x0,
 429         MLX5_ENCRYPTION_ORDER_ENCRYPTED_MEMORY_SIGNATURE = 0x1,
 430         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE = 0x2,
 431         MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY = 0x3,
 432 };
 433
 434 enum {
 435         MLX5_ENCRYPTION_STANDARD_AES_XTS = 0x0,
 436 };
 437
 438 enum {
 439         MLX5_BLOCK_SIZE_512B    = 0x1,
 440         MLX5_BLOCK_SIZE_520B    = 0x2,
 441         MLX5_BLOCK_SIZE_4096B   = 0x3,
 442         MLX5_BLOCK_SIZE_4160B   = 0x4,
 443         MLX5_BLOCK_SIZE_1MB     = 0x5,
 444         MLX5_BLOCK_SIZE_4048B   = 0x6,
 445 };
 446
 447 #define MLX5_BSF_SIZE_OFFSET            30
 448 #define MLX5_BSF_P_TYPE_OFFSET          24
 449 #define MLX5_ENCRYPTION_ORDER_OFFSET    16
 450 #define MLX5_BLOCK_SIZE_OFFSET          24
 451
 452 struct mlx5_wqe_umr_bsf_seg {
 453         /*
 454          * bs_bpt_eo_es contains:
 455          * bs   bsf_size                2 bits at MLX5_BSF_SIZE_OFFSET
 456          * bpt  bsf_p_type              2 bits at MLX5_BSF_P_TYPE_OFFSET
 457          * eo   encryption_order        4 bits at MLX5_ENCRYPTION_ORDER_OFFSET
 458          * es   encryption_standard     4 bits at offset 0
 459          */
 460         uint32_t bs_bpt_eo_es;
 461         uint32_t raw_data_size;
 462         /*
 463          * bsp_res contains:
 464          * bsp  crypto_block_size_pointer       8 bits at MLX5_BLOCK_SIZE_OFFSET
 465          * res  reserved 24 bits
 466          */
 467         uint32_t bsp_res;
 468         uint32_t reserved0;
 469         uint8_t xts_initial_tweak[16];
 470         /*
 471          * res_dp contains:
 472          * res  reserved 8 bits
 473          * dp   dek_pointer             24 bits at offset 0
 474          */
 475         uint32_t res_dp;
 476         uint32_t reserved1;
 477         uint64_t keytag;
 478         uint32_t reserved2[4];
 479 } __rte_packed;
 480
 481 /* GGA */
 482 /* MMO metadata segment */
 483
 484 #define MLX5_OPCODE_MMO 0x2fu
 485 #define MLX5_OPC_MOD_MMO_REGEX 0x4u
 486 #define MLX5_OPC_MOD_MMO_COMP 0x2u
 487 #define MLX5_OPC_MOD_MMO_DECOMP 0x3u
 488 #define MLX5_OPC_MOD_MMO_DMA 0x1u
 489
 490 #define WQE_GGA_COMP_WIN_SIZE_OFFSET 12u
 491 #define WQE_GGA_COMP_BLOCK_SIZE_OFFSET 16u
 492 #define WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET 20u
 493 #define MLX5_GGA_COMP_WIN_SIZE_UNITS 1024u
 494 #define MLX5_GGA_COMP_WIN_SIZE_MAX (32u * MLX5_GGA_COMP_WIN_SIZE_UNITS)
 495 #define MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX 15u
 496 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX 15u
 497 #define MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN 0u
 498
 499 struct mlx5_wqe_metadata_seg {
 500         uint32_t mmo_control_31_0; /* mmo_control_63_32 is in ctrl_seg.imm */
 501         uint32_t lkey;
 502         uint64_t addr;
 503 };
 504
 505 struct mlx5_gga_wqe {
 506         uint32_t opcode;
 507         uint32_t sq_ds;
 508         uint32_t flags;
 509         uint32_t gga_ctrl1;  /* ws 12-15, bs 16-19, dyns 20-23. */
 510         uint32_t gga_ctrl2;
 511         uint32_t opaque_lkey;
 512         uint64_t opaque_vaddr;
 513         struct mlx5_wqe_dseg gather;
 514         struct mlx5_wqe_dseg scatter;
 515 } __rte_packed;
 516
 517 struct mlx5_gga_compress_opaque {
 518         uint32_t syndrom;
 519         uint32_t reserved0;
 520         uint32_t scattered_length;
 521         uint32_t gathered_length;
 522         uint64_t scatter_crc;
 523         uint64_t gather_crc;
 524         uint32_t crc32;
 525         uint32_t adler32;
 526         uint8_t reserved1[216];
 527 } __rte_packed;
 528
 529 struct mlx5_ifc_regexp_mmo_control_bits {
 530         uint8_t reserved_at_31[0x2];
 531         uint8_t le[0x1];
 532         uint8_t reserved_at_28[0x1];
 533         uint8_t subset_id_0[0xc];
 534         uint8_t reserved_at_16[0x4];
 535         uint8_t subset_id_1[0xc];
 536         uint8_t ctrl[0x4];
 537         uint8_t subset_id_2[0xc];
 538         uint8_t reserved_at_16_1[0x4];
 539         uint8_t subset_id_3[0xc];
 540 };
 541
 542 struct mlx5_ifc_regexp_metadata_bits {
 543         uint8_t rof_version[0x10];
 544         uint8_t latency_count[0x10];
 545         uint8_t instruction_count[0x10];
 546         uint8_t primary_thread_count[0x10];
 547         uint8_t match_count[0x8];
 548         uint8_t detected_match_count[0x8];
 549         uint8_t status[0x10];
 550         uint8_t job_id[0x20];
 551         uint8_t reserved[0x80];
 552 };
 553
 554 struct mlx5_ifc_regexp_match_tuple_bits {
 555         uint8_t length[0x10];
 556         uint8_t start_ptr[0x10];
 557         uint8_t rule_id[0x20];
 558 };
 559
 560 /* Adding direct verbs to data-path. */
 561
 562 /* CQ sequence number mask. */
 563 #define MLX5_CQ_SQN_MASK 0x3
 564
 565 /* CQ sequence number index. */
 566 #define MLX5_CQ_SQN_OFFSET 28
 567
 568 /* CQ doorbell index mask. */
 569 #define MLX5_CI_MASK 0xffffff
 570
 571 /* CQ doorbell offset. */
 572 #define MLX5_CQ_ARM_DB 1
 573
 574 /* CQ doorbell offset*/
 575 #define MLX5_CQ_DOORBELL 0x20
 576
 577 /* CQE format value. */
 578 #define MLX5_COMPRESSED 0x3
 579
 580 /* CQ doorbell cmd types. */
 581 #define MLX5_CQ_DBR_CMD_SOL_ONLY (1 << 24)
 582 #define MLX5_CQ_DBR_CMD_ALL (0 << 24)
 583
 584 /* Action type of header modification. */
 585 enum {
 586         MLX5_MODIFICATION_TYPE_SET = 0x1,
 587         MLX5_MODIFICATION_TYPE_ADD = 0x2,
 588         MLX5_MODIFICATION_TYPE_COPY = 0x3,
 589 };
 590
 591 /* The field of packet to be modified. */
 592 enum mlx5_modification_field {
 593         MLX5_MODI_OUT_NONE = -1,
 594         MLX5_MODI_OUT_SMAC_47_16 = 1,
 595         MLX5_MODI_OUT_SMAC_15_0,
 596         MLX5_MODI_OUT_ETHERTYPE,
 597         MLX5_MODI_OUT_DMAC_47_16,
 598         MLX5_MODI_OUT_DMAC_15_0,
 599         MLX5_MODI_OUT_IP_DSCP,
 600         MLX5_MODI_OUT_TCP_FLAGS,
 601         MLX5_MODI_OUT_TCP_SPORT,
 602         MLX5_MODI_OUT_TCP_DPORT,
 603         MLX5_MODI_OUT_IPV4_TTL,
 604         MLX5_MODI_OUT_UDP_SPORT,
 605         MLX5_MODI_OUT_UDP_DPORT,
 606         MLX5_MODI_OUT_SIPV6_127_96,
 607         MLX5_MODI_OUT_SIPV6_95_64,
 608         MLX5_MODI_OUT_SIPV6_63_32,
 609         MLX5_MODI_OUT_SIPV6_31_0,
 610         MLX5_MODI_OUT_DIPV6_127_96,
 611         MLX5_MODI_OUT_DIPV6_95_64,
 612         MLX5_MODI_OUT_DIPV6_63_32,
 613         MLX5_MODI_OUT_DIPV6_31_0,
 614         MLX5_MODI_OUT_SIPV4,
 615         MLX5_MODI_OUT_DIPV4,
 616         MLX5_MODI_OUT_FIRST_VID,
 617         MLX5_MODI_IN_SMAC_47_16 = 0x31,
 618         MLX5_MODI_IN_SMAC_15_0,
 619         MLX5_MODI_IN_ETHERTYPE,
 620         MLX5_MODI_IN_DMAC_47_16,
 621         MLX5_MODI_IN_DMAC_15_0,
 622         MLX5_MODI_IN_IP_DSCP,
 623         MLX5_MODI_IN_TCP_FLAGS,
 624         MLX5_MODI_IN_TCP_SPORT,
 625         MLX5_MODI_IN_TCP_DPORT,
 626         MLX5_MODI_IN_IPV4_TTL,
 627         MLX5_MODI_IN_UDP_SPORT,
 628         MLX5_MODI_IN_UDP_DPORT,
 629         MLX5_MODI_IN_SIPV6_127_96,
 630         MLX5_MODI_IN_SIPV6_95_64,
 631         MLX5_MODI_IN_SIPV6_63_32,
 632         MLX5_MODI_IN_SIPV6_31_0,
 633         MLX5_MODI_IN_DIPV6_127_96,
 634         MLX5_MODI_IN_DIPV6_95_64,
 635         MLX5_MODI_IN_DIPV6_63_32,
 636         MLX5_MODI_IN_DIPV6_31_0,
 637         MLX5_MODI_IN_SIPV4,
 638         MLX5_MODI_IN_DIPV4,
 639         MLX5_MODI_OUT_IPV6_HOPLIMIT,
 640         MLX5_MODI_IN_IPV6_HOPLIMIT,
 641         MLX5_MODI_META_DATA_REG_A,
 642         MLX5_MODI_META_DATA_REG_B = 0x50,
 643         MLX5_MODI_META_REG_C_0,
 644         MLX5_MODI_META_REG_C_1,
 645         MLX5_MODI_META_REG_C_2,
 646         MLX5_MODI_META_REG_C_3,
 647         MLX5_MODI_META_REG_C_4,
 648         MLX5_MODI_META_REG_C_5,
 649         MLX5_MODI_META_REG_C_6,
 650         MLX5_MODI_META_REG_C_7,
 651         MLX5_MODI_OUT_TCP_SEQ_NUM,
 652         MLX5_MODI_IN_TCP_SEQ_NUM,
 653         MLX5_MODI_OUT_TCP_ACK_NUM,
 654         MLX5_MODI_IN_TCP_ACK_NUM = 0x5C,
 655         MLX5_MODI_GTP_TEID = 0x6E,
 656 };
 657
 658 /* Total number of metadata reg_c's. */
 659 #define MLX5_MREG_C_NUM (MLX5_MODI_META_REG_C_7 - MLX5_MODI_META_REG_C_0 + 1)
 660
 661 enum modify_reg {
 662         REG_NON = 0,
 663         REG_A,
 664         REG_B,
 665         REG_C_0,
 666         REG_C_1,
 667         REG_C_2,
 668         REG_C_3,
 669         REG_C_4,
 670         REG_C_5,
 671         REG_C_6,
 672         REG_C_7,
 673 };
 674
 675 /* Modification sub command. */
 676 struct mlx5_modification_cmd {
 677         union {
 678                 uint32_t data0;
 679                 struct {
 680                         unsigned int length:5;
 681                         unsigned int rsvd0:3;
 682                         unsigned int offset:5;
 683                         unsigned int rsvd1:3;
 684                         unsigned int field:12;
 685                         unsigned int action_type:4;
 686                 };
 687         };
 688         union {
 689                 uint32_t data1;
 690                 uint8_t data[4];
 691                 struct {
 692                         unsigned int rsvd2:8;
 693                         unsigned int dst_offset:5;
 694                         unsigned int rsvd3:3;
 695                         unsigned int dst_field:12;
 696                         unsigned int rsvd4:4;
 697                 };
 698         };
 699 };
 700
 701 typedef uint64_t u64;
 702 typedef uint32_t u32;
 703 typedef uint16_t u16;
 704 typedef uint8_t u8;
 705
 706 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
 707 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
 708 #define __mlx5_bit_off(typ, fld) ((unsigned int)(uintptr_t) \
 709                                   (&(__mlx5_nullp(typ)->fld)))
 710 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - \
 711                                     (__mlx5_bit_off(typ, fld) & 0x1f))
 712 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
 713 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
 714 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << \
 715                                   __mlx5_dw_bit_off(typ, fld))
 716 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 717 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
 718 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - \
 719                                     (__mlx5_bit_off(typ, fld) & 0xf))
 720 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
 721 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << \
 722                                   __mlx5_16_bit_off(typ, fld))
 723 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
 724 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
 725 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
 726 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
 727
 728 /* insert a value to a struct */
 729 #define MLX5_SET(typ, p, fld, v) \
 730         do { \
 731                 u32 _v = v; \
 732                 *((rte_be32_t *)(p) + __mlx5_dw_off(typ, fld)) = \
 733                 rte_cpu_to_be_32((rte_be_to_cpu_32(*((u32 *)(p) + \
 734                                   __mlx5_dw_off(typ, fld))) & \
 735                                   (~__mlx5_dw_mask(typ, fld))) | \
 736                                  (((_v) & __mlx5_mask(typ, fld)) << \
 737                                    __mlx5_dw_bit_off(typ, fld))); \
 738         } while (0)
 739
 740 #define MLX5_SET64(typ, p, fld, v) \
 741         do { \
 742                 MLX5_ASSERT(__mlx5_bit_sz(typ, fld) == 64); \
 743                 *((rte_be64_t *)(p) + __mlx5_64_off(typ, fld)) = \
 744                         rte_cpu_to_be_64(v); \
 745         } while (0)
 746
 747 #define MLX5_SET16(typ, p, fld, v) \
 748         do { \
 749                 u16 _v = v; \
 750                 *((rte_be16_t *)(p) + __mlx5_16_off(typ, fld)) = \
 751                 rte_cpu_to_be_16((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 752                                   __mlx5_16_off(typ, fld))) & \
 753                                   (~__mlx5_16_mask(typ, fld))) | \
 754                                  (((_v) & __mlx5_mask16(typ, fld)) << \
 755                                   __mlx5_16_bit_off(typ, fld))); \
 756         } while (0)
 757
 758 #define MLX5_GET_VOLATILE(typ, p, fld) \
 759         ((rte_be_to_cpu_32(*((volatile __be32 *)(p) +\
 760         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 761         __mlx5_mask(typ, fld))
 762 #define MLX5_GET(typ, p, fld) \
 763         ((rte_be_to_cpu_32(*((rte_be32_t *)(p) +\
 764         __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 765         __mlx5_mask(typ, fld))
 766 #define MLX5_GET16(typ, p, fld) \
 767         ((rte_be_to_cpu_16(*((rte_be16_t *)(p) + \
 768           __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 769          __mlx5_mask16(typ, fld))
 770 #define MLX5_GET64(typ, p, fld) rte_be_to_cpu_64(*((rte_be64_t *)(p) + \
 771                                                    __mlx5_64_off(typ, fld)))
 772 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
 773 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
 774
 775 struct mlx5_ifc_fte_match_set_misc_bits {
 776         u8 gre_c_present[0x1];
 777         u8 reserved_at_1[0x1];
 778         u8 gre_k_present[0x1];
 779         u8 gre_s_present[0x1];
 780         u8 source_vhci_port[0x4];
 781         u8 source_sqn[0x18];
 782         u8 reserved_at_20[0x10];
 783         u8 source_port[0x10];
 784         u8 outer_second_prio[0x3];
 785         u8 outer_second_cfi[0x1];
 786         u8 outer_second_vid[0xc];
 787         u8 inner_second_prio[0x3];
 788         u8 inner_second_cfi[0x1];
 789         u8 inner_second_vid[0xc];
 790         u8 outer_second_cvlan_tag[0x1];
 791         u8 inner_second_cvlan_tag[0x1];
 792         u8 outer_second_svlan_tag[0x1];
 793         u8 inner_second_svlan_tag[0x1];
 794         u8 reserved_at_64[0xc];
 795         u8 gre_protocol[0x10];
 796         u8 gre_key_h[0x18];
 797         u8 gre_key_l[0x8];
 798         u8 vxlan_vni[0x18];
 799         u8 reserved_at_b8[0x8];
 800         u8 geneve_vni[0x18];
 801         u8 reserved_at_e4[0x7];
 802         u8 geneve_oam[0x1];
 803         u8 reserved_at_e0[0xc];
 804         u8 outer_ipv6_flow_label[0x14];
 805         u8 reserved_at_100[0xc];
 806         u8 inner_ipv6_flow_label[0x14];
 807         u8 reserved_at_120[0xa];
 808         u8 geneve_opt_len[0x6];
 809         u8 geneve_protocol_type[0x10];
 810         u8 reserved_at_140[0xc0];
 811 };
 812
 813 struct mlx5_ifc_ipv4_layout_bits {
 814         u8 reserved_at_0[0x60];
 815         u8 ipv4[0x20];
 816 };
 817
 818 struct mlx5_ifc_ipv6_layout_bits {
 819         u8 ipv6[16][0x8];
 820 };
 821
 822 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
 823         struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
 824         struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
 825         u8 reserved_at_0[0x80];
 826 };
 827
 828 struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
 829         u8 smac_47_16[0x20];
 830         u8 smac_15_0[0x10];
 831         u8 ethertype[0x10];
 832         u8 dmac_47_16[0x20];
 833         u8 dmac_15_0[0x10];
 834         u8 first_prio[0x3];
 835         u8 first_cfi[0x1];
 836         u8 first_vid[0xc];
 837         u8 ip_protocol[0x8];
 838         u8 ip_dscp[0x6];
 839         u8 ip_ecn[0x2];
 840         u8 cvlan_tag[0x1];
 841         u8 svlan_tag[0x1];
 842         u8 frag[0x1];
 843         u8 ip_version[0x4];
 844         u8 tcp_flags[0x9];
 845         u8 tcp_sport[0x10];
 846         u8 tcp_dport[0x10];
 847         u8 reserved_at_c0[0x18];
 848         u8 ip_ttl_hoplimit[0x8];
 849         u8 udp_sport[0x10];
 850         u8 udp_dport[0x10];
 851         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
 852         union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
 853 };
 854
 855 struct mlx5_ifc_fte_match_mpls_bits {
 856         u8 mpls_label[0x14];
 857         u8 mpls_exp[0x3];
 858         u8 mpls_s_bos[0x1];
 859         u8 mpls_ttl[0x8];
 860 };
 861
 862 struct mlx5_ifc_fte_match_set_misc2_bits {
 863         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls;
 864         struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls;
 865         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre;
 866         struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp;
 867         u8 metadata_reg_c_7[0x20];
 868         u8 metadata_reg_c_6[0x20];
 869         u8 metadata_reg_c_5[0x20];
 870         u8 metadata_reg_c_4[0x20];
 871         u8 metadata_reg_c_3[0x20];
 872         u8 metadata_reg_c_2[0x20];
 873         u8 metadata_reg_c_1[0x20];
 874         u8 metadata_reg_c_0[0x20];
 875         u8 metadata_reg_a[0x20];
 876         u8 metadata_reg_b[0x20];
 877         u8 reserved_at_1c0[0x40];
 878 };
 879
 880 struct mlx5_ifc_fte_match_set_misc3_bits {
 881         u8 inner_tcp_seq_num[0x20];
 882         u8 outer_tcp_seq_num[0x20];
 883         u8 inner_tcp_ack_num[0x20];
 884         u8 outer_tcp_ack_num[0x20];
 885         u8 reserved_at_auto1[0x8];
 886         u8 outer_vxlan_gpe_vni[0x18];
 887         u8 outer_vxlan_gpe_next_protocol[0x8];
 888         u8 outer_vxlan_gpe_flags[0x8];
 889         u8 reserved_at_a8[0x10];
 890         u8 icmp_header_data[0x20];
 891         u8 icmpv6_header_data[0x20];
 892         u8 icmp_type[0x8];
 893         u8 icmp_code[0x8];
 894         u8 icmpv6_type[0x8];
 895         u8 icmpv6_code[0x8];
 896         u8 geneve_tlv_option_0_data[0x20];
 897         u8 gtpu_teid[0x20];
 898         u8 gtpu_msg_type[0x08];
 899         u8 gtpu_msg_flags[0x08];
 900         u8 reserved_at_170[0x10];
 901         u8 gtpu_dw_2[0x20];
 902         u8 gtpu_first_ext_dw_0[0x20];
 903         u8 gtpu_dw_0[0x20];
 904         u8 reserved_at_240[0x20];
 905
 906 };
 907
 908 struct mlx5_ifc_fte_match_set_misc4_bits {
 909         u8 prog_sample_field_value_0[0x20];
 910         u8 prog_sample_field_id_0[0x20];
 911         u8 prog_sample_field_value_1[0x20];
 912         u8 prog_sample_field_id_1[0x20];
 913         u8 prog_sample_field_value_2[0x20];
 914         u8 prog_sample_field_id_2[0x20];
 915         u8 prog_sample_field_value_3[0x20];
 916         u8 prog_sample_field_id_3[0x20];
 917         u8 reserved_at_100[0x100];
 918 };
 919
 920 /* Flow matcher. */
 921 struct mlx5_ifc_fte_match_param_bits {
 922         struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
 923         struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
 924         struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
 925         struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2;
 926         struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3;
 927         struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4;
 928 /*
 929  * Add reserved bit to match the struct size with the size defined in PRM.
 930  * This extension is not required in Linux.
 931  */
 932 #ifndef HAVE_INFINIBAND_VERBS_H
 933         u8 reserved_0[0x400];
 934 #endif
 935 };
 936
 937 struct mlx5_ifc_dest_format_struct_bits {
 938         u8 destination_type[0x8];
 939         u8 destination_id[0x18];
 940         u8 reserved_0[0x20];
 941 };
 942
 943 enum {
 944         MLX5_MATCH_CRITERIA_ENABLE_OUTER_BIT,
 945         MLX5_MATCH_CRITERIA_ENABLE_MISC_BIT,
 946         MLX5_MATCH_CRITERIA_ENABLE_INNER_BIT,
 947         MLX5_MATCH_CRITERIA_ENABLE_MISC2_BIT,
 948         MLX5_MATCH_CRITERIA_ENABLE_MISC3_BIT,
 949         MLX5_MATCH_CRITERIA_ENABLE_MISC4_BIT,
 950 };
 951
 952 enum {
 953         MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
 954         MLX5_CMD_OP_CREATE_MKEY = 0x200,
 955         MLX5_CMD_OP_CREATE_CQ = 0x400,
 956         MLX5_CMD_OP_CREATE_QP = 0x500,
 957         MLX5_CMD_OP_RST2INIT_QP = 0x502,
 958         MLX5_CMD_OP_INIT2RTR_QP = 0x503,
 959         MLX5_CMD_OP_RTR2RTS_QP = 0x504,
 960         MLX5_CMD_OP_RTS2RTS_QP = 0x505,
 961         MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
 962         MLX5_CMD_OP_QP_2ERR = 0x507,
 963         MLX5_CMD_OP_QP_2RST = 0x50A,
 964         MLX5_CMD_OP_QUERY_QP = 0x50B,
 965         MLX5_CMD_OP_SQD2RTS_QP = 0x50C,
 966         MLX5_CMD_OP_INIT2INIT_QP = 0x50E,
 967         MLX5_CMD_OP_SUSPEND_QP = 0x50F,
 968         MLX5_CMD_OP_RESUME_QP = 0x510,
 969         MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
 970         MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
 971         MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
 972         MLX5_CMD_OP_ALLOC_PD = 0x800,
 973         MLX5_CMD_OP_DEALLOC_PD = 0x801,
 974         MLX5_CMD_OP_ACCESS_REGISTER = 0x805,
 975         MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
 976         MLX5_CMD_OP_CREATE_TIR = 0x900,
 977         MLX5_CMD_OP_MODIFY_TIR = 0x901,
 978         MLX5_CMD_OP_CREATE_SQ = 0X904,
 979         MLX5_CMD_OP_MODIFY_SQ = 0X905,
 980         MLX5_CMD_OP_CREATE_RQ = 0x908,
 981         MLX5_CMD_OP_MODIFY_RQ = 0x909,
 982         MLX5_CMD_OP_QUERY_RQ = 0x90b,
 983         MLX5_CMD_OP_CREATE_TIS = 0x912,
 984         MLX5_CMD_OP_QUERY_TIS = 0x915,
 985         MLX5_CMD_OP_CREATE_RQT = 0x916,
 986         MLX5_CMD_OP_MODIFY_RQT = 0x917,
 987         MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
 988         MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
 989         MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
 990         MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
 991         MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
 992         MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
 993         MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
 994         MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
 995         MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
 996         MLX5_CMD_OP_ACCESS_REGISTER_USER = 0xb0c,
 997 };
 998
 999 enum {
1000         MLX5_MKC_ACCESS_MODE_MTT   = 0x1,
1001         MLX5_MKC_ACCESS_MODE_KLM   = 0x2,
1002         MLX5_MKC_ACCESS_MODE_KLM_FBS = 0x3,
1003 };
1004
1005 #define MLX5_ADAPTER_PAGE_SHIFT 12
1006 #define MLX5_LOG_RQ_STRIDE_SHIFT 4
1007 /**
1008  * The batch counter dcs id starts from 0x800000 and none batch counter
1009  * starts from 0. As currently, the counter is changed to be indexed by
1010  * pool index and the offset of the counter in the pool counters_raw array.
1011  * It means now the counter index is same for batch and none batch counter.
1012  * Add the 0x800000 batch counter offset to the batch counter index helps
1013  * indicate the counter index is from batch or none batch container pool.
1014  */
1015 #define MLX5_CNT_BATCH_OFFSET 0x800000
1016
1017 /* The counter batch query requires ID align with 4. */
1018 #define MLX5_CNT_BATCH_QUERY_ID_ALIGNMENT 4
1019
1020 /* Flow counters. */
1021 struct mlx5_ifc_alloc_flow_counter_out_bits {
1022         u8 status[0x8];
1023         u8 reserved_at_8[0x18];
1024         u8 syndrome[0x20];
1025         u8 flow_counter_id[0x20];
1026         u8 reserved_at_60[0x20];
1027 };
1028
1029 struct mlx5_ifc_alloc_flow_counter_in_bits {
1030         u8 opcode[0x10];
1031         u8 reserved_at_10[0x10];
1032         u8 reserved_at_20[0x10];
1033         u8 op_mod[0x10];
1034         u8 flow_counter_id[0x20];
1035         u8 reserved_at_40[0x18];
1036         u8 flow_counter_bulk[0x8];
1037 };
1038
1039 struct mlx5_ifc_dealloc_flow_counter_out_bits {
1040         u8 status[0x8];
1041         u8 reserved_at_8[0x18];
1042         u8 syndrome[0x20];
1043         u8 reserved_at_40[0x40];
1044 };
1045
1046 struct mlx5_ifc_dealloc_flow_counter_in_bits {
1047         u8 opcode[0x10];
1048         u8 reserved_at_10[0x10];
1049         u8 reserved_at_20[0x10];
1050         u8 op_mod[0x10];
1051         u8 flow_counter_id[0x20];
1052         u8 reserved_at_60[0x20];
1053 };
1054
1055 struct mlx5_ifc_traffic_counter_bits {
1056         u8 packets[0x40];
1057         u8 octets[0x40];
1058 };
1059
1060 struct mlx5_ifc_query_flow_counter_out_bits {
1061         u8 status[0x8];
1062         u8 reserved_at_8[0x18];
1063         u8 syndrome[0x20];
1064         u8 reserved_at_40[0x40];
1065         struct mlx5_ifc_traffic_counter_bits flow_statistics[];
1066 };
1067
1068 struct mlx5_ifc_query_flow_counter_in_bits {
1069         u8 opcode[0x10];
1070         u8 reserved_at_10[0x10];
1071         u8 reserved_at_20[0x10];
1072         u8 op_mod[0x10];
1073         u8 reserved_at_40[0x20];
1074         u8 mkey[0x20];
1075         u8 address[0x40];
1076         u8 clear[0x1];
1077         u8 dump_to_memory[0x1];
1078         u8 num_of_counters[0x1e];
1079         u8 flow_counter_id[0x20];
1080 };
1081
1082 #define MLX5_MAX_KLM_BYTE_COUNT 0x80000000u
1083 #define MLX5_MIN_KLM_FIXED_BUFFER_SIZE 0x1000u
1084
1085 struct mlx5_ifc_klm_bits {
1086         u8 byte_count[0x20];
1087         u8 mkey[0x20];
1088         u8 address[0x40];
1089 };
1090
1091 struct mlx5_ifc_mkc_bits {
1092         u8 reserved_at_0[0x1];
1093         u8 free[0x1];
1094         u8 reserved_at_2[0x1];
1095         u8 access_mode_4_2[0x3];
1096         u8 reserved_at_6[0x7];
1097         u8 relaxed_ordering_write[0x1];
1098         u8 reserved_at_e[0x1];
1099         u8 small_fence_on_rdma_read_response[0x1];
1100         u8 umr_en[0x1];
1101         u8 a[0x1];
1102         u8 rw[0x1];
1103         u8 rr[0x1];
1104         u8 lw[0x1];
1105         u8 lr[0x1];
1106         u8 access_mode_1_0[0x2];
1107         u8 reserved_at_18[0x8];
1108         u8 qpn[0x18];
1109         u8 mkey_7_0[0x8];
1110         u8 reserved_at_40[0x20];
1111         u8 length64[0x1];
1112         u8 bsf_en[0x1];
1113         u8 sync_umr[0x1];
1114         u8 reserved_at_63[0x2];
1115         u8 expected_sigerr_count[0x1];
1116         u8 reserved_at_66[0x1];
1117         u8 en_rinval[0x1];
1118         u8 pd[0x18];
1119         u8 start_addr[0x40];
1120         u8 len[0x40];
1121         u8 bsf_octword_size[0x20];
1122         u8 reserved_at_120[0x80];
1123         u8 translations_octword_size[0x20];
1124         u8 reserved_at_1c0[0x19];
1125         u8 relaxed_ordering_read[0x1];
1126         u8 reserved_at_1da[0x1];
1127         u8 log_page_size[0x5];
1128         u8 reserved_at_1e0[0x3];
1129         u8 crypto_en[0x2];
1130         u8 reserved_at_1e5[0x1b];
1131 };
1132
1133 /* Range of values for MKEY context crypto_en field. */
1134 enum {
1135         MLX5_MKEY_CRYPTO_DISABLED = 0x0,
1136         MLX5_MKEY_CRYPTO_ENABLED = 0x1,
1137 };
1138
1139 struct mlx5_ifc_create_mkey_out_bits {
1140         u8 status[0x8];
1141         u8 reserved_at_8[0x18];
1142         u8 syndrome[0x20];
1143         u8 reserved_at_40[0x8];
1144         u8 mkey_index[0x18];
1145         u8 reserved_at_60[0x20];
1146 };
1147
1148 struct mlx5_ifc_create_mkey_in_bits {
1149         u8 opcode[0x10];
1150         u8 reserved_at_10[0x10];
1151         u8 reserved_at_20[0x10];
1152         u8 op_mod[0x10];
1153         u8 reserved_at_40[0x20];
1154         u8 pg_access[0x1];
1155         u8 reserved_at_61[0x1f];
1156         struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
1157         u8 reserved_at_280[0x80];
1158         u8 translations_octword_actual_size[0x20];
1159         u8 mkey_umem_id[0x20];
1160         u8 mkey_umem_offset[0x40];
1161         u8 reserved_at_380[0x500];
1162         u8 klm_pas_mtt[][0x20];
1163 };
1164
1165 enum {
1166         MLX5_GET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0 << 1,
1167         MLX5_GET_HCA_CAP_OP_MOD_ETHERNET_OFFLOAD_CAPS = 0x1 << 1,
1168         MLX5_GET_HCA_CAP_OP_MOD_QOS_CAP = 0xc << 1,
1169         MLX5_GET_HCA_CAP_OP_MOD_ROCE = 0x4 << 1,
1170         MLX5_GET_HCA_CAP_OP_MOD_NIC_FLOW_TABLE = 0x7 << 1,
1171         MLX5_GET_HCA_CAP_OP_MOD_VDPA_EMULATION = 0x13 << 1,
1172 };
1173
1174 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTQ_NET_Q \
1175                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTQ)
1176 #define MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_Q_COUNTERS \
1177                         (1ULL << MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS)
1178 #define MLX5_GENERAL_OBJ_TYPES_CAP_PARSE_GRAPH_FLEX_NODE \
1179                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH)
1180 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_HIT_ASO \
1181                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO)
1182 #define MLX5_GENERAL_OBJ_TYPES_CAP_FLOW_METER_ASO \
1183                         (1ULL << MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO)
1184 #define MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT \
1185                         (1ULL << MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT)
1186 #define MLX5_GENERAL_OBJ_TYPES_CAP_DEK \
1187                         (1ULL << MLX5_GENERAL_OBJ_TYPE_DEK)
1188 #define MLX5_GENERAL_OBJ_TYPES_CAP_IMPORT_KEK \
1189                         (1ULL << MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK)
1190 #define MLX5_GENERAL_OBJ_TYPES_CAP_CREDENTIAL \
1191                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CREDENTIAL)
1192 #define MLX5_GENERAL_OBJ_TYPES_CAP_CRYPTO_LOGIN \
1193                         (1ULL << MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN)
1194
1195 enum {
1196         MLX5_HCA_CAP_OPMOD_GET_MAX   = 0,
1197         MLX5_HCA_CAP_OPMOD_GET_CUR   = 1,
1198 };
1199
1200 enum {
1201         MLX5_CAP_INLINE_MODE_L2,
1202         MLX5_CAP_INLINE_MODE_VPORT_CONTEXT,
1203         MLX5_CAP_INLINE_MODE_NOT_REQUIRED,
1204 };
1205
1206 enum {
1207         MLX5_INLINE_MODE_NONE,
1208         MLX5_INLINE_MODE_L2,
1209         MLX5_INLINE_MODE_IP,
1210         MLX5_INLINE_MODE_TCP_UDP,
1211         MLX5_INLINE_MODE_RESERVED4,
1212         MLX5_INLINE_MODE_INNER_L2,
1213         MLX5_INLINE_MODE_INNER_IP,
1214         MLX5_INLINE_MODE_INNER_TCP_UDP,
1215 };
1216
1217 /* The supported timestamp formats reported in HCA attributes. */
1218 enum {
1219         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR = 0x0,
1220         MLX5_HCA_CAP_TIMESTAMP_FORMAT_RT = 0x1,
1221         MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR_RT = 0x2,
1222 };
1223
1224 /* The timestamp format attributes to configure queues (RQ/SQ/QP). */
1225 enum {
1226         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0,
1227         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT      = 0x1,
1228         MLX5_QPC_TIMESTAMP_FORMAT_REAL_TIME    = 0x2,
1229 };
1230
1231 /* HCA bit masks indicating which Flex parser protocols are already enabled. */
1232 #define MLX5_HCA_FLEX_IPV4_OVER_VXLAN_ENABLED (1UL << 0)
1233 #define MLX5_HCA_FLEX_IPV6_OVER_VXLAN_ENABLED (1UL << 1)
1234 #define MLX5_HCA_FLEX_IPV6_OVER_IP_ENABLED (1UL << 2)
1235 #define MLX5_HCA_FLEX_GENEVE_ENABLED (1UL << 3)
1236 #define MLX5_HCA_FLEX_CW_MPLS_OVER_GRE_ENABLED (1UL << 4)
1237 #define MLX5_HCA_FLEX_CW_MPLS_OVER_UDP_ENABLED (1UL << 5)
1238 #define MLX5_HCA_FLEX_P_BIT_VXLAN_GPE_ENABLED (1UL << 6)
1239 #define MLX5_HCA_FLEX_VXLAN_GPE_ENABLED (1UL << 7)
1240 #define MLX5_HCA_FLEX_ICMP_ENABLED (1UL << 8)
1241 #define MLX5_HCA_FLEX_ICMPV6_ENABLED (1UL << 9)
1242
1243 struct mlx5_ifc_cmd_hca_cap_bits {
1244         u8 reserved_at_0[0x30];
1245         u8 vhca_id[0x10];
1246         u8 reserved_at_40[0x20];
1247         u8 reserved_at_60[0x3];
1248         u8 log_regexp_scatter_gather_size[0x5];
1249         u8 reserved_at_68[0x3];
1250         u8 log_dma_mmo_size[0x5];
1251         u8 reserved_at_70[0x3];
1252         u8 log_compress_mmo_size[0x5];
1253         u8 reserved_at_78[0x3];
1254         u8 log_decompress_mmo_size[0x5];
1255         u8 log_max_srq_sz[0x8];
1256         u8 log_max_qp_sz[0x8];
1257         u8 reserved_at_90[0x9];
1258         u8 wqe_index_ignore_cap[0x1];
1259         u8 dynamic_qp_allocation[0x1];
1260         u8 log_max_qp[0x5];
1261         u8 regexp[0x1];
1262         u8 reserved_at_a1[0x3];
1263         u8 regexp_num_of_engines[0x4];
1264         u8 reserved_at_a8[0x1];
1265         u8 reg_c_preserve[0x1];
1266         u8 reserved_at_aa[0x1];
1267         u8 log_max_srq[0x5];
1268         u8 reserved_at_b0[0x3];
1269         u8 regexp_log_crspace_size[0x5];
1270         u8 reserved_at_b8[0x3];
1271         u8 scatter_fcs_w_decap_disable[0x1];
1272         u8 reserved_at_bc[0x4];
1273         u8 reserved_at_c0[0x8];
1274         u8 log_max_cq_sz[0x8];
1275         u8 reserved_at_d0[0xb];
1276         u8 log_max_cq[0x5];
1277         u8 log_max_eq_sz[0x8];
1278         u8 relaxed_ordering_write[0x1];
1279         u8 relaxed_ordering_read[0x1];
1280         u8 access_register_user[0x1];
1281         u8 log_max_mkey[0x5];
1282         u8 reserved_at_f0[0x8];
1283         u8 dump_fill_mkey[0x1];
1284         u8 reserved_at_f9[0x3];
1285         u8 log_max_eq[0x4];
1286         u8 max_indirection[0x8];
1287         u8 fixed_buffer_size[0x1];
1288         u8 log_max_mrw_sz[0x7];
1289         u8 force_teardown[0x1];
1290         u8 reserved_at_111[0x1];
1291         u8 log_max_bsf_list_size[0x6];
1292         u8 umr_extended_translation_offset[0x1];
1293         u8 null_mkey[0x1];
1294         u8 log_max_klm_list_size[0x6];
1295         u8 non_wire_sq[0x1];
1296         u8 reserved_at_121[0x9];
1297         u8 log_max_ra_req_dc[0x6];
1298         u8 reserved_at_130[0x3];
1299         u8 log_max_static_sq_wq[0x5];
1300         u8 reserved_at_138[0x2];
1301         u8 log_max_ra_res_dc[0x6];
1302         u8 reserved_at_140[0xa];
1303         u8 log_max_ra_req_qp[0x6];
1304         u8 rtr2rts_qp_counters_set_id[0x1];
1305         u8 rts2rts_udp_sport[0x1];
1306         u8 rts2rts_lag_tx_port_affinity[0x1];
1307         u8 dma_mmo[0x1];
1308         u8 compress_min_block_size[0x4];
1309         u8 compress[0x1];
1310         u8 decompress[0x1];
1311         u8 log_max_ra_res_qp[0x6];
1312         u8 end_pad[0x1];
1313         u8 cc_query_allowed[0x1];
1314         u8 cc_modify_allowed[0x1];
1315         u8 start_pad[0x1];
1316         u8 cache_line_128byte[0x1];
1317         u8 reserved_at_165[0xa];
1318         u8 qcam_reg[0x1];
1319         u8 gid_table_size[0x10];
1320         u8 out_of_seq_cnt[0x1];
1321         u8 vport_counters[0x1];
1322         u8 retransmission_q_counters[0x1];
1323         u8 debug[0x1];
1324         u8 modify_rq_counter_set_id[0x1];
1325         u8 rq_delay_drop[0x1];
1326         u8 max_qp_cnt[0xa];
1327         u8 pkey_table_size[0x10];
1328         u8 vport_group_manager[0x1];
1329         u8 vhca_group_manager[0x1];
1330         u8 ib_virt[0x1];
1331         u8 eth_virt[0x1];
1332         u8 vnic_env_queue_counters[0x1];
1333         u8 ets[0x1];
1334         u8 nic_flow_table[0x1];
1335         u8 eswitch_manager[0x1];
1336         u8 device_memory[0x1];
1337         u8 mcam_reg[0x1];
1338         u8 pcam_reg[0x1];
1339         u8 local_ca_ack_delay[0x5];
1340         u8 port_module_event[0x1];
1341         u8 enhanced_error_q_counters[0x1];
1342         u8 ports_check[0x1];
1343         u8 reserved_at_1b3[0x1];
1344         u8 disable_link_up[0x1];
1345         u8 beacon_led[0x1];
1346         u8 port_type[0x2];
1347         u8 num_ports[0x8];
1348         u8 reserved_at_1c0[0x1];
1349         u8 pps[0x1];
1350         u8 pps_modify[0x1];
1351         u8 log_max_msg[0x5];
1352         u8 reserved_at_1c8[0x4];
1353         u8 max_tc[0x4];
1354         u8 temp_warn_event[0x1];
1355         u8 dcbx[0x1];
1356         u8 general_notification_event[0x1];
1357         u8 reserved_at_1d3[0x2];
1358         u8 fpga[0x1];
1359         u8 rol_s[0x1];
1360         u8 rol_g[0x1];
1361         u8 reserved_at_1d8[0x1];
1362         u8 wol_s[0x1];
1363         u8 wol_g[0x1];
1364         u8 wol_a[0x1];
1365         u8 wol_b[0x1];
1366         u8 wol_m[0x1];
1367         u8 wol_u[0x1];
1368         u8 wol_p[0x1];
1369         u8 stat_rate_support[0x10];
1370         u8 reserved_at_1f0[0xc];
1371         u8 cqe_version[0x4];
1372         u8 compact_address_vector[0x1];
1373         u8 striding_rq[0x1];
1374         u8 reserved_at_202[0x1];
1375         u8 ipoib_enhanced_offloads[0x1];
1376         u8 ipoib_basic_offloads[0x1];
1377         u8 reserved_at_205[0x1];
1378         u8 repeated_block_disabled[0x1];
1379         u8 umr_modify_entity_size_disabled[0x1];
1380         u8 umr_modify_atomic_disabled[0x1];
1381         u8 umr_indirect_mkey_disabled[0x1];
1382         u8 umr_fence[0x2];
1383         u8 reserved_at_20c[0x3];
1384         u8 drain_sigerr[0x1];
1385         u8 cmdif_checksum[0x2];
1386         u8 sigerr_cqe[0x1];
1387         u8 reserved_at_213[0x1];
1388         u8 wq_signature[0x1];
1389         u8 sctr_data_cqe[0x1];
1390         u8 reserved_at_216[0x1];
1391         u8 sho[0x1];
1392         u8 tph[0x1];
1393         u8 rf[0x1];
1394         u8 dct[0x1];
1395         u8 qos[0x1];
1396         u8 eth_net_offloads[0x1];
1397         u8 roce[0x1];
1398         u8 atomic[0x1];
1399         u8 reserved_at_21f[0x1];
1400         u8 cq_oi[0x1];
1401         u8 cq_resize[0x1];
1402         u8 cq_moderation[0x1];
1403         u8 reserved_at_223[0x3];
1404         u8 cq_eq_remap[0x1];
1405         u8 pg[0x1];
1406         u8 block_lb_mc[0x1];
1407         u8 reserved_at_229[0x1];
1408         u8 scqe_break_moderation[0x1];
1409         u8 cq_period_start_from_cqe[0x1];
1410         u8 cd[0x1];
1411         u8 reserved_at_22d[0x1];
1412         u8 apm[0x1];
1413         u8 vector_calc[0x1];
1414         u8 umr_ptr_rlky[0x1];
1415         u8 imaicl[0x1];
1416         u8 reserved_at_232[0x4];
1417         u8 qkv[0x1];
1418         u8 pkv[0x1];
1419         u8 set_deth_sqpn[0x1];
1420         u8 reserved_at_239[0x3];
1421         u8 xrc[0x1];
1422         u8 ud[0x1];
1423         u8 uc[0x1];
1424         u8 rc[0x1];
1425         u8 uar_4k[0x1];
1426         u8 reserved_at_241[0x9];
1427         u8 uar_sz[0x6];
1428         u8 reserved_at_250[0x8];
1429         u8 log_pg_sz[0x8];
1430         u8 bf[0x1];
1431         u8 driver_version[0x1];
1432         u8 pad_tx_eth_packet[0x1];
1433         u8 reserved_at_263[0x8];
1434         u8 log_bf_reg_size[0x5];
1435         u8 reserved_at_270[0xb];
1436         u8 lag_master[0x1];
1437         u8 num_lag_ports[0x4];
1438         u8 reserved_at_280[0x10];
1439         u8 max_wqe_sz_sq[0x10];
1440         u8 reserved_at_2a0[0x10];
1441         u8 max_wqe_sz_rq[0x10];
1442         u8 max_flow_counter_31_16[0x10];
1443         u8 max_wqe_sz_sq_dc[0x10];
1444         u8 reserved_at_2e0[0x7];
1445         u8 max_qp_mcg[0x19];
1446         u8 reserved_at_300[0x10];
1447         u8 flow_counter_bulk_alloc[0x08];
1448         u8 log_max_mcg[0x8];
1449         u8 reserved_at_320[0x3];
1450         u8 log_max_transport_domain[0x5];
1451         u8 reserved_at_328[0x3];
1452         u8 log_max_pd[0x5];
1453         u8 reserved_at_330[0xb];
1454         u8 log_max_xrcd[0x5];
1455         u8 nic_receive_steering_discard[0x1];
1456         u8 receive_discard_vport_down[0x1];
1457         u8 transmit_discard_vport_down[0x1];
1458         u8 reserved_at_343[0x5];
1459         u8 log_max_flow_counter_bulk[0x8];
1460         u8 max_flow_counter_15_0[0x10];
1461         u8 modify_tis[0x1];
1462         u8 flow_counters_dump[0x1];
1463         u8 reserved_at_360[0x1];
1464         u8 log_max_rq[0x5];
1465         u8 reserved_at_368[0x3];
1466         u8 log_max_sq[0x5];
1467         u8 reserved_at_370[0x3];
1468         u8 log_max_tir[0x5];
1469         u8 reserved_at_378[0x3];
1470         u8 log_max_tis[0x5];
1471         u8 basic_cyclic_rcv_wqe[0x1];
1472         u8 reserved_at_381[0x2];
1473         u8 log_max_rmp[0x5];
1474         u8 reserved_at_388[0x3];
1475         u8 log_max_rqt[0x5];
1476         u8 reserved_at_390[0x3];
1477         u8 log_max_rqt_size[0x5];
1478         u8 reserved_at_398[0x3];
1479         u8 log_max_tis_per_sq[0x5];
1480         u8 ext_stride_num_range[0x1];
1481         u8 reserved_at_3a1[0x2];
1482         u8 log_max_stride_sz_rq[0x5];
1483         u8 reserved_at_3a8[0x3];
1484         u8 log_min_stride_sz_rq[0x5];
1485         u8 reserved_at_3b0[0x3];
1486         u8 log_max_stride_sz_sq[0x5];
1487         u8 reserved_at_3b8[0x3];
1488         u8 log_min_stride_sz_sq[0x5];
1489         u8 hairpin[0x1];
1490         u8 reserved_at_3c1[0x2];
1491         u8 log_max_hairpin_queues[0x5];
1492         u8 reserved_at_3c8[0x3];
1493         u8 log_max_hairpin_wq_data_sz[0x5];
1494         u8 reserved_at_3d0[0x3];
1495         u8 log_max_hairpin_num_packets[0x5];
1496         u8 reserved_at_3d8[0x3];
1497         u8 log_max_wq_sz[0x5];
1498         u8 nic_vport_change_event[0x1];
1499         u8 disable_local_lb_uc[0x1];
1500         u8 disable_local_lb_mc[0x1];
1501         u8 log_min_hairpin_wq_data_sz[0x5];
1502         u8 reserved_at_3e8[0x3];
1503         u8 log_max_vlan_list[0x5];
1504         u8 reserved_at_3f0[0x3];
1505         u8 log_max_current_mc_list[0x5];
1506         u8 reserved_at_3f8[0x3];
1507         u8 log_max_current_uc_list[0x5];
1508         u8 general_obj_types[0x40];
1509         u8 sq_ts_format[0x2];
1510         u8 rq_ts_format[0x2];
1511         u8 reserved_at_444[0x1C];
1512         u8 reserved_at_460[0x8];
1513         u8 aes_xts[0x1];
1514         u8 crypto[0x1];
1515         u8 reserved_at_46a[0x6];
1516         u8 max_num_eqs[0x10];
1517         u8 reserved_at_480[0x3];
1518         u8 log_max_l2_table[0x5];
1519         u8 reserved_at_488[0x8];
1520         u8 log_uar_page_sz[0x10];
1521         u8 reserved_at_4a0[0x20];
1522         u8 device_frequency_mhz[0x20];
1523         u8 device_frequency_khz[0x20];
1524         u8 reserved_at_500[0x20];
1525         u8 num_of_uars_per_page[0x20];
1526         u8 flex_parser_protocols[0x20];
1527         u8 max_geneve_tlv_options[0x8];
1528         u8 reserved_at_568[0x3];
1529         u8 max_geneve_tlv_option_data_len[0x5];
1530         u8 reserved_at_570[0x49];
1531         u8 mini_cqe_resp_l3_l4_tag[0x1];
1532         u8 mini_cqe_resp_flow_tag[0x1];
1533         u8 enhanced_cqe_compression[0x1];
1534         u8 mini_cqe_resp_stride_index[0x1];
1535         u8 cqe_128_always[0x1];
1536         u8 cqe_compression_128[0x1];
1537         u8 cqe_compression[0x1];
1538         u8 cqe_compression_timeout[0x10];
1539         u8 cqe_compression_max_num[0x10];
1540         u8 reserved_at_5e0[0x10];
1541         u8 tag_matching[0x1];
1542         u8 rndv_offload_rc[0x1];
1543         u8 rndv_offload_dc[0x1];
1544         u8 log_tag_matching_list_sz[0x5];
1545         u8 reserved_at_5f8[0x3];
1546         u8 log_max_xrq[0x5];
1547         u8 affiliate_nic_vport_criteria[0x8];
1548         u8 native_port_num[0x8];
1549         u8 num_vhca_ports[0x8];
1550         u8 reserved_at_618[0x6];
1551         u8 sw_owner_id[0x1];
1552         u8 reserved_at_61f[0x1e1];
1553 };
1554
1555 struct mlx5_ifc_qos_cap_bits {
1556         u8 packet_pacing[0x1];
1557         u8 esw_scheduling[0x1];
1558         u8 esw_bw_share[0x1];
1559         u8 esw_rate_limit[0x1];
1560         u8 reserved_at_4[0x1];
1561         u8 packet_pacing_burst_bound[0x1];
1562         u8 packet_pacing_typical_size[0x1];
1563         u8 flow_meter_old[0x1];
1564         u8 reserved_at_8[0x8];
1565         u8 log_max_flow_meter[0x8];
1566         u8 flow_meter_reg_id[0x8];
1567         u8 wqe_rate_pp[0x1];
1568         u8 reserved_at_25[0x7];
1569         u8 flow_meter[0x1];
1570         u8 reserved_at_2e[0x17];
1571         u8 packet_pacing_max_rate[0x20];
1572         u8 packet_pacing_min_rate[0x20];
1573         u8 reserved_at_80[0x10];
1574         u8 packet_pacing_rate_table_size[0x10];
1575         u8 esw_element_type[0x10];
1576         u8 esw_tsar_type[0x10];
1577         u8 reserved_at_c0[0x10];
1578         u8 max_qos_para_vport[0x10];
1579         u8 max_tsar_bw_share[0x20];
1580         u8 nic_element_type[0x10];
1581         u8 nic_tsar_type[0x10];
1582         u8 reserved_at_120[0x3];
1583         u8 log_meter_aso_granularity[0x5];
1584         u8 reserved_at_128[0x3];
1585         u8 log_meter_aso_max_alloc[0x5];
1586         u8 reserved_at_130[0x3];
1587         u8 log_max_num_meter_aso[0x5];
1588         u8 reserved_at_138[0x6b0];
1589 };
1590
1591 struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
1592         u8 csum_cap[0x1];
1593         u8 vlan_cap[0x1];
1594         u8 lro_cap[0x1];
1595         u8 lro_psh_flag[0x1];
1596         u8 lro_time_stamp[0x1];
1597         u8 lro_max_msg_sz_mode[0x2];
1598         u8 wqe_vlan_insert[0x1];
1599         u8 self_lb_en_modifiable[0x1];
1600         u8 self_lb_mc[0x1];
1601         u8 self_lb_uc[0x1];
1602         u8 max_lso_cap[0x5];
1603         u8 multi_pkt_send_wqe[0x2];
1604         u8 wqe_inline_mode[0x2];
1605         u8 rss_ind_tbl_cap[0x4];
1606         u8 reg_umr_sq[0x1];
1607         u8 scatter_fcs[0x1];
1608         u8 enhanced_multi_pkt_send_wqe[0x1];
1609         u8 tunnel_lso_const_out_ip_id[0x1];
1610         u8 tunnel_lro_gre[0x1];
1611         u8 tunnel_lro_vxlan[0x1];
1612         u8 tunnel_stateless_gre[0x1];
1613         u8 tunnel_stateless_vxlan[0x1];
1614         u8 swp[0x1];
1615         u8 swp_csum[0x1];
1616         u8 swp_lso[0x1];
1617         u8 reserved_at_23[0x8];
1618         u8 tunnel_stateless_gtp[0x1];
1619         u8 reserved_at_25[0x4];
1620         u8 max_vxlan_udp_ports[0x8];
1621         u8 reserved_at_38[0x6];
1622         u8 max_geneve_opt_len[0x1];
1623         u8 tunnel_stateless_geneve_rx[0x1];
1624         u8 reserved_at_40[0x10];
1625         u8 lro_min_mss_size[0x10];
1626         u8 reserved_at_60[0x120];
1627         u8 lro_timer_supported_periods[4][0x20];
1628         u8 reserved_at_200[0x600];
1629 };
1630
1631 enum {
1632         MLX5_VIRTQ_TYPE_SPLIT = 0,
1633         MLX5_VIRTQ_TYPE_PACKED = 1,
1634 };
1635
1636 enum {
1637         MLX5_VIRTQ_EVENT_MODE_NO_MSIX = 0,
1638         MLX5_VIRTQ_EVENT_MODE_QP = 1,
1639         MLX5_VIRTQ_EVENT_MODE_MSIX = 2,
1640 };
1641
1642 struct mlx5_ifc_virtio_emulation_cap_bits {
1643         u8 desc_tunnel_offload_type[0x1];
1644         u8 eth_frame_offload_type[0x1];
1645         u8 virtio_version_1_0[0x1];
1646         u8 tso_ipv4[0x1];
1647         u8 tso_ipv6[0x1];
1648         u8 tx_csum[0x1];
1649         u8 rx_csum[0x1];
1650         u8 reserved_at_7[0x1][0x9];
1651         u8 event_mode[0x8];
1652         u8 virtio_queue_type[0x8];
1653         u8 reserved_at_20[0x13];
1654         u8 log_doorbell_stride[0x5];
1655         u8 reserved_at_3b[0x3];
1656         u8 log_doorbell_bar_size[0x5];
1657         u8 doorbell_bar_offset[0x40];
1658         u8 reserved_at_80[0x8];
1659         u8 max_num_virtio_queues[0x18];
1660         u8 reserved_at_a0[0x60];
1661         u8 umem_1_buffer_param_a[0x20];
1662         u8 umem_1_buffer_param_b[0x20];
1663         u8 umem_2_buffer_param_a[0x20];
1664         u8 umem_2_buffer_param_b[0x20];
1665         u8 umem_3_buffer_param_a[0x20];
1666         u8 umem_3_buffer_param_b[0x20];
1667         u8 reserved_at_1c0[0x620];
1668 };
1669
1670 struct mlx5_ifc_flow_table_prop_layout_bits {
1671         u8 ft_support[0x1];
1672         u8 flow_tag[0x1];
1673         u8 flow_counter[0x1];
1674         u8 flow_modify_en[0x1];
1675         u8 modify_root[0x1];
1676         u8 identified_miss_table[0x1];
1677         u8 flow_table_modify[0x1];
1678         u8 reformat[0x1];
1679         u8 decap[0x1];
1680         u8 reset_root_to_default[0x1];
1681         u8 pop_vlan[0x1];
1682         u8 push_vlan[0x1];
1683         u8 fpga_vendor_acceleration[0x1];
1684         u8 pop_vlan_2[0x1];
1685         u8 push_vlan_2[0x1];
1686         u8 reformat_and_vlan_action[0x1];
1687         u8 modify_and_vlan_action[0x1];
1688         u8 sw_owner[0x1];
1689         u8 reformat_l3_tunnel_to_l2[0x1];
1690         u8 reformat_l2_to_l3_tunnel[0x1];
1691         u8 reformat_and_modify_action[0x1];
1692         u8 reserved_at_15[0x9];
1693         u8 sw_owner_v2[0x1];
1694         u8 reserved_at_1f[0x1];
1695         u8 reserved_at_20[0x2];
1696         u8 log_max_ft_size[0x6];
1697         u8 log_max_modify_header_context[0x8];
1698         u8 max_modify_header_actions[0x8];
1699         u8 max_ft_level[0x8];
1700         u8 reserved_at_40[0x8];
1701         u8 log_max_ft_sampler_num[8];
1702         u8 metadata_reg_b_width[0x8];
1703         u8 metadata_reg_a_width[0x8];
1704         u8 reserved_at_60[0x18];
1705         u8 log_max_ft_num[0x8];
1706         u8 reserved_at_80[0x10];
1707         u8 log_max_flow_counter[0x8];
1708         u8 log_max_destination[0x8];
1709         u8 reserved_at_a0[0x18];
1710         u8 log_max_flow[0x8];
1711         u8 reserved_at_c0[0x140];
1712 };
1713
1714 struct mlx5_ifc_roce_caps_bits {
1715         u8 reserved_0[0x1e];
1716         u8 qp_ts_format[0x2];
1717         u8 reserved_at_20[0x7e0];
1718 };
1719
1720 struct mlx5_ifc_flow_table_nic_cap_bits {
1721         u8         reserved_at_0[0x200];
1722         struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties;
1723 };
1724
1725 union mlx5_ifc_hca_cap_union_bits {
1726         struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1727         struct mlx5_ifc_per_protocol_networking_offload_caps_bits
1728                per_protocol_networking_offload_caps;
1729         struct mlx5_ifc_qos_cap_bits qos_cap;
1730         struct mlx5_ifc_virtio_emulation_cap_bits vdpa_caps;
1731         struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1732         struct mlx5_ifc_roce_caps_bits roce_caps;
1733         u8 reserved_at_0[0x8000];
1734 };
1735
1736 struct mlx5_ifc_set_action_in_bits {
1737         u8 action_type[0x4];
1738         u8 field[0xc];
1739         u8 reserved_at_10[0x3];
1740         u8 offset[0x5];
1741         u8 reserved_at_18[0x3];
1742         u8 length[0x5];
1743         u8 data[0x20];
1744 };
1745
1746 struct mlx5_ifc_query_hca_cap_out_bits {
1747         u8 status[0x8];
1748         u8 reserved_at_8[0x18];
1749         u8 syndrome[0x20];
1750         u8 reserved_at_40[0x40];
1751         union mlx5_ifc_hca_cap_union_bits capability;
1752 };
1753
1754 struct mlx5_ifc_query_hca_cap_in_bits {
1755         u8 opcode[0x10];
1756         u8 reserved_at_10[0x10];
1757         u8 reserved_at_20[0x10];
1758         u8 op_mod[0x10];
1759         u8 reserved_at_40[0x40];
1760 };
1761
1762 struct mlx5_ifc_mac_address_layout_bits {
1763         u8 reserved_at_0[0x10];
1764         u8 mac_addr_47_32[0x10];
1765         u8 mac_addr_31_0[0x20];
1766 };
1767
1768 struct mlx5_ifc_nic_vport_context_bits {
1769         u8 reserved_at_0[0x5];
1770         u8 min_wqe_inline_mode[0x3];
1771         u8 reserved_at_8[0x15];
1772         u8 disable_mc_local_lb[0x1];
1773         u8 disable_uc_local_lb[0x1];
1774         u8 roce_en[0x1];
1775         u8 arm_change_event[0x1];
1776         u8 reserved_at_21[0x1a];
1777         u8 event_on_mtu[0x1];
1778         u8 event_on_promisc_change[0x1];
1779         u8 event_on_vlan_change[0x1];
1780         u8 event_on_mc_address_change[0x1];
1781         u8 event_on_uc_address_change[0x1];
1782         u8 reserved_at_40[0xc];
1783         u8 affiliation_criteria[0x4];
1784         u8 affiliated_vhca_id[0x10];
1785         u8 reserved_at_60[0xd0];
1786         u8 mtu[0x10];
1787         u8 system_image_guid[0x40];
1788         u8 port_guid[0x40];
1789         u8 node_guid[0x40];
1790         u8 reserved_at_200[0x140];
1791         u8 qkey_violation_counter[0x10];
1792         u8 reserved_at_350[0x430];
1793         u8 promisc_uc[0x1];
1794         u8 promisc_mc[0x1];
1795         u8 promisc_all[0x1];
1796         u8 reserved_at_783[0x2];
1797         u8 allowed_list_type[0x3];
1798         u8 reserved_at_788[0xc];
1799         u8 allowed_list_size[0xc];
1800         struct mlx5_ifc_mac_address_layout_bits permanent_address;
1801         u8 reserved_at_7e0[0x20];
1802 };
1803
1804 struct mlx5_ifc_query_nic_vport_context_out_bits {
1805         u8 status[0x8];
1806         u8 reserved_at_8[0x18];
1807         u8 syndrome[0x20];
1808         u8 reserved_at_40[0x40];
1809         struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
1810 };
1811
1812 struct mlx5_ifc_query_nic_vport_context_in_bits {
1813         u8 opcode[0x10];
1814         u8 reserved_at_10[0x10];
1815         u8 reserved_at_20[0x10];
1816         u8 op_mod[0x10];
1817         u8 other_vport[0x1];
1818         u8 reserved_at_41[0xf];
1819         u8 vport_number[0x10];
1820         u8 reserved_at_60[0x5];
1821         u8 allowed_list_type[0x3];
1822         u8 reserved_at_68[0x18];
1823 };
1824
1825 struct mlx5_ifc_tisc_bits {
1826         u8 strict_lag_tx_port_affinity[0x1];
1827         u8 reserved_at_1[0x3];
1828         u8 lag_tx_port_affinity[0x04];
1829         u8 reserved_at_8[0x4];
1830         u8 prio[0x4];
1831         u8 reserved_at_10[0x10];
1832         u8 reserved_at_20[0x100];
1833         u8 reserved_at_120[0x8];
1834         u8 transport_domain[0x18];
1835         u8 reserved_at_140[0x8];
1836         u8 underlay_qpn[0x18];
1837         u8 reserved_at_160[0x3a0];
1838 };
1839
1840 struct mlx5_ifc_query_tis_out_bits {
1841         u8 status[0x8];
1842         u8 reserved_at_8[0x18];
1843         u8 syndrome[0x20];
1844         u8 reserved_at_40[0x40];
1845         struct mlx5_ifc_tisc_bits tis_context;
1846 };
1847
1848 struct mlx5_ifc_query_tis_in_bits {
1849         u8 opcode[0x10];
1850         u8 reserved_at_10[0x10];
1851         u8 reserved_at_20[0x10];
1852         u8 op_mod[0x10];
1853         u8 reserved_at_40[0x8];
1854         u8 tisn[0x18];
1855         u8 reserved_at_60[0x20];
1856 };
1857
1858 struct mlx5_ifc_alloc_transport_domain_out_bits {
1859         u8 status[0x8];
1860         u8 reserved_at_8[0x18];
1861         u8 syndrome[0x20];
1862         u8 reserved_at_40[0x8];
1863         u8 transport_domain[0x18];
1864         u8 reserved_at_60[0x20];
1865 };
1866
1867 struct mlx5_ifc_alloc_transport_domain_in_bits {
1868         u8 opcode[0x10];
1869         u8 reserved_at_10[0x10];
1870         u8 reserved_at_20[0x10];
1871         u8 op_mod[0x10];
1872         u8 reserved_at_40[0x40];
1873 };
1874
1875 enum {
1876         MLX5_WQ_TYPE_LINKED_LIST                = 0x0,
1877         MLX5_WQ_TYPE_CYCLIC                     = 0x1,
1878         MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ    = 0x2,
1879         MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ         = 0x3,
1880 };
1881
1882 enum {
1883         MLX5_WQ_END_PAD_MODE_NONE  = 0x0,
1884         MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
1885 };
1886
1887 struct mlx5_ifc_wq_bits {
1888         u8 wq_type[0x4];
1889         u8 wq_signature[0x1];
1890         u8 end_padding_mode[0x2];
1891         u8 cd_slave[0x1];
1892         u8 reserved_at_8[0x18];
1893         u8 hds_skip_first_sge[0x1];
1894         u8 log2_hds_buf_size[0x3];
1895         u8 reserved_at_24[0x7];
1896         u8 page_offset[0x5];
1897         u8 lwm[0x10];
1898         u8 reserved_at_40[0x8];
1899         u8 pd[0x18];
1900         u8 reserved_at_60[0x8];
1901         u8 uar_page[0x18];
1902         u8 dbr_addr[0x40];
1903         u8 hw_counter[0x20];
1904         u8 sw_counter[0x20];
1905         u8 reserved_at_100[0xc];
1906         u8 log_wq_stride[0x4];
1907         u8 reserved_at_110[0x3];
1908         u8 log_wq_pg_sz[0x5];
1909         u8 reserved_at_118[0x3];
1910         u8 log_wq_sz[0x5];
1911         u8 dbr_umem_valid[0x1];
1912         u8 wq_umem_valid[0x1];
1913         u8 reserved_at_122[0x1];
1914         u8 log_hairpin_num_packets[0x5];
1915         u8 reserved_at_128[0x3];
1916         u8 log_hairpin_data_sz[0x5];
1917         u8 reserved_at_130[0x4];
1918         u8 single_wqe_log_num_of_strides[0x4];
1919         u8 two_byte_shift_en[0x1];
1920         u8 reserved_at_139[0x4];
1921         u8 single_stride_log_num_of_bytes[0x3];
1922         u8 dbr_umem_id[0x20];
1923         u8 wq_umem_id[0x20];
1924         u8 wq_umem_offset[0x40];
1925         u8 reserved_at_1c0[0x440];
1926 };
1927
1928 enum {
1929         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE  = 0x0,
1930         MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP     = 0x1,
1931 };
1932
1933 enum {
1934         MLX5_RQC_STATE_RST  = 0x0,
1935         MLX5_RQC_STATE_RDY  = 0x1,
1936         MLX5_RQC_STATE_ERR  = 0x3,
1937 };
1938
1939 struct mlx5_ifc_rqc_bits {
1940         u8 rlky[0x1];
1941         u8 delay_drop_en[0x1];
1942         u8 scatter_fcs[0x1];
1943         u8 vsd[0x1];
1944         u8 mem_rq_type[0x4];
1945         u8 state[0x4];
1946         u8 reserved_at_c[0x1];
1947         u8 flush_in_error_en[0x1];
1948         u8 hairpin[0x1];
1949         u8 reserved_at_f[0xB];
1950         u8 ts_format[0x02];
1951         u8 reserved_at_1c[0x4];
1952         u8 reserved_at_20[0x8];
1953         u8 user_index[0x18];
1954         u8 reserved_at_40[0x8];
1955         u8 cqn[0x18];
1956         u8 counter_set_id[0x8];
1957         u8 reserved_at_68[0x18];
1958         u8 reserved_at_80[0x8];
1959         u8 rmpn[0x18];
1960         u8 reserved_at_a0[0x8];
1961         u8 hairpin_peer_sq[0x18];
1962         u8 reserved_at_c0[0x10];
1963         u8 hairpin_peer_vhca[0x10];
1964         u8 reserved_at_e0[0xa0];
1965         struct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */
1966 };
1967
1968 struct mlx5_ifc_create_rq_out_bits {
1969         u8 status[0x8];
1970         u8 reserved_at_8[0x18];
1971         u8 syndrome[0x20];
1972         u8 reserved_at_40[0x8];
1973         u8 rqn[0x18];
1974         u8 reserved_at_60[0x20];
1975 };
1976
1977 struct mlx5_ifc_create_rq_in_bits {
1978         u8 opcode[0x10];
1979         u8 uid[0x10];
1980         u8 reserved_at_20[0x10];
1981         u8 op_mod[0x10];
1982         u8 reserved_at_40[0xc0];
1983         struct mlx5_ifc_rqc_bits ctx;
1984 };
1985
1986 struct mlx5_ifc_modify_rq_out_bits {
1987         u8 status[0x8];
1988         u8 reserved_at_8[0x18];
1989         u8 syndrome[0x20];
1990         u8 reserved_at_40[0x40];
1991 };
1992
1993 struct mlx5_ifc_query_rq_out_bits {
1994         u8 status[0x8];
1995         u8 reserved_at_8[0x18];
1996         u8 syndrome[0x20];
1997         u8 reserved_at_40[0xc0];
1998         struct mlx5_ifc_rqc_bits rq_context;
1999 };
2000
2001 struct mlx5_ifc_query_rq_in_bits {
2002         u8 opcode[0x10];
2003         u8 reserved_at_10[0x10];
2004         u8 reserved_at_20[0x10];
2005         u8 op_mod[0x10];
2006         u8 reserved_at_40[0x8];
2007         u8 rqn[0x18];
2008         u8 reserved_at_60[0x20];
2009 };
2010
2011 struct mlx5_ifc_create_tis_out_bits {
2012         u8 status[0x8];
2013         u8 reserved_at_8[0x18];
2014         u8 syndrome[0x20];
2015         u8 reserved_at_40[0x8];
2016         u8 tisn[0x18];
2017         u8 reserved_at_60[0x20];
2018 };
2019
2020 struct mlx5_ifc_create_tis_in_bits {
2021         u8 opcode[0x10];
2022         u8 uid[0x10];
2023         u8 reserved_at_20[0x10];
2024         u8 op_mod[0x10];
2025         u8 reserved_at_40[0xc0];
2026         struct mlx5_ifc_tisc_bits ctx;
2027 };
2028
2029 enum {
2030         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
2031         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
2032         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
2033         MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
2034 };
2035
2036 struct mlx5_ifc_modify_rq_in_bits {
2037         u8 opcode[0x10];
2038         u8 uid[0x10];
2039         u8 reserved_at_20[0x10];
2040         u8 op_mod[0x10];
2041         u8 rq_state[0x4];
2042         u8 reserved_at_44[0x4];
2043         u8 rqn[0x18];
2044         u8 reserved_at_60[0x20];
2045         u8 modify_bitmask[0x40];
2046         u8 reserved_at_c0[0x40];
2047         struct mlx5_ifc_rqc_bits ctx;
2048 };
2049
2050 enum {
2051         MLX5_L3_PROT_TYPE_IPV4 = 0,
2052         MLX5_L3_PROT_TYPE_IPV6 = 1,
2053 };
2054
2055 enum {
2056         MLX5_L4_PROT_TYPE_TCP = 0,
2057         MLX5_L4_PROT_TYPE_UDP = 1,
2058 };
2059
2060 enum {
2061         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP     = 0x0,
2062         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP     = 0x1,
2063         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT   = 0x2,
2064         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT   = 0x3,
2065         MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI  = 0x4,
2066 };
2067
2068 struct mlx5_ifc_rx_hash_field_select_bits {
2069         u8 l3_prot_type[0x1];
2070         u8 l4_prot_type[0x1];
2071         u8 selected_fields[0x1e];
2072 };
2073
2074 enum {
2075         MLX5_TIRC_DISP_TYPE_DIRECT    = 0x0,
2076         MLX5_TIRC_DISP_TYPE_INDIRECT  = 0x1,
2077 };
2078
2079 enum {
2080         MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO  = 0x1,
2081         MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO  = 0x2,
2082 };
2083
2084 enum {
2085         MLX5_RX_HASH_FN_NONE           = 0x0,
2086         MLX5_RX_HASH_FN_INVERTED_XOR8  = 0x1,
2087         MLX5_RX_HASH_FN_TOEPLITZ       = 0x2,
2088 };
2089
2090 enum {
2091         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST    = 0x1,
2092         MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST  = 0x2,
2093 };
2094
2095 enum {
2096         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L4    = 0x0,
2097         MLX5_LRO_MAX_MSG_SIZE_START_FROM_L2  = 0x1,
2098 };
2099
2100 struct mlx5_ifc_tirc_bits {
2101         u8 reserved_at_0[0x20];
2102         u8 disp_type[0x4];
2103         u8 reserved_at_24[0x1c];
2104         u8 reserved_at_40[0x40];
2105         u8 reserved_at_80[0x4];
2106         u8 lro_timeout_period_usecs[0x10];
2107         u8 lro_enable_mask[0x4];
2108         u8 lro_max_msg_sz[0x8];
2109         u8 reserved_at_a0[0x40];
2110         u8 reserved_at_e0[0x8];
2111         u8 inline_rqn[0x18];
2112         u8 rx_hash_symmetric[0x1];
2113         u8 reserved_at_101[0x1];
2114         u8 tunneled_offload_en[0x1];
2115         u8 reserved_at_103[0x5];
2116         u8 indirect_table[0x18];
2117         u8 rx_hash_fn[0x4];
2118         u8 reserved_at_124[0x2];
2119         u8 self_lb_block[0x2];
2120         u8 transport_domain[0x18];
2121         u8 rx_hash_toeplitz_key[10][0x20];
2122         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2123         struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2124         u8 reserved_at_2c0[0x4c0];
2125 };
2126
2127 struct mlx5_ifc_create_tir_out_bits {
2128         u8 status[0x8];
2129         u8 reserved_at_8[0x18];
2130         u8 syndrome[0x20];
2131         u8 reserved_at_40[0x8];
2132         u8 tirn[0x18];
2133         u8 reserved_at_60[0x20];
2134 };
2135
2136 struct mlx5_ifc_create_tir_in_bits {
2137         u8 opcode[0x10];
2138         u8 uid[0x10];
2139         u8 reserved_at_20[0x10];
2140         u8 op_mod[0x10];
2141         u8 reserved_at_40[0xc0];
2142         struct mlx5_ifc_tirc_bits ctx;
2143 };
2144
2145 enum {
2146         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_LRO = 1ULL << 0,
2147         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_INDIRECT_TABLE = 1ULL << 1,
2148         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_HASH = 1ULL << 2,
2149         /* bit 3 - tunneled_offload_en modify not supported. */
2150         MLX5_MODIFY_TIR_IN_MODIFY_BITMASK_SELF_LB_EN = 1ULL << 4,
2151 };
2152
2153 struct mlx5_ifc_modify_tir_out_bits {
2154         u8 status[0x8];
2155         u8 reserved_at_8[0x18];
2156         u8 syndrome[0x20];
2157         u8 reserved_at_40[0x40];
2158 };
2159
2160 struct mlx5_ifc_modify_tir_in_bits {
2161         u8 opcode[0x10];
2162         u8 uid[0x10];
2163         u8 reserved_at_20[0x10];
2164         u8 op_mod[0x10];
2165         u8 reserved_at_40[0x8];
2166         u8 tirn[0x18];
2167         u8 reserved_at_60[0x20];
2168         u8 modify_bitmask[0x40];
2169         u8 reserved_at_c0[0x40];
2170         struct mlx5_ifc_tirc_bits ctx;
2171 };
2172
2173 enum {
2174         MLX5_INLINE_Q_TYPE_RQ = 0x0,
2175         MLX5_INLINE_Q_TYPE_VIRTQ = 0x1,
2176 };
2177
2178 struct mlx5_ifc_rq_num_bits {
2179         u8 reserved_at_0[0x8];
2180         u8 rq_num[0x18];
2181 };
2182
2183 struct mlx5_ifc_rqtc_bits {
2184         u8 reserved_at_0[0xa5];
2185         u8 list_q_type[0x3];
2186         u8 reserved_at_a8[0x8];
2187         u8 rqt_max_size[0x10];
2188         u8 reserved_at_c0[0x10];
2189         u8 rqt_actual_size[0x10];
2190         u8 reserved_at_e0[0x6a0];
2191         struct mlx5_ifc_rq_num_bits rq_num[];
2192 };
2193
2194 struct mlx5_ifc_create_rqt_out_bits {
2195         u8 status[0x8];
2196         u8 reserved_at_8[0x18];
2197         u8 syndrome[0x20];
2198         u8 reserved_at_40[0x8];
2199         u8 rqtn[0x18];
2200         u8 reserved_at_60[0x20];
2201 };
2202
2203 #ifdef PEDANTIC
2204 #pragma GCC diagnostic ignored "-Wpedantic"
2205 #endif
2206 struct mlx5_ifc_create_rqt_in_bits {
2207         u8 opcode[0x10];
2208         u8 uid[0x10];
2209         u8 reserved_at_20[0x10];
2210         u8 op_mod[0x10];
2211         u8 reserved_at_40[0xc0];
2212         struct mlx5_ifc_rqtc_bits rqt_context;
2213 };
2214
2215 struct mlx5_ifc_modify_rqt_in_bits {
2216         u8 opcode[0x10];
2217         u8 uid[0x10];
2218         u8 reserved_at_20[0x10];
2219         u8 op_mod[0x10];
2220         u8 reserved_at_40[0x8];
2221         u8 rqtn[0x18];
2222         u8 reserved_at_60[0x20];
2223         u8 modify_bitmask[0x40];
2224         u8 reserved_at_c0[0x40];
2225         struct mlx5_ifc_rqtc_bits rqt_context;
2226 };
2227 #ifdef PEDANTIC
2228 #pragma GCC diagnostic error "-Wpedantic"
2229 #endif
2230
2231 struct mlx5_ifc_modify_rqt_out_bits {
2232         u8 status[0x8];
2233         u8 reserved_at_8[0x18];
2234         u8 syndrome[0x20];
2235         u8 reserved_at_40[0x40];
2236 };
2237
2238 enum {
2239         MLX5_SQC_STATE_RST  = 0x0,
2240         MLX5_SQC_STATE_RDY  = 0x1,
2241         MLX5_SQC_STATE_ERR  = 0x3,
2242 };
2243
2244 struct mlx5_ifc_sqc_bits {
2245         u8 rlky[0x1];
2246         u8 cd_master[0x1];
2247         u8 fre[0x1];
2248         u8 flush_in_error_en[0x1];
2249         u8 allow_multi_pkt_send_wqe[0x1];
2250         u8 min_wqe_inline_mode[0x3];
2251         u8 state[0x4];
2252         u8 reg_umr[0x1];
2253         u8 allow_swp[0x1];
2254         u8 hairpin[0x1];
2255         u8 non_wire[0x1];
2256         u8 static_sq_wq[0x1];
2257         u8 reserved_at_11[0x9];
2258         u8 ts_format[0x02];
2259         u8 reserved_at_1c[0x4];
2260         u8 reserved_at_20[0x8];
2261         u8 user_index[0x18];
2262         u8 reserved_at_40[0x8];
2263         u8 cqn[0x18];
2264         u8 reserved_at_60[0x8];
2265         u8 hairpin_peer_rq[0x18];
2266         u8 reserved_at_80[0x10];
2267         u8 hairpin_peer_vhca[0x10];
2268         u8 reserved_at_a0[0x50];
2269         u8 packet_pacing_rate_limit_index[0x10];
2270         u8 tis_lst_sz[0x10];
2271         u8 reserved_at_110[0x10];
2272         u8 reserved_at_120[0x40];
2273         u8 reserved_at_160[0x8];
2274         u8 tis_num_0[0x18];
2275         struct mlx5_ifc_wq_bits wq;
2276 };
2277
2278 struct mlx5_ifc_query_sq_in_bits {
2279         u8 opcode[0x10];
2280         u8 reserved_at_10[0x10];
2281         u8 reserved_at_20[0x10];
2282         u8 op_mod[0x10];
2283         u8 reserved_at_40[0x8];
2284         u8 sqn[0x18];
2285         u8 reserved_at_60[0x20];
2286 };
2287
2288 struct mlx5_ifc_modify_sq_out_bits {
2289         u8 status[0x8];
2290         u8 reserved_at_8[0x18];
2291         u8 syndrome[0x20];
2292         u8 reserved_at_40[0x40];
2293 };
2294
2295 struct mlx5_ifc_modify_sq_in_bits {
2296         u8 opcode[0x10];
2297         u8 uid[0x10];
2298         u8 reserved_at_20[0x10];
2299         u8 op_mod[0x10];
2300         u8 sq_state[0x4];
2301         u8 reserved_at_44[0x4];
2302         u8 sqn[0x18];
2303         u8 reserved_at_60[0x20];
2304         u8 modify_bitmask[0x40];
2305         u8 reserved_at_c0[0x40];
2306         struct mlx5_ifc_sqc_bits ctx;
2307 };
2308
2309 struct mlx5_ifc_create_sq_out_bits {
2310         u8 status[0x8];
2311         u8 reserved_at_8[0x18];
2312         u8 syndrome[0x20];
2313         u8 reserved_at_40[0x8];
2314         u8 sqn[0x18];
2315         u8 reserved_at_60[0x20];
2316 };
2317
2318 struct mlx5_ifc_create_sq_in_bits {
2319         u8 opcode[0x10];
2320         u8 uid[0x10];
2321         u8 reserved_at_20[0x10];
2322         u8 op_mod[0x10];
2323         u8 reserved_at_40[0xc0];
2324         struct mlx5_ifc_sqc_bits ctx;
2325 };
2326
2327 enum {
2328         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_ACTIVE = (1ULL << 0),
2329         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CBS = (1ULL << 1),
2330         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_CIR = (1ULL << 2),
2331         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EBS = (1ULL << 3),
2332         MLX5_FLOW_METER_OBJ_MODIFY_FIELD_EIR = (1ULL << 4),
2333 };
2334
2335 struct mlx5_ifc_flow_meter_parameters_bits {
2336         u8 valid[0x1];
2337         u8 bucket_overflow[0x1];
2338         u8 start_color[0x2];
2339         u8 both_buckets_on_green[0x1];
2340         u8 meter_mode[0x2];
2341         u8 reserved_at_1[0x19];
2342         u8 reserved_at_2[0x20];
2343         u8 reserved_at_3[0x3];
2344         u8 cbs_exponent[0x5];
2345         u8 cbs_mantissa[0x8];
2346         u8 reserved_at_4[0x3];
2347         u8 cir_exponent[0x5];
2348         u8 cir_mantissa[0x8];
2349         u8 reserved_at_5[0x20];
2350         u8 reserved_at_6[0x3];
2351         u8 ebs_exponent[0x5];
2352         u8 ebs_mantissa[0x8];
2353         u8 reserved_at_7[0x3];
2354         u8 eir_exponent[0x5];
2355         u8 eir_mantissa[0x8];
2356         u8 reserved_at_8[0x60];
2357 };
2358 #define MLX5_IFC_FLOW_METER_PARAM_MASK UINT64_C(0x80FFFFFF)
2359 #define MLX5_IFC_FLOW_METER_DISABLE_CBS_CIR_VAL 0x14BF00C8
2360
2361 enum {
2362         MLX5_CQE_SIZE_64B = 0x0,
2363         MLX5_CQE_SIZE_128B = 0x1,
2364 };
2365
2366 struct mlx5_ifc_cqc_bits {
2367         u8 status[0x4];
2368         u8 as_notify[0x1];
2369         u8 initiator_src_dct[0x1];
2370         u8 dbr_umem_valid[0x1];
2371         u8 reserved_at_7[0x1];
2372         u8 cqe_sz[0x3];
2373         u8 cc[0x1];
2374         u8 reserved_at_c[0x1];
2375         u8 scqe_break_moderation_en[0x1];
2376         u8 oi[0x1];
2377         u8 cq_period_mode[0x2];
2378         u8 cqe_comp_en[0x1];
2379         u8 mini_cqe_res_format[0x2];
2380         u8 st[0x4];
2381         u8 reserved_at_18[0x1];
2382         u8 cqe_comp_layout[0x7];
2383         u8 dbr_umem_id[0x20];
2384         u8 reserved_at_40[0x14];
2385         u8 page_offset[0x6];
2386         u8 reserved_at_5a[0x2];
2387         u8 mini_cqe_res_format_ext[0x2];
2388         u8 cq_timestamp_format[0x2];
2389         u8 reserved_at_60[0x3];
2390         u8 log_cq_size[0x5];
2391         u8 uar_page[0x18];
2392         u8 reserved_at_80[0x4];
2393         u8 cq_period[0xc];
2394         u8 cq_max_count[0x10];
2395         u8 reserved_at_a0[0x18];
2396         u8 c_eqn[0x8];
2397         u8 reserved_at_c0[0x3];
2398         u8 log_page_size[0x5];
2399         u8 reserved_at_c8[0x18];
2400         u8 reserved_at_e0[0x20];
2401         u8 reserved_at_100[0x8];
2402         u8 last_notified_index[0x18];
2403         u8 reserved_at_120[0x8];
2404         u8 last_solicit_index[0x18];
2405         u8 reserved_at_140[0x8];
2406         u8 consumer_counter[0x18];
2407         u8 reserved_at_160[0x8];
2408         u8 producer_counter[0x18];
2409         u8 local_partition_id[0xc];
2410         u8 process_id[0x14];
2411         u8 reserved_at_1A0[0x20];
2412         u8 dbr_addr[0x40];
2413 };
2414
2415 struct mlx5_ifc_health_buffer_bits {
2416         u8 reserved_0[0x100];
2417         u8 assert_existptr[0x20];
2418         u8 assert_callra[0x20];
2419         u8 reserved_1[0x40];
2420         u8 fw_version[0x20];
2421         u8 hw_id[0x20];
2422         u8 reserved_2[0x20];
2423         u8 irisc_index[0x8];
2424         u8 synd[0x8];
2425         u8 ext_synd[0x10];
2426 };
2427
2428 struct mlx5_ifc_initial_seg_bits {
2429         u8 fw_rev_minor[0x10];
2430         u8 fw_rev_major[0x10];
2431         u8 cmd_interface_rev[0x10];
2432         u8 fw_rev_subminor[0x10];
2433         u8 reserved_0[0x40];
2434         u8 cmdq_phy_addr_63_32[0x20];
2435         u8 cmdq_phy_addr_31_12[0x14];
2436         u8 reserved_1[0x2];
2437         u8 nic_interface[0x2];
2438         u8 log_cmdq_size[0x4];
2439         u8 log_cmdq_stride[0x4];
2440         u8 command_doorbell_vector[0x20];
2441         u8 reserved_2[0xf00];
2442         u8 initializing[0x1];
2443         u8 nic_interface_supported[0x7];
2444         u8 reserved_4[0x18];
2445         struct mlx5_ifc_health_buffer_bits health_buffer;
2446         u8 no_dram_nic_offset[0x20];
2447         u8 reserved_5[0x6de0];
2448         u8 internal_timer_h[0x20];
2449         u8 internal_timer_l[0x20];
2450         u8 reserved_6[0x20];
2451         u8 reserved_7[0x1f];
2452         u8 clear_int[0x1];
2453         u8 health_syndrome[0x8];
2454         u8 health_counter[0x18];
2455         u8 reserved_8[0x17fc0];
2456 };
2457
2458 struct mlx5_ifc_create_cq_out_bits {
2459         u8 status[0x8];
2460         u8 reserved_at_8[0x18];
2461         u8 syndrome[0x20];
2462         u8 reserved_at_40[0x8];
2463         u8 cqn[0x18];
2464         u8 reserved_at_60[0x20];
2465 };
2466
2467 struct mlx5_ifc_create_cq_in_bits {
2468         u8 opcode[0x10];
2469         u8 uid[0x10];
2470         u8 reserved_at_20[0x10];
2471         u8 op_mod[0x10];
2472         u8 reserved_at_40[0x40];
2473         struct mlx5_ifc_cqc_bits cq_context;
2474         u8 cq_umem_offset[0x40];
2475         u8 cq_umem_id[0x20];
2476         u8 cq_umem_valid[0x1];
2477         u8 reserved_at_2e1[0x1f];
2478         u8 reserved_at_300[0x580];
2479         u8 pas[];
2480 };
2481
2482 enum {
2483         MLX5_GENERAL_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b,
2484         MLX5_GENERAL_OBJ_TYPE_DEK = 0x000c,
2485         MLX5_GENERAL_OBJ_TYPE_VIRTQ = 0x000d,
2486         MLX5_GENERAL_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c,
2487         MLX5_GENERAL_OBJ_TYPE_IMPORT_KEK = 0x001d,
2488         MLX5_GENERAL_OBJ_TYPE_CREDENTIAL = 0x001e,
2489         MLX5_GENERAL_OBJ_TYPE_CRYPTO_LOGIN = 0x001f,
2490         MLX5_GENERAL_OBJ_TYPE_FLEX_PARSE_GRAPH = 0x0022,
2491         MLX5_GENERAL_OBJ_TYPE_FLOW_METER_ASO = 0x0024,
2492         MLX5_GENERAL_OBJ_TYPE_FLOW_HIT_ASO = 0x0025,
2493 };
2494
2495 struct mlx5_ifc_general_obj_in_cmd_hdr_bits {
2496         u8 opcode[0x10];
2497         u8 reserved_at_10[0x20];
2498         u8 obj_type[0x10];
2499         u8 obj_id[0x20];
2500         u8 reserved_at_60[0x3];
2501         u8 log_obj_range[0x5];
2502         u8 reserved_at_58[0x18];
2503 };
2504
2505 struct mlx5_ifc_general_obj_out_cmd_hdr_bits {
2506         u8 status[0x8];
2507         u8 reserved_at_8[0x18];
2508         u8 syndrome[0x20];
2509         u8 obj_id[0x20];
2510         u8 reserved_at_60[0x20];
2511 };
2512
2513 struct mlx5_ifc_virtio_q_counters_bits {
2514         u8 modify_field_select[0x40];
2515         u8 reserved_at_40[0x40];
2516         u8 received_desc[0x40];
2517         u8 completed_desc[0x40];
2518         u8 error_cqes[0x20];
2519         u8 bad_desc_errors[0x20];
2520         u8 exceed_max_chain[0x20];
2521         u8 invalid_buffer[0x20];
2522         u8 reserved_at_180[0x50];
2523 };
2524
2525 struct mlx5_ifc_geneve_tlv_option_bits {
2526         u8 modify_field_select[0x40];
2527         u8 reserved_at_40[0x18];
2528         u8 geneve_option_fte_index[0x8];
2529         u8 option_class[0x10];
2530         u8 option_type[0x8];
2531         u8 reserved_at_78[0x3];
2532         u8 option_data_length[0x5];
2533         u8 reserved_at_80[0x180];
2534 };
2535
2536 struct mlx5_ifc_create_virtio_q_counters_in_bits {
2537         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2538         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2539 };
2540
2541 struct mlx5_ifc_query_virtio_q_counters_out_bits {
2542         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2543         struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
2544 };
2545
2546 struct mlx5_ifc_create_geneve_tlv_option_in_bits {
2547         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2548         struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt;
2549 };
2550
2551 enum {
2552         MLX5_CRYPTO_KEY_SIZE_128b = 0x0,
2553         MLX5_CRYPTO_KEY_SIZE_256b = 0x1,
2554 };
2555
2556 enum {
2557         MLX5_CRYPTO_KEY_PURPOSE_TLS     = 0x1,
2558         MLX5_CRYPTO_KEY_PURPOSE_IPSEC   = 0x2,
2559         MLX5_CRYPTO_KEY_PURPOSE_AES_XTS = 0x3,
2560         MLX5_CRYPTO_KEY_PURPOSE_MACSEC  = 0x4,
2561         MLX5_CRYPTO_KEY_PURPOSE_GCM     = 0x5,
2562         MLX5_CRYPTO_KEY_PURPOSE_PSP     = 0x6,
2563 };
2564
2565 struct mlx5_ifc_dek_bits {
2566         u8 modify_field_select[0x40];
2567         u8 state[0x8];
2568         u8 reserved_at_48[0xc];
2569         u8 key_size[0x4];
2570         u8 has_keytag[0x1];
2571         u8 reserved_at_59[0x3];
2572         u8 key_purpose[0x4];
2573         u8 reserved_at_60[0x8];
2574         u8 pd[0x18];
2575         u8 reserved_at_80[0x100];
2576         u8 opaque[0x40];
2577         u8 reserved_at_1c0[0x40];
2578         u8 key[0x400];
2579         u8 reserved_at_600[0x200];
2580 };
2581
2582 struct mlx5_ifc_create_dek_in_bits {
2583         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2584         struct mlx5_ifc_dek_bits dek;
2585 };
2586
2587 struct mlx5_ifc_import_kek_bits {
2588         u8 modify_field_select[0x40];
2589         u8 state[0x8];
2590         u8 reserved_at_48[0xc];
2591         u8 key_size[0x4];
2592         u8 reserved_at_58[0x1a8];
2593         u8 key[0x400];
2594         u8 reserved_at_600[0x200];
2595 };
2596
2597 struct mlx5_ifc_create_import_kek_in_bits {
2598         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2599         struct mlx5_ifc_import_kek_bits import_kek;
2600 };
2601
2602 enum {
2603         MLX5_CREDENTIAL_ROLE_OFFICER = 0x0,
2604         MLX5_CREDENTIAL_ROLE_USER = 0x1,
2605 };
2606
2607 struct mlx5_ifc_credential_bits {
2608         u8 modify_field_select[0x40];
2609         u8 state[0x8];
2610         u8 reserved_at_48[0x10];
2611         u8 credential_role[0x8];
2612         u8 reserved_at_60[0x1a0];
2613         u8 credential[0x180];
2614         u8 reserved_at_380[0x480];
2615 };
2616
2617 struct mlx5_ifc_create_credential_in_bits {
2618         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2619         struct mlx5_ifc_credential_bits credential;
2620 };
2621
2622 struct mlx5_ifc_crypto_login_bits {
2623         u8 modify_field_select[0x40];
2624         u8 reserved_at_40[0x48];
2625         u8 credential_pointer[0x18];
2626         u8 reserved_at_a0[0x8];
2627         u8 session_import_kek_ptr[0x18];
2628         u8 reserved_at_c0[0x140];
2629         u8 credential[0x180];
2630         u8 reserved_at_380[0x480];
2631 };
2632
2633 struct mlx5_ifc_create_crypto_login_in_bits {
2634         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2635         struct mlx5_ifc_crypto_login_bits crypto_login;
2636 };
2637
2638 enum {
2639         MLX5_VIRTQ_STATE_INIT = 0,
2640         MLX5_VIRTQ_STATE_RDY = 1,
2641         MLX5_VIRTQ_STATE_SUSPEND = 2,
2642         MLX5_VIRTQ_STATE_ERROR = 3,
2643 };
2644
2645 enum {
2646         MLX5_VIRTQ_MODIFY_TYPE_STATE = (1UL << 0),
2647         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS = (1UL << 3),
2648         MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_DUMP_ENABLE = (1UL << 4),
2649 };
2650
2651 struct mlx5_ifc_virtio_q_bits {
2652         u8 virtio_q_type[0x8];
2653         u8 reserved_at_8[0x5];
2654         u8 event_mode[0x3];
2655         u8 queue_index[0x10];
2656         u8 full_emulation[0x1];
2657         u8 virtio_version_1_0[0x1];
2658         u8 reserved_at_22[0x2];
2659         u8 offload_type[0x4];
2660         u8 event_qpn_or_msix[0x18];
2661         u8 doorbell_stride_idx[0x10];
2662         u8 queue_size[0x10];
2663         u8 device_emulation_id[0x20];
2664         u8 desc_addr[0x40];
2665         u8 used_addr[0x40];
2666         u8 available_addr[0x40];
2667         u8 virtio_q_mkey[0x20];
2668         u8 reserved_at_160[0x18];
2669         u8 error_type[0x8];
2670         u8 umem_1_id[0x20];
2671         u8 umem_1_size[0x20];
2672         u8 umem_1_offset[0x40];
2673         u8 umem_2_id[0x20];
2674         u8 umem_2_size[0x20];
2675         u8 umem_2_offset[0x40];
2676         u8 umem_3_id[0x20];
2677         u8 umem_3_size[0x20];
2678         u8 umem_3_offset[0x40];
2679         u8 counter_set_id[0x20];
2680         u8 reserved_at_320[0x8];
2681         u8 pd[0x18];
2682         u8 reserved_at_340[0x2];
2683         u8 queue_period_mode[0x2];
2684         u8 queue_period_us[0xc];
2685         u8 queue_max_count[0x10];
2686         u8 reserved_at_360[0xa0];
2687 };
2688
2689 struct mlx5_ifc_virtio_net_q_bits {
2690         u8 modify_field_select[0x40];
2691         u8 reserved_at_40[0x40];
2692         u8 tso_ipv4[0x1];
2693         u8 tso_ipv6[0x1];
2694         u8 tx_csum[0x1];
2695         u8 rx_csum[0x1];
2696         u8 reserved_at_84[0x6];
2697         u8 dirty_bitmap_dump_enable[0x1];
2698         u8 vhost_log_page[0x5];
2699         u8 reserved_at_90[0xc];
2700         u8 state[0x4];
2701         u8 reserved_at_a0[0x8];
2702         u8 tisn_or_qpn[0x18];
2703         u8 dirty_bitmap_mkey[0x20];
2704         u8 dirty_bitmap_size[0x20];
2705         u8 dirty_bitmap_addr[0x40];
2706         u8 hw_available_index[0x10];
2707         u8 hw_used_index[0x10];
2708         u8 reserved_at_160[0xa0];
2709         struct mlx5_ifc_virtio_q_bits virtio_q_context;
2710 };
2711
2712 struct mlx5_ifc_create_virtq_in_bits {
2713         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2714         struct mlx5_ifc_virtio_net_q_bits virtq;
2715 };
2716
2717 struct mlx5_ifc_query_virtq_out_bits {
2718         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2719         struct mlx5_ifc_virtio_net_q_bits virtq;
2720 };
2721
2722 struct mlx5_ifc_flow_hit_aso_bits {
2723         u8 modify_field_select[0x40];
2724         u8 reserved_at_40[0x48];
2725         u8 access_pd[0x18];
2726         u8 reserved_at_a0[0x160];
2727         u8 flag[0x200];
2728 };
2729
2730 struct mlx5_ifc_create_flow_hit_aso_in_bits {
2731         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2732         struct mlx5_ifc_flow_hit_aso_bits flow_hit_aso;
2733 };
2734
2735 struct mlx5_ifc_flow_meter_aso_bits {
2736         u8 modify_field_select[0x40];
2737         u8 reserved_at_40[0x48];
2738         u8 access_pd[0x18];
2739         u8 reserved_at_a0[0x160];
2740         u8 parameters[0x200];
2741 };
2742
2743 struct mlx5_ifc_create_flow_meter_aso_in_bits {
2744         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
2745         struct mlx5_ifc_flow_meter_aso_bits flow_meter_aso;
2746 };
2747 enum mlx5_access_aso_opc_mod {
2748         ASO_OPC_MOD_IPSEC = 0x0,
2749         ASO_OPC_MOD_CONNECTION_TRACKING = 0x1,
2750         ASO_OPC_MOD_POLICER = 0x2,
2751         ASO_OPC_MOD_RACE_AVOIDANCE = 0x3,
2752         ASO_OPC_MOD_FLOW_HIT = 0x4,
2753 };
2754
2755 #define ASO_CSEG_DATA_MASK_MODE_OFFSET  30
2756
2757 enum mlx5_aso_data_mask_mode {
2758         BITWISE_64BIT = 0x0,
2759         BYTEWISE_64BYTE = 0x1,
2760         CALCULATED_64BYTE = 0x2,
2761 };
2762
2763 #define ASO_CSEG_COND_0_OPER_OFFSET     20
2764 #define ASO_CSEG_COND_1_OPER_OFFSET     16
2765
2766 enum mlx5_aso_pre_cond_op {
2767         ASO_OP_ALWAYS_FALSE = 0x0,
2768         ASO_OP_ALWAYS_TRUE = 0x1,
2769         ASO_OP_EQUAL = 0x2,
2770         ASO_OP_NOT_EQUAL = 0x3,
2771         ASO_OP_GREATER_OR_EQUAL = 0x4,
2772         ASO_OP_LESSER_OR_EQUAL = 0x5,
2773         ASO_OP_LESSER = 0x6,
2774         ASO_OP_GREATER = 0x7,
2775         ASO_OP_CYCLIC_GREATER = 0x8,
2776         ASO_OP_CYCLIC_LESSER = 0x9,
2777 };
2778
2779 #define ASO_CSEG_COND_OPER_OFFSET       6
2780
2781 enum mlx5_aso_op {
2782         ASO_OPER_LOGICAL_AND = 0x0,
2783         ASO_OPER_LOGICAL_OR = 0x1,
2784 };
2785
2786 /* ASO WQE CTRL segment. */
2787 struct mlx5_aso_cseg {
2788         uint32_t va_h;
2789         uint32_t va_l_r;
2790         uint32_t lkey;
2791         uint32_t operand_masks;
2792         uint32_t condition_0_data;
2793         uint32_t condition_0_mask;
2794         uint32_t condition_1_data;
2795         uint32_t condition_1_mask;
2796         uint64_t bitwise_data;
2797         uint64_t data_mask;
2798 } __rte_packed;
2799
2800 /* A meter data segment - 2 per ASO WQE. */
2801 struct mlx5_aso_mtr_dseg {
2802         uint32_t v_bo_sc_bbog_mm;
2803         /*
2804          * bit 31: valid, 30: bucket overflow, 28-29: start color,
2805          * 27: both buckets on green, 24-25: meter mode.
2806          */
2807         uint32_t reserved;
2808         uint32_t cbs_cir;
2809         /*
2810          * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa,
2811          * bit 8-12: cir_exponent, bit 0-7 cir_mantissa.
2812          */
2813         uint32_t c_tokens;
2814         uint32_t ebs_eir;
2815         /*
2816          * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa,
2817          * bit 8-12: eir_exponent, bit 0-7 eir_mantissa.
2818          */
2819         uint32_t e_tokens;
2820         uint64_t timestamp;
2821 } __rte_packed;
2822
2823 #define ASO_DSEG_VALID_OFFSET 31
2824 #define ASO_DSEG_BO_OFFSET 30
2825 #define ASO_DSEG_SC_OFFSET 28
2826 #define ASO_DSEG_CBS_EXP_OFFSET 24
2827 #define ASO_DSEG_CBS_MAN_OFFSET 16
2828 #define ASO_DSEG_CIR_EXP_MASK 0x1F
2829 #define ASO_DSEG_CIR_EXP_OFFSET 8
2830 #define ASO_DSEG_EBS_EXP_OFFSET 24
2831 #define ASO_DSEG_EBS_MAN_OFFSET 16
2832 #define ASO_DSEG_EXP_MASK 0x1F
2833 #define ASO_DSEG_MAN_MASK 0xFF
2834
2835 #define MLX5_ASO_WQE_DSEG_SIZE  0x40
2836 #define MLX5_ASO_METERS_PER_WQE 2
2837 #define MLX5_ASO_MTRS_PER_POOL 128
2838
2839 /* ASO WQE data segment. */
2840 struct mlx5_aso_dseg {
2841         union {
2842                 uint8_t data[MLX5_ASO_WQE_DSEG_SIZE];
2843                 struct mlx5_aso_mtr_dseg mtrs[MLX5_ASO_METERS_PER_WQE];
2844         };
2845 } __rte_packed;
2846
2847 /* ASO WQE. */
2848 struct mlx5_aso_wqe {
2849         struct mlx5_wqe_cseg general_cseg;
2850         struct mlx5_aso_cseg aso_cseg;
2851         struct mlx5_aso_dseg aso_dseg;
2852 } __rte_packed;
2853
2854 enum {
2855         MLX5_EVENT_TYPE_OBJECT_CHANGE = 0x27,
2856 };
2857
2858 enum {
2859         MLX5_QP_ST_RC = 0x0,
2860 };
2861
2862 enum {
2863         MLX5_QP_PM_MIGRATED = 0x3,
2864 };
2865
2866 enum {
2867         MLX5_NON_ZERO_RQ = 0x0,
2868         MLX5_SRQ_RQ = 0x1,
2869         MLX5_CRQ_RQ = 0x2,
2870         MLX5_ZERO_LEN_RQ = 0x3,
2871 };
2872
2873 struct mlx5_ifc_ads_bits {
2874         u8 fl[0x1];
2875         u8 free_ar[0x1];
2876         u8 reserved_at_2[0xe];
2877         u8 pkey_index[0x10];
2878         u8 reserved_at_20[0x8];
2879         u8 grh[0x1];
2880         u8 mlid[0x7];
2881         u8 rlid[0x10];
2882         u8 ack_timeout[0x5];
2883         u8 reserved_at_45[0x3];
2884         u8 src_addr_index[0x8];
2885         u8 reserved_at_50[0x4];
2886         u8 stat_rate[0x4];
2887         u8 hop_limit[0x8];
2888         u8 reserved_at_60[0x4];
2889         u8 tclass[0x8];
2890         u8 flow_label[0x14];
2891         u8 rgid_rip[16][0x8];
2892         u8 reserved_at_100[0x4];
2893         u8 f_dscp[0x1];
2894         u8 f_ecn[0x1];
2895         u8 reserved_at_106[0x1];
2896         u8 f_eth_prio[0x1];
2897         u8 ecn[0x2];
2898         u8 dscp[0x6];
2899         u8 udp_sport[0x10];
2900         u8 dei_cfi[0x1];
2901         u8 eth_prio[0x3];
2902         u8 sl[0x4];
2903         u8 vhca_port_num[0x8];
2904         u8 rmac_47_32[0x10];
2905         u8 rmac_31_0[0x20];
2906 };
2907
2908 struct mlx5_ifc_qpc_bits {
2909         u8 state[0x4];
2910         u8 lag_tx_port_affinity[0x4];
2911         u8 st[0x8];
2912         u8 reserved_at_10[0x3];
2913         u8 pm_state[0x2];
2914         u8 reserved_at_15[0x1];
2915         u8 req_e2e_credit_mode[0x2];
2916         u8 offload_type[0x4];
2917         u8 end_padding_mode[0x2];
2918         u8 reserved_at_1e[0x2];
2919         u8 wq_signature[0x1];
2920         u8 block_lb_mc[0x1];
2921         u8 atomic_like_write_en[0x1];
2922         u8 latency_sensitive[0x1];
2923         u8 reserved_at_24[0x1];
2924         u8 drain_sigerr[0x1];
2925         u8 reserved_at_26[0x2];
2926         u8 pd[0x18];
2927         u8 mtu[0x3];
2928         u8 log_msg_max[0x5];
2929         u8 reserved_at_48[0x1];
2930         u8 log_rq_size[0x4];
2931         u8 log_rq_stride[0x3];
2932         u8 no_sq[0x1];
2933         u8 log_sq_size[0x4];
2934         u8 reserved_at_55[0x3];
2935         u8 ts_format[0x2];
2936         u8 reserved_at_5a[0x1];
2937         u8 rlky[0x1];
2938         u8 ulp_stateless_offload_mode[0x4];
2939         u8 counter_set_id[0x8];
2940         u8 uar_page[0x18];
2941         u8 reserved_at_80[0x8];
2942         u8 user_index[0x18];
2943         u8 reserved_at_a0[0x3];
2944         u8 log_page_size[0x5];
2945         u8 remote_qpn[0x18];
2946         struct mlx5_ifc_ads_bits primary_address_path;
2947         struct mlx5_ifc_ads_bits secondary_address_path;
2948         u8 log_ack_req_freq[0x4];
2949         u8 reserved_at_384[0x4];
2950         u8 log_sra_max[0x3];
2951         u8 reserved_at_38b[0x2];
2952         u8 retry_count[0x3];
2953         u8 rnr_retry[0x3];
2954         u8 reserved_at_393[0x1];
2955         u8 fre[0x1];
2956         u8 cur_rnr_retry[0x3];
2957         u8 cur_retry_count[0x3];
2958         u8 reserved_at_39b[0x5];
2959         u8 reserved_at_3a0[0x20];
2960         u8 reserved_at_3c0[0x8];
2961         u8 next_send_psn[0x18];
2962         u8 reserved_at_3e0[0x8];
2963         u8 cqn_snd[0x18];
2964         u8 reserved_at_400[0x8];
2965         u8 deth_sqpn[0x18];
2966         u8 reserved_at_420[0x20];
2967         u8 reserved_at_440[0x8];
2968         u8 last_acked_psn[0x18];
2969         u8 reserved_at_460[0x8];
2970         u8 ssn[0x18];
2971         u8 reserved_at_480[0x8];
2972         u8 log_rra_max[0x3];
2973         u8 reserved_at_48b[0x1];
2974         u8 atomic_mode[0x4];
2975         u8 rre[0x1];
2976         u8 rwe[0x1];
2977         u8 rae[0x1];
2978         u8 reserved_at_493[0x1];
2979         u8 page_offset[0x6];
2980         u8 reserved_at_49a[0x3];
2981         u8 cd_slave_receive[0x1];
2982         u8 cd_slave_send[0x1];
2983         u8 cd_master[0x1];
2984         u8 reserved_at_4a0[0x3];
2985         u8 min_rnr_nak[0x5];
2986         u8 next_rcv_psn[0x18];
2987         u8 reserved_at_4c0[0x8];
2988         u8 xrcd[0x18];
2989         u8 reserved_at_4e0[0x8];
2990         u8 cqn_rcv[0x18];
2991         u8 dbr_addr[0x40];
2992         u8 q_key[0x20];
2993         u8 reserved_at_560[0x5];
2994         u8 rq_type[0x3];
2995         u8 srqn_rmpn_xrqn[0x18];
2996         u8 reserved_at_580[0x8];
2997         u8 rmsn[0x18];
2998         u8 hw_sq_wqebb_counter[0x10];
2999         u8 sw_sq_wqebb_counter[0x10];
3000         u8 hw_rq_counter[0x20];
3001         u8 sw_rq_counter[0x20];
3002         u8 reserved_at_600[0x20];
3003         u8 reserved_at_620[0xf];
3004         u8 cgs[0x1];
3005         u8 cs_req[0x8];
3006         u8 cs_res[0x8];
3007         u8 dc_access_key[0x40];
3008         u8 reserved_at_680[0x3];
3009         u8 dbr_umem_valid[0x1];
3010         u8 reserved_at_684[0x9c];
3011         u8 dbr_umem_id[0x20];
3012 };
3013
3014 struct mlx5_ifc_create_qp_out_bits {
3015         u8 status[0x8];
3016         u8 reserved_at_8[0x18];
3017         u8 syndrome[0x20];
3018         u8 reserved_at_40[0x8];
3019         u8 qpn[0x18];
3020         u8 reserved_at_60[0x20];
3021 };
3022
3023 #ifdef PEDANTIC
3024 #pragma GCC diagnostic ignored "-Wpedantic"
3025 #endif
3026 struct mlx5_ifc_create_qp_in_bits {
3027         u8 opcode[0x10];
3028         u8 uid[0x10];
3029         u8 reserved_at_20[0x10];
3030         u8 op_mod[0x10];
3031         u8 reserved_at_40[0x40];
3032         u8 opt_param_mask[0x20];
3033         u8 reserved_at_a0[0x20];
3034         struct mlx5_ifc_qpc_bits qpc;
3035         u8 wq_umem_offset[0x40];
3036         u8 wq_umem_id[0x20];
3037         u8 wq_umem_valid[0x1];
3038         u8 reserved_at_861[0x1f];
3039         u8 pas[0][0x40];
3040 };
3041 #ifdef PEDANTIC
3042 #pragma GCC diagnostic error "-Wpedantic"
3043 #endif
3044
3045 struct mlx5_ifc_sqerr2rts_qp_out_bits {
3046         u8 status[0x8];
3047         u8 reserved_at_8[0x18];
3048         u8 syndrome[0x20];
3049         u8 reserved_at_40[0x40];
3050 };
3051
3052 struct mlx5_ifc_sqerr2rts_qp_in_bits {
3053         u8 opcode[0x10];
3054         u8 uid[0x10];
3055         u8 reserved_at_20[0x10];
3056         u8 op_mod[0x10];
3057         u8 reserved_at_40[0x8];
3058         u8 qpn[0x18];
3059         u8 reserved_at_60[0x20];
3060         u8 opt_param_mask[0x20];
3061         u8 reserved_at_a0[0x20];
3062         struct mlx5_ifc_qpc_bits qpc;
3063         u8 reserved_at_800[0x80];
3064 };
3065
3066 struct mlx5_ifc_sqd2rts_qp_out_bits {
3067         u8 status[0x8];
3068         u8 reserved_at_8[0x18];
3069         u8 syndrome[0x20];
3070         u8 reserved_at_40[0x40];
3071 };
3072
3073 struct mlx5_ifc_sqd2rts_qp_in_bits {
3074         u8 opcode[0x10];
3075         u8 uid[0x10];
3076         u8 reserved_at_20[0x10];
3077         u8 op_mod[0x10];
3078         u8 reserved_at_40[0x8];
3079         u8 qpn[0x18];
3080         u8 reserved_at_60[0x20];
3081         u8 opt_param_mask[0x20];
3082         u8 reserved_at_a0[0x20];
3083         struct mlx5_ifc_qpc_bits qpc;
3084         u8 reserved_at_800[0x80];
3085 };
3086
3087 struct mlx5_ifc_rts2rts_qp_out_bits {
3088         u8 status[0x8];
3089         u8 reserved_at_8[0x18];
3090         u8 syndrome[0x20];
3091         u8 reserved_at_40[0x40];
3092 };
3093
3094 struct mlx5_ifc_rts2rts_qp_in_bits {
3095         u8 opcode[0x10];
3096         u8 uid[0x10];
3097         u8 reserved_at_20[0x10];
3098         u8 op_mod[0x10];
3099         u8 reserved_at_40[0x8];
3100         u8 qpn[0x18];
3101         u8 reserved_at_60[0x20];
3102         u8 opt_param_mask[0x20];
3103         u8 reserved_at_a0[0x20];
3104         struct mlx5_ifc_qpc_bits qpc;
3105         u8 reserved_at_800[0x80];
3106 };
3107
3108 struct mlx5_ifc_rtr2rts_qp_out_bits {
3109         u8 status[0x8];
3110         u8 reserved_at_8[0x18];
3111         u8 syndrome[0x20];
3112         u8 reserved_at_40[0x40];
3113 };
3114
3115 struct mlx5_ifc_rtr2rts_qp_in_bits {
3116         u8 opcode[0x10];
3117         u8 uid[0x10];
3118         u8 reserved_at_20[0x10];
3119         u8 op_mod[0x10];
3120         u8 reserved_at_40[0x8];
3121         u8 qpn[0x18];
3122         u8 reserved_at_60[0x20];
3123         u8 opt_param_mask[0x20];
3124         u8 reserved_at_a0[0x20];
3125         struct mlx5_ifc_qpc_bits qpc;
3126         u8 reserved_at_800[0x80];
3127 };
3128
3129 struct mlx5_ifc_rst2init_qp_out_bits {
3130         u8 status[0x8];
3131         u8 reserved_at_8[0x18];
3132         u8 syndrome[0x20];
3133         u8 reserved_at_40[0x40];
3134 };
3135
3136 struct mlx5_ifc_rst2init_qp_in_bits {
3137         u8 opcode[0x10];
3138         u8 uid[0x10];
3139         u8 reserved_at_20[0x10];
3140         u8 op_mod[0x10];
3141         u8 reserved_at_40[0x8];
3142         u8 qpn[0x18];
3143         u8 reserved_at_60[0x20];
3144         u8 opt_param_mask[0x20];
3145         u8 reserved_at_a0[0x20];
3146         struct mlx5_ifc_qpc_bits qpc;
3147         u8 reserved_at_800[0x80];
3148 };
3149
3150 struct mlx5_ifc_init2rtr_qp_out_bits {
3151         u8 status[0x8];
3152         u8 reserved_at_8[0x18];
3153         u8 syndrome[0x20];
3154         u8 reserved_at_40[0x40];
3155 };
3156
3157 struct mlx5_ifc_init2rtr_qp_in_bits {
3158         u8 opcode[0x10];
3159         u8 uid[0x10];
3160         u8 reserved_at_20[0x10];
3161         u8 op_mod[0x10];
3162         u8 reserved_at_40[0x8];
3163         u8 qpn[0x18];
3164         u8 reserved_at_60[0x20];
3165         u8 opt_param_mask[0x20];
3166         u8 reserved_at_a0[0x20];
3167         struct mlx5_ifc_qpc_bits qpc;
3168         u8 reserved_at_800[0x80];
3169 };
3170
3171 struct mlx5_ifc_init2init_qp_out_bits {
3172         u8 status[0x8];
3173         u8 reserved_at_8[0x18];
3174         u8 syndrome[0x20];
3175         u8 reserved_at_40[0x40];
3176 };
3177
3178 struct mlx5_ifc_init2init_qp_in_bits {
3179         u8 opcode[0x10];
3180         u8 uid[0x10];
3181         u8 reserved_at_20[0x10];
3182         u8 op_mod[0x10];
3183         u8 reserved_at_40[0x8];
3184         u8 qpn[0x18];
3185         u8 reserved_at_60[0x20];
3186         u8 opt_param_mask[0x20];
3187         u8 reserved_at_a0[0x20];
3188         struct mlx5_ifc_qpc_bits qpc;
3189         u8 reserved_at_800[0x80];
3190 };
3191
3192 struct mlx5_ifc_dealloc_pd_out_bits {
3193         u8 status[0x8];
3194         u8 reserved_0[0x18];
3195         u8 syndrome[0x20];
3196         u8 reserved_1[0x40];
3197 };
3198
3199 struct mlx5_ifc_dealloc_pd_in_bits {
3200         u8 opcode[0x10];
3201         u8 reserved_0[0x10];
3202         u8 reserved_1[0x10];
3203         u8 op_mod[0x10];
3204         u8 reserved_2[0x8];
3205         u8 pd[0x18];
3206         u8 reserved_3[0x20];
3207 };
3208
3209 struct mlx5_ifc_alloc_pd_out_bits {
3210         u8 status[0x8];
3211         u8 reserved_0[0x18];
3212         u8 syndrome[0x20];
3213         u8 reserved_1[0x8];
3214         u8 pd[0x18];
3215         u8 reserved_2[0x20];
3216 };
3217
3218 struct mlx5_ifc_alloc_pd_in_bits {
3219         u8 opcode[0x10];
3220         u8 reserved_0[0x10];
3221         u8 reserved_1[0x10];
3222         u8 op_mod[0x10];
3223         u8 reserved_2[0x40];
3224 };
3225
3226 #ifdef PEDANTIC
3227 #pragma GCC diagnostic ignored "-Wpedantic"
3228 #endif
3229 struct mlx5_ifc_query_qp_out_bits {
3230         u8 status[0x8];
3231         u8 reserved_at_8[0x18];
3232         u8 syndrome[0x20];
3233         u8 reserved_at_40[0x40];
3234         u8 opt_param_mask[0x20];
3235         u8 reserved_at_a0[0x20];
3236         struct mlx5_ifc_qpc_bits qpc;
3237         u8 reserved_at_800[0x80];
3238         u8 pas[0][0x40];
3239 };
3240 #ifdef PEDANTIC
3241 #pragma GCC diagnostic error "-Wpedantic"
3242 #endif
3243
3244 struct mlx5_ifc_query_qp_in_bits {
3245         u8 opcode[0x10];
3246         u8 reserved_at_10[0x10];
3247         u8 reserved_at_20[0x10];
3248         u8 op_mod[0x10];
3249         u8 reserved_at_40[0x8];
3250         u8 qpn[0x18];
3251         u8 reserved_at_60[0x20];
3252 };
3253
3254 enum {
3255         MLX5_DATA_RATE = 0x0,
3256         MLX5_WQE_RATE = 0x1,
3257 };
3258
3259 struct mlx5_ifc_set_pp_rate_limit_context_bits {
3260         u8 rate_limit[0x20];
3261         u8 burst_upper_bound[0x20];
3262         u8 reserved_at_40[0xC];
3263         u8 rate_mode[0x4];
3264         u8 typical_packet_size[0x10];
3265         u8 reserved_at_60[0x120];
3266 };
3267
3268 #define MLX5_ACCESS_REGISTER_DATA_DWORD_MAX 8u
3269
3270 #ifdef PEDANTIC
3271 #pragma GCC diagnostic ignored "-Wpedantic"
3272 #endif
3273 struct mlx5_ifc_access_register_out_bits {
3274         u8 status[0x8];
3275         u8 reserved_at_8[0x18];
3276         u8 syndrome[0x20];
3277         u8 reserved_at_40[0x40];
3278         u8 register_data[0][0x20];
3279 };
3280
3281 struct mlx5_ifc_access_register_in_bits {
3282         u8 opcode[0x10];
3283         u8 reserved_at_10[0x10];
3284         u8 reserved_at_20[0x10];
3285         u8 op_mod[0x10];
3286         u8 reserved_at_40[0x10];
3287         u8 register_id[0x10];
3288         u8 argument[0x20];
3289         u8 register_data[0][0x20];
3290 };
3291 #ifdef PEDANTIC
3292 #pragma GCC diagnostic error "-Wpedantic"
3293 #endif
3294
3295 enum {
3296         MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE  = 0x0,
3297         MLX5_ACCESS_REGISTER_IN_OP_MOD_READ   = 0x1,
3298 };
3299
3300 enum {
3301         MLX5_REGISTER_ID_MTUTC  = 0x9055,
3302         MLX5_CRYPTO_OPERATIONAL_REGISTER_ID = 0xC002,
3303         MLX5_CRYPTO_COMMISSIONING_REGISTER_ID = 0xC003,
3304         MLX5_IMPORT_KEK_HANDLE_REGISTER_ID = 0xC004,
3305         MLX5_CREDENTIAL_HANDLE_REGISTER_ID = 0xC005,
3306 };
3307
3308 struct mlx5_ifc_register_mtutc_bits {
3309         u8 time_stamp_mode[0x2];
3310         u8 time_stamp_state[0x2];
3311         u8 reserved_at_4[0x18];
3312         u8 operation[0x4];
3313         u8 freq_adjustment[0x20];
3314         u8 reserved_at_40[0x40];
3315         u8 utc_sec[0x20];
3316         u8 utc_nsec[0x20];
3317         u8 time_adjustment[0x20];
3318 };
3319
3320 #define MLX5_MTUTC_TIMESTAMP_MODE_INTERNAL_TIMER 0
3321 #define MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME 1
3322
3323 struct mlx5_ifc_crypto_operational_register_bits {
3324         u8 wrapped_crypto_operational[0x1];
3325         u8 reserved_at_1[0x1b];
3326         u8 kek_size[0x4];
3327         u8 reserved_at_20[0x20];
3328         u8 credential[0x140];
3329         u8 kek[0x100];
3330         u8 reserved_at_280[0x180];
3331 };
3332
3333 struct mlx5_ifc_crypto_commissioning_register_bits {
3334         u8 token[0x1]; /* TODO: add size after PRM update */
3335 };
3336
3337 struct mlx5_ifc_import_kek_handle_register_bits {
3338         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3339         struct mlx5_ifc_import_kek_bits import_kek_object;
3340         u8 reserved_at_200[0x4];
3341         u8 write_operation[0x4];
3342         u8 import_kek_id[0x18];
3343         u8 reserved_at_220[0xe0];
3344 };
3345
3346 struct mlx5_ifc_credential_handle_register_bits {
3347         struct mlx5_ifc_crypto_login_bits crypto_login_object;
3348         struct mlx5_ifc_credential_bits credential_object;
3349         u8 reserved_at_200[0x4];
3350         u8 write_operation[0x4];
3351         u8 credential_id[0x18];
3352         u8 reserved_at_220[0xe0];
3353 };
3354
3355 enum {
3356         MLX5_REGISTER_ADD_OPERATION = 0x1,
3357         MLX5_REGISTER_DELETE_OPERATION = 0x2,
3358 };
3359
3360 struct mlx5_ifc_parse_graph_arc_bits {
3361         u8 start_inner_tunnel[0x1];
3362         u8 reserved_at_1[0x7];
3363         u8 arc_parse_graph_node[0x8];
3364         u8 compare_condition_value[0x10];
3365         u8 parse_graph_node_handle[0x20];
3366         u8 reserved_at_40[0x40];
3367 };
3368
3369 struct mlx5_ifc_parse_graph_flow_match_sample_bits {
3370         u8 flow_match_sample_en[0x1];
3371         u8 reserved_at_1[0x3];
3372         u8 flow_match_sample_offset_mode[0x4];
3373         u8 reserved_at_5[0x8];
3374         u8 flow_match_sample_field_offset[0x10];
3375         u8 reserved_at_32[0x4];
3376         u8 flow_match_sample_field_offset_shift[0x4];
3377         u8 flow_match_sample_field_base_offset[0x8];
3378         u8 reserved_at_48[0xd];
3379         u8 flow_match_sample_tunnel_mode[0x3];
3380         u8 flow_match_sample_field_offset_mask[0x20];
3381         u8 flow_match_sample_field_id[0x20];
3382 };
3383
3384 struct mlx5_ifc_parse_graph_flex_bits {
3385         u8 modify_field_select[0x40];
3386         u8 reserved_at_64[0x20];
3387         u8 header_length_base_value[0x10];
3388         u8 reserved_at_112[0x4];
3389         u8 header_length_field_shift[0x4];
3390         u8 reserved_at_120[0x4];
3391         u8 header_length_mode[0x4];
3392         u8 header_length_field_offset[0x10];
3393         u8 next_header_field_offset[0x10];
3394         u8 reserved_at_160[0x1b];
3395         u8 next_header_field_size[0x5];
3396         u8 header_length_field_mask[0x20];
3397         u8 reserved_at_224[0x20];
3398         struct mlx5_ifc_parse_graph_flow_match_sample_bits sample_table[0x8];
3399         struct mlx5_ifc_parse_graph_arc_bits input_arc[0x8];
3400         struct mlx5_ifc_parse_graph_arc_bits output_arc[0x8];
3401 };
3402
3403 struct mlx5_ifc_create_flex_parser_in_bits {
3404         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3405         struct mlx5_ifc_parse_graph_flex_bits flex;
3406 };
3407
3408 struct mlx5_ifc_create_flex_parser_out_bits {
3409         struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
3410         struct mlx5_ifc_parse_graph_flex_bits flex;
3411 };
3412
3413 struct mlx5_ifc_parse_graph_flex_out_bits {
3414         u8 status[0x8];
3415         u8 reserved_at_8[0x18];
3416         u8 syndrome[0x20];
3417         u8 reserved_at_40[0x40];
3418         struct mlx5_ifc_parse_graph_flex_bits capability;
3419 };
3420
3421 struct regexp_params_field_select_bits {
3422         u8 reserved_at_0[0x1e];
3423         u8 stop_engine[0x1];
3424         u8 db_umem_id[0x1];
3425 };
3426
3427 struct mlx5_ifc_regexp_params_bits {
3428         u8 reserved_at_0[0x1f];
3429         u8 stop_engine[0x1];
3430         u8 db_umem_id[0x20];
3431         u8 db_umem_offset[0x40];
3432         u8 reserved_at_80[0x100];
3433 };
3434
3435 struct mlx5_ifc_set_regexp_params_in_bits {
3436         u8 opcode[0x10];
3437         u8 uid[0x10];
3438         u8 reserved_at_20[0x10];
3439         u8 op_mod[0x10];
3440         u8 reserved_at_40[0x18];
3441         u8 engine_id[0x8];
3442         struct regexp_params_field_select_bits field_select;
3443         struct mlx5_ifc_regexp_params_bits regexp_params;
3444 };
3445
3446 struct mlx5_ifc_set_regexp_params_out_bits {
3447         u8 status[0x8];
3448         u8 reserved_at_8[0x18];
3449         u8 syndrome[0x20];
3450         u8 reserved_at_18[0x40];
3451 };
3452
3453 struct mlx5_ifc_query_regexp_params_in_bits {
3454         u8 opcode[0x10];
3455         u8 uid[0x10];
3456         u8 reserved_at_20[0x10];
3457         u8 op_mod[0x10];
3458         u8 reserved_at_40[0x18];
3459         u8 engine_id[0x8];
3460         u8 reserved[0x20];
3461 };
3462
3463 struct mlx5_ifc_query_regexp_params_out_bits {
3464         u8 status[0x8];
3465         u8 reserved_at_8[0x18];
3466         u8 syndrome[0x20];
3467         u8 reserved[0x40];
3468         struct mlx5_ifc_regexp_params_bits regexp_params;
3469 };
3470
3471 struct mlx5_ifc_set_regexp_register_in_bits {
3472         u8 opcode[0x10];
3473         u8 uid[0x10];
3474         u8 reserved_at_20[0x10];
3475         u8 op_mod[0x10];
3476         u8 reserved_at_40[0x18];
3477         u8 engine_id[0x8];
3478         u8 register_address[0x20];
3479         u8 register_data[0x20];
3480         u8 reserved[0x60];
3481 };
3482
3483 struct mlx5_ifc_set_regexp_register_out_bits {
3484         u8 status[0x8];
3485         u8 reserved_at_8[0x18];
3486         u8 syndrome[0x20];
3487         u8 reserved[0x40];
3488 };
3489
3490 struct mlx5_ifc_query_regexp_register_in_bits {
3491         u8 opcode[0x10];
3492         u8 uid[0x10];
3493         u8 reserved_at_20[0x10];
3494         u8 op_mod[0x10];
3495         u8 reserved_at_40[0x18];
3496         u8 engine_id[0x8];
3497         u8 register_address[0x20];
3498 };
3499
3500 struct mlx5_ifc_query_regexp_register_out_bits {
3501         u8 status[0x8];
3502         u8 reserved_at_8[0x18];
3503         u8 syndrome[0x20];
3504         u8 reserved[0x20];
3505         u8 register_data[0x20];
3506 };
3507
3508 /* Queue counters. */
3509 struct mlx5_ifc_alloc_q_counter_out_bits {
3510         u8 status[0x8];
3511         u8 reserved_at_8[0x18];
3512         u8 syndrome[0x20];
3513         u8 reserved_at_40[0x18];
3514         u8 counter_set_id[0x8];
3515         u8 reserved_at_60[0x20];
3516 };
3517
3518 struct mlx5_ifc_alloc_q_counter_in_bits {
3519         u8 opcode[0x10];
3520         u8 uid[0x10];
3521         u8 reserved_at_20[0x10];
3522         u8 op_mod[0x10];
3523         u8 reserved_at_40[0x40];
3524 };
3525
3526 struct mlx5_ifc_query_q_counter_out_bits {
3527         u8 status[0x8];
3528         u8 reserved_at_8[0x18];
3529         u8 syndrome[0x20];
3530         u8 reserved_at_40[0x40];
3531         u8 rx_write_requests[0x20];
3532         u8 reserved_at_a0[0x20];
3533         u8 rx_read_requests[0x20];
3534         u8 reserved_at_e0[0x20];
3535         u8 rx_atomic_requests[0x20];
3536         u8 reserved_at_120[0x20];
3537         u8 rx_dct_connect[0x20];
3538         u8 reserved_at_160[0x20];
3539         u8 out_of_buffer[0x20];
3540         u8 reserved_at_1a0[0x20];
3541         u8 out_of_sequence[0x20];
3542         u8 reserved_at_1e0[0x20];
3543         u8 duplicate_request[0x20];
3544         u8 reserved_at_220[0x20];
3545         u8 rnr_nak_retry_err[0x20];
3546         u8 reserved_at_260[0x20];
3547         u8 packet_seq_err[0x20];
3548         u8 reserved_at_2a0[0x20];
3549         u8 implied_nak_seq_err[0x20];
3550         u8 reserved_at_2e0[0x20];
3551         u8 local_ack_timeout_err[0x20];
3552         u8 reserved_at_320[0xa0];
3553         u8 resp_local_length_error[0x20];
3554         u8 req_local_length_error[0x20];
3555         u8 resp_local_qp_error[0x20];
3556         u8 local_operation_error[0x20];
3557         u8 resp_local_protection[0x20];
3558         u8 req_local_protection[0x20];
3559         u8 resp_cqe_error[0x20];
3560         u8 req_cqe_error[0x20];
3561         u8 req_mw_binding[0x20];
3562         u8 req_bad_response[0x20];
3563         u8 req_remote_invalid_request[0x20];
3564         u8 resp_remote_invalid_request[0x20];
3565         u8 req_remote_access_errors[0x20];
3566         u8 resp_remote_access_errors[0x20];
3567         u8 req_remote_operation_errors[0x20];
3568         u8 req_transport_retries_exceeded[0x20];
3569         u8 cq_overflow[0x20];
3570         u8 resp_cqe_flush_error[0x20];
3571         u8 req_cqe_flush_error[0x20];
3572         u8 reserved_at_620[0x1e0];
3573 };
3574
3575 struct mlx5_ifc_query_q_counter_in_bits {
3576         u8 opcode[0x10];
3577         u8 uid[0x10];
3578         u8 reserved_at_20[0x10];
3579         u8 op_mod[0x10];
3580         u8 reserved_at_40[0x80];
3581         u8 clear[0x1];
3582         u8 reserved_at_c1[0x1f];
3583         u8 reserved_at_e0[0x18];
3584         u8 counter_set_id[0x8];
3585 };
3586
3587 /* CQE format mask. */
3588 #define MLX5E_CQE_FORMAT_MASK 0xc
3589
3590 /* MPW opcode. */
3591 #define MLX5_OPC_MOD_MPW 0x01
3592
3593 /* Compressed Rx CQE structure. */
3594 struct mlx5_mini_cqe8 {
3595         union {
3596                 uint32_t rx_hash_result;
3597                 struct {
3598                         union {
3599                                 uint16_t checksum;
3600                                 uint16_t flow_tag_high;
3601                                 struct {
3602                                         uint8_t reserved;
3603                                         uint8_t hdr_type;
3604                                 };
3605                         };
3606                         uint16_t stride_idx;
3607                 };
3608                 struct {
3609                         uint16_t wqe_counter;
3610                         uint8_t  s_wqe_opcode;
3611                         uint8_t  reserved;
3612                 } s_wqe_info;
3613         };
3614         union {
3615                 uint32_t byte_cnt_flow;
3616                 uint32_t byte_cnt;
3617         };
3618 };
3619
3620 /* Mini CQE responder format. */
3621 enum {
3622         MLX5_CQE_RESP_FORMAT_HASH = 0x0,
3623         MLX5_CQE_RESP_FORMAT_CSUM = 0x1,
3624         MLX5_CQE_RESP_FORMAT_FTAG_STRIDX = 0x2,
3625         MLX5_CQE_RESP_FORMAT_CSUM_STRIDX = 0x3,
3626         MLX5_CQE_RESP_FORMAT_L34H_STRIDX = 0x4,
3627 };
3628
3629 /* srTCM PRM flow meter parameters. */
3630 enum {
3631         MLX5_FLOW_COLOR_RED = 0,
3632         MLX5_FLOW_COLOR_YELLOW,
3633         MLX5_FLOW_COLOR_GREEN,
3634         MLX5_FLOW_COLOR_UNDEFINED,
3635 };
3636
3637 /* Maximum value of srTCM metering parameters. */
3638 #define MLX5_SRTCM_CBS_MAX (0xFF * (1ULL << 0x1F))
3639 #define MLX5_SRTCM_CIR_MAX (8 * (1ULL << 30) * 0xFF)
3640 #define MLX5_SRTCM_EBS_MAX 0
3641
3642 /* The bits meter color use. */
3643 #define MLX5_MTR_COLOR_BITS 8
3644
3645 /* The bit size of one register. */
3646 #define MLX5_REG_BITS 32
3647
3648 /* Idle bits for non-color usage in color register. */
3649 #define MLX5_MTR_IDLE_BITS_IN_COLOR_REG (MLX5_REG_BITS - MLX5_MTR_COLOR_BITS)
3650
3651 /* Length mode of dynamic flex parser graph node. */
3652 enum mlx5_parse_graph_node_len_mode {
3653         MLX5_GRAPH_NODE_LEN_FIXED = 0x0,
3654         MLX5_GRAPH_NODE_LEN_FIELD = 0x1,
3655         MLX5_GRAPH_NODE_LEN_BITMASK = 0x2,
3656 };
3657
3658 /* Offset mode of the samples of flex parser. */
3659 enum mlx5_parse_graph_flow_match_sample_offset_mode {
3660         MLX5_GRAPH_SAMPLE_OFFSET_FIXED = 0x0,
3661         MLX5_GRAPH_SAMPLE_OFFSET_FIELD = 0x1,
3662         MLX5_GRAPH_SAMPLE_OFFSET_BITMASK = 0x2,
3663 };
3664
3665 /* Node index for an input / output arc of the flex parser graph. */
3666 enum mlx5_parse_graph_arc_node_index {
3667         MLX5_GRAPH_ARC_NODE_NULL = 0x0,
3668         MLX5_GRAPH_ARC_NODE_HEAD = 0x1,
3669         MLX5_GRAPH_ARC_NODE_MAC = 0x2,
3670         MLX5_GRAPH_ARC_NODE_IP = 0x3,
3671         MLX5_GRAPH_ARC_NODE_GRE = 0x4,
3672         MLX5_GRAPH_ARC_NODE_UDP = 0x5,
3673         MLX5_GRAPH_ARC_NODE_MPLS = 0x6,
3674         MLX5_GRAPH_ARC_NODE_TCP = 0x7,
3675         MLX5_GRAPH_ARC_NODE_VXLAN_GPE = 0x8,
3676         MLX5_GRAPH_ARC_NODE_GENEVE = 0x9,
3677         MLX5_GRAPH_ARC_NODE_IPSEC_ESP = 0xa,
3678         MLX5_GRAPH_ARC_NODE_PROGRAMMABLE = 0x1f,
3679 };
3680
3681 /**
3682  * Convert a user mark to flow mark.
3683  *
3684  * @param val
3685  *   Mark value to convert.
3686  *
3687  * @return
3688  *   Converted mark value.
3689  */
3690 static inline uint32_t
3691 mlx5_flow_mark_set(uint32_t val)
3692 {
3693         uint32_t ret;
3694
3695         /*
3696          * Add one to the user value to differentiate un-marked flows from
3697          * marked flows, if the ID is equal to MLX5_FLOW_MARK_DEFAULT it
3698          * remains untouched.
3699          */
3700         if (val != MLX5_FLOW_MARK_DEFAULT)
3701                 ++val;
3702 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3703         /*
3704          * Mark is 24 bits (minus reserved values) but is stored on a 32 bit
3705          * word, byte-swapped by the kernel on little-endian systems. In this
3706          * case, left-shifting the resulting big-endian value ensures the
3707          * least significant 24 bits are retained when converting it back.
3708          */
3709         ret = rte_cpu_to_be_32(val) >> 8;
3710 #else
3711         ret = val;
3712 #endif
3713         return ret;
3714 }
3715
3716 /**
3717  * Convert a mark to user mark.
3718  *
3719  * @param val
3720  *   Mark value to convert.
3721  *
3722  * @return
3723  *   Converted mark value.
3724  */
3725 static inline uint32_t
3726 mlx5_flow_mark_get(uint32_t val)
3727 {
3728         /*
3729          * Subtract one from the retrieved value. It was added by
3730          * mlx5_flow_mark_set() to distinguish unmarked flows.
3731          */
3732 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
3733         return (val >> 8) - 1;
3734 #else
3735         return val - 1;
3736 #endif
3737 }
3738
3739 /**
3740  * Convert a timestamp format to configure settings in the queue context.
3741  *
3742  * @param val
3743  *   timestamp format supported by the queue.
3744  *
3745  * @return
3746  *   Converted timstamp format settings.
3747  */
3748 static inline uint32_t
3749 mlx5_ts_format_conv(uint32_t ts_format)
3750 {
3751         return ts_format == MLX5_HCA_CAP_TIMESTAMP_FORMAT_FR ?
3752                         MLX5_QPC_TIMESTAMP_FORMAT_FREE_RUNNING :
3753                         MLX5_QPC_TIMESTAMP_FORMAT_DEFAULT;
3754 }
3755
3756 #endif /* RTE_PMD_MLX5_PRM_H_ */