common/mlx5: share UAR allocation routine
[dpdk.git] / drivers / common / mlx5 / version.map
1 INTERNAL {
2         global:
3
4         mlx5_common_init;
5
6         mlx5_common_verbs_reg_mr;
7         mlx5_common_verbs_dereg_mr;
8
9         mlx5_create_mr_ext;
10
11         mlx5_dev_to_pci_addr;
12
13         mlx5_devx_cmd_create_cq;
14         mlx5_devx_cmd_create_flex_parser;
15         mlx5_devx_cmd_create_qp;
16         mlx5_devx_cmd_create_rq;
17         mlx5_devx_cmd_create_rqt;
18         mlx5_devx_cmd_create_sq;
19         mlx5_devx_cmd_create_tir;
20         mlx5_devx_cmd_create_td;
21         mlx5_devx_cmd_create_tis;
22         mlx5_devx_cmd_create_virtio_q_counters;
23         mlx5_devx_cmd_create_virtq;
24         mlx5_devx_cmd_create_flow_hit_aso_obj;
25         mlx5_devx_cmd_destroy;
26         mlx5_devx_cmd_flow_counter_alloc;
27         mlx5_devx_cmd_flow_counter_query;
28         mlx5_devx_cmd_flow_dump;
29         mlx5_devx_cmd_mkey_create;
30         mlx5_devx_cmd_modify_qp_state;
31         mlx5_devx_cmd_modify_rq;
32         mlx5_devx_cmd_modify_rqt;
33         mlx5_devx_cmd_modify_sq;
34         mlx5_devx_cmd_modify_tir;
35         mlx5_devx_cmd_modify_virtq;
36         mlx5_devx_cmd_qp_query_tis_td;
37         mlx5_devx_cmd_query_hca_attr;
38         mlx5_devx_cmd_query_parse_samples;
39         mlx5_devx_cmd_query_virtio_q_counters;
40         mlx5_devx_cmd_query_virtq;
41         mlx5_devx_cmd_register_read;
42         mlx5_devx_get_out_command_status;
43         mlx5_devx_alloc_uar;
44
45         mlx5_get_ifname_sysfs;
46         mlx5_get_dbr;
47
48         mlx5_mp_init_primary;
49         mlx5_mp_uninit_primary;
50         mlx5_mp_init_secondary;
51         mlx5_mp_uninit_secondary;
52         mlx5_mp_req_mr_create;
53         mlx5_mp_req_queue_state_modify;
54         mlx5_mp_req_verbs_cmd_fd;
55
56         mlx5_mr_btree_init;
57         mlx5_mr_btree_free;
58         mlx5_mr_btree_dump;
59         mlx5_mr_addr2mr_bh;
60         mlx5_mr_release_cache;
61         mlx5_mr_dump_cache;
62         mlx5_mr_rebuild_cache;
63         mlx5_mr_insert_cache;
64         mlx5_mr_lookup_cache;
65         mlx5_mr_lookup_list;
66         mlx5_mr_create_primary;
67         mlx5_mr_flush_local_cache;
68
69         mlx5_nl_allmulti;
70         mlx5_nl_devlink_family_id_get;
71         mlx5_nl_driver_reload;
72         mlx5_nl_enable_roce_get;
73         mlx5_nl_enable_roce_set;
74         mlx5_nl_ifindex;
75         mlx5_nl_init;
76         mlx5_nl_mac_addr_add;
77         mlx5_nl_mac_addr_flush;
78         mlx5_nl_mac_addr_remove;
79         mlx5_nl_mac_addr_sync;
80         mlx5_nl_portnum;
81         mlx5_nl_promisc;
82         mlx5_nl_switch_info;
83         mlx5_nl_vf_mac_addr_modify;
84         mlx5_nl_vlan_vmwa_create;
85         mlx5_nl_vlan_vmwa_delete;
86
87         mlx5_release_dbr;
88
89         mlx5_translate_port_name;
90
91         mlx5_malloc_mem_select;
92         mlx5_memory_stat_dump;
93         mlx5_malloc;
94         mlx5_realloc;
95         mlx5_free;
96
97         mlx5_pci_driver_register;
98 };