drivers/common/qat/qat_qp.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4
   5 #include <rte_common.h>
   6 #include <rte_cycles.h>
   7 #include <rte_dev.h>
   8 #include <rte_malloc.h>
   9 #include <rte_memzone.h>
  10 #include <rte_pci.h>
  11 #include <rte_bus_pci.h>
  12 #include <rte_atomic.h>
  13 #include <rte_prefetch.h>
  14
  15 #include "qat_logs.h"
  16 #include "qat_device.h"
  17 #include "qat_qp.h"
  18 #include "qat_sym.h"
  19 #include "qat_asym.h"
  20 #include "qat_comp.h"
  21 #include "adf_transport_access_macros.h"
  22
  23 #define QAT_CQ_MAX_DEQ_RETRIES 10
  24
  25 #define ADF_MAX_DESC                            4096
  26 #define ADF_MIN_DESC                            128
  27
  28 #define ADF_ARB_REG_SLOT                        0x1000
  29 #define ADF_ARB_RINGSRVARBEN_OFFSET             0x19C
  30
  31 #define WRITE_CSR_ARB_RINGSRVARBEN(csr_addr, index, value) \
  32         ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
  33         (ADF_ARB_REG_SLOT * index), value)
  34
  35 __extension__
  36 const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
  37                                          [ADF_MAX_QPS_ON_ANY_SERVICE] = {
  38         /* queue pairs which provide an asymmetric crypto service */
  39         [QAT_SERVICE_ASYMMETRIC] = {
  40                 {
  41                         .service_type = QAT_SERVICE_ASYMMETRIC,
  42                         .hw_bundle_num = 0,
  43                         .tx_ring_num = 0,
  44                         .rx_ring_num = 8,
  45                         .tx_msg_size = 64,
  46                         .rx_msg_size = 32,
  47
  48                 }, {
  49                         .service_type = QAT_SERVICE_ASYMMETRIC,
  50                         .hw_bundle_num = 0,
  51                         .tx_ring_num = 1,
  52                         .rx_ring_num = 9,
  53                         .tx_msg_size = 64,
  54                         .rx_msg_size = 32,
  55                 }
  56         },
  57         /* queue pairs which provide a symmetric crypto service */
  58         [QAT_SERVICE_SYMMETRIC] = {
  59                 {
  60                         .service_type = QAT_SERVICE_SYMMETRIC,
  61                         .hw_bundle_num = 0,
  62                         .tx_ring_num = 2,
  63                         .rx_ring_num = 10,
  64                         .tx_msg_size = 128,
  65                         .rx_msg_size = 32,
  66                 },
  67                 {
  68                         .service_type = QAT_SERVICE_SYMMETRIC,
  69                         .hw_bundle_num = 0,
  70                         .tx_ring_num = 3,
  71                         .rx_ring_num = 11,
  72                         .tx_msg_size = 128,
  73                         .rx_msg_size = 32,
  74                 }
  75         },
  76         /* queue pairs which provide a compression service */
  77         [QAT_SERVICE_COMPRESSION] = {
  78                 {
  79                         .service_type = QAT_SERVICE_COMPRESSION,
  80                         .hw_bundle_num = 0,
  81                         .tx_ring_num = 6,
  82                         .rx_ring_num = 14,
  83                         .tx_msg_size = 128,
  84                         .rx_msg_size = 32,
  85                 }, {
  86                         .service_type = QAT_SERVICE_COMPRESSION,
  87                         .hw_bundle_num = 0,
  88                         .tx_ring_num = 7,
  89                         .rx_ring_num = 15,
  90                         .tx_msg_size = 128,
  91                         .rx_msg_size = 32,
  92                 }
  93         }
  94 };
  95
  96 __extension__
  97 const struct qat_qp_hw_data qat_gen3_qps[QAT_MAX_SERVICES]
  98                                          [ADF_MAX_QPS_ON_ANY_SERVICE] = {
  99         /* queue pairs which provide an asymmetric crypto service */
 100         [QAT_SERVICE_ASYMMETRIC] = {
 101                 {
 102                         .service_type = QAT_SERVICE_ASYMMETRIC,
 103                         .hw_bundle_num = 0,
 104                         .tx_ring_num = 0,
 105                         .rx_ring_num = 4,
 106                         .tx_msg_size = 64,
 107                         .rx_msg_size = 32,
 108                 }
 109         },
 110         /* queue pairs which provide a symmetric crypto service */
 111         [QAT_SERVICE_SYMMETRIC] = {
 112                 {
 113                         .service_type = QAT_SERVICE_SYMMETRIC,
 114                         .hw_bundle_num = 0,
 115                         .tx_ring_num = 1,
 116                         .rx_ring_num = 5,
 117                         .tx_msg_size = 128,
 118                         .rx_msg_size = 32,
 119                 }
 120         },
 121         /* queue pairs which provide a compression service */
 122         [QAT_SERVICE_COMPRESSION] = {
 123                 {
 124                         .service_type = QAT_SERVICE_COMPRESSION,
 125                         .hw_bundle_num = 0,
 126                         .tx_ring_num = 3,
 127                         .rx_ring_num = 7,
 128                         .tx_msg_size = 128,
 129                         .rx_msg_size = 32,
 130                 }
 131         }
 132 };
 133
 134 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
 135         uint32_t queue_size_bytes);
 136 static void qat_queue_delete(struct qat_queue *queue);
 137 static int qat_queue_create(struct qat_pci_device *qat_dev,
 138         struct qat_queue *queue, struct qat_qp_config *, uint8_t dir);
 139 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
 140         uint32_t *queue_size_for_csr);
 141 static void adf_configure_queues(struct qat_qp *queue);
 142 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
 143         rte_spinlock_t *lock);
 144 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
 145         rte_spinlock_t *lock);
 146
 147
 148 int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data,
 149                 enum qat_service_type service)
 150 {
 151         int i, count;
 152
 153         for (i = 0, count = 0; i < ADF_MAX_QPS_ON_ANY_SERVICE; i++)
 154                 if (qp_hw_data[i].service_type == service)
 155                         count++;
 156         return count;
 157 }
 158
 159 static const struct rte_memzone *
 160 queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
 161                         int socket_id)
 162 {
 163         const struct rte_memzone *mz;
 164
 165         mz = rte_memzone_lookup(queue_name);
 166         if (mz != 0) {
 167                 if (((size_t)queue_size <= mz->len) &&
 168                                 ((socket_id == SOCKET_ID_ANY) ||
 169                                         (socket_id == mz->socket_id))) {
 170                         QAT_LOG(DEBUG, "re-use memzone already "
 171                                         "allocated for %s", queue_name);
 172                         return mz;
 173                 }
 174
 175                 QAT_LOG(ERR, "Incompatible memzone already "
 176                                 "allocated %s, size %u, socket %d. "
 177                                 "Requested size %u, socket %u",
 178                                 queue_name, (uint32_t)mz->len,
 179                                 mz->socket_id, queue_size, socket_id);
 180                 return NULL;
 181         }
 182
 183         QAT_LOG(DEBUG, "Allocate memzone for %s, size %u on socket %u",
 184                                         queue_name, queue_size, socket_id);
 185         return rte_memzone_reserve_aligned(queue_name, queue_size,
 186                 socket_id, RTE_MEMZONE_IOVA_CONTIG, queue_size);
 187 }
 188
 189 int qat_qp_setup(struct qat_pci_device *qat_dev,
 190                 struct qat_qp **qp_addr,
 191                 uint16_t queue_pair_id,
 192                 struct qat_qp_config *qat_qp_conf)
 193
 194 {
 195         struct qat_qp *qp;
 196         struct rte_pci_device *pci_dev =
 197                         qat_pci_devs[qat_dev->qat_dev_id].pci_dev;
 198         char op_cookie_pool_name[RTE_RING_NAMESIZE];
 199         uint32_t i;
 200
 201         QAT_LOG(DEBUG, "Setup qp %u on qat pci device %d gen %d",
 202                 queue_pair_id, qat_dev->qat_dev_id, qat_dev->qat_dev_gen);
 203
 204         if ((qat_qp_conf->nb_descriptors > ADF_MAX_DESC) ||
 205                 (qat_qp_conf->nb_descriptors < ADF_MIN_DESC)) {
 206                 QAT_LOG(ERR, "Can't create qp for %u descriptors",
 207                                 qat_qp_conf->nb_descriptors);
 208                 return -EINVAL;
 209         }
 210
 211         if (pci_dev->mem_resource[0].addr == NULL) {
 212                 QAT_LOG(ERR, "Could not find VF config space "
 213                                 "(UIO driver attached?).");
 214                 return -EINVAL;
 215         }
 216
 217         /* Allocate the queue pair data structure. */
 218         qp = rte_zmalloc_socket("qat PMD qp metadata",
 219                                 sizeof(*qp), RTE_CACHE_LINE_SIZE,
 220                                 qat_qp_conf->socket_id);
 221         if (qp == NULL) {
 222                 QAT_LOG(ERR, "Failed to alloc mem for qp struct");
 223                 return -ENOMEM;
 224         }
 225         qp->nb_descriptors = qat_qp_conf->nb_descriptors;
 226         qp->op_cookies = rte_zmalloc_socket("qat PMD op cookie pointer",
 227                         qat_qp_conf->nb_descriptors * sizeof(*qp->op_cookies),
 228                         RTE_CACHE_LINE_SIZE, qat_qp_conf->socket_id);
 229         if (qp->op_cookies == NULL) {
 230                 QAT_LOG(ERR, "Failed to alloc mem for cookie");
 231                 rte_free(qp);
 232                 return -ENOMEM;
 233         }
 234
 235         qp->mmap_bar_addr = pci_dev->mem_resource[0].addr;
 236         qp->enqueued = qp->dequeued = 0;
 237
 238         if (qat_queue_create(qat_dev, &(qp->tx_q), qat_qp_conf,
 239                                         ADF_RING_DIR_TX) != 0) {
 240                 QAT_LOG(ERR, "Tx queue create failed "
 241                                 "queue_pair_id=%u", queue_pair_id);
 242                 goto create_err;
 243         }
 244
 245         qp->max_inflights = ADF_MAX_INFLIGHTS(qp->tx_q.queue_size,
 246                                 ADF_BYTES_TO_MSG_SIZE(qp->tx_q.msg_size));
 247
 248         if (qp->max_inflights < 2) {
 249                 QAT_LOG(ERR, "Invalid num inflights");
 250                 qat_queue_delete(&(qp->tx_q));
 251                 goto create_err;
 252         }
 253
 254         if (qat_queue_create(qat_dev, &(qp->rx_q), qat_qp_conf,
 255                                         ADF_RING_DIR_RX) != 0) {
 256                 QAT_LOG(ERR, "Rx queue create failed "
 257                                 "queue_pair_id=%hu", queue_pair_id);
 258                 qat_queue_delete(&(qp->tx_q));
 259                 goto create_err;
 260         }
 261
 262         adf_configure_queues(qp);
 263         adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr,
 264                                         &qat_dev->arb_csr_lock);
 265
 266         snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE,
 267                                         "%s%d_cookies_%s_qp%hu",
 268                 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
 269                 qat_qp_conf->service_str, queue_pair_id);
 270
 271         QAT_LOG(DEBUG, "cookiepool: %s", op_cookie_pool_name);
 272         qp->op_cookie_pool = rte_mempool_lookup(op_cookie_pool_name);
 273         if (qp->op_cookie_pool == NULL)
 274                 qp->op_cookie_pool = rte_mempool_create(op_cookie_pool_name,
 275                                 qp->nb_descriptors,
 276                                 qat_qp_conf->cookie_size, 64, 0,
 277                                 NULL, NULL, NULL, NULL,
 278                                 pci_dev->device.numa_node,
 279                                 0);
 280         if (!qp->op_cookie_pool) {
 281                 QAT_LOG(ERR, "QAT PMD Cannot create"
 282                                 " op mempool");
 283                 goto create_err;
 284         }
 285
 286         for (i = 0; i < qp->nb_descriptors; i++) {
 287                 if (rte_mempool_get(qp->op_cookie_pool, &qp->op_cookies[i])) {
 288                         QAT_LOG(ERR, "QAT PMD Cannot get op_cookie");
 289                         goto create_err;
 290                 }
 291                 memset(qp->op_cookies[i], 0, qat_qp_conf->cookie_size);
 292         }
 293
 294         qp->qat_dev_gen = qat_dev->qat_dev_gen;
 295         qp->build_request = qat_qp_conf->build_request;
 296         qp->service_type = qat_qp_conf->hw->service_type;
 297         qp->qat_dev = qat_dev;
 298
 299         QAT_LOG(DEBUG, "QP setup complete: id: %d, cookiepool: %s",
 300                         queue_pair_id, op_cookie_pool_name);
 301
 302         *qp_addr = qp;
 303         return 0;
 304
 305 create_err:
 306         if (qp->op_cookie_pool)
 307                 rte_mempool_free(qp->op_cookie_pool);
 308         rte_free(qp->op_cookies);
 309         rte_free(qp);
 310         return -EFAULT;
 311 }
 312
 313 int qat_qp_release(struct qat_qp **qp_addr)
 314 {
 315         struct qat_qp *qp = *qp_addr;
 316         uint32_t i;
 317
 318         if (qp == NULL) {
 319                 QAT_LOG(DEBUG, "qp already freed");
 320                 return 0;
 321         }
 322
 323         QAT_LOG(DEBUG, "Free qp on qat_pci device %d",
 324                                 qp->qat_dev->qat_dev_id);
 325
 326         /* Don't free memory if there are still responses to be processed */
 327         if ((qp->enqueued - qp->dequeued) == 0) {
 328                 qat_queue_delete(&(qp->tx_q));
 329                 qat_queue_delete(&(qp->rx_q));
 330         } else {
 331                 return -EAGAIN;
 332         }
 333
 334         adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr,
 335                                         &qp->qat_dev->arb_csr_lock);
 336
 337         for (i = 0; i < qp->nb_descriptors; i++)
 338                 rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]);
 339
 340         if (qp->op_cookie_pool)
 341                 rte_mempool_free(qp->op_cookie_pool);
 342
 343         rte_free(qp->op_cookies);
 344         rte_free(qp);
 345         *qp_addr = NULL;
 346         return 0;
 347 }
 348
 349
 350 static void qat_queue_delete(struct qat_queue *queue)
 351 {
 352         const struct rte_memzone *mz;
 353         int status = 0;
 354
 355         if (queue == NULL) {
 356                 QAT_LOG(DEBUG, "Invalid queue");
 357                 return;
 358         }
 359         QAT_LOG(DEBUG, "Free ring %d, memzone: %s",
 360                         queue->hw_queue_number, queue->memz_name);
 361
 362         mz = rte_memzone_lookup(queue->memz_name);
 363         if (mz != NULL) {
 364                 /* Write an unused pattern to the queue memory. */
 365                 memset(queue->base_addr, 0x7F, queue->queue_size);
 366                 status = rte_memzone_free(mz);
 367                 if (status != 0)
 368                         QAT_LOG(ERR, "Error %d on freeing queue %s",
 369                                         status, queue->memz_name);
 370         } else {
 371                 QAT_LOG(DEBUG, "queue %s doesn't exist",
 372                                 queue->memz_name);
 373         }
 374 }
 375
 376 static int
 377 qat_queue_create(struct qat_pci_device *qat_dev, struct qat_queue *queue,
 378                 struct qat_qp_config *qp_conf, uint8_t dir)
 379 {
 380         uint64_t queue_base;
 381         void *io_addr;
 382         const struct rte_memzone *qp_mz;
 383         struct rte_pci_device *pci_dev =
 384                         qat_pci_devs[qat_dev->qat_dev_id].pci_dev;
 385         int ret = 0;
 386         uint16_t desc_size = (dir == ADF_RING_DIR_TX ?
 387                         qp_conf->hw->tx_msg_size : qp_conf->hw->rx_msg_size);
 388         uint32_t queue_size_bytes = (qp_conf->nb_descriptors)*(desc_size);
 389
 390         queue->hw_bundle_number = qp_conf->hw->hw_bundle_num;
 391         queue->hw_queue_number = (dir == ADF_RING_DIR_TX ?
 392                         qp_conf->hw->tx_ring_num : qp_conf->hw->rx_ring_num);
 393
 394         if (desc_size > ADF_MSG_SIZE_TO_BYTES(ADF_MAX_MSG_SIZE)) {
 395                 QAT_LOG(ERR, "Invalid descriptor size %d", desc_size);
 396                 return -EINVAL;
 397         }
 398
 399         /*
 400          * Allocate a memzone for the queue - create a unique name.
 401          */
 402         snprintf(queue->memz_name, sizeof(queue->memz_name),
 403                         "%s_%d_%s_%s_%d_%d",
 404                 pci_dev->driver->driver.name, qat_dev->qat_dev_id,
 405                 qp_conf->service_str, "qp_mem",
 406                 queue->hw_bundle_number, queue->hw_queue_number);
 407         qp_mz = queue_dma_zone_reserve(queue->memz_name, queue_size_bytes,
 408                         pci_dev->device.numa_node);
 409         if (qp_mz == NULL) {
 410                 QAT_LOG(ERR, "Failed to allocate ring memzone");
 411                 return -ENOMEM;
 412         }
 413
 414         queue->base_addr = (char *)qp_mz->addr;
 415         queue->base_phys_addr = qp_mz->iova;
 416         if (qat_qp_check_queue_alignment(queue->base_phys_addr,
 417                         queue_size_bytes)) {
 418                 QAT_LOG(ERR, "Invalid alignment on queue create "
 419                                         " 0x%"PRIx64"\n",
 420                                         queue->base_phys_addr);
 421                 ret = -EFAULT;
 422                 goto queue_create_err;
 423         }
 424
 425         if (adf_verify_queue_size(desc_size, qp_conf->nb_descriptors,
 426                         &(queue->queue_size)) != 0) {
 427                 QAT_LOG(ERR, "Invalid num inflights");
 428                 ret = -EINVAL;
 429                 goto queue_create_err;
 430         }
 431
 432         queue->modulo_mask = (1 << ADF_RING_SIZE_MODULO(queue->queue_size)) - 1;
 433         queue->head = 0;
 434         queue->tail = 0;
 435         queue->msg_size = desc_size;
 436
 437         /* For fast calculation of cookie index, relies on msg_size being 2^n */
 438         queue->trailz = __builtin_ctz(desc_size);
 439
 440         /*
 441          * Write an unused pattern to the queue memory.
 442          */
 443         memset(queue->base_addr, 0x7F, queue_size_bytes);
 444
 445         queue_base = BUILD_RING_BASE_ADDR(queue->base_phys_addr,
 446                                         queue->queue_size);
 447
 448         io_addr = pci_dev->mem_resource[0].addr;
 449
 450         WRITE_CSR_RING_BASE(io_addr, queue->hw_bundle_number,
 451                         queue->hw_queue_number, queue_base);
 452
 453         QAT_LOG(DEBUG, "RING: Name:%s, size in CSR: %u, in bytes %u,"
 454                 " nb msgs %u, msg_size %u, modulo mask %u",
 455                         queue->memz_name,
 456                         queue->queue_size, queue_size_bytes,
 457                         qp_conf->nb_descriptors, desc_size,
 458                         queue->modulo_mask);
 459
 460         return 0;
 461
 462 queue_create_err:
 463         rte_memzone_free(qp_mz);
 464         return ret;
 465 }
 466
 467 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
 468                                         uint32_t queue_size_bytes)
 469 {
 470         if (((queue_size_bytes - 1) & phys_addr) != 0)
 471                 return -EINVAL;
 472         return 0;
 473 }
 474
 475 static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num,
 476         uint32_t *p_queue_size_for_csr)
 477 {
 478         uint8_t i = ADF_MIN_RING_SIZE;
 479
 480         for (; i <= ADF_MAX_RING_SIZE; i++)
 481                 if ((msg_size * msg_num) ==
 482                                 (uint32_t)ADF_SIZE_TO_RING_SIZE_IN_BYTES(i)) {
 483                         *p_queue_size_for_csr = i;
 484                         return 0;
 485                 }
 486         QAT_LOG(ERR, "Invalid ring size %d", msg_size * msg_num);
 487         return -EINVAL;
 488 }
 489
 490 static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr,
 491                                         rte_spinlock_t *lock)
 492 {
 493         uint32_t arb_csr_offset =  ADF_ARB_RINGSRVARBEN_OFFSET +
 494                                         (ADF_ARB_REG_SLOT *
 495                                                         txq->hw_bundle_number);
 496         uint32_t value;
 497
 498         rte_spinlock_lock(lock);
 499         value = ADF_CSR_RD(base_addr, arb_csr_offset);
 500         value |= (0x01 << txq->hw_queue_number);
 501         ADF_CSR_WR(base_addr, arb_csr_offset, value);
 502         rte_spinlock_unlock(lock);
 503 }
 504
 505 static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr,
 506                                         rte_spinlock_t *lock)
 507 {
 508         uint32_t arb_csr_offset =  ADF_ARB_RINGSRVARBEN_OFFSET +
 509                                         (ADF_ARB_REG_SLOT *
 510                                                         txq->hw_bundle_number);
 511         uint32_t value;
 512
 513         rte_spinlock_lock(lock);
 514         value = ADF_CSR_RD(base_addr, arb_csr_offset);
 515         value &= ~(0x01 << txq->hw_queue_number);
 516         ADF_CSR_WR(base_addr, arb_csr_offset, value);
 517         rte_spinlock_unlock(lock);
 518 }
 519
 520 static void adf_configure_queues(struct qat_qp *qp)
 521 {
 522         uint32_t queue_config;
 523         struct qat_queue *queue = &qp->tx_q;
 524
 525         queue_config = BUILD_RING_CONFIG(queue->queue_size);
 526
 527         WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
 528                         queue->hw_queue_number, queue_config);
 529
 530         queue = &qp->rx_q;
 531         queue_config =
 532                         BUILD_RESP_RING_CONFIG(queue->queue_size,
 533                                         ADF_RING_NEAR_WATERMARK_512,
 534                                         ADF_RING_NEAR_WATERMARK_0);
 535
 536         WRITE_CSR_RING_CONFIG(qp->mmap_bar_addr, queue->hw_bundle_number,
 537                         queue->hw_queue_number, queue_config);
 538 }
 539
 540 static inline uint32_t adf_modulo(uint32_t data, uint32_t modulo_mask)
 541 {
 542         return data & modulo_mask;
 543 }
 544
 545 static inline void
 546 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
 547         WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
 548                         q->hw_queue_number, q->tail);
 549         q->csr_tail = q->tail;
 550 }
 551
 552 static inline
 553 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
 554 {
 555         uint32_t old_head, new_head;
 556         uint32_t max_head;
 557
 558         old_head = q->csr_head;
 559         new_head = q->head;
 560         max_head = qp->nb_descriptors * q->msg_size;
 561
 562         /* write out free descriptors */
 563         void *cur_desc = (uint8_t *)q->base_addr + old_head;
 564
 565         if (new_head < old_head) {
 566                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
 567                 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
 568         } else {
 569                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
 570         }
 571         q->nb_processed_responses = 0;
 572         q->csr_head = new_head;
 573
 574         /* write current head to CSR */
 575         WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
 576                             q->hw_queue_number, new_head);
 577 }
 578
 579 uint16_t
 580 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 581 {
 582         register struct qat_queue *queue;
 583         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 584         register uint32_t nb_ops_sent = 0;
 585         register int ret;
 586         uint16_t nb_ops_possible = nb_ops;
 587         register uint8_t *base_addr;
 588         register uint32_t tail;
 589
 590         if (unlikely(nb_ops == 0))
 591                 return 0;
 592
 593         /* read params used a lot in main loop into registers */
 594         queue = &(tmp_qp->tx_q);
 595         base_addr = (uint8_t *)queue->base_addr;
 596         tail = queue->tail;
 597
 598         /* Find how many can actually fit on the ring */
 599         {
 600                 /* dequeued can only be written by one thread, but it may not
 601                  * be this thread. As it's 4-byte aligned it will be read
 602                  * atomically here by any Intel CPU.
 603                  * enqueued can wrap before dequeued, but cannot
 604                  * lap it as var size of enq/deq (uint32_t) > var size of
 605                  * max_inflights (uint16_t). In reality inflights is never
 606                  * even as big as max uint16_t, as it's <= ADF_MAX_DESC.
 607                  * On wrapping, the calculation still returns the correct
 608                  * positive value as all three vars are unsigned.
 609                  */
 610                 uint32_t inflights =
 611                         tmp_qp->enqueued - tmp_qp->dequeued;
 612
 613                 if ((inflights + nb_ops) > tmp_qp->max_inflights) {
 614                         nb_ops_possible = tmp_qp->max_inflights - inflights;
 615                         if (nb_ops_possible == 0)
 616                                 return 0;
 617                 }
 618                 /* QAT has plenty of work queued already, so don't waste cycles
 619                  * enqueueing, wait til the application has gathered a bigger
 620                  * burst or some completed ops have been dequeued
 621                  */
 622                 if (tmp_qp->min_enq_burst_threshold && inflights >
 623                                 QAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <
 624                                 tmp_qp->min_enq_burst_threshold) {
 625                         tmp_qp->stats.threshold_hit_count++;
 626                         return 0;
 627                 }
 628         }
 629
 630
 631         while (nb_ops_sent != nb_ops_possible) {
 632                 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC) {
 633 #ifdef BUILD_QAT_SYM
 634                         ret = qat_sym_build_request(*ops, base_addr + tail,
 635                                 tmp_qp->op_cookies[tail >> queue->trailz],
 636                                 tmp_qp->qat_dev_gen);
 637 #endif
 638                 } else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION) {
 639                         ret = qat_comp_build_request(*ops, base_addr + tail,
 640                                 tmp_qp->op_cookies[tail >> queue->trailz],
 641                                 tmp_qp->qat_dev_gen);
 642                 } else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC) {
 643 #ifdef BUILD_QAT_ASYM
 644                         ret = qat_asym_build_request(*ops, base_addr + tail,
 645                                 tmp_qp->op_cookies[tail >> queue->trailz],
 646                                 tmp_qp->qat_dev_gen);
 647 #endif
 648                 }
 649                 if (ret != 0) {
 650                         tmp_qp->stats.enqueue_err_count++;
 651                         /* This message cannot be enqueued */
 652                         if (nb_ops_sent == 0)
 653                                 return 0;
 654                         goto kick_tail;
 655                 }
 656
 657                 tail = adf_modulo(tail + queue->msg_size, queue->modulo_mask);
 658                 ops++;
 659                 nb_ops_sent++;
 660         }
 661 kick_tail:
 662         queue->tail = tail;
 663         tmp_qp->enqueued += nb_ops_sent;
 664         tmp_qp->stats.enqueued_count += nb_ops_sent;
 665         txq_write_tail(tmp_qp, queue);
 666         return nb_ops_sent;
 667 }
 668
 669 /* Use this for compression only - but keep consistent with above common
 670  * function as much as possible.
 671  */
 672 uint16_t
 673 qat_enqueue_comp_op_burst(void *qp, void **ops, uint16_t nb_ops)
 674 {
 675         register struct qat_queue *queue;
 676         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 677         register uint32_t nb_ops_sent = 0;
 678         register int nb_desc_to_build;
 679         uint16_t nb_ops_possible = nb_ops;
 680         register uint8_t *base_addr;
 681         register uint32_t tail;
 682
 683         int descriptors_built, total_descriptors_built = 0;
 684         int nb_remaining_descriptors;
 685         int overflow = 0;
 686
 687         if (unlikely(nb_ops == 0))
 688                 return 0;
 689
 690         /* read params used a lot in main loop into registers */
 691         queue = &(tmp_qp->tx_q);
 692         base_addr = (uint8_t *)queue->base_addr;
 693         tail = queue->tail;
 694
 695         /* Find how many can actually fit on the ring */
 696         {
 697                 /* dequeued can only be written by one thread, but it may not
 698                  * be this thread. As it's 4-byte aligned it will be read
 699                  * atomically here by any Intel CPU.
 700                  * enqueued can wrap before dequeued, but cannot
 701                  * lap it as var size of enq/deq (uint32_t) > var size of
 702                  * max_inflights (uint16_t). In reality inflights is never
 703                  * even as big as max uint16_t, as it's <= ADF_MAX_DESC.
 704                  * On wrapping, the calculation still returns the correct
 705                  * positive value as all three vars are unsigned.
 706                  */
 707                 uint32_t inflights =
 708                         tmp_qp->enqueued - tmp_qp->dequeued;
 709
 710                 /* Find how many can actually fit on the ring */
 711                 overflow = (inflights + nb_ops) - tmp_qp->max_inflights;
 712                 if (overflow > 0) {
 713                         nb_ops_possible = nb_ops - overflow;
 714                         if (nb_ops_possible == 0)
 715                                 return 0;
 716                 }
 717
 718                 /* QAT has plenty of work queued already, so don't waste cycles
 719                  * enqueueing, wait til the application has gathered a bigger
 720                  * burst or some completed ops have been dequeued
 721                  */
 722                 if (tmp_qp->min_enq_burst_threshold && inflights >
 723                                 QAT_QP_MIN_INFL_THRESHOLD && nb_ops_possible <
 724                                 tmp_qp->min_enq_burst_threshold) {
 725                         tmp_qp->stats.threshold_hit_count++;
 726                         return 0;
 727                 }
 728         }
 729
 730         /* At this point nb_ops_possible is assuming a 1:1 mapping
 731          * between ops and descriptors.
 732          * Fewer may be sent if some ops have to be split.
 733          * nb_ops_possible is <= burst size.
 734          * Find out how many spaces are actually available on the qp in case
 735          * more are needed.
 736          */
 737         nb_remaining_descriptors = nb_ops_possible
 738                          + ((overflow >= 0) ? 0 : overflow * (-1));
 739         QAT_DP_LOG(DEBUG, "Nb ops requested %d, nb descriptors remaining %d",
 740                         nb_ops, nb_remaining_descriptors);
 741
 742         while (nb_ops_sent != nb_ops_possible &&
 743                                 nb_remaining_descriptors > 0) {
 744                 struct qat_comp_op_cookie *cookie =
 745                                 tmp_qp->op_cookies[tail >> queue->trailz];
 746
 747                 descriptors_built = 0;
 748
 749                 QAT_DP_LOG(DEBUG, "--- data length: %u",
 750                            ((struct rte_comp_op *)*ops)->src.length);
 751
 752                 nb_desc_to_build = qat_comp_build_request(*ops,
 753                                 base_addr + tail, cookie, tmp_qp->qat_dev_gen);
 754                 QAT_DP_LOG(DEBUG, "%d descriptors built, %d remaining, "
 755                         "%d ops sent, %d descriptors needed",
 756                         total_descriptors_built, nb_remaining_descriptors,
 757                         nb_ops_sent, nb_desc_to_build);
 758
 759                 if (unlikely(nb_desc_to_build < 0)) {
 760                         /* this message cannot be enqueued */
 761                         tmp_qp->stats.enqueue_err_count++;
 762                         if (nb_ops_sent == 0)
 763                                 return 0;
 764                         goto kick_tail;
 765                 } else if (unlikely(nb_desc_to_build > 1)) {
 766                         /* this op is too big and must be split - get more
 767                          * descriptors and retry
 768                          */
 769
 770                         QAT_DP_LOG(DEBUG, "Build %d descriptors for this op",
 771                                         nb_desc_to_build);
 772
 773                         nb_remaining_descriptors -= nb_desc_to_build;
 774                         if (nb_remaining_descriptors >= 0) {
 775                                 /* There are enough remaining descriptors
 776                                  * so retry
 777                                  */
 778                                 int ret2 = qat_comp_build_multiple_requests(
 779                                                 *ops, tmp_qp, tail,
 780                                                 nb_desc_to_build);
 781
 782                                 if (unlikely(ret2 < 1)) {
 783                                         QAT_DP_LOG(DEBUG,
 784                                                         "Failed to build (%d) descriptors, status %d",
 785                                                         nb_desc_to_build, ret2);
 786
 787                                         qat_comp_free_split_op_memzones(cookie,
 788                                                         nb_desc_to_build - 1);
 789
 790                                         tmp_qp->stats.enqueue_err_count++;
 791
 792                                         /* This message cannot be enqueued */
 793                                         if (nb_ops_sent == 0)
 794                                                 return 0;
 795                                         goto kick_tail;
 796                                 } else {
 797                                         descriptors_built = ret2;
 798                                         total_descriptors_built +=
 799                                                         descriptors_built;
 800                                         nb_remaining_descriptors -=
 801                                                         descriptors_built;
 802                                         QAT_DP_LOG(DEBUG,
 803                                                         "Multiple descriptors (%d) built ok",
 804                                                         descriptors_built);
 805                                 }
 806                         } else {
 807                                 QAT_DP_LOG(ERR, "For the current op, number of requested descriptors (%d) "
 808                                                 "exceeds number of available descriptors (%d)",
 809                                                 nb_desc_to_build,
 810                                                 nb_remaining_descriptors +
 811                                                         nb_desc_to_build);
 812
 813                                 qat_comp_free_split_op_memzones(cookie,
 814                                                 nb_desc_to_build - 1);
 815
 816                                 /* Not enough extra descriptors */
 817                                 if (nb_ops_sent == 0)
 818                                         return 0;
 819                                 goto kick_tail;
 820                         }
 821                 } else {
 822                         descriptors_built = 1;
 823                         total_descriptors_built++;
 824                         nb_remaining_descriptors--;
 825                         QAT_DP_LOG(DEBUG, "Single descriptor built ok");
 826                 }
 827
 828                 tail = adf_modulo(tail + (queue->msg_size * descriptors_built),
 829                                   queue->modulo_mask);
 830                 ops++;
 831                 nb_ops_sent++;
 832         }
 833
 834 kick_tail:
 835         queue->tail = tail;
 836         tmp_qp->enqueued += total_descriptors_built;
 837         tmp_qp->stats.enqueued_count += nb_ops_sent;
 838         txq_write_tail(tmp_qp, queue);
 839         return nb_ops_sent;
 840 }
 841
 842 uint16_t
 843 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 844 {
 845         struct qat_queue *rx_queue;
 846         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 847         uint32_t head;
 848         uint32_t op_resp_counter = 0, fw_resp_counter = 0;
 849         uint8_t *resp_msg;
 850         int nb_fw_responses;
 851
 852         rx_queue = &(tmp_qp->rx_q);
 853         head = rx_queue->head;
 854         resp_msg = (uint8_t *)rx_queue->base_addr + rx_queue->head;
 855
 856         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 857                         op_resp_counter != nb_ops) {
 858
 859                 nb_fw_responses = 1;
 860
 861                 if (tmp_qp->service_type == QAT_SERVICE_SYMMETRIC)
 862                         qat_sym_process_response(ops, resp_msg);
 863                 else if (tmp_qp->service_type == QAT_SERVICE_COMPRESSION)
 864                         nb_fw_responses = qat_comp_process_response(
 865                                 ops, resp_msg,
 866                                 tmp_qp->op_cookies[head >> rx_queue->trailz],
 867                                 &tmp_qp->stats.dequeue_err_count);
 868 #ifdef BUILD_QAT_ASYM
 869                 else if (tmp_qp->service_type == QAT_SERVICE_ASYMMETRIC)
 870                         qat_asym_process_response(ops, resp_msg,
 871                                 tmp_qp->op_cookies[head >> rx_queue->trailz]);
 872 #endif
 873
 874                 head = adf_modulo(head + rx_queue->msg_size,
 875                                   rx_queue->modulo_mask);
 876
 877                 resp_msg = (uint8_t *)rx_queue->base_addr + head;
 878
 879                 if (nb_fw_responses) {
 880                         /* only move on to next op if one was ready to return
 881                          * to API
 882                          */
 883                         ops++;
 884                         op_resp_counter++;
 885                 }
 886
 887                  /* A compression op may be broken up into multiple fw requests.
 888                   * Only count fw responses as complete once ALL the responses
 889                   * associated with an op have been processed, as the cookie
 890                   * data from the first response must be available until
 891                   * finished with all firmware responses.
 892                   */
 893                 fw_resp_counter += nb_fw_responses;
 894
 895                 rx_queue->nb_processed_responses++;
 896         }
 897
 898         tmp_qp->dequeued += fw_resp_counter;
 899         tmp_qp->stats.dequeued_count += op_resp_counter;
 900
 901         rx_queue->head = head;
 902         if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
 903                 rxq_free_desc(tmp_qp, rx_queue);
 904
 905         QAT_DP_LOG(DEBUG, "Dequeue burst return: %u, QAT responses: %u",
 906                         op_resp_counter, fw_resp_counter);
 907
 908         return op_resp_counter;
 909 }
 910
 911 /* This is almost same as dequeue_op_burst, without the atomic, without stats
 912  * and without the op. Dequeues one response.
 913  */
 914 static uint8_t
 915 qat_cq_dequeue_response(struct qat_qp *qp, void *out_data)
 916 {
 917         uint8_t result = 0;
 918         uint8_t retries = 0;
 919         struct qat_queue *queue = &(qp->rx_q);
 920         struct icp_qat_fw_comn_resp *resp_msg = (struct icp_qat_fw_comn_resp *)
 921                         ((uint8_t *)queue->base_addr + queue->head);
 922
 923         while (retries++ < QAT_CQ_MAX_DEQ_RETRIES &&
 924                         *(uint32_t *)resp_msg == ADF_RING_EMPTY_SIG) {
 925                 /* loop waiting for response until we reach the timeout */
 926                 rte_delay_ms(20);
 927         }
 928
 929         if (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG) {
 930                 /* response received */
 931                 result = 1;
 932
 933                 /* check status flag */
 934                 if (ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 935                                 resp_msg->comn_hdr.comn_status) ==
 936                                 ICP_QAT_FW_COMN_STATUS_FLAG_OK) {
 937                         /* success */
 938                         memcpy(out_data, resp_msg, queue->msg_size);
 939                 } else {
 940                         memset(out_data, 0, queue->msg_size);
 941                 }
 942
 943                 queue->head = adf_modulo(queue->head + queue->msg_size,
 944                                 queue->modulo_mask);
 945                 rxq_free_desc(qp, queue);
 946         }
 947
 948         return result;
 949 }
 950
 951 /* Sends a NULL message and extracts QAT fw version from the response.
 952  * Used to determine detailed capabilities based on the fw version number.
 953  * This assumes that there are no inflight messages, i.e. assumes there's space
 954  * on the qp, one message is sent and only one response collected.
 955  * Returns fw version number or 0 for unknown version or a negative error code.
 956  */
 957 int
 958 qat_cq_get_fw_version(struct qat_qp *qp)
 959 {
 960         struct qat_queue *queue = &(qp->tx_q);
 961         uint8_t *base_addr = (uint8_t *)queue->base_addr;
 962         struct icp_qat_fw_comn_req null_msg;
 963         struct icp_qat_fw_comn_resp response;
 964
 965         /* prepare the NULL request */
 966         memset(&null_msg, 0, sizeof(null_msg));
 967         null_msg.comn_hdr.hdr_flags =
 968                 ICP_QAT_FW_COMN_HDR_FLAGS_BUILD(ICP_QAT_FW_COMN_REQ_FLAG_SET);
 969         null_msg.comn_hdr.service_type = ICP_QAT_FW_COMN_REQ_NULL;
 970         null_msg.comn_hdr.service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;
 971
 972 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
 973         QAT_DP_HEXDUMP_LOG(DEBUG, "NULL request", &null_msg, sizeof(null_msg));
 974 #endif
 975
 976         /* send the NULL request */
 977         memcpy(base_addr + queue->tail, &null_msg, sizeof(null_msg));
 978         queue->tail = adf_modulo(queue->tail + queue->msg_size,
 979                         queue->modulo_mask);
 980         txq_write_tail(qp, queue);
 981
 982         /* receive a response */
 983         if (qat_cq_dequeue_response(qp, &response)) {
 984
 985 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
 986                 QAT_DP_HEXDUMP_LOG(DEBUG, "NULL response:", &response,
 987                                 sizeof(response));
 988 #endif
 989                 /* if LW0 bit 24 is set - then the fw version was returned */
 990                 if (QAT_FIELD_GET(response.comn_hdr.hdr_flags,
 991                                 ICP_QAT_FW_COMN_NULL_VERSION_FLAG_BITPOS,
 992                                 ICP_QAT_FW_COMN_NULL_VERSION_FLAG_MASK))
 993                         return response.resrvd[0]; /* return LW4 */
 994                 else
 995                         return 0; /* not set - we don't know fw version */
 996         }
 997
 998         QAT_LOG(ERR, "No response received");
 999         return -EINVAL;
1000 }
1001
1002 __rte_weak int
1003 qat_comp_process_response(void **op __rte_unused, uint8_t *resp __rte_unused,
1004                           void *op_cookie __rte_unused,
1005                           uint64_t *dequeue_err_count __rte_unused)
1006 {
1007         return  0;
1008 }