1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
62 typedef enum efx_bar_type_e {
67 typedef struct efx_bar_region_s {
68 efx_bar_type_t ebr_type;
70 efsys_dma_addr_t ebr_offset;
71 efsys_dma_addr_t ebr_length;
74 /* The function is deprecated. It is used only if Riverhead is not supported. */
76 extern __checkReturn efx_rc_t
80 __out efx_family_t *efp,
81 __out unsigned int *membarp);
85 typedef struct efx_pci_ops_s {
87 * Function for reading PCIe configuration space.
89 * espcp System-specific PCIe device handle;
90 * offset Offset inside PCIe configuration space to start reading
92 * edp EFX DWORD structure that should be populated by function
93 * in little-endian order;
95 * Returns status code, 0 on success, any other value on error.
97 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp,
98 uint32_t offset, efx_dword_t *edp);
100 * Function for finding PCIe memory bar handle by its index from a PCIe
101 * device handle. The found memory bar is available in read-only mode.
103 * configp System-specific PCIe device handle;
104 * index Memory bar index;
105 * memp Pointer to the found memory bar handle;
107 * Returns status code, 0 on success, any other value on error.
109 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp,
110 int index, efsys_bar_t *memp);
113 /* Determine EFX family and perform lookup of the function control window
115 * The function requires PCI config handle from which all memory bars can
117 * A user of the API must be aware of memory bars indexes (not available
121 extern __checkReturn efx_rc_t
122 efx_family_probe_bar(
125 __in efsys_pci_config_t *espcp,
126 __in const efx_pci_ops_t *epop,
127 __out efx_family_t *efp,
128 __out efx_bar_region_t *ebrp);
130 #endif /* EFSYS_OPT_PCI */
133 #define EFX_PCI_VENID_SFC 0x1924
134 #define EFX_PCI_VENID_XILINX 0x10EE
136 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
138 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
139 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
140 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
142 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
143 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
144 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
146 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
147 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
149 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
150 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
151 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
153 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
154 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
155 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
157 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
158 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
160 #define EFX_MEM_BAR_SIENA 2
162 #define EFX_MEM_BAR_HUNTINGTON_PF 2
163 #define EFX_MEM_BAR_HUNTINGTON_VF 0
165 #define EFX_MEM_BAR_MEDFORD_PF 2
166 #define EFX_MEM_BAR_MEDFORD_VF 0
168 #define EFX_MEM_BAR_MEDFORD2 0
170 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
171 #define EFX_MEM_BAR_RIVERHEAD 2
179 EFX_ERR_BUFID_DC_OOB,
192 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
194 extern __checkReturn uint32_t
196 __in uint32_t crc_init,
197 __in_ecount(length) uint8_t const *input,
201 /* Type prototypes */
203 typedef struct efx_rxq_s efx_rxq_t;
207 typedef struct efx_nic_s efx_nic_t;
210 extern __checkReturn efx_rc_t
212 __in efx_family_t family,
213 __in efsys_identifier_t *esip,
214 __in efsys_bar_t *esbp,
215 __in uint32_t fcw_offset,
216 __in efsys_lock_t *eslp,
217 __deref_out efx_nic_t **enpp);
219 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
220 typedef enum efx_fw_variant_e {
221 EFX_FW_VARIANT_FULL_FEATURED,
222 EFX_FW_VARIANT_LOW_LATENCY,
223 EFX_FW_VARIANT_PACKED_STREAM,
224 EFX_FW_VARIANT_HIGH_TX_RATE,
225 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
226 EFX_FW_VARIANT_RULES_ENGINE,
228 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
232 extern __checkReturn efx_rc_t
235 __in efx_fw_variant_t efv);
238 extern __checkReturn efx_rc_t
240 __in efx_nic_t *enp);
243 extern __checkReturn efx_rc_t
245 __in efx_nic_t *enp);
248 extern __checkReturn boolean_t
249 efx_nic_hw_unavailable(
250 __in efx_nic_t *enp);
254 efx_nic_set_hw_unavailable(
255 __in efx_nic_t *enp);
260 extern __checkReturn efx_rc_t
261 efx_nic_register_test(
262 __in efx_nic_t *enp);
264 #endif /* EFSYS_OPT_DIAG */
269 __in efx_nic_t *enp);
274 __in efx_nic_t *enp);
279 __in efx_nic_t *enp);
281 #define EFX_PCIE_LINK_SPEED_GEN1 1
282 #define EFX_PCIE_LINK_SPEED_GEN2 2
283 #define EFX_PCIE_LINK_SPEED_GEN3 3
285 typedef enum efx_pcie_link_performance_e {
286 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
287 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
288 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
289 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
290 } efx_pcie_link_performance_t;
293 extern __checkReturn efx_rc_t
294 efx_nic_calculate_pcie_link_bandwidth(
295 __in uint32_t pcie_link_width,
296 __in uint32_t pcie_link_gen,
297 __out uint32_t *bandwidth_mbpsp);
300 extern __checkReturn efx_rc_t
301 efx_nic_check_pcie_link_speed(
303 __in uint32_t pcie_link_width,
304 __in uint32_t pcie_link_gen,
305 __out efx_pcie_link_performance_t *resultp);
309 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
310 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */
311 #define WITH_MCDI_V2 1
314 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
316 typedef enum efx_mcdi_exception_e {
317 EFX_MCDI_EXCEPTION_MC_REBOOT,
318 EFX_MCDI_EXCEPTION_MC_BADASSERT,
319 } efx_mcdi_exception_t;
321 #if EFSYS_OPT_MCDI_LOGGING
322 typedef enum efx_log_msg_e {
324 EFX_LOG_MCDI_REQUEST,
325 EFX_LOG_MCDI_RESPONSE,
327 #endif /* EFSYS_OPT_MCDI_LOGGING */
329 typedef struct efx_mcdi_transport_s {
331 efsys_mem_t *emt_dma_mem;
332 void (*emt_execute)(void *, efx_mcdi_req_t *);
333 void (*emt_ev_cpl)(void *);
334 void (*emt_exception)(void *, efx_mcdi_exception_t);
335 #if EFSYS_OPT_MCDI_LOGGING
336 void (*emt_logger)(void *, efx_log_msg_t,
337 void *, size_t, void *, size_t);
338 #endif /* EFSYS_OPT_MCDI_LOGGING */
339 #if EFSYS_OPT_MCDI_PROXY_AUTH
340 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
341 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
342 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
343 void (*emt_ev_proxy_request)(void *, uint32_t);
344 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
345 } efx_mcdi_transport_t;
348 extern __checkReturn efx_rc_t
351 __in const efx_mcdi_transport_t *mtp);
354 extern __checkReturn efx_rc_t
356 __in efx_nic_t *enp);
361 __in efx_nic_t *enp);
365 efx_mcdi_get_timeout(
367 __in efx_mcdi_req_t *emrp,
368 __out uint32_t *usec_timeoutp);
372 efx_mcdi_request_start(
374 __in efx_mcdi_req_t *emrp,
375 __in boolean_t ev_cpl);
378 extern __checkReturn boolean_t
379 efx_mcdi_request_poll(
380 __in efx_nic_t *enp);
383 extern __checkReturn boolean_t
384 efx_mcdi_request_abort(
385 __in efx_nic_t *enp);
390 __in efx_nic_t *enp);
392 #endif /* EFSYS_OPT_MCDI */
396 #define EFX_NINTR_SIENA 1024
398 typedef enum efx_intr_type_e {
399 EFX_INTR_INVALID = 0,
405 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
408 extern __checkReturn efx_rc_t
411 __in efx_intr_type_t type,
412 __in_opt efsys_mem_t *esmp);
417 __in efx_nic_t *enp);
422 __in efx_nic_t *enp);
426 efx_intr_disable_unlocked(
427 __in efx_nic_t *enp);
429 #define EFX_INTR_NEVQS 32
432 extern __checkReturn efx_rc_t
435 __in unsigned int level);
439 efx_intr_status_line(
441 __out boolean_t *fatalp,
442 __out uint32_t *maskp);
446 efx_intr_status_message(
448 __in unsigned int message,
449 __out boolean_t *fatalp);
454 __in efx_nic_t *enp);
459 __in efx_nic_t *enp);
463 #if EFSYS_OPT_MAC_STATS
465 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
466 typedef enum efx_mac_stat_e {
469 EFX_MAC_RX_UNICST_PKTS,
470 EFX_MAC_RX_MULTICST_PKTS,
471 EFX_MAC_RX_BRDCST_PKTS,
472 EFX_MAC_RX_PAUSE_PKTS,
473 EFX_MAC_RX_LE_64_PKTS,
474 EFX_MAC_RX_65_TO_127_PKTS,
475 EFX_MAC_RX_128_TO_255_PKTS,
476 EFX_MAC_RX_256_TO_511_PKTS,
477 EFX_MAC_RX_512_TO_1023_PKTS,
478 EFX_MAC_RX_1024_TO_15XX_PKTS,
479 EFX_MAC_RX_GE_15XX_PKTS,
481 EFX_MAC_RX_FCS_ERRORS,
482 EFX_MAC_RX_DROP_EVENTS,
483 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
484 EFX_MAC_RX_SYMBOL_ERRORS,
485 EFX_MAC_RX_ALIGN_ERRORS,
486 EFX_MAC_RX_INTERNAL_ERRORS,
487 EFX_MAC_RX_JABBER_PKTS,
488 EFX_MAC_RX_LANE0_CHAR_ERR,
489 EFX_MAC_RX_LANE1_CHAR_ERR,
490 EFX_MAC_RX_LANE2_CHAR_ERR,
491 EFX_MAC_RX_LANE3_CHAR_ERR,
492 EFX_MAC_RX_LANE0_DISP_ERR,
493 EFX_MAC_RX_LANE1_DISP_ERR,
494 EFX_MAC_RX_LANE2_DISP_ERR,
495 EFX_MAC_RX_LANE3_DISP_ERR,
496 EFX_MAC_RX_MATCH_FAULT,
497 EFX_MAC_RX_NODESC_DROP_CNT,
500 EFX_MAC_TX_UNICST_PKTS,
501 EFX_MAC_TX_MULTICST_PKTS,
502 EFX_MAC_TX_BRDCST_PKTS,
503 EFX_MAC_TX_PAUSE_PKTS,
504 EFX_MAC_TX_LE_64_PKTS,
505 EFX_MAC_TX_65_TO_127_PKTS,
506 EFX_MAC_TX_128_TO_255_PKTS,
507 EFX_MAC_TX_256_TO_511_PKTS,
508 EFX_MAC_TX_512_TO_1023_PKTS,
509 EFX_MAC_TX_1024_TO_15XX_PKTS,
510 EFX_MAC_TX_GE_15XX_PKTS,
512 EFX_MAC_TX_SGL_COL_PKTS,
513 EFX_MAC_TX_MULT_COL_PKTS,
514 EFX_MAC_TX_EX_COL_PKTS,
515 EFX_MAC_TX_LATE_COL_PKTS,
517 EFX_MAC_TX_EX_DEF_PKTS,
518 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
519 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
520 EFX_MAC_PM_TRUNC_VFIFO_FULL,
521 EFX_MAC_PM_DISCARD_VFIFO_FULL,
522 EFX_MAC_PM_TRUNC_QBB,
523 EFX_MAC_PM_DISCARD_QBB,
524 EFX_MAC_PM_DISCARD_MAPPING,
525 EFX_MAC_RXDP_Q_DISABLED_PKTS,
526 EFX_MAC_RXDP_DI_DROPPED_PKTS,
527 EFX_MAC_RXDP_STREAMING_PKTS,
528 EFX_MAC_RXDP_HLB_FETCH,
529 EFX_MAC_RXDP_HLB_WAIT,
530 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
531 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
532 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
533 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
534 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
535 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
536 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
537 EFX_MAC_VADAPTER_RX_BAD_BYTES,
538 EFX_MAC_VADAPTER_RX_OVERFLOW,
539 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
540 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
541 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
542 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
543 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
544 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
545 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
546 EFX_MAC_VADAPTER_TX_BAD_BYTES,
547 EFX_MAC_VADAPTER_TX_OVERFLOW,
548 EFX_MAC_FEC_UNCORRECTED_ERRORS,
549 EFX_MAC_FEC_CORRECTED_ERRORS,
550 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
551 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
552 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
553 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
554 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
555 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
556 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
557 EFX_MAC_CTPIO_OVERFLOW_FAIL,
558 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
559 EFX_MAC_CTPIO_TIMEOUT_FAIL,
560 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
561 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
562 EFX_MAC_CTPIO_INVALID_WR_FAIL,
563 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
564 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
565 EFX_MAC_CTPIO_RUNT_FALLBACK,
566 EFX_MAC_CTPIO_SUCCESS,
567 EFX_MAC_CTPIO_FALLBACK,
568 EFX_MAC_CTPIO_POISON,
570 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
571 EFX_MAC_RXDP_HLB_IDLE,
572 EFX_MAC_RXDP_HLB_TIMEOUT,
576 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
578 #endif /* EFSYS_OPT_MAC_STATS */
580 typedef enum efx_link_mode_e {
581 EFX_LINK_UNKNOWN = 0,
597 #define EFX_MAC_ADDR_LEN 6
599 #define EFX_VNI_OR_VSID_LEN 3
601 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
603 #define EFX_MAC_MULTICAST_LIST_MAX 256
605 #define EFX_MAC_SDU_MAX 9202
607 #define EFX_MAC_PDU_ADJUSTMENT \
611 + /* bug16011 */ 16) \
613 #define EFX_MAC_PDU(_sdu) \
614 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
617 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
618 * the SDU rounded up slightly.
620 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
622 #define EFX_MAC_PDU_MIN 60
623 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
626 extern __checkReturn efx_rc_t
632 extern __checkReturn efx_rc_t
638 extern __checkReturn efx_rc_t
644 extern __checkReturn efx_rc_t
647 __in boolean_t all_unicst,
648 __in boolean_t mulcst,
649 __in boolean_t all_mulcst,
650 __in boolean_t brdcst);
654 efx_mac_filter_get_all_ucast_mcast(
656 __out boolean_t *all_unicst,
657 __out boolean_t *all_mulcst);
660 extern __checkReturn efx_rc_t
661 efx_mac_multicast_list_set(
663 __in_ecount(6*count) uint8_t const *addrs,
667 extern __checkReturn efx_rc_t
668 efx_mac_filter_default_rxq_set(
671 __in boolean_t using_rss);
675 efx_mac_filter_default_rxq_clear(
676 __in efx_nic_t *enp);
679 extern __checkReturn efx_rc_t
682 __in boolean_t enabled);
685 extern __checkReturn efx_rc_t
688 __out boolean_t *mac_upp);
690 #define EFX_FCNTL_RESPOND 0x00000001
691 #define EFX_FCNTL_GENERATE 0x00000002
694 extern __checkReturn efx_rc_t
697 __in unsigned int fcntl,
698 __in boolean_t autoneg);
704 __out unsigned int *fcntl_wantedp,
705 __out unsigned int *fcntl_linkp);
708 #if EFSYS_OPT_MAC_STATS
713 extern __checkReturn const char *
716 __in unsigned int id);
718 #endif /* EFSYS_OPT_NAMES */
720 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
722 #define EFX_MAC_STATS_MASK_NPAGES \
723 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
724 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
725 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
728 * Get mask of MAC statistics supported by the hardware.
730 * If mask_size is insufficient to return the mask, EINVAL error is
731 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
732 * (which is sizeof (uint32_t)) is sufficient.
735 extern __checkReturn efx_rc_t
736 efx_mac_stats_get_mask(
738 __out_bcount(mask_size) uint32_t *maskp,
739 __in size_t mask_size);
741 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
742 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
743 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
747 extern __checkReturn efx_rc_t
749 __in efx_nic_t *enp);
752 * Upload mac statistics supported by the hardware into the given buffer.
754 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
755 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
757 * The hardware will only DMA statistics that it understands (of course).
758 * Drivers should not make any assumptions about which statistics are
759 * supported, especially when the statistics are generated by firmware.
761 * Thus, drivers should zero this buffer before use, so that not-understood
762 * statistics read back as zero.
765 extern __checkReturn efx_rc_t
766 efx_mac_stats_upload(
768 __in efsys_mem_t *esmp);
771 extern __checkReturn efx_rc_t
772 efx_mac_stats_periodic(
774 __in efsys_mem_t *esmp,
775 __in uint16_t period_ms,
776 __in boolean_t events);
779 extern __checkReturn efx_rc_t
780 efx_mac_stats_update(
782 __in efsys_mem_t *esmp,
783 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
784 __inout_opt uint32_t *generationp);
786 #endif /* EFSYS_OPT_MAC_STATS */
790 typedef enum efx_mon_type_e {
803 __in efx_nic_t *enp);
805 #endif /* EFSYS_OPT_NAMES */
808 extern __checkReturn efx_rc_t
810 __in efx_nic_t *enp);
812 #if EFSYS_OPT_MON_STATS
814 #define EFX_MON_STATS_PAGE_SIZE 0x100
815 #define EFX_MON_MASK_ELEMENT_SIZE 32
817 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
818 typedef enum efx_mon_stat_e {
819 EFX_MON_STAT_CONTROLLER_TEMP,
820 EFX_MON_STAT_PHY_COMMON_TEMP,
821 EFX_MON_STAT_CONTROLLER_COOLING,
822 EFX_MON_STAT_PHY0_TEMP,
823 EFX_MON_STAT_PHY0_COOLING,
824 EFX_MON_STAT_PHY1_TEMP,
825 EFX_MON_STAT_PHY1_COOLING,
831 EFX_MON_STAT_IN_12V0,
832 EFX_MON_STAT_IN_1V2A,
833 EFX_MON_STAT_IN_VREF,
834 EFX_MON_STAT_OUT_VAOE,
835 EFX_MON_STAT_AOE_TEMP,
836 EFX_MON_STAT_PSU_AOE_TEMP,
837 EFX_MON_STAT_PSU_TEMP,
843 EFX_MON_STAT_IN_VAOE,
844 EFX_MON_STAT_OUT_IAOE,
845 EFX_MON_STAT_IN_IAOE,
846 EFX_MON_STAT_NIC_POWER,
848 EFX_MON_STAT_IN_I0V9,
849 EFX_MON_STAT_IN_I1V2,
850 EFX_MON_STAT_IN_0V9_ADC,
851 EFX_MON_STAT_CONTROLLER_2_TEMP,
852 EFX_MON_STAT_VREG_INTERNAL_TEMP,
853 EFX_MON_STAT_VREG_0V9_TEMP,
854 EFX_MON_STAT_VREG_1V2_TEMP,
855 EFX_MON_STAT_CONTROLLER_VPTAT,
856 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
857 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
858 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
859 EFX_MON_STAT_AMBIENT_TEMP,
860 EFX_MON_STAT_AIRFLOW,
861 EFX_MON_STAT_VDD08D_VSS08D_CSR,
862 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
863 EFX_MON_STAT_HOTPOINT_TEMP,
864 EFX_MON_STAT_PHY_POWER_PORT0,
865 EFX_MON_STAT_PHY_POWER_PORT1,
866 EFX_MON_STAT_MUM_VCC,
867 EFX_MON_STAT_IN_0V9_A,
868 EFX_MON_STAT_IN_I0V9_A,
869 EFX_MON_STAT_VREG_0V9_A_TEMP,
870 EFX_MON_STAT_IN_0V9_B,
871 EFX_MON_STAT_IN_I0V9_B,
872 EFX_MON_STAT_VREG_0V9_B_TEMP,
873 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
874 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
875 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
876 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
877 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
878 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
879 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
880 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
881 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
882 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
883 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
884 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
885 EFX_MON_STAT_SODIMM_VOUT,
886 EFX_MON_STAT_SODIMM_0_TEMP,
887 EFX_MON_STAT_SODIMM_1_TEMP,
888 EFX_MON_STAT_PHY0_VCC,
889 EFX_MON_STAT_PHY1_VCC,
890 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
891 EFX_MON_STAT_BOARD_FRONT_TEMP,
892 EFX_MON_STAT_BOARD_BACK_TEMP,
893 EFX_MON_STAT_IN_I1V8,
894 EFX_MON_STAT_IN_I2V5,
895 EFX_MON_STAT_IN_I3V3,
896 EFX_MON_STAT_IN_I12V0,
898 EFX_MON_STAT_IN_I1V3,
902 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
904 typedef enum efx_mon_stat_state_e {
905 EFX_MON_STAT_STATE_OK = 0,
906 EFX_MON_STAT_STATE_WARNING = 1,
907 EFX_MON_STAT_STATE_FATAL = 2,
908 EFX_MON_STAT_STATE_BROKEN = 3,
909 EFX_MON_STAT_STATE_NO_READING = 4,
910 } efx_mon_stat_state_t;
912 typedef enum efx_mon_stat_unit_e {
913 EFX_MON_STAT_UNIT_UNKNOWN = 0,
914 EFX_MON_STAT_UNIT_BOOL,
915 EFX_MON_STAT_UNIT_TEMP_C,
916 EFX_MON_STAT_UNIT_VOLTAGE_MV,
917 EFX_MON_STAT_UNIT_CURRENT_MA,
918 EFX_MON_STAT_UNIT_POWER_W,
919 EFX_MON_STAT_UNIT_RPM,
921 } efx_mon_stat_unit_t;
923 typedef struct efx_mon_stat_value_s {
925 efx_mon_stat_state_t emsv_state;
926 efx_mon_stat_unit_t emsv_unit;
927 } efx_mon_stat_value_t;
929 typedef struct efx_mon_limit_value_s {
930 uint16_t emlv_warning_min;
931 uint16_t emlv_warning_max;
932 uint16_t emlv_fatal_min;
933 uint16_t emlv_fatal_max;
934 } efx_mon_stat_limits_t;
936 typedef enum efx_mon_stat_portmask_e {
937 EFX_MON_STAT_PORTMAP_NONE = 0,
938 EFX_MON_STAT_PORTMAP_PORT0 = 1,
939 EFX_MON_STAT_PORTMAP_PORT1 = 2,
940 EFX_MON_STAT_PORTMAP_PORT2 = 3,
941 EFX_MON_STAT_PORTMAP_PORT3 = 4,
942 EFX_MON_STAT_PORTMAP_ALL = (-1),
943 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
944 } efx_mon_stat_portmask_t;
952 __in efx_mon_stat_t id);
956 efx_mon_stat_description(
958 __in efx_mon_stat_t id);
960 #endif /* EFSYS_OPT_NAMES */
963 extern __checkReturn boolean_t
964 efx_mon_mcdi_to_efx_stat(
966 __out efx_mon_stat_t *statp);
969 extern __checkReturn boolean_t
970 efx_mon_get_stat_unit(
971 __in efx_mon_stat_t stat,
972 __out efx_mon_stat_unit_t *unitp);
975 extern __checkReturn boolean_t
976 efx_mon_get_stat_portmap(
977 __in efx_mon_stat_t stat,
978 __out efx_mon_stat_portmask_t *maskp);
981 extern __checkReturn efx_rc_t
982 efx_mon_stats_update(
984 __in efsys_mem_t *esmp,
985 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
988 extern __checkReturn efx_rc_t
989 efx_mon_limits_update(
991 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
993 #endif /* EFSYS_OPT_MON_STATS */
998 __in efx_nic_t *enp);
1003 extern __checkReturn efx_rc_t
1005 __in efx_nic_t *enp);
1007 typedef enum efx_phy_led_mode_e {
1008 EFX_PHY_LED_DEFAULT = 0,
1013 } efx_phy_led_mode_t;
1015 #if EFSYS_OPT_PHY_LED_CONTROL
1018 extern __checkReturn efx_rc_t
1020 __in efx_nic_t *enp,
1021 __in efx_phy_led_mode_t mode);
1023 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1026 extern __checkReturn efx_rc_t
1028 __in efx_nic_t *enp);
1030 #if EFSYS_OPT_LOOPBACK
1032 typedef enum efx_loopback_type_e {
1033 EFX_LOOPBACK_OFF = 0,
1034 EFX_LOOPBACK_DATA = 1,
1035 EFX_LOOPBACK_GMAC = 2,
1036 EFX_LOOPBACK_XGMII = 3,
1037 EFX_LOOPBACK_XGXS = 4,
1038 EFX_LOOPBACK_XAUI = 5,
1039 EFX_LOOPBACK_GMII = 6,
1040 EFX_LOOPBACK_SGMII = 7,
1041 EFX_LOOPBACK_XGBR = 8,
1042 EFX_LOOPBACK_XFI = 9,
1043 EFX_LOOPBACK_XAUI_FAR = 10,
1044 EFX_LOOPBACK_GMII_FAR = 11,
1045 EFX_LOOPBACK_SGMII_FAR = 12,
1046 EFX_LOOPBACK_XFI_FAR = 13,
1047 EFX_LOOPBACK_GPHY = 14,
1048 EFX_LOOPBACK_PHY_XS = 15,
1049 EFX_LOOPBACK_PCS = 16,
1050 EFX_LOOPBACK_PMA_PMD = 17,
1051 EFX_LOOPBACK_XPORT = 18,
1052 EFX_LOOPBACK_XGMII_WS = 19,
1053 EFX_LOOPBACK_XAUI_WS = 20,
1054 EFX_LOOPBACK_XAUI_WS_FAR = 21,
1055 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
1056 EFX_LOOPBACK_GMII_WS = 23,
1057 EFX_LOOPBACK_XFI_WS = 24,
1058 EFX_LOOPBACK_XFI_WS_FAR = 25,
1059 EFX_LOOPBACK_PHYXS_WS = 26,
1060 EFX_LOOPBACK_PMA_INT = 27,
1061 EFX_LOOPBACK_SD_NEAR = 28,
1062 EFX_LOOPBACK_SD_FAR = 29,
1063 EFX_LOOPBACK_PMA_INT_WS = 30,
1064 EFX_LOOPBACK_SD_FEP2_WS = 31,
1065 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1066 EFX_LOOPBACK_SD_FEP_WS = 33,
1067 EFX_LOOPBACK_SD_FES_WS = 34,
1068 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1069 EFX_LOOPBACK_DATA_WS = 36,
1070 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1072 } efx_loopback_type_t;
1074 typedef enum efx_loopback_kind_e {
1075 EFX_LOOPBACK_KIND_OFF = 0,
1076 EFX_LOOPBACK_KIND_ALL,
1077 EFX_LOOPBACK_KIND_MAC,
1078 EFX_LOOPBACK_KIND_PHY,
1080 } efx_loopback_kind_t;
1085 __in efx_loopback_kind_t loopback_kind,
1086 __out efx_qword_t *maskp);
1089 extern __checkReturn efx_rc_t
1090 efx_port_loopback_set(
1091 __in efx_nic_t *enp,
1092 __in efx_link_mode_t link_mode,
1093 __in efx_loopback_type_t type);
1098 extern __checkReturn const char *
1099 efx_loopback_type_name(
1100 __in efx_nic_t *enp,
1101 __in efx_loopback_type_t type);
1103 #endif /* EFSYS_OPT_NAMES */
1105 #endif /* EFSYS_OPT_LOOPBACK */
1108 extern __checkReturn efx_rc_t
1110 __in efx_nic_t *enp,
1111 __out_opt efx_link_mode_t *link_modep);
1116 __in efx_nic_t *enp);
1118 typedef enum efx_phy_cap_type_e {
1119 EFX_PHY_CAP_INVALID = 0,
1124 EFX_PHY_CAP_1000HDX,
1125 EFX_PHY_CAP_1000FDX,
1126 EFX_PHY_CAP_10000FDX,
1130 EFX_PHY_CAP_40000FDX,
1132 EFX_PHY_CAP_100000FDX,
1133 EFX_PHY_CAP_25000FDX,
1134 EFX_PHY_CAP_50000FDX,
1135 EFX_PHY_CAP_BASER_FEC,
1136 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1138 EFX_PHY_CAP_RS_FEC_REQUESTED,
1139 EFX_PHY_CAP_25G_BASER_FEC,
1140 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1142 } efx_phy_cap_type_t;
1145 #define EFX_PHY_CAP_CURRENT 0x00000000
1146 #define EFX_PHY_CAP_DEFAULT 0x00000001
1147 #define EFX_PHY_CAP_PERM 0x00000002
1151 efx_phy_adv_cap_get(
1152 __in efx_nic_t *enp,
1154 __out uint32_t *maskp);
1157 extern __checkReturn efx_rc_t
1158 efx_phy_adv_cap_set(
1159 __in efx_nic_t *enp,
1160 __in uint32_t mask);
1165 __in efx_nic_t *enp,
1166 __out uint32_t *maskp);
1169 extern __checkReturn efx_rc_t
1171 __in efx_nic_t *enp,
1172 __out uint32_t *ouip);
1174 typedef enum efx_phy_media_type_e {
1175 EFX_PHY_MEDIA_INVALID = 0,
1180 EFX_PHY_MEDIA_SFP_PLUS,
1181 EFX_PHY_MEDIA_BASE_T,
1182 EFX_PHY_MEDIA_QSFP_PLUS,
1183 EFX_PHY_MEDIA_NTYPES
1184 } efx_phy_media_type_t;
1187 * Get the type of medium currently used. If the board has ports for
1188 * modules, a module is present, and we recognise the media type of
1189 * the module, then this will be the media type of the module.
1190 * Otherwise it will be the media type of the port.
1194 efx_phy_media_type_get(
1195 __in efx_nic_t *enp,
1196 __out efx_phy_media_type_t *typep);
1199 * 2-wire device address of the base information in accordance with SFF-8472
1200 * Diagnostic Monitoring Interface for Optical Transceivers section
1201 * 4 Memory Organization.
1203 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1206 * 2-wire device address of the digital diagnostics monitoring interface
1207 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1208 * Transceivers section 4 Memory Organization.
1210 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1213 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1214 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1217 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1220 * Maximum accessible data offset for PHY module information.
1222 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1226 extern __checkReturn efx_rc_t
1227 efx_phy_module_get_info(
1228 __in efx_nic_t *enp,
1229 __in uint8_t dev_addr,
1232 __out_bcount(len) uint8_t *data);
1234 #if EFSYS_OPT_PHY_STATS
1236 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1237 typedef enum efx_phy_stat_e {
1239 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1240 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1241 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1242 EFX_PHY_STAT_PMA_PMD_REV_A,
1243 EFX_PHY_STAT_PMA_PMD_REV_B,
1244 EFX_PHY_STAT_PMA_PMD_REV_C,
1245 EFX_PHY_STAT_PMA_PMD_REV_D,
1246 EFX_PHY_STAT_PCS_LINK_UP,
1247 EFX_PHY_STAT_PCS_RX_FAULT,
1248 EFX_PHY_STAT_PCS_TX_FAULT,
1249 EFX_PHY_STAT_PCS_BER,
1250 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1251 EFX_PHY_STAT_PHY_XS_LINK_UP,
1252 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1253 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1254 EFX_PHY_STAT_PHY_XS_ALIGN,
1255 EFX_PHY_STAT_PHY_XS_SYNC_A,
1256 EFX_PHY_STAT_PHY_XS_SYNC_B,
1257 EFX_PHY_STAT_PHY_XS_SYNC_C,
1258 EFX_PHY_STAT_PHY_XS_SYNC_D,
1259 EFX_PHY_STAT_AN_LINK_UP,
1260 EFX_PHY_STAT_AN_MASTER,
1261 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1262 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1263 EFX_PHY_STAT_CL22EXT_LINK_UP,
1268 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1269 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1270 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1271 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1272 EFX_PHY_STAT_AN_COMPLETE,
1273 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1274 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1275 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1276 EFX_PHY_STAT_PCS_FW_VERSION_0,
1277 EFX_PHY_STAT_PCS_FW_VERSION_1,
1278 EFX_PHY_STAT_PCS_FW_VERSION_2,
1279 EFX_PHY_STAT_PCS_FW_VERSION_3,
1280 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1281 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1282 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1283 EFX_PHY_STAT_PCS_OP_MODE,
1287 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1294 __in efx_nic_t *enp,
1295 __in efx_phy_stat_t stat);
1297 #endif /* EFSYS_OPT_NAMES */
1299 #define EFX_PHY_STATS_SIZE 0x100
1302 extern __checkReturn efx_rc_t
1303 efx_phy_stats_update(
1304 __in efx_nic_t *enp,
1305 __in efsys_mem_t *esmp,
1306 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1308 #endif /* EFSYS_OPT_PHY_STATS */
1313 typedef enum efx_bist_type_e {
1314 EFX_BIST_TYPE_UNKNOWN,
1315 EFX_BIST_TYPE_PHY_NORMAL,
1316 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1317 EFX_BIST_TYPE_PHY_CABLE_LONG,
1318 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1319 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1320 EFX_BIST_TYPE_REG, /* Test the register memories */
1321 EFX_BIST_TYPE_NTYPES,
1324 typedef enum efx_bist_result_e {
1325 EFX_BIST_RESULT_UNKNOWN,
1326 EFX_BIST_RESULT_RUNNING,
1327 EFX_BIST_RESULT_PASSED,
1328 EFX_BIST_RESULT_FAILED,
1329 } efx_bist_result_t;
1331 typedef enum efx_phy_cable_status_e {
1332 EFX_PHY_CABLE_STATUS_OK,
1333 EFX_PHY_CABLE_STATUS_INVALID,
1334 EFX_PHY_CABLE_STATUS_OPEN,
1335 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1336 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1337 EFX_PHY_CABLE_STATUS_BUSY,
1338 } efx_phy_cable_status_t;
1340 typedef enum efx_bist_value_e {
1341 EFX_BIST_PHY_CABLE_LENGTH_A,
1342 EFX_BIST_PHY_CABLE_LENGTH_B,
1343 EFX_BIST_PHY_CABLE_LENGTH_C,
1344 EFX_BIST_PHY_CABLE_LENGTH_D,
1345 EFX_BIST_PHY_CABLE_STATUS_A,
1346 EFX_BIST_PHY_CABLE_STATUS_B,
1347 EFX_BIST_PHY_CABLE_STATUS_C,
1348 EFX_BIST_PHY_CABLE_STATUS_D,
1349 EFX_BIST_FAULT_CODE,
1351 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1357 EFX_BIST_MEM_EXPECT,
1358 EFX_BIST_MEM_ACTUAL,
1360 EFX_BIST_MEM_ECC_PARITY,
1361 EFX_BIST_MEM_ECC_FATAL,
1366 extern __checkReturn efx_rc_t
1367 efx_bist_enable_offline(
1368 __in efx_nic_t *enp);
1371 extern __checkReturn efx_rc_t
1373 __in efx_nic_t *enp,
1374 __in efx_bist_type_t type);
1377 extern __checkReturn efx_rc_t
1379 __in efx_nic_t *enp,
1380 __in efx_bist_type_t type,
1381 __out efx_bist_result_t *resultp,
1382 __out_opt uint32_t *value_maskp,
1383 __out_ecount_opt(count) unsigned long *valuesp,
1389 __in efx_nic_t *enp,
1390 __in efx_bist_type_t type);
1392 #endif /* EFSYS_OPT_BIST */
1394 #define EFX_FEATURE_IPV6 0x00000001
1395 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1396 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1397 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1398 #define EFX_FEATURE_MCDI 0x00000020
1399 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1400 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1401 #define EFX_FEATURE_TURBO 0x00000100
1402 #define EFX_FEATURE_MCDI_DMA 0x00000200
1403 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1404 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1405 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1406 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1407 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1408 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1410 typedef enum efx_tunnel_protocol_e {
1411 EFX_TUNNEL_PROTOCOL_NONE = 0,
1412 EFX_TUNNEL_PROTOCOL_VXLAN,
1413 EFX_TUNNEL_PROTOCOL_GENEVE,
1414 EFX_TUNNEL_PROTOCOL_NVGRE,
1416 } efx_tunnel_protocol_t;
1418 typedef enum efx_vi_window_shift_e {
1419 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1420 EFX_VI_WINDOW_SHIFT_8K = 13,
1421 EFX_VI_WINDOW_SHIFT_16K = 14,
1422 EFX_VI_WINDOW_SHIFT_64K = 16,
1423 } efx_vi_window_shift_t;
1425 typedef struct efx_nic_cfg_s {
1426 uint32_t enc_board_type;
1427 uint32_t enc_phy_type;
1429 char enc_phy_name[21];
1431 char enc_phy_revision[21];
1432 efx_mon_type_t enc_mon_type;
1433 #if EFSYS_OPT_MON_STATS
1434 uint32_t enc_mon_stat_dma_buf_size;
1435 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1437 unsigned int enc_features;
1438 efx_vi_window_shift_t enc_vi_window_shift;
1439 uint8_t enc_mac_addr[6];
1440 uint8_t enc_port; /* PHY port number */
1441 uint32_t enc_intr_vec_base;
1442 uint32_t enc_intr_limit;
1443 uint32_t enc_evq_limit;
1444 uint32_t enc_txq_limit;
1445 uint32_t enc_rxq_limit;
1446 uint32_t enc_evq_max_nevs;
1447 uint32_t enc_evq_min_nevs;
1448 uint32_t enc_rxq_max_ndescs;
1449 uint32_t enc_rxq_min_ndescs;
1450 uint32_t enc_txq_max_ndescs;
1451 uint32_t enc_txq_min_ndescs;
1452 uint32_t enc_buftbl_limit;
1453 uint32_t enc_piobuf_limit;
1454 uint32_t enc_piobuf_size;
1455 uint32_t enc_piobuf_min_alloc_size;
1456 uint32_t enc_evq_timer_quantum_ns;
1457 uint32_t enc_evq_timer_max_us;
1458 uint32_t enc_clk_mult;
1459 uint32_t enc_ev_ew_desc_size;
1460 uint32_t enc_ev_desc_size;
1461 uint32_t enc_rx_desc_size;
1462 uint32_t enc_tx_desc_size;
1463 /* Maximum Rx prefix size if many Rx prefixes are supported */
1464 uint32_t enc_rx_prefix_size;
1465 uint32_t enc_rx_buf_align_start;
1466 uint32_t enc_rx_buf_align_end;
1467 #if EFSYS_OPT_RX_SCALE
1468 uint32_t enc_rx_scale_max_exclusive_contexts;
1470 * Mask of supported hash algorithms.
1471 * Hash algorithm types are used as the bit indices.
1473 uint32_t enc_rx_scale_hash_alg_mask;
1475 * Indicates whether port numbers can be included to the
1476 * input data for hash computation.
1478 boolean_t enc_rx_scale_l4_hash_supported;
1479 boolean_t enc_rx_scale_additional_modes_supported;
1480 #endif /* EFSYS_OPT_RX_SCALE */
1481 #if EFSYS_OPT_LOOPBACK
1482 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1483 #endif /* EFSYS_OPT_LOOPBACK */
1484 #if EFSYS_OPT_PHY_FLAGS
1485 uint32_t enc_phy_flags_mask;
1486 #endif /* EFSYS_OPT_PHY_FLAGS */
1487 #if EFSYS_OPT_PHY_LED_CONTROL
1488 uint32_t enc_led_mask;
1489 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1490 #if EFSYS_OPT_PHY_STATS
1491 uint64_t enc_phy_stat_mask;
1492 #endif /* EFSYS_OPT_PHY_STATS */
1494 uint8_t enc_mcdi_mdio_channel;
1495 #if EFSYS_OPT_PHY_STATS
1496 uint32_t enc_mcdi_phy_stat_mask;
1497 #endif /* EFSYS_OPT_PHY_STATS */
1498 #if EFSYS_OPT_MON_STATS
1499 uint32_t *enc_mcdi_sensor_maskp;
1500 uint32_t enc_mcdi_sensor_mask_size;
1501 #endif /* EFSYS_OPT_MON_STATS */
1502 #endif /* EFSYS_OPT_MCDI */
1504 uint32_t enc_bist_mask;
1505 #endif /* EFSYS_OPT_BIST */
1506 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1509 uint32_t enc_privilege_mask;
1510 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1511 boolean_t enc_evq_init_done_ev_supported;
1512 boolean_t enc_bug26807_workaround;
1513 boolean_t enc_bug35388_workaround;
1514 boolean_t enc_bug41750_workaround;
1515 boolean_t enc_bug61265_workaround;
1516 boolean_t enc_bug61297_workaround;
1517 boolean_t enc_rx_batching_enabled;
1518 /* Maximum number of descriptors completed in an rx event. */
1519 uint32_t enc_rx_batch_max;
1520 /* Number of rx descriptors the hardware requires for a push. */
1521 uint32_t enc_rx_push_align;
1522 /* Maximum amount of data in DMA descriptor */
1523 uint32_t enc_tx_dma_desc_size_max;
1525 * Boundary which DMA descriptor data must not cross or 0 if no
1528 uint32_t enc_tx_dma_desc_boundary;
1530 * Maximum number of bytes into the packet the TCP header can start for
1531 * the hardware to apply TSO packet edits.
1533 uint32_t enc_tx_tso_tcp_header_offset_limit;
1534 /* Maximum number of header DMA descriptors per TSO transaction. */
1535 uint32_t enc_tx_tso_max_header_ndescs;
1536 /* Maximum header length acceptable by TSO transaction. */
1537 uint32_t enc_tx_tso_max_header_length;
1538 /* Maximum number of payload DMA descriptors per TSO transaction. */
1539 uint32_t enc_tx_tso_max_payload_ndescs;
1540 /* Maximum payload length per TSO transaction. */
1541 uint32_t enc_tx_tso_max_payload_length;
1542 /* Maximum number of frames to be generated per TSO transaction. */
1543 uint32_t enc_tx_tso_max_nframes;
1544 boolean_t enc_fw_assisted_tso_enabled;
1545 boolean_t enc_fw_assisted_tso_v2_enabled;
1546 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1547 boolean_t enc_tso_v3_enabled;
1548 /* Number of TSO contexts on the NIC (FATSOv2) */
1549 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1550 boolean_t enc_hw_tx_insert_vlan_enabled;
1551 /* Number of PFs on the NIC */
1552 uint32_t enc_hw_pf_count;
1553 /* Datapath firmware vadapter/vport/vswitch support */
1554 boolean_t enc_datapath_cap_evb;
1555 /* Datapath firmware vport reconfigure support */
1556 boolean_t enc_vport_reconfigure_supported;
1557 boolean_t enc_rx_disable_scatter_supported;
1558 /* Maximum number of Rx scatter segments supported by HW */
1559 uint32_t enc_rx_scatter_max;
1560 boolean_t enc_allow_set_mac_with_installed_filters;
1561 boolean_t enc_enhanced_set_mac_supported;
1562 boolean_t enc_init_evq_v2_supported;
1563 boolean_t enc_init_evq_extended_width_supported;
1564 boolean_t enc_no_cont_ev_mode_supported;
1565 boolean_t enc_init_rxq_with_buffer_size;
1566 boolean_t enc_rx_packed_stream_supported;
1567 boolean_t enc_rx_var_packed_stream_supported;
1568 boolean_t enc_rx_es_super_buffer_supported;
1569 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1570 boolean_t enc_pm_and_rxdp_counters;
1571 boolean_t enc_mac_stats_40g_tx_size_bins;
1572 uint32_t enc_tunnel_encapsulations_supported;
1574 * NIC global maximum for unique UDP tunnel ports shared by all
1577 uint32_t enc_tunnel_config_udp_entries_max;
1578 /* External port identifier */
1579 uint8_t enc_external_port;
1580 uint32_t enc_mcdi_max_payload_length;
1581 /* VPD may be per-PF or global */
1582 boolean_t enc_vpd_is_global;
1583 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1584 uint32_t enc_required_pcie_bandwidth_mbps;
1585 uint32_t enc_max_pcie_link_gen;
1586 /* Firmware verifies integrity of NVRAM updates */
1587 boolean_t enc_nvram_update_verify_result_supported;
1588 /* Firmware supports polled NVRAM updates on select partitions */
1589 boolean_t enc_nvram_update_poll_verify_result_supported;
1590 /* Firmware accepts updates via the BUNDLE partition */
1591 boolean_t enc_nvram_bundle_update_supported;
1592 /* Firmware support for extended MAC_STATS buffer */
1593 uint32_t enc_mac_stats_nstats;
1594 boolean_t enc_fec_counters;
1595 boolean_t enc_hlb_counters;
1596 /* NIC support for Match-Action Engine (MAE). */
1597 boolean_t enc_mae_supported;
1598 /* Firmware support for "FLAG" and "MARK" filter actions */
1599 boolean_t enc_filter_action_flag_supported;
1600 boolean_t enc_filter_action_mark_supported;
1601 uint32_t enc_filter_action_mark_max;
1602 /* Port assigned to this PCI function */
1603 uint32_t enc_assigned_port;
1606 #define EFX_PCI_VF_INVALID 0xffff
1608 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1609 ((configp)->evc_function == EFX_PCI_VF_INVALID)
1611 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == EFX_PCI_VF_INVALID)
1612 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != EFX_PCI_VF_INVALID)
1614 #define EFX_PCI_FUNCTION(_encp) \
1615 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1617 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1620 extern const efx_nic_cfg_t *
1622 __in const efx_nic_t *enp);
1624 /* RxDPCPU firmware id values by which FW variant can be identified */
1625 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1626 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1627 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1628 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1629 #define EFX_RXDP_DPDK_FW_ID 0x6
1631 typedef struct efx_nic_fw_info_s {
1632 /* Basic FW version information */
1633 uint16_t enfi_mc_fw_version[4];
1635 * If datapath capabilities can be detected,
1636 * additional FW information is to be shown
1638 boolean_t enfi_dpcpu_fw_ids_valid;
1639 /* Rx and Tx datapath CPU FW IDs */
1640 uint16_t enfi_rx_dpcpu_fw_id;
1641 uint16_t enfi_tx_dpcpu_fw_id;
1642 } efx_nic_fw_info_t;
1645 extern __checkReturn efx_rc_t
1646 efx_nic_get_fw_version(
1647 __in efx_nic_t *enp,
1648 __out efx_nic_fw_info_t *enfip);
1650 #define EFX_NIC_BOARD_INFO_SERIAL_LEN (64)
1651 #define EFX_NIC_BOARD_INFO_NAME_LEN (16)
1653 typedef struct efx_nic_board_info_s {
1654 /* The following two fields are NUL-terminated ASCII strings. */
1655 char enbi_serial[EFX_NIC_BOARD_INFO_SERIAL_LEN];
1656 char enbi_name[EFX_NIC_BOARD_INFO_NAME_LEN];
1657 uint32_t enbi_revision;
1658 } efx_nic_board_info_t;
1661 extern __checkReturn efx_rc_t
1662 efx_nic_get_board_info(
1663 __in efx_nic_t *enp,
1664 __out efx_nic_board_info_t *board_infop);
1666 /* Driver resource limits (minimum required/maximum usable). */
1667 typedef struct efx_drv_limits_s {
1668 uint32_t edl_min_evq_count;
1669 uint32_t edl_max_evq_count;
1671 uint32_t edl_min_rxq_count;
1672 uint32_t edl_max_rxq_count;
1674 uint32_t edl_min_txq_count;
1675 uint32_t edl_max_txq_count;
1677 /* PIO blocks (sub-allocated from piobuf) */
1678 uint32_t edl_min_pio_alloc_size;
1679 uint32_t edl_max_pio_alloc_count;
1683 extern __checkReturn efx_rc_t
1684 efx_nic_set_drv_limits(
1685 __inout efx_nic_t *enp,
1686 __in efx_drv_limits_t *edlp);
1689 * Register the OS driver version string for management agents
1690 * (e.g. via NC-SI). The content length is provided (i.e. no
1691 * NUL terminator). Use length 0 to indicate no version string
1692 * should be advertised. It is valid to set the version string
1693 * only before efx_nic_probe() is called.
1696 extern __checkReturn efx_rc_t
1697 efx_nic_set_drv_version(
1698 __inout efx_nic_t *enp,
1699 __in_ecount(length) char const *verp,
1700 __in size_t length);
1702 typedef enum efx_nic_region_e {
1703 EFX_REGION_VI, /* Memory BAR UC mapping */
1704 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1708 extern __checkReturn efx_rc_t
1709 efx_nic_get_bar_region(
1710 __in efx_nic_t *enp,
1711 __in efx_nic_region_t region,
1712 __out uint32_t *offsetp,
1713 __out size_t *sizep);
1716 extern __checkReturn efx_rc_t
1717 efx_nic_get_vi_pool(
1718 __in efx_nic_t *enp,
1719 __out uint32_t *evq_countp,
1720 __out uint32_t *rxq_countp,
1721 __out uint32_t *txq_countp);
1726 typedef enum efx_vpd_tag_e {
1733 typedef uint16_t efx_vpd_keyword_t;
1735 typedef struct efx_vpd_value_s {
1736 efx_vpd_tag_t evv_tag;
1737 efx_vpd_keyword_t evv_keyword;
1739 uint8_t evv_value[0x100];
1743 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1746 extern __checkReturn efx_rc_t
1748 __in efx_nic_t *enp);
1751 extern __checkReturn efx_rc_t
1753 __in efx_nic_t *enp,
1754 __out size_t *sizep);
1757 extern __checkReturn efx_rc_t
1759 __in efx_nic_t *enp,
1760 __out_bcount(size) caddr_t data,
1764 extern __checkReturn efx_rc_t
1766 __in efx_nic_t *enp,
1767 __in_bcount(size) caddr_t data,
1771 extern __checkReturn efx_rc_t
1773 __in efx_nic_t *enp,
1774 __in_bcount(size) caddr_t data,
1778 extern __checkReturn efx_rc_t
1780 __in efx_nic_t *enp,
1781 __in_bcount(size) caddr_t data,
1783 __inout efx_vpd_value_t *evvp);
1786 extern __checkReturn efx_rc_t
1788 __in efx_nic_t *enp,
1789 __inout_bcount(size) caddr_t data,
1791 __in efx_vpd_value_t *evvp);
1794 extern __checkReturn efx_rc_t
1796 __in efx_nic_t *enp,
1797 __inout_bcount(size) caddr_t data,
1799 __out efx_vpd_value_t *evvp,
1800 __inout unsigned int *contp);
1803 extern __checkReturn efx_rc_t
1805 __in efx_nic_t *enp,
1806 __in_bcount(size) caddr_t data,
1812 __in efx_nic_t *enp);
1814 #endif /* EFSYS_OPT_VPD */
1820 typedef enum efx_nvram_type_e {
1821 EFX_NVRAM_INVALID = 0,
1823 EFX_NVRAM_BOOTROM_CFG,
1824 EFX_NVRAM_MC_FIRMWARE,
1825 EFX_NVRAM_MC_GOLDEN,
1831 EFX_NVRAM_FPGA_BACKUP,
1832 EFX_NVRAM_DYNAMIC_CFG,
1835 EFX_NVRAM_MUM_FIRMWARE,
1836 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1837 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1839 EFX_NVRAM_BUNDLE_METADATA,
1843 typedef struct efx_nvram_info_s {
1845 uint32_t eni_partn_size;
1846 uint32_t eni_address;
1847 uint32_t eni_erase_size;
1848 uint32_t eni_write_size;
1851 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1854 extern __checkReturn efx_rc_t
1856 __in efx_nic_t *enp);
1861 extern __checkReturn efx_rc_t
1863 __in efx_nic_t *enp);
1865 #endif /* EFSYS_OPT_DIAG */
1868 extern __checkReturn efx_rc_t
1870 __in efx_nic_t *enp,
1871 __in efx_nvram_type_t type,
1872 __out size_t *sizep);
1875 extern __checkReturn efx_rc_t
1877 __in efx_nic_t *enp,
1878 __in efx_nvram_type_t type,
1879 __out efx_nvram_info_t *enip);
1882 extern __checkReturn efx_rc_t
1884 __in efx_nic_t *enp,
1885 __in efx_nvram_type_t type,
1886 __out_opt size_t *pref_chunkp);
1889 extern __checkReturn efx_rc_t
1890 efx_nvram_rw_finish(
1891 __in efx_nic_t *enp,
1892 __in efx_nvram_type_t type,
1893 __out_opt uint32_t *verify_resultp);
1896 extern __checkReturn efx_rc_t
1897 efx_nvram_get_version(
1898 __in efx_nic_t *enp,
1899 __in efx_nvram_type_t type,
1900 __out uint32_t *subtypep,
1901 __out_ecount(4) uint16_t version[4]);
1904 extern __checkReturn efx_rc_t
1905 efx_nvram_read_chunk(
1906 __in efx_nic_t *enp,
1907 __in efx_nvram_type_t type,
1908 __in unsigned int offset,
1909 __out_bcount(size) caddr_t data,
1913 extern __checkReturn efx_rc_t
1914 efx_nvram_read_backup(
1915 __in efx_nic_t *enp,
1916 __in efx_nvram_type_t type,
1917 __in unsigned int offset,
1918 __out_bcount(size) caddr_t data,
1922 extern __checkReturn efx_rc_t
1923 efx_nvram_set_version(
1924 __in efx_nic_t *enp,
1925 __in efx_nvram_type_t type,
1926 __in_ecount(4) uint16_t version[4]);
1929 extern __checkReturn efx_rc_t
1931 __in efx_nic_t *enp,
1932 __in efx_nvram_type_t type,
1933 __in_bcount(partn_size) caddr_t partn_data,
1934 __in size_t partn_size);
1937 extern __checkReturn efx_rc_t
1939 __in efx_nic_t *enp,
1940 __in efx_nvram_type_t type);
1943 extern __checkReturn efx_rc_t
1944 efx_nvram_write_chunk(
1945 __in efx_nic_t *enp,
1946 __in efx_nvram_type_t type,
1947 __in unsigned int offset,
1948 __in_bcount(size) caddr_t data,
1954 __in efx_nic_t *enp);
1956 #endif /* EFSYS_OPT_NVRAM */
1958 #if EFSYS_OPT_BOOTCFG
1960 /* Report size and offset of bootcfg sector in NVRAM partition. */
1962 extern __checkReturn efx_rc_t
1963 efx_bootcfg_sector_info(
1964 __in efx_nic_t *enp,
1966 __out_opt uint32_t *sector_countp,
1967 __out size_t *offsetp,
1968 __out size_t *max_sizep);
1971 * Copy bootcfg sector data to a target buffer which may differ in size.
1972 * Optionally corrects format errors in source buffer.
1976 efx_bootcfg_copy_sector(
1977 __in efx_nic_t *enp,
1978 __inout_bcount(sector_length)
1980 __in size_t sector_length,
1981 __out_bcount(data_size) uint8_t *data,
1982 __in size_t data_size,
1983 __in boolean_t handle_format_errors);
1988 __in efx_nic_t *enp,
1989 __out_bcount(size) uint8_t *data,
1995 __in efx_nic_t *enp,
1996 __in_bcount(size) uint8_t *data,
2001 * Processing routines for buffers arranged in the DHCP/BOOTP option format
2002 * (see https://tools.ietf.org/html/rfc1533)
2004 * Summarising the format: the buffer is a sequence of options. All options
2005 * begin with a tag octet, which uniquely identifies the option. Fixed-
2006 * length options without data consist of only a tag octet. Only options PAD
2007 * (0) and END (255) are fixed length. All other options are variable-length
2008 * with a length octet following the tag octet. The value of the length
2009 * octet does not include the two octets specifying the tag and length. The
2010 * length octet is followed by "length" octets of data.
2012 * Option data may be a sequence of sub-options in the same format. The data
2013 * content of the encapsulating option is one or more encapsulated sub-options,
2014 * with no terminating END tag is required.
2016 * To be valid, the top-level sequence of options should be terminated by an
2017 * END tag. The buffer should be padded with the PAD byte.
2019 * When stored to NVRAM, the DHCP option format buffer is preceded by a
2020 * checksum octet. The full buffer (including after the END tag) contributes
2021 * to the checksum, hence the need to fill the buffer to the end with PAD.
2024 #define EFX_DHCP_END ((uint8_t)0xff)
2025 #define EFX_DHCP_PAD ((uint8_t)0)
2027 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
2028 (uint16_t)(((encapsulator) << 8) | (encapsulated))
2031 extern __checkReturn uint8_t
2033 __in_bcount(size) uint8_t const *data,
2037 extern __checkReturn efx_rc_t
2039 __in_bcount(size) uint8_t const *data,
2041 __out_opt size_t *usedp);
2044 extern __checkReturn efx_rc_t
2046 __in_bcount(buffer_length) uint8_t *bufferp,
2047 __in size_t buffer_length,
2049 __deref_out uint8_t **valuepp,
2050 __out size_t *value_lengthp);
2053 extern __checkReturn efx_rc_t
2055 __in_bcount(buffer_length) uint8_t *bufferp,
2056 __in size_t buffer_length,
2057 __deref_out uint8_t **endpp);
2061 extern __checkReturn efx_rc_t
2062 efx_dhcp_delete_tag(
2063 __inout_bcount(buffer_length) uint8_t *bufferp,
2064 __in size_t buffer_length,
2068 extern __checkReturn efx_rc_t
2070 __inout_bcount(buffer_length) uint8_t *bufferp,
2071 __in size_t buffer_length,
2073 __in_bcount_opt(value_length) uint8_t *valuep,
2074 __in size_t value_length);
2077 extern __checkReturn efx_rc_t
2078 efx_dhcp_update_tag(
2079 __inout_bcount(buffer_length) uint8_t *bufferp,
2080 __in size_t buffer_length,
2082 __in uint8_t *value_locationp,
2083 __in_bcount_opt(value_length) uint8_t *valuep,
2084 __in size_t value_length);
2087 #endif /* EFSYS_OPT_BOOTCFG */
2089 #if EFSYS_OPT_IMAGE_LAYOUT
2091 #include "ef10_signed_image_layout.h"
2094 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
2097 * The image header format is extensible. However, older drivers require an
2098 * exact match of image header version and header length when validating and
2099 * writing firmware images.
2101 * To avoid breaking backward compatibility, we use the upper bits of the
2102 * controller version fields to contain an extra version number used for
2103 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2104 * version). See bug39254 and SF-102785-PS for details.
2106 typedef struct efx_image_header_s {
2108 uint32_t eih_version;
2110 uint32_t eih_subtype;
2111 uint32_t eih_code_size;
2114 uint32_t eih_controller_version_min;
2116 uint16_t eih_controller_version_min_short;
2117 uint8_t eih_extra_version_a;
2118 uint8_t eih_extra_version_b;
2122 uint32_t eih_controller_version_max;
2124 uint16_t eih_controller_version_max_short;
2125 uint8_t eih_extra_version_c;
2126 uint8_t eih_extra_version_d;
2129 uint16_t eih_code_version_a;
2130 uint16_t eih_code_version_b;
2131 uint16_t eih_code_version_c;
2132 uint16_t eih_code_version_d;
2133 } efx_image_header_t;
2135 #define EFX_IMAGE_HEADER_SIZE (40)
2136 #define EFX_IMAGE_HEADER_VERSION (4)
2137 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2140 typedef struct efx_image_trailer_s {
2142 } efx_image_trailer_t;
2144 #define EFX_IMAGE_TRAILER_SIZE (4)
2146 typedef enum efx_image_format_e {
2147 EFX_IMAGE_FORMAT_NO_IMAGE,
2148 EFX_IMAGE_FORMAT_INVALID,
2149 EFX_IMAGE_FORMAT_UNSIGNED,
2150 EFX_IMAGE_FORMAT_SIGNED,
2151 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2152 } efx_image_format_t;
2154 typedef struct efx_image_info_s {
2155 efx_image_format_t eii_format;
2156 uint8_t * eii_imagep;
2157 size_t eii_image_size;
2158 efx_image_header_t * eii_headerp;
2162 extern __checkReturn efx_rc_t
2163 efx_check_reflash_image(
2165 __in uint32_t buffer_size,
2166 __out efx_image_info_t *infop);
2169 extern __checkReturn efx_rc_t
2170 efx_build_signed_image_write_buffer(
2171 __out_bcount(buffer_size)
2173 __in uint32_t buffer_size,
2174 __in efx_image_info_t *infop,
2175 __out efx_image_header_t **headerpp);
2177 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2181 typedef enum efx_pattern_type_t {
2182 EFX_PATTERN_BYTE_INCREMENT = 0,
2183 EFX_PATTERN_ALL_THE_SAME,
2184 EFX_PATTERN_BIT_ALTERNATE,
2185 EFX_PATTERN_BYTE_ALTERNATE,
2186 EFX_PATTERN_BYTE_CHANGING,
2187 EFX_PATTERN_BIT_SWEEP,
2189 } efx_pattern_type_t;
2192 (*efx_sram_pattern_fn_t)(
2194 __in boolean_t negate,
2195 __out efx_qword_t *eqp);
2198 extern __checkReturn efx_rc_t
2200 __in efx_nic_t *enp,
2201 __in efx_pattern_type_t type);
2203 #endif /* EFSYS_OPT_DIAG */
2206 extern __checkReturn efx_rc_t
2207 efx_sram_buf_tbl_set(
2208 __in efx_nic_t *enp,
2210 __in efsys_mem_t *esmp,
2215 efx_sram_buf_tbl_clear(
2216 __in efx_nic_t *enp,
2220 #define EFX_BUF_TBL_SIZE 0x20000
2222 #define EFX_BUF_SIZE 4096
2226 typedef struct efx_evq_s efx_evq_t;
2228 #if EFSYS_OPT_QSTATS
2230 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2231 typedef enum efx_ev_qstat_e {
2237 EV_RX_PAUSE_FRM_ERR,
2238 EV_RX_BUF_OWNER_ID_ERR,
2239 EV_RX_IPV4_HDR_CHKSUM_ERR,
2240 EV_RX_TCP_UDP_CHKSUM_ERR,
2244 EV_RX_MCAST_HASH_MATCH,
2261 EV_DRIVER_SRM_UPD_DONE,
2262 EV_DRIVER_TX_DESCQ_FLS_DONE,
2263 EV_DRIVER_RX_DESCQ_FLS_DONE,
2264 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2265 EV_DRIVER_RX_DSC_ERROR,
2266 EV_DRIVER_TX_DSC_ERROR,
2269 EV_RX_PARSE_INCOMPLETE,
2273 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2275 #endif /* EFSYS_OPT_QSTATS */
2278 extern __checkReturn efx_rc_t
2280 __in efx_nic_t *enp);
2285 __in efx_nic_t *enp);
2288 extern __checkReturn size_t
2290 __in const efx_nic_t *enp,
2291 __in unsigned int ndescs,
2292 __in uint32_t flags);
2295 extern __checkReturn unsigned int
2297 __in const efx_nic_t *enp,
2298 __in unsigned int ndescs,
2299 __in uint32_t flags);
2301 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2302 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2303 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2304 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2306 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2307 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2308 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2311 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2312 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2315 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2316 * which is the case when an event queue is set to THROUGHPUT mode.
2318 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2320 /* Configure EVQ for extended width events (EF100 only) */
2321 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20)
2325 extern __checkReturn efx_rc_t
2327 __in efx_nic_t *enp,
2328 __in unsigned int index,
2329 __in efsys_mem_t *esmp,
2333 __in uint32_t flags,
2334 __deref_out efx_evq_t **eepp);
2339 __in efx_evq_t *eep,
2340 __in uint16_t data);
2342 typedef __checkReturn boolean_t
2343 (*efx_initialized_ev_t)(
2344 __in_opt void *arg);
2346 #define EFX_PKT_UNICAST 0x0004
2347 #define EFX_PKT_START 0x0008
2349 #define EFX_PKT_VLAN_TAGGED 0x0010
2350 #define EFX_CKSUM_TCPUDP 0x0020
2351 #define EFX_CKSUM_IPV4 0x0040
2352 #define EFX_PKT_CONT 0x0080
2354 #define EFX_CHECK_VLAN 0x0100
2355 #define EFX_PKT_TCP 0x0200
2356 #define EFX_PKT_UDP 0x0400
2357 #define EFX_PKT_IPV4 0x0800
2359 #define EFX_PKT_IPV6 0x1000
2360 #define EFX_PKT_PREFIX_LEN 0x2000
2361 #define EFX_ADDR_MISMATCH 0x4000
2362 #define EFX_DISCARD 0x8000
2365 * The following flags are used only for packed stream
2366 * mode. The values for the flags are reused to fit into 16 bit,
2367 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2368 * packed stream mode
2370 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2371 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2374 #define EFX_EV_RX_NLABELS 32
2375 #define EFX_EV_TX_NLABELS 32
2377 typedef __checkReturn boolean_t
2380 __in uint32_t label,
2383 __in uint16_t flags);
2385 typedef __checkReturn boolean_t
2386 (*efx_rx_packets_ev_t)(
2388 __in uint32_t label,
2389 __in unsigned int num_packets,
2390 __in uint32_t flags);
2392 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2395 * Packed stream mode is documented in SF-112241-TC.
2396 * The general idea is that, instead of putting each incoming
2397 * packet into a separate buffer which is specified in a RX
2398 * descriptor, a large buffer is provided to the hardware and
2399 * packets are put there in a continuous stream.
2400 * The main advantage of such an approach is that RX queue refilling
2401 * happens much less frequently.
2403 * Equal stride packed stream mode is documented in SF-119419-TC.
2404 * The general idea is to utilize advantages of the packed stream,
2405 * but avoid indirection in packets representation.
2406 * The main advantage of such an approach is that RX queue refilling
2407 * happens much less frequently and packets buffers are independent
2408 * from upper layers point of view.
2411 typedef __checkReturn boolean_t
2414 __in uint32_t label,
2416 __in uint32_t pkt_count,
2417 __in uint16_t flags);
2421 typedef __checkReturn boolean_t
2424 __in uint32_t label,
2427 typedef __checkReturn boolean_t
2428 (*efx_tx_ndescs_ev_t)(
2430 __in uint32_t label,
2431 __in unsigned int ndescs);
2433 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2434 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2435 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2436 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2437 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2438 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2439 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2440 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2441 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2443 typedef __checkReturn boolean_t
2444 (*efx_exception_ev_t)(
2446 __in uint32_t label,
2447 __in uint32_t data);
2449 typedef __checkReturn boolean_t
2450 (*efx_rxq_flush_done_ev_t)(
2452 __in uint32_t rxq_index);
2454 typedef __checkReturn boolean_t
2455 (*efx_rxq_flush_failed_ev_t)(
2457 __in uint32_t rxq_index);
2459 typedef __checkReturn boolean_t
2460 (*efx_txq_flush_done_ev_t)(
2462 __in uint32_t txq_index);
2464 typedef __checkReturn boolean_t
2465 (*efx_software_ev_t)(
2467 __in uint16_t magic);
2469 typedef __checkReturn boolean_t
2472 __in uint32_t code);
2474 #define EFX_SRAM_CLEAR 0
2475 #define EFX_SRAM_UPDATE 1
2476 #define EFX_SRAM_ILLEGAL_CLEAR 2
2478 typedef __checkReturn boolean_t
2479 (*efx_wake_up_ev_t)(
2481 __in uint32_t label);
2483 typedef __checkReturn boolean_t
2486 __in uint32_t label);
2488 typedef __checkReturn boolean_t
2489 (*efx_link_change_ev_t)(
2491 __in efx_link_mode_t link_mode);
2493 #if EFSYS_OPT_MON_STATS
2495 typedef __checkReturn boolean_t
2496 (*efx_monitor_ev_t)(
2498 __in efx_mon_stat_t id,
2499 __in efx_mon_stat_value_t value);
2501 #endif /* EFSYS_OPT_MON_STATS */
2503 #if EFSYS_OPT_MAC_STATS
2505 typedef __checkReturn boolean_t
2506 (*efx_mac_stats_ev_t)(
2508 __in uint32_t generation);
2510 #endif /* EFSYS_OPT_MAC_STATS */
2512 #if EFSYS_OPT_DESC_PROXY
2515 * NOTE: This callback returns the raw descriptor data, which has not been
2516 * converted to host endian. The callback must use the EFX_OWORD macros
2517 * to extract the descriptor fields as host endian values.
2519 typedef __checkReturn boolean_t
2520 (*efx_desc_proxy_txq_desc_ev_t)(
2522 __in uint16_t vi_id,
2523 __in efx_oword_t txq_desc);
2526 * NOTE: This callback returns the raw descriptor data, which has not been
2527 * converted to host endian. The callback must use the EFX_OWORD macros
2528 * to extract the descriptor fields as host endian values.
2530 typedef __checkReturn boolean_t
2531 (*efx_desc_proxy_virtq_desc_ev_t)(
2533 __in uint16_t vi_id,
2534 __in uint16_t avail,
2535 __in efx_oword_t virtq_desc);
2537 #endif /* EFSYS_OPT_DESC_PROXY */
2539 typedef struct efx_ev_callbacks_s {
2540 efx_initialized_ev_t eec_initialized;
2542 efx_rx_packets_ev_t eec_rx_packets;
2543 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2544 efx_rx_ps_ev_t eec_rx_ps;
2547 efx_tx_ndescs_ev_t eec_tx_ndescs;
2548 efx_exception_ev_t eec_exception;
2549 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2550 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2551 efx_txq_flush_done_ev_t eec_txq_flush_done;
2552 efx_software_ev_t eec_software;
2553 efx_sram_ev_t eec_sram;
2554 efx_wake_up_ev_t eec_wake_up;
2555 efx_timer_ev_t eec_timer;
2556 efx_link_change_ev_t eec_link_change;
2557 #if EFSYS_OPT_MON_STATS
2558 efx_monitor_ev_t eec_monitor;
2559 #endif /* EFSYS_OPT_MON_STATS */
2560 #if EFSYS_OPT_MAC_STATS
2561 efx_mac_stats_ev_t eec_mac_stats;
2562 #endif /* EFSYS_OPT_MAC_STATS */
2563 #if EFSYS_OPT_DESC_PROXY
2564 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc;
2565 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc;
2566 #endif /* EFSYS_OPT_DESC_PROXY */
2568 } efx_ev_callbacks_t;
2571 extern __checkReturn boolean_t
2573 __in efx_evq_t *eep,
2574 __in unsigned int count);
2576 #if EFSYS_OPT_EV_PREFETCH
2581 __in efx_evq_t *eep,
2582 __in unsigned int count);
2584 #endif /* EFSYS_OPT_EV_PREFETCH */
2588 efx_ev_qcreate_check_init_done(
2589 __in efx_evq_t *eep,
2590 __in const efx_ev_callbacks_t *eecp,
2591 __in_opt void *arg);
2596 __in efx_evq_t *eep,
2597 __inout unsigned int *countp,
2598 __in const efx_ev_callbacks_t *eecp,
2599 __in_opt void *arg);
2602 extern __checkReturn efx_rc_t
2603 efx_ev_usecs_to_ticks(
2604 __in efx_nic_t *enp,
2605 __in unsigned int usecs,
2606 __out unsigned int *ticksp);
2609 extern __checkReturn efx_rc_t
2611 __in efx_evq_t *eep,
2612 __in unsigned int us);
2615 extern __checkReturn efx_rc_t
2617 __in efx_evq_t *eep,
2618 __in unsigned int count);
2620 #if EFSYS_OPT_QSTATS
2627 __in efx_nic_t *enp,
2628 __in unsigned int id);
2630 #endif /* EFSYS_OPT_NAMES */
2634 efx_ev_qstats_update(
2635 __in efx_evq_t *eep,
2636 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2638 #endif /* EFSYS_OPT_QSTATS */
2643 __in efx_evq_t *eep);
2648 extern __checkReturn efx_rc_t
2650 __inout efx_nic_t *enp);
2655 __in efx_nic_t *enp);
2657 #if EFSYS_OPT_RX_SCATTER
2659 extern __checkReturn efx_rc_t
2660 efx_rx_scatter_enable(
2661 __in efx_nic_t *enp,
2662 __in unsigned int buf_size);
2663 #endif /* EFSYS_OPT_RX_SCATTER */
2665 /* Handle to represent use of the default RSS context. */
2666 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2668 #if EFSYS_OPT_RX_SCALE
2670 typedef enum efx_rx_hash_alg_e {
2671 EFX_RX_HASHALG_LFSR = 0,
2672 EFX_RX_HASHALG_TOEPLITZ,
2673 EFX_RX_HASHALG_PACKED_STREAM,
2675 } efx_rx_hash_alg_t;
2678 * Legacy hash type flags.
2680 * They represent standard tuples for distinct traffic classes.
2682 #define EFX_RX_HASH_IPV4 (1U << 0)
2683 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2684 #define EFX_RX_HASH_IPV6 (1U << 2)
2685 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2687 #define EFX_RX_HASH_LEGACY_MASK \
2688 (EFX_RX_HASH_IPV4 | \
2689 EFX_RX_HASH_TCPIPV4 | \
2690 EFX_RX_HASH_IPV6 | \
2691 EFX_RX_HASH_TCPIPV6)
2694 * The type of the argument used by efx_rx_scale_mode_set() to
2695 * provide a means for the client drivers to configure hashing.
2697 * A properly constructed value can either be:
2698 * - a combination of legacy flags
2699 * - a combination of EFX_RX_HASH() flags
2701 typedef uint32_t efx_rx_hash_type_t;
2703 typedef enum efx_rx_hash_support_e {
2704 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2705 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2706 } efx_rx_hash_support_t;
2708 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2709 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2710 #define EFX_MAXRSS 64 /* RX indirection entry range */
2711 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2713 typedef enum efx_rx_scale_context_type_e {
2714 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2715 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2716 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2717 } efx_rx_scale_context_type_t;
2720 * Traffic classes eligible for hash computation.
2722 * Select packet headers used in computing the receive hash.
2723 * This uses the same encoding as the RSS_MODES field of
2724 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2726 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2727 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2728 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2729 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2730 #define EFX_RX_CLASS_IPV4_LBN 16
2731 #define EFX_RX_CLASS_IPV4_WIDTH 4
2732 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2733 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2734 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2735 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2736 #define EFX_RX_CLASS_IPV6_LBN 28
2737 #define EFX_RX_CLASS_IPV6_WIDTH 4
2739 #define EFX_RX_NCLASSES 6
2742 * Ancillary flags used to construct generic hash tuples.
2743 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2745 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2746 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2747 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2748 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2751 * Generic hash tuples.
2753 * They express combinations of packet fields
2754 * which can contribute to the hash value for
2755 * a particular traffic class.
2757 #define EFX_RX_CLASS_HASH_DISABLE 0
2759 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2760 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2762 #define EFX_RX_CLASS_HASH_2TUPLE \
2763 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2764 EFX_RX_CLASS_HASH_DST_ADDR)
2766 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2767 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2768 EFX_RX_CLASS_HASH_SRC_PORT)
2770 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2771 (EFX_RX_CLASS_HASH_DST_ADDR | \
2772 EFX_RX_CLASS_HASH_DST_PORT)
2774 #define EFX_RX_CLASS_HASH_4TUPLE \
2775 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2776 EFX_RX_CLASS_HASH_DST_ADDR | \
2777 EFX_RX_CLASS_HASH_SRC_PORT | \
2778 EFX_RX_CLASS_HASH_DST_PORT)
2780 #define EFX_RX_CLASS_HASH_NTUPLES 7
2783 * Hash flag constructor.
2785 * Resulting flags encode hash tuples for specific traffic classes.
2786 * The client drivers are encouraged to use these flags to form
2787 * a hash type value.
2789 #define EFX_RX_HASH(_class, _tuple) \
2790 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2791 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2794 * The maximum number of EFX_RX_HASH() flags.
2796 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2799 extern __checkReturn efx_rc_t
2800 efx_rx_scale_hash_flags_get(
2801 __in efx_nic_t *enp,
2802 __in efx_rx_hash_alg_t hash_alg,
2803 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2804 __in unsigned int max_nflags,
2805 __out unsigned int *nflagsp);
2808 extern __checkReturn efx_rc_t
2809 efx_rx_hash_default_support_get(
2810 __in efx_nic_t *enp,
2811 __out efx_rx_hash_support_t *supportp);
2815 extern __checkReturn efx_rc_t
2816 efx_rx_scale_default_support_get(
2817 __in efx_nic_t *enp,
2818 __out efx_rx_scale_context_type_t *typep);
2821 extern __checkReturn efx_rc_t
2822 efx_rx_scale_context_alloc(
2823 __in efx_nic_t *enp,
2824 __in efx_rx_scale_context_type_t type,
2825 __in uint32_t num_queues,
2826 __out uint32_t *rss_contextp);
2829 extern __checkReturn efx_rc_t
2830 efx_rx_scale_context_free(
2831 __in efx_nic_t *enp,
2832 __in uint32_t rss_context);
2835 extern __checkReturn efx_rc_t
2836 efx_rx_scale_mode_set(
2837 __in efx_nic_t *enp,
2838 __in uint32_t rss_context,
2839 __in efx_rx_hash_alg_t alg,
2840 __in efx_rx_hash_type_t type,
2841 __in boolean_t insert);
2844 extern __checkReturn efx_rc_t
2845 efx_rx_scale_tbl_set(
2846 __in efx_nic_t *enp,
2847 __in uint32_t rss_context,
2848 __in_ecount(n) unsigned int *table,
2852 extern __checkReturn efx_rc_t
2853 efx_rx_scale_key_set(
2854 __in efx_nic_t *enp,
2855 __in uint32_t rss_context,
2856 __in_ecount(n) uint8_t *key,
2860 extern __checkReturn uint32_t
2861 efx_pseudo_hdr_hash_get(
2862 __in efx_rxq_t *erp,
2863 __in efx_rx_hash_alg_t func,
2864 __in uint8_t *buffer);
2866 #endif /* EFSYS_OPT_RX_SCALE */
2869 extern __checkReturn efx_rc_t
2870 efx_pseudo_hdr_pkt_length_get(
2871 __in efx_rxq_t *erp,
2872 __in uint8_t *buffer,
2873 __out uint16_t *pkt_lengthp);
2876 extern __checkReturn size_t
2878 __in const efx_nic_t *enp,
2879 __in unsigned int ndescs);
2882 extern __checkReturn unsigned int
2884 __in const efx_nic_t *enp,
2885 __in unsigned int ndescs);
2887 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2890 * libefx representation of the Rx prefix layout information.
2892 * The information may be used inside libefx to implement Rx prefix fields
2893 * accessors and by drivers which process Rx prefix itself.
2897 * All known Rx prefix fields.
2899 * An Rx prefix may have a subset of these fields.
2901 typedef enum efx_rx_prefix_field_e {
2902 EFX_RX_PREFIX_FIELD_LENGTH = 0,
2903 EFX_RX_PREFIX_FIELD_ORIG_LENGTH,
2904 EFX_RX_PREFIX_FIELD_CLASS,
2905 EFX_RX_PREFIX_FIELD_RSS_HASH,
2906 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID,
2907 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP,
2908 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI,
2909 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI,
2910 EFX_RX_PREFIX_FIELD_USER_FLAG,
2911 EFX_RX_PREFIX_FIELD_USER_MARK,
2912 EFX_RX_PREFIX_FIELD_USER_MARK_VALID,
2913 EFX_RX_PREFIX_FIELD_CSUM_FRAME,
2914 EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2915 EFX_RX_PREFIX_NFIELDS
2916 } efx_rx_prefix_field_t;
2919 * Location and endianness of a field in Rx prefix.
2921 * If width is zero, the field is not present.
2923 typedef struct efx_rx_prefix_field_info_s {
2924 uint16_t erpfi_offset_bits;
2925 uint8_t erpfi_width_bits;
2926 boolean_t erpfi_big_endian;
2927 } efx_rx_prefix_field_info_t;
2929 /* Helper macro to define Rx prefix fields */
2930 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \
2931 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \
2932 .erpfi_offset_bits = EFX_LOW_BIT(_field), \
2933 .erpfi_width_bits = EFX_WIDTH(_field), \
2934 .erpfi_big_endian = (_big_endian), \
2937 typedef struct efx_rx_prefix_layout_s {
2939 uint8_t erpl_length;
2940 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS];
2941 } efx_rx_prefix_layout_t;
2944 * Helper function to find out a bit mask of wanted but not available
2947 * A field is considered as not available if any parameter mismatch.
2950 extern __checkReturn uint32_t
2951 efx_rx_prefix_layout_check(
2952 __in const efx_rx_prefix_layout_t *available,
2953 __in const efx_rx_prefix_layout_t *wanted);
2956 extern __checkReturn efx_rc_t
2957 efx_rx_prefix_get_layout(
2958 __in const efx_rxq_t *erp,
2959 __out efx_rx_prefix_layout_t *erplp);
2961 typedef enum efx_rxq_type_e {
2962 EFX_RXQ_TYPE_DEFAULT,
2963 EFX_RXQ_TYPE_PACKED_STREAM,
2964 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2969 * Dummy flag to be used instead of 0 to make it clear that the argument
2970 * is receive queue flags.
2972 #define EFX_RXQ_FLAG_NONE 0x0
2973 #define EFX_RXQ_FLAG_SCATTER 0x1
2975 * If tunnels are supported and Rx event can provide information about
2976 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2977 * full-feature firmware variant running), outer classes are requested by
2978 * default. However, if the driver supports tunnels, the flag allows to
2979 * request inner classes which are required to be able to interpret inner
2980 * Rx checksum offload results.
2982 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2984 * Request delivery of the RSS hash calculated by HW to be used by
2987 #define EFX_RXQ_FLAG_RSS_HASH 0x4
2990 extern __checkReturn efx_rc_t
2992 __in efx_nic_t *enp,
2993 __in unsigned int index,
2994 __in unsigned int label,
2995 __in efx_rxq_type_t type,
2996 __in size_t buf_size,
2997 __in efsys_mem_t *esmp,
3000 __in unsigned int flags,
3001 __in efx_evq_t *eep,
3002 __deref_out efx_rxq_t **erpp);
3004 #if EFSYS_OPT_RX_PACKED_STREAM
3006 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
3007 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
3008 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
3009 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
3010 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
3013 extern __checkReturn efx_rc_t
3014 efx_rx_qcreate_packed_stream(
3015 __in efx_nic_t *enp,
3016 __in unsigned int index,
3017 __in unsigned int label,
3018 __in uint32_t ps_buf_size,
3019 __in efsys_mem_t *esmp,
3021 __in efx_evq_t *eep,
3022 __deref_out efx_rxq_t **erpp);
3026 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
3028 /* Maximum head-of-line block timeout in nanoseconds */
3029 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
3032 extern __checkReturn efx_rc_t
3033 efx_rx_qcreate_es_super_buffer(
3034 __in efx_nic_t *enp,
3035 __in unsigned int index,
3036 __in unsigned int label,
3037 __in uint32_t n_bufs_per_desc,
3038 __in uint32_t max_dma_len,
3039 __in uint32_t buf_stride,
3040 __in uint32_t hol_block_timeout,
3041 __in efsys_mem_t *esmp,
3043 __in unsigned int flags,
3044 __in efx_evq_t *eep,
3045 __deref_out efx_rxq_t **erpp);
3049 typedef struct efx_buffer_s {
3050 efsys_dma_addr_t eb_addr;
3055 typedef struct efx_desc_s {
3062 __in efx_rxq_t *erp,
3063 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
3065 __in unsigned int ndescs,
3066 __in unsigned int completed,
3067 __in unsigned int added);
3072 __in efx_rxq_t *erp,
3073 __in unsigned int added,
3074 __inout unsigned int *pushedp);
3076 #if EFSYS_OPT_RX_PACKED_STREAM
3080 efx_rx_qpush_ps_credits(
3081 __in efx_rxq_t *erp);
3084 extern __checkReturn uint8_t *
3085 efx_rx_qps_packet_info(
3086 __in efx_rxq_t *erp,
3087 __in uint8_t *buffer,
3088 __in uint32_t buffer_length,
3089 __in uint32_t current_offset,
3090 __out uint16_t *lengthp,
3091 __out uint32_t *next_offsetp,
3092 __out uint32_t *timestamp);
3096 extern __checkReturn efx_rc_t
3098 __in efx_rxq_t *erp);
3103 __in efx_rxq_t *erp);
3108 __in efx_rxq_t *erp);
3112 typedef struct efx_txq_s efx_txq_t;
3114 #if EFSYS_OPT_QSTATS
3116 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
3117 typedef enum efx_tx_qstat_e {
3123 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
3125 #endif /* EFSYS_OPT_QSTATS */
3128 extern __checkReturn efx_rc_t
3130 __in efx_nic_t *enp);
3135 __in efx_nic_t *enp);
3138 extern __checkReturn size_t
3140 __in const efx_nic_t *enp,
3141 __in unsigned int ndescs);
3144 extern __checkReturn unsigned int
3146 __in const efx_nic_t *enp,
3147 __in unsigned int ndescs);
3149 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
3151 #define EFX_TXQ_CKSUM_IPV4 0x0001
3152 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
3153 #define EFX_TXQ_FATSOV2 0x0004
3154 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
3155 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
3158 extern __checkReturn efx_rc_t
3160 __in efx_nic_t *enp,
3161 __in unsigned int index,
3162 __in unsigned int label,
3163 __in efsys_mem_t *esmp,
3166 __in uint16_t flags,
3167 __in efx_evq_t *eep,
3168 __deref_out efx_txq_t **etpp,
3169 __out unsigned int *addedp);
3172 extern __checkReturn efx_rc_t
3174 __in efx_txq_t *etp,
3175 __in_ecount(ndescs) efx_buffer_t *eb,
3176 __in unsigned int ndescs,
3177 __in unsigned int completed,
3178 __inout unsigned int *addedp);
3181 extern __checkReturn efx_rc_t
3183 __in efx_txq_t *etp,
3184 __in unsigned int ns);
3189 __in efx_txq_t *etp,
3190 __in unsigned int added,
3191 __in unsigned int pushed);
3194 extern __checkReturn efx_rc_t
3196 __in efx_txq_t *etp);
3201 __in efx_txq_t *etp);
3204 extern __checkReturn efx_rc_t
3206 __in efx_txq_t *etp);
3210 efx_tx_qpio_disable(
3211 __in efx_txq_t *etp);
3214 extern __checkReturn efx_rc_t
3216 __in efx_txq_t *etp,
3217 __in_ecount(buf_length) uint8_t *buffer,
3218 __in size_t buf_length,
3219 __in size_t pio_buf_offset);
3222 extern __checkReturn efx_rc_t
3224 __in efx_txq_t *etp,
3225 __in size_t pkt_length,
3226 __in unsigned int completed,
3227 __inout unsigned int *addedp);
3230 extern __checkReturn efx_rc_t
3232 __in efx_txq_t *etp,
3233 __in_ecount(n) efx_desc_t *ed,
3234 __in unsigned int n,
3235 __in unsigned int completed,
3236 __inout unsigned int *addedp);
3240 efx_tx_qdesc_dma_create(
3241 __in efx_txq_t *etp,
3242 __in efsys_dma_addr_t addr,
3245 __out efx_desc_t *edp);
3249 efx_tx_qdesc_tso_create(
3250 __in efx_txq_t *etp,
3251 __in uint16_t ipv4_id,
3252 __in uint32_t tcp_seq,
3253 __in uint8_t tcp_flags,
3254 __out efx_desc_t *edp);
3256 /* Number of FATSOv2 option descriptors */
3257 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3259 /* Maximum number of DMA segments per TSO packet (not superframe) */
3260 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3264 efx_tx_qdesc_tso2_create(
3265 __in efx_txq_t *etp,
3266 __in uint16_t ipv4_id,
3267 __in uint16_t outer_ipv4_id,
3268 __in uint32_t tcp_seq,
3269 __in uint16_t tcp_mss,
3270 __out_ecount(count) efx_desc_t *edp,
3275 efx_tx_qdesc_vlantci_create(
3276 __in efx_txq_t *etp,
3278 __out efx_desc_t *edp);
3282 efx_tx_qdesc_checksum_create(
3283 __in efx_txq_t *etp,
3284 __in uint16_t flags,
3285 __out efx_desc_t *edp);
3287 #if EFSYS_OPT_QSTATS
3294 __in efx_nic_t *etp,
3295 __in unsigned int id);
3297 #endif /* EFSYS_OPT_NAMES */
3301 efx_tx_qstats_update(
3302 __in efx_txq_t *etp,
3303 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3305 #endif /* EFSYS_OPT_QSTATS */
3310 __in efx_txq_t *etp);
3315 #if EFSYS_OPT_FILTER
3317 #define EFX_ETHER_TYPE_IPV4 0x0800
3318 #define EFX_ETHER_TYPE_IPV6 0x86DD
3320 #define EFX_IPPROTO_TCP 6
3321 #define EFX_IPPROTO_UDP 17
3322 #define EFX_IPPROTO_GRE 47
3324 /* Use RSS to spread across multiple queues */
3325 #define EFX_FILTER_FLAG_RX_RSS 0x01
3326 /* Enable RX scatter */
3327 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3329 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3330 * May only be set by the filter implementation for each type.
3331 * A removal request will restore the automatic filter in its place.
3333 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3334 /* Filter is for RX */
3335 #define EFX_FILTER_FLAG_RX 0x08
3336 /* Filter is for TX */
3337 #define EFX_FILTER_FLAG_TX 0x10
3338 /* Set match flag on the received packet */
3339 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3340 /* Set match mark on the received packet */
3341 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3343 typedef uint8_t efx_filter_flags_t;
3346 * Flags which specify the fields to match on. The values are the same as in the
3347 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3350 /* Match by remote IP host address */
3351 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3352 /* Match by local IP host address */
3353 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3354 /* Match by remote MAC address */
3355 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3356 /* Match by remote TCP/UDP port */
3357 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3358 /* Match by remote TCP/UDP port */
3359 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3360 /* Match by local TCP/UDP port */
3361 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3362 /* Match by Ether-type */
3363 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3364 /* Match by inner VLAN ID */
3365 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3366 /* Match by outer VLAN ID */
3367 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3368 /* Match by IP transport protocol */
3369 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3370 /* Match by VNI or VSID */
3371 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3372 /* For encapsulated packets, match by inner frame local MAC address */
3373 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3374 /* For encapsulated packets, match all multicast inner frames */
3375 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3376 /* For encapsulated packets, match all unicast inner frames */
3377 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3379 * Match by encap type, this flag does not correspond to
3380 * the MCDI match flags and any unoccupied value may be used
3382 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3383 /* Match otherwise-unmatched multicast and broadcast packets */
3384 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3385 /* Match otherwise-unmatched unicast packets */
3386 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3388 typedef uint32_t efx_filter_match_flags_t;
3390 /* Filter priority from lowest to highest */
3391 typedef enum efx_filter_priority_s {
3392 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3393 * address list or hardware
3394 * requirements. This may only be used
3395 * by the filter implementation for
3397 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3399 } efx_filter_priority_t;
3402 * FIXME: All these fields are assumed to be in little-endian byte order.
3403 * It may be better for some to be big-endian. See bug42804.
3406 typedef struct efx_filter_spec_s {
3407 efx_filter_match_flags_t efs_match_flags;
3408 uint8_t efs_priority;
3409 efx_filter_flags_t efs_flags;
3410 uint16_t efs_dmaq_id;
3411 uint32_t efs_rss_context;
3414 * Saved lower-priority filter. If it is set, it is restored on
3415 * filter delete operation.
3417 struct efx_filter_spec_s *efs_overridden_spec;
3418 /* Fields below here are hashed for software filter lookup */
3419 uint16_t efs_outer_vid;
3420 uint16_t efs_inner_vid;
3421 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3422 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3423 uint16_t efs_ether_type;
3424 uint8_t efs_ip_proto;
3425 efx_tunnel_protocol_t efs_encap_type;
3426 uint16_t efs_loc_port;
3427 uint16_t efs_rem_port;
3428 efx_oword_t efs_rem_host;
3429 efx_oword_t efs_loc_host;
3430 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3431 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3432 } efx_filter_spec_t;
3435 /* Default values for use in filter specifications */
3436 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3437 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3440 extern __checkReturn efx_rc_t
3442 __in efx_nic_t *enp);
3447 __in efx_nic_t *enp);
3450 extern __checkReturn efx_rc_t
3452 __in efx_nic_t *enp,
3453 __inout efx_filter_spec_t *spec);
3456 extern __checkReturn efx_rc_t
3458 __in efx_nic_t *enp,
3459 __inout efx_filter_spec_t *spec);
3462 extern __checkReturn efx_rc_t
3464 __in efx_nic_t *enp);
3467 extern __checkReturn efx_rc_t
3468 efx_filter_supported_filters(
3469 __in efx_nic_t *enp,
3470 __out_ecount(buffer_length) uint32_t *buffer,
3471 __in size_t buffer_length,
3472 __out size_t *list_lengthp);
3476 efx_filter_spec_init_rx(
3477 __out efx_filter_spec_t *spec,
3478 __in efx_filter_priority_t priority,
3479 __in efx_filter_flags_t flags,
3480 __in efx_rxq_t *erp);
3484 efx_filter_spec_init_tx(
3485 __out efx_filter_spec_t *spec,
3486 __in efx_txq_t *etp);
3489 extern __checkReturn efx_rc_t
3490 efx_filter_spec_set_ipv4_local(
3491 __inout efx_filter_spec_t *spec,
3494 __in uint16_t port);
3497 extern __checkReturn efx_rc_t
3498 efx_filter_spec_set_ipv4_full(
3499 __inout efx_filter_spec_t *spec,
3501 __in uint32_t lhost,
3502 __in uint16_t lport,
3503 __in uint32_t rhost,
3504 __in uint16_t rport);
3507 extern __checkReturn efx_rc_t
3508 efx_filter_spec_set_eth_local(
3509 __inout efx_filter_spec_t *spec,
3511 __in const uint8_t *addr);
3515 efx_filter_spec_set_ether_type(
3516 __inout efx_filter_spec_t *spec,
3517 __in uint16_t ether_type);
3520 extern __checkReturn efx_rc_t
3521 efx_filter_spec_set_uc_def(
3522 __inout efx_filter_spec_t *spec);
3525 extern __checkReturn efx_rc_t
3526 efx_filter_spec_set_mc_def(
3527 __inout efx_filter_spec_t *spec);
3529 typedef enum efx_filter_inner_frame_match_e {
3530 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3531 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3532 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3533 } efx_filter_inner_frame_match_t;
3536 extern __checkReturn efx_rc_t
3537 efx_filter_spec_set_encap_type(
3538 __inout efx_filter_spec_t *spec,
3539 __in efx_tunnel_protocol_t encap_type,
3540 __in efx_filter_inner_frame_match_t inner_frame_match);
3543 extern __checkReturn efx_rc_t
3544 efx_filter_spec_set_vxlan(
3545 __inout efx_filter_spec_t *spec,
3546 __in const uint8_t *vni,
3547 __in const uint8_t *inner_addr,
3548 __in const uint8_t *outer_addr);
3551 extern __checkReturn efx_rc_t
3552 efx_filter_spec_set_geneve(
3553 __inout efx_filter_spec_t *spec,
3554 __in const uint8_t *vni,
3555 __in const uint8_t *inner_addr,
3556 __in const uint8_t *outer_addr);
3559 extern __checkReturn efx_rc_t
3560 efx_filter_spec_set_nvgre(
3561 __inout efx_filter_spec_t *spec,
3562 __in const uint8_t *vsid,
3563 __in const uint8_t *inner_addr,
3564 __in const uint8_t *outer_addr);
3566 #if EFSYS_OPT_RX_SCALE
3568 extern __checkReturn efx_rc_t
3569 efx_filter_spec_set_rss_context(
3570 __inout efx_filter_spec_t *spec,
3571 __in uint32_t rss_context);
3573 #endif /* EFSYS_OPT_FILTER */
3578 extern __checkReturn uint32_t
3580 __in_ecount(count) uint32_t const *input,
3582 __in uint32_t init);
3585 extern __checkReturn uint32_t
3587 __in_ecount(length) uint8_t const *input,
3589 __in uint32_t init);
3591 #if EFSYS_OPT_LICENSING
3595 typedef struct efx_key_stats_s {
3597 uint32_t eks_invalid;
3598 uint32_t eks_blacklisted;
3599 uint32_t eks_unverifiable;
3600 uint32_t eks_wrong_node;
3601 uint32_t eks_licensed_apps_lo;
3602 uint32_t eks_licensed_apps_hi;
3603 uint32_t eks_licensed_features_lo;
3604 uint32_t eks_licensed_features_hi;
3608 extern __checkReturn efx_rc_t
3610 __in efx_nic_t *enp);
3615 __in efx_nic_t *enp);
3618 extern __checkReturn boolean_t
3619 efx_lic_check_support(
3620 __in efx_nic_t *enp);
3623 extern __checkReturn efx_rc_t
3624 efx_lic_update_licenses(
3625 __in efx_nic_t *enp);
3628 extern __checkReturn efx_rc_t
3629 efx_lic_get_key_stats(
3630 __in efx_nic_t *enp,
3631 __out efx_key_stats_t *ksp);
3634 extern __checkReturn efx_rc_t
3636 __in efx_nic_t *enp,
3637 __in uint64_t app_id,
3638 __out boolean_t *licensedp);
3641 extern __checkReturn efx_rc_t
3643 __in efx_nic_t *enp,
3644 __in size_t buffer_size,
3645 __out uint32_t *typep,
3646 __out size_t *lengthp,
3647 __out_opt uint8_t *bufferp);
3651 extern __checkReturn efx_rc_t
3653 __in efx_nic_t *enp,
3654 __in_bcount(buffer_size)
3656 __in size_t buffer_size,
3657 __out uint32_t *startp);
3660 extern __checkReturn efx_rc_t
3662 __in efx_nic_t *enp,
3663 __in_bcount(buffer_size)
3665 __in size_t buffer_size,
3666 __in uint32_t offset,
3667 __out uint32_t *endp);
3670 extern __checkReturn __success(return != B_FALSE) boolean_t
3672 __in efx_nic_t *enp,
3673 __in_bcount(buffer_size)
3675 __in size_t buffer_size,
3676 __in uint32_t offset,
3677 __out uint32_t *startp,
3678 __out uint32_t *lengthp);
3681 extern __checkReturn __success(return != B_FALSE) boolean_t
3682 efx_lic_validate_key(
3683 __in efx_nic_t *enp,
3684 __in_bcount(length) caddr_t keyp,
3685 __in uint32_t length);
3688 extern __checkReturn efx_rc_t
3690 __in efx_nic_t *enp,
3691 __in_bcount(buffer_size)
3693 __in size_t buffer_size,
3694 __in uint32_t offset,
3695 __in uint32_t length,
3696 __out_bcount_part(key_max_size, *lengthp)
3698 __in size_t key_max_size,
3699 __out uint32_t *lengthp);
3702 extern __checkReturn efx_rc_t
3704 __in efx_nic_t *enp,
3705 __in_bcount(buffer_size)
3707 __in size_t buffer_size,
3708 __in uint32_t offset,
3709 __in_bcount(length) caddr_t keyp,
3710 __in uint32_t length,
3711 __out uint32_t *lengthp);
3714 extern __checkReturn efx_rc_t
3716 __in efx_nic_t *enp,
3717 __in_bcount(buffer_size)
3719 __in size_t buffer_size,
3720 __in uint32_t offset,
3721 __in uint32_t length,
3723 __out uint32_t *deltap);
3726 extern __checkReturn efx_rc_t
3727 efx_lic_create_partition(
3728 __in efx_nic_t *enp,
3729 __in_bcount(buffer_size)
3731 __in size_t buffer_size);
3733 extern __checkReturn efx_rc_t
3734 efx_lic_finish_partition(
3735 __in efx_nic_t *enp,
3736 __in_bcount(buffer_size)
3738 __in size_t buffer_size);
3740 #endif /* EFSYS_OPT_LICENSING */
3744 #if EFSYS_OPT_TUNNEL
3747 extern __checkReturn efx_rc_t
3749 __in efx_nic_t *enp);
3754 __in efx_nic_t *enp);
3757 * For overlay network encapsulation using UDP, the firmware needs to know
3758 * the configured UDP port for the overlay so it can decode encapsulated
3760 * The UDP port/protocol list is global.
3764 extern __checkReturn efx_rc_t
3765 efx_tunnel_config_udp_add(
3766 __in efx_nic_t *enp,
3767 __in uint16_t port /* host/cpu-endian */,
3768 __in efx_tunnel_protocol_t protocol);
3771 * Returns EBUSY if reconfiguration of the port is in progress in other thread.
3774 extern __checkReturn efx_rc_t
3775 efx_tunnel_config_udp_remove(
3776 __in efx_nic_t *enp,
3777 __in uint16_t port /* host/cpu-endian */,
3778 __in efx_tunnel_protocol_t protocol);
3781 * Returns EBUSY if reconfiguration of any of the tunnel entries
3782 * is in progress in other thread.
3785 extern __checkReturn efx_rc_t
3786 efx_tunnel_config_clear(
3787 __in efx_nic_t *enp);
3790 * Apply tunnel UDP ports configuration to hardware.
3792 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3796 extern __checkReturn efx_rc_t
3797 efx_tunnel_reconfigure(
3798 __in efx_nic_t *enp);
3800 #endif /* EFSYS_OPT_TUNNEL */
3802 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3805 * Firmware subvariant choice options.
3807 * It may be switched to no Tx checksum if attached drivers are either
3808 * preboot or firmware subvariant aware and no VIS are allocated.
3809 * If may be always switched to default explicitly using set request or
3810 * implicitly if unaware driver is attaching. If switching is done when
3811 * a driver is attached, it gets MC_REBOOT event and should recreate its
3814 * See SF-119419-TC DPDK Firmware Driver Interface and
3815 * SF-109306-TC EF10 for Driver Writers for details.
3817 typedef enum efx_nic_fw_subvariant_e {
3818 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3819 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3820 EFX_NIC_FW_SUBVARIANT_NTYPES
3821 } efx_nic_fw_subvariant_t;
3824 extern __checkReturn efx_rc_t
3825 efx_nic_get_fw_subvariant(
3826 __in efx_nic_t *enp,
3827 __out efx_nic_fw_subvariant_t *subvariantp);
3830 extern __checkReturn efx_rc_t
3831 efx_nic_set_fw_subvariant(
3832 __in efx_nic_t *enp,
3833 __in efx_nic_fw_subvariant_t subvariant);
3835 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3837 typedef enum efx_phy_fec_type_e {
3838 EFX_PHY_FEC_NONE = 0,
3841 } efx_phy_fec_type_t;
3844 extern __checkReturn efx_rc_t
3845 efx_phy_fec_type_get(
3846 __in efx_nic_t *enp,
3847 __out efx_phy_fec_type_t *typep);
3849 typedef struct efx_phy_link_state_s {
3850 uint32_t epls_adv_cap_mask;
3851 uint32_t epls_lp_cap_mask;
3852 uint32_t epls_ld_cap_mask;
3853 unsigned int epls_fcntl;
3854 efx_phy_fec_type_t epls_fec;
3855 efx_link_mode_t epls_link_mode;
3856 } efx_phy_link_state_t;
3859 extern __checkReturn efx_rc_t
3860 efx_phy_link_state_get(
3861 __in efx_nic_t *enp,
3862 __out efx_phy_link_state_t *eplsp);
3867 typedef uint32_t efx_vswitch_id_t;
3868 typedef uint32_t efx_vport_id_t;
3870 typedef enum efx_vswitch_type_e {
3871 EFX_VSWITCH_TYPE_VLAN = 1,
3872 EFX_VSWITCH_TYPE_VEB,
3873 /* VSWITCH_TYPE_VEPA: obsolete */
3874 EFX_VSWITCH_TYPE_MUX = 4,
3875 } efx_vswitch_type_t;
3877 typedef enum efx_vport_type_e {
3878 EFX_VPORT_TYPE_NORMAL = 4,
3879 EFX_VPORT_TYPE_EXPANSION,
3880 EFX_VPORT_TYPE_TEST,
3883 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3884 #define EFX_FILTER_VID_UNSPEC 0xffff
3885 #define EFX_DEFAULT_VSWITCH_ID 1
3887 /* Default VF VLAN ID on creation */
3888 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3889 #define EFX_VPORT_ID_INVALID 0
3891 typedef struct efx_vport_config_s {
3892 /* Either VF index or EFX_PCI_VF_INVALID for PF */
3893 uint16_t evc_function;
3894 /* VLAN ID of the associated function */
3896 /* vport id shared with client driver */
3897 efx_vport_id_t evc_vport_id;
3898 /* MAC address of the associated function */
3899 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3901 * vports created with this flag set may only transfer traffic on the
3902 * VLANs permitted by the vport. Also, an attempt to install filter with
3903 * VLAN will be refused unless requesting function has VLAN privilege.
3905 boolean_t evc_vlan_restrict;
3906 /* Whether this function is assigned or not */
3907 boolean_t evc_vport_assigned;
3908 } efx_vport_config_t;
3910 typedef struct efx_vswitch_s efx_vswitch_t;
3913 extern __checkReturn efx_rc_t
3915 __in efx_nic_t *enp);
3920 __in efx_nic_t *enp);
3923 extern __checkReturn efx_rc_t
3924 efx_evb_vswitch_create(
3925 __in efx_nic_t *enp,
3926 __in uint32_t num_vports,
3927 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3928 __deref_out efx_vswitch_t **evpp);
3931 extern __checkReturn efx_rc_t
3932 efx_evb_vswitch_destroy(
3933 __in efx_nic_t *enp,
3934 __in efx_vswitch_t *evp);
3937 extern __checkReturn efx_rc_t
3938 efx_evb_vport_mac_set(
3939 __in efx_nic_t *enp,
3940 __in efx_vswitch_t *evp,
3941 __in efx_vport_id_t vport_id,
3942 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3945 extern __checkReturn efx_rc_t
3946 efx_evb_vport_vlan_set(
3947 __in efx_nic_t *enp,
3948 __in efx_vswitch_t *evp,
3949 __in efx_vport_id_t vport_id,
3953 extern __checkReturn efx_rc_t
3954 efx_evb_vport_reset(
3955 __in efx_nic_t *enp,
3956 __in efx_vswitch_t *evp,
3957 __in efx_vport_id_t vport_id,
3958 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3960 __out boolean_t *is_fn_resetp);
3963 extern __checkReturn efx_rc_t
3964 efx_evb_vport_stats(
3965 __in efx_nic_t *enp,
3966 __in efx_vswitch_t *evp,
3967 __in efx_vport_id_t vport_id,
3968 __out efsys_mem_t *stats_bufferp);
3970 #endif /* EFSYS_OPT_EVB */
3972 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3974 typedef struct efx_proxy_auth_config_s {
3975 efsys_mem_t *request_bufferp;
3976 efsys_mem_t *response_bufferp;
3977 efsys_mem_t *status_bufferp;
3981 uint32_t handled_privileges;
3982 } efx_proxy_auth_config_t;
3984 typedef struct efx_proxy_cmd_params_s {
3987 uint8_t *request_bufferp;
3988 size_t request_size;
3989 uint8_t *response_bufferp;
3990 size_t response_size;
3991 size_t *response_size_actualp;
3992 } efx_proxy_cmd_params_t;
3995 extern __checkReturn efx_rc_t
3996 efx_proxy_auth_init(
3997 __in efx_nic_t *enp);
4001 efx_proxy_auth_fini(
4002 __in efx_nic_t *enp);
4005 extern __checkReturn efx_rc_t
4006 efx_proxy_auth_configure(
4007 __in efx_nic_t *enp,
4008 __in efx_proxy_auth_config_t *configp);
4011 extern __checkReturn efx_rc_t
4012 efx_proxy_auth_destroy(
4013 __in efx_nic_t *enp,
4014 __in uint32_t handled_privileges);
4017 extern __checkReturn efx_rc_t
4018 efx_proxy_auth_complete_request(
4019 __in efx_nic_t *enp,
4020 __in uint32_t fn_index,
4021 __in uint32_t proxy_result,
4022 __in uint32_t handle);
4025 extern __checkReturn efx_rc_t
4026 efx_proxy_auth_exec_cmd(
4027 __in efx_nic_t *enp,
4028 __inout efx_proxy_cmd_params_t *paramsp);
4031 extern __checkReturn efx_rc_t
4032 efx_proxy_auth_set_privilege_mask(
4033 __in efx_nic_t *enp,
4034 __in uint32_t vf_index,
4036 __in uint32_t value);
4039 extern __checkReturn efx_rc_t
4040 efx_proxy_auth_privilege_mask_get(
4041 __in efx_nic_t *enp,
4042 __in uint32_t pf_index,
4043 __in uint32_t vf_index,
4044 __out uint32_t *maskp);
4047 extern __checkReturn efx_rc_t
4048 efx_proxy_auth_privilege_modify(
4049 __in efx_nic_t *enp,
4050 __in uint32_t pf_index,
4051 __in uint32_t vf_index,
4052 __in uint32_t add_privileges_mask,
4053 __in uint32_t remove_privileges_mask);
4055 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
4060 extern __checkReturn efx_rc_t
4062 __in efx_nic_t *enp);
4067 __in efx_nic_t *enp);
4069 typedef struct efx_mae_limits_s {
4070 uint32_t eml_max_n_action_prios;
4071 uint32_t eml_max_n_outer_prios;
4072 uint32_t eml_encap_types_supported;
4076 extern __checkReturn efx_rc_t
4078 __in efx_nic_t *enp,
4079 __out efx_mae_limits_t *emlp);
4081 typedef enum efx_mae_rule_type_e {
4082 EFX_MAE_RULE_ACTION = 0,
4086 } efx_mae_rule_type_t;
4088 typedef struct efx_mae_match_spec_s efx_mae_match_spec_t;
4091 extern __checkReturn efx_rc_t
4092 efx_mae_match_spec_init(
4093 __in efx_nic_t *enp,
4094 __in efx_mae_rule_type_t type,
4096 __out efx_mae_match_spec_t **specp);
4100 efx_mae_match_spec_fini(
4101 __in efx_nic_t *enp,
4102 __in efx_mae_match_spec_t *spec);
4104 typedef enum efx_mae_field_id_e {
4105 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR = 0,
4106 EFX_MAE_FIELD_ETHER_TYPE_BE,
4107 EFX_MAE_FIELD_ETH_SADDR_BE,
4108 EFX_MAE_FIELD_ETH_DADDR_BE,
4109 EFX_MAE_FIELD_VLAN0_TCI_BE,
4110 EFX_MAE_FIELD_VLAN0_PROTO_BE,
4111 EFX_MAE_FIELD_VLAN1_TCI_BE,
4112 EFX_MAE_FIELD_VLAN1_PROTO_BE,
4113 EFX_MAE_FIELD_SRC_IP4_BE,
4114 EFX_MAE_FIELD_DST_IP4_BE,
4115 EFX_MAE_FIELD_IP_PROTO,
4116 EFX_MAE_FIELD_IP_TOS,
4117 EFX_MAE_FIELD_IP_TTL,
4118 EFX_MAE_FIELD_SRC_IP6_BE,
4119 EFX_MAE_FIELD_DST_IP6_BE,
4120 EFX_MAE_FIELD_L4_SPORT_BE,
4121 EFX_MAE_FIELD_L4_DPORT_BE,
4122 EFX_MAE_FIELD_TCP_FLAGS_BE,
4123 EFX_MAE_FIELD_ENC_ETHER_TYPE_BE,
4124 EFX_MAE_FIELD_ENC_ETH_SADDR_BE,
4125 EFX_MAE_FIELD_ENC_ETH_DADDR_BE,
4126 EFX_MAE_FIELD_ENC_VLAN0_TCI_BE,
4127 EFX_MAE_FIELD_ENC_VLAN0_PROTO_BE,
4128 EFX_MAE_FIELD_ENC_VLAN1_TCI_BE,
4129 EFX_MAE_FIELD_ENC_VLAN1_PROTO_BE,
4130 EFX_MAE_FIELD_ENC_SRC_IP4_BE,
4131 EFX_MAE_FIELD_ENC_DST_IP4_BE,
4132 EFX_MAE_FIELD_ENC_IP_PROTO,
4133 EFX_MAE_FIELD_ENC_IP_TOS,
4134 EFX_MAE_FIELD_ENC_IP_TTL,
4135 EFX_MAE_FIELD_ENC_SRC_IP6_BE,
4136 EFX_MAE_FIELD_ENC_DST_IP6_BE,
4137 EFX_MAE_FIELD_ENC_L4_SPORT_BE,
4138 EFX_MAE_FIELD_ENC_L4_DPORT_BE,
4139 EFX_MAE_FIELD_ENC_VNET_ID_BE,
4140 EFX_MAE_FIELD_OUTER_RULE_ID,
4143 } efx_mae_field_id_t;
4145 /* MPORT selector. Used to refer to MPORTs in match/action rules. */
4146 typedef struct efx_mport_sel_s {
4150 #define EFX_MPORT_NULL (0U)
4153 * Get MPORT selector of a physical port.
4155 * The resulting MPORT selector is opaque to the caller and can be
4156 * passed as an argument to efx_mae_match_spec_mport_set()
4157 * and efx_mae_action_set_populate_deliver().
4160 extern __checkReturn efx_rc_t
4161 efx_mae_mport_by_phy_port(
4162 __in uint32_t phy_port,
4163 __out efx_mport_sel_t *mportp);
4166 * Get MPORT selector of a PCIe function.
4168 * The resulting MPORT selector is opaque to the caller and can be
4169 * passed as an argument to efx_mae_match_spec_mport_set()
4170 * and efx_mae_action_set_populate_deliver().
4173 extern __checkReturn efx_rc_t
4174 efx_mae_mport_by_pcie_function(
4177 __out efx_mport_sel_t *mportp);
4180 * Fields which have BE postfix in their named constants are expected
4181 * to be passed by callers in big-endian byte order. They will appear
4182 * in the MCDI buffer, which is a part of the match specification, in
4183 * the very same byte order, that is, no conversion will be performed.
4185 * Fields which don't have BE postfix in their named constants are in
4186 * host byte order. MCDI expects them to be little-endian, so the API
4187 * will take care to carry out conversion to little-endian byte order.
4188 * At the moment, the only field in host byte order is MPORT selector.
4191 extern __checkReturn efx_rc_t
4192 efx_mae_match_spec_field_set(
4193 __in efx_mae_match_spec_t *spec,
4194 __in efx_mae_field_id_t field_id,
4195 __in size_t value_size,
4196 __in_bcount(value_size) const uint8_t *value,
4197 __in size_t mask_size,
4198 __in_bcount(mask_size) const uint8_t *mask);
4200 /* If the mask argument is NULL, the API will use full mask by default. */
4202 extern __checkReturn efx_rc_t
4203 efx_mae_match_spec_mport_set(
4204 __in efx_mae_match_spec_t *spec,
4205 __in const efx_mport_sel_t *valuep,
4206 __in_opt const efx_mport_sel_t *maskp);
4209 extern __checkReturn boolean_t
4210 efx_mae_match_specs_equal(
4211 __in const efx_mae_match_spec_t *left,
4212 __in const efx_mae_match_spec_t *right);
4215 * Make sure that match fields known by EFX have proper masks set
4216 * in the match specification as per requirements of SF-122526-TC.
4218 * In the case efx_mae_field_id_t lacks named identifiers for any
4219 * fields which the FW maintains with support status MATCH_ALWAYS,
4220 * the validation result may not be accurate.
4223 extern __checkReturn boolean_t
4224 efx_mae_match_spec_is_valid(
4225 __in efx_nic_t *enp,
4226 __in const efx_mae_match_spec_t *spec);
4228 typedef struct efx_mae_actions_s efx_mae_actions_t;
4231 extern __checkReturn efx_rc_t
4232 efx_mae_action_set_spec_init(
4233 __in efx_nic_t *enp,
4234 __out efx_mae_actions_t **specp);
4238 efx_mae_action_set_spec_fini(
4239 __in efx_nic_t *enp,
4240 __in efx_mae_actions_t *spec);
4243 extern __checkReturn efx_rc_t
4244 efx_mae_action_set_populate_vlan_pop(
4245 __in efx_mae_actions_t *spec);
4248 extern __checkReturn efx_rc_t
4249 efx_mae_action_set_populate_vlan_push(
4250 __in efx_mae_actions_t *spec,
4251 __in uint16_t tpid_be,
4252 __in uint16_t tci_be);
4255 extern __checkReturn efx_rc_t
4256 efx_mae_action_set_populate_flag(
4257 __in efx_mae_actions_t *spec);
4260 extern __checkReturn efx_rc_t
4261 efx_mae_action_set_populate_mark(
4262 __in efx_mae_actions_t *spec,
4263 __in uint32_t mark_value);
4266 extern __checkReturn efx_rc_t
4267 efx_mae_action_set_populate_deliver(
4268 __in efx_mae_actions_t *spec,
4269 __in const efx_mport_sel_t *mportp);
4272 extern __checkReturn efx_rc_t
4273 efx_mae_action_set_populate_drop(
4274 __in efx_mae_actions_t *spec);
4277 extern __checkReturn boolean_t
4278 efx_mae_action_set_specs_equal(
4279 __in const efx_mae_actions_t *left,
4280 __in const efx_mae_actions_t *right);
4283 * Conduct a comparison to check whether two match specifications
4284 * of equal rule type (action / outer) and priority would map to
4285 * the very same rule class from the firmware's standpoint.
4288 extern __checkReturn efx_rc_t
4289 efx_mae_match_specs_class_cmp(
4290 __in efx_nic_t *enp,
4291 __in const efx_mae_match_spec_t *left,
4292 __in const efx_mae_match_spec_t *right,
4293 __out boolean_t *have_same_classp);
4295 #define EFX_MAE_RSRC_ID_INVALID UINT32_MAX
4298 typedef struct efx_mae_rule_id_s {
4300 } efx_mae_rule_id_t;
4303 extern __checkReturn efx_rc_t
4304 efx_mae_outer_rule_insert(
4305 __in efx_nic_t *enp,
4306 __in const efx_mae_match_spec_t *spec,
4307 __in efx_tunnel_protocol_t encap_type,
4308 __out efx_mae_rule_id_t *or_idp);
4311 extern __checkReturn efx_rc_t
4312 efx_mae_outer_rule_remove(
4313 __in efx_nic_t *enp,
4314 __in const efx_mae_rule_id_t *or_idp);
4317 extern __checkReturn efx_rc_t
4318 efx_mae_match_spec_outer_rule_id_set(
4319 __in efx_mae_match_spec_t *spec,
4320 __in const efx_mae_rule_id_t *or_idp);
4323 typedef struct efx_mae_aset_id_s {
4325 } efx_mae_aset_id_t;
4328 extern __checkReturn efx_rc_t
4329 efx_mae_action_set_alloc(
4330 __in efx_nic_t *enp,
4331 __in const efx_mae_actions_t *spec,
4332 __out efx_mae_aset_id_t *aset_idp);
4335 extern __checkReturn efx_rc_t
4336 efx_mae_action_set_free(
4337 __in efx_nic_t *enp,
4338 __in const efx_mae_aset_id_t *aset_idp);
4340 /* Action set list ID */
4341 typedef struct efx_mae_aset_list_id_s {
4343 } efx_mae_aset_list_id_t;
4346 * Either action set list ID or action set ID must be passed to this API,
4350 extern __checkReturn efx_rc_t
4351 efx_mae_action_rule_insert(
4352 __in efx_nic_t *enp,
4353 __in const efx_mae_match_spec_t *spec,
4354 __in const efx_mae_aset_list_id_t *asl_idp,
4355 __in const efx_mae_aset_id_t *as_idp,
4356 __out efx_mae_rule_id_t *ar_idp);
4359 extern __checkReturn efx_rc_t
4360 efx_mae_action_rule_remove(
4361 __in efx_nic_t *enp,
4362 __in const efx_mae_rule_id_t *ar_idp);
4364 #endif /* EFSYS_OPT_MAE */
4370 #endif /* _SYS_EFX_H */