1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019-2020 Xilinx, Inc.
4 * Copyright(c) 2006-2019 Solarflare Communications Inc.
10 #include "efx_annote.h"
12 #include "efx_types.h"
13 #include "efx_check.h"
14 #include "efx_phy_ids.h"
20 #define EFX_STATIC_ASSERT(_cond) \
21 ((void)sizeof (char[(_cond) ? 1 : -1]))
23 #define EFX_ARRAY_SIZE(_array) \
24 (sizeof (_array) / sizeof ((_array)[0]))
26 #define EFX_FIELD_OFFSET(_type, _field) \
27 ((size_t)&(((_type *)0)->_field))
29 /* The macro expands divider twice */
30 #define EFX_DIV_ROUND_UP(_n, _d) (((_n) + (_d) - 1) / (_d))
32 /* Round value up to the nearest power of two. */
33 #define EFX_P2ROUNDUP(_type, _value, _align) \
34 (-(-(_type)(_value) & -(_type)(_align)))
36 /* Align value down to the nearest power of two. */
37 #define EFX_P2ALIGN(_type, _value, _align) \
38 ((_type)(_value) & -(_type)(_align))
40 /* Test if value is power of 2 aligned. */
41 #define EFX_IS_P2ALIGNED(_type, _value, _align) \
42 ((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
46 typedef __success(return == 0) int efx_rc_t;
51 typedef enum efx_family_e {
53 EFX_FAMILY_FALCON, /* Obsolete and not supported */
55 EFX_FAMILY_HUNTINGTON,
62 typedef enum efx_bar_type_e {
67 typedef struct efx_bar_region_s {
68 efx_bar_type_t ebr_type;
70 efsys_dma_addr_t ebr_offset;
71 efsys_dma_addr_t ebr_length;
74 /* The function is deprecated. It is used only if Riverhead is not supported. */
76 extern __checkReturn efx_rc_t
80 __out efx_family_t *efp,
81 __out unsigned int *membarp);
85 typedef struct efx_pci_ops_s {
87 * Function for reading PCIe configuration space.
89 * espcp System-specific PCIe device handle;
90 * offset Offset inside PCIe configuration space to start reading
92 * edp EFX DWORD structure that should be populated by function
93 * in little-endian order;
95 * Returns status code, 0 on success, any other value on error.
97 efx_rc_t (*epo_config_readd)(efsys_pci_config_t *espcp,
98 uint32_t offset, efx_dword_t *edp);
100 * Function for finding PCIe memory bar handle by its index from a PCIe
101 * device handle. The found memory bar is available in read-only mode.
103 * configp System-specific PCIe device handle;
104 * index Memory bar index;
105 * memp Pointer to the found memory bar handle;
107 * Returns status code, 0 on success, any other value on error.
109 efx_rc_t (*epo_find_mem_bar)(efsys_pci_config_t *configp,
110 int index, efsys_bar_t *memp);
113 /* Determine EFX family and perform lookup of the function control window
115 * The function requires PCI config handle from which all memory bars can
117 * A user of the API must be aware of memory bars indexes (not available
121 extern __checkReturn efx_rc_t
122 efx_family_probe_bar(
125 __in efsys_pci_config_t *espcp,
126 __in const efx_pci_ops_t *epop,
127 __out efx_family_t *efp,
128 __out efx_bar_region_t *ebrp);
130 #endif /* EFSYS_OPT_PCI */
133 #define EFX_PCI_VENID_SFC 0x1924
134 #define EFX_PCI_VENID_XILINX 0x10EE
136 #define EFX_PCI_DEVID_FALCON 0x0710 /* SFC4000 */
138 #define EFX_PCI_DEVID_BETHPAGE 0x0803 /* SFC9020 */
139 #define EFX_PCI_DEVID_SIENA 0x0813 /* SFL9021 */
140 #define EFX_PCI_DEVID_SIENA_F1_UNINIT 0x0810
142 #define EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT 0x0901
143 #define EFX_PCI_DEVID_FARMINGDALE 0x0903 /* SFC9120 PF */
144 #define EFX_PCI_DEVID_GREENPORT 0x0923 /* SFC9140 PF */
146 #define EFX_PCI_DEVID_FARMINGDALE_VF 0x1903 /* SFC9120 VF */
147 #define EFX_PCI_DEVID_GREENPORT_VF 0x1923 /* SFC9140 VF */
149 #define EFX_PCI_DEVID_MEDFORD_PF_UNINIT 0x0913
150 #define EFX_PCI_DEVID_MEDFORD 0x0A03 /* SFC9240 PF */
151 #define EFX_PCI_DEVID_MEDFORD_VF 0x1A03 /* SFC9240 VF */
153 #define EFX_PCI_DEVID_MEDFORD2_PF_UNINIT 0x0B13
154 #define EFX_PCI_DEVID_MEDFORD2 0x0B03 /* SFC9250 PF */
155 #define EFX_PCI_DEVID_MEDFORD2_VF 0x1B03 /* SFC9250 VF */
157 #define EFX_PCI_DEVID_RIVERHEAD 0x0100
158 #define EFX_PCI_DEVID_RIVERHEAD_VF 0x1100
160 #define EFX_MEM_BAR_SIENA 2
162 #define EFX_MEM_BAR_HUNTINGTON_PF 2
163 #define EFX_MEM_BAR_HUNTINGTON_VF 0
165 #define EFX_MEM_BAR_MEDFORD_PF 2
166 #define EFX_MEM_BAR_MEDFORD_VF 0
168 #define EFX_MEM_BAR_MEDFORD2 0
170 /* FIXME Fix it when memory bar is fixed in FPGA image. It must be 0. */
171 #define EFX_MEM_BAR_RIVERHEAD 2
179 EFX_ERR_BUFID_DC_OOB,
192 /* Calculate the IEEE 802.3 CRC32 of a MAC addr */
194 extern __checkReturn uint32_t
196 __in uint32_t crc_init,
197 __in_ecount(length) uint8_t const *input,
201 /* Type prototypes */
203 typedef struct efx_rxq_s efx_rxq_t;
207 typedef struct efx_nic_s efx_nic_t;
210 extern __checkReturn efx_rc_t
212 __in efx_family_t family,
213 __in efsys_identifier_t *esip,
214 __in efsys_bar_t *esbp,
215 __in uint32_t fcw_offset,
216 __in efsys_lock_t *eslp,
217 __deref_out efx_nic_t **enpp);
219 /* EFX_FW_VARIANT codes map one to one on MC_CMD_FW codes */
220 typedef enum efx_fw_variant_e {
221 EFX_FW_VARIANT_FULL_FEATURED,
222 EFX_FW_VARIANT_LOW_LATENCY,
223 EFX_FW_VARIANT_PACKED_STREAM,
224 EFX_FW_VARIANT_HIGH_TX_RATE,
225 EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1,
226 EFX_FW_VARIANT_RULES_ENGINE,
228 EFX_FW_VARIANT_DONT_CARE = 0xffffffff
232 extern __checkReturn efx_rc_t
235 __in efx_fw_variant_t efv);
238 extern __checkReturn efx_rc_t
240 __in efx_nic_t *enp);
243 extern __checkReturn efx_rc_t
245 __in efx_nic_t *enp);
248 extern __checkReturn boolean_t
249 efx_nic_hw_unavailable(
250 __in efx_nic_t *enp);
254 efx_nic_set_hw_unavailable(
255 __in efx_nic_t *enp);
260 extern __checkReturn efx_rc_t
261 efx_nic_register_test(
262 __in efx_nic_t *enp);
264 #endif /* EFSYS_OPT_DIAG */
269 __in efx_nic_t *enp);
274 __in efx_nic_t *enp);
279 __in efx_nic_t *enp);
281 #define EFX_PCIE_LINK_SPEED_GEN1 1
282 #define EFX_PCIE_LINK_SPEED_GEN2 2
283 #define EFX_PCIE_LINK_SPEED_GEN3 3
285 typedef enum efx_pcie_link_performance_e {
286 EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
287 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
288 EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
289 EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
290 } efx_pcie_link_performance_t;
293 extern __checkReturn efx_rc_t
294 efx_nic_calculate_pcie_link_bandwidth(
295 __in uint32_t pcie_link_width,
296 __in uint32_t pcie_link_gen,
297 __out uint32_t *bandwidth_mbpsp);
300 extern __checkReturn efx_rc_t
301 efx_nic_check_pcie_link_speed(
303 __in uint32_t pcie_link_width,
304 __in uint32_t pcie_link_gen,
305 __out efx_pcie_link_performance_t *resultp);
309 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
310 /* EF10 architecture and Riverhead NICs require MCDIv2 commands */
311 #define WITH_MCDI_V2 1
314 typedef struct efx_mcdi_req_s efx_mcdi_req_t;
316 typedef enum efx_mcdi_exception_e {
317 EFX_MCDI_EXCEPTION_MC_REBOOT,
318 EFX_MCDI_EXCEPTION_MC_BADASSERT,
319 } efx_mcdi_exception_t;
321 #if EFSYS_OPT_MCDI_LOGGING
322 typedef enum efx_log_msg_e {
324 EFX_LOG_MCDI_REQUEST,
325 EFX_LOG_MCDI_RESPONSE,
327 #endif /* EFSYS_OPT_MCDI_LOGGING */
329 typedef struct efx_mcdi_transport_s {
331 efsys_mem_t *emt_dma_mem;
332 void (*emt_execute)(void *, efx_mcdi_req_t *);
333 void (*emt_ev_cpl)(void *);
334 void (*emt_exception)(void *, efx_mcdi_exception_t);
335 #if EFSYS_OPT_MCDI_LOGGING
336 void (*emt_logger)(void *, efx_log_msg_t,
337 void *, size_t, void *, size_t);
338 #endif /* EFSYS_OPT_MCDI_LOGGING */
339 #if EFSYS_OPT_MCDI_PROXY_AUTH
340 void (*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
341 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
342 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
343 void (*emt_ev_proxy_request)(void *, uint32_t);
344 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
345 } efx_mcdi_transport_t;
348 extern __checkReturn efx_rc_t
351 __in const efx_mcdi_transport_t *mtp);
354 extern __checkReturn efx_rc_t
356 __in efx_nic_t *enp);
361 __in efx_nic_t *enp);
365 efx_mcdi_get_timeout(
367 __in efx_mcdi_req_t *emrp,
368 __out uint32_t *usec_timeoutp);
372 efx_mcdi_request_start(
374 __in efx_mcdi_req_t *emrp,
375 __in boolean_t ev_cpl);
378 extern __checkReturn boolean_t
379 efx_mcdi_request_poll(
380 __in efx_nic_t *enp);
383 extern __checkReturn boolean_t
384 efx_mcdi_request_abort(
385 __in efx_nic_t *enp);
390 __in efx_nic_t *enp);
392 #endif /* EFSYS_OPT_MCDI */
396 #define EFX_NINTR_SIENA 1024
398 typedef enum efx_intr_type_e {
399 EFX_INTR_INVALID = 0,
405 #define EFX_INTR_SIZE (sizeof (efx_oword_t))
408 extern __checkReturn efx_rc_t
411 __in efx_intr_type_t type,
412 __in_opt efsys_mem_t *esmp);
417 __in efx_nic_t *enp);
422 __in efx_nic_t *enp);
426 efx_intr_disable_unlocked(
427 __in efx_nic_t *enp);
429 #define EFX_INTR_NEVQS 32
432 extern __checkReturn efx_rc_t
435 __in unsigned int level);
439 efx_intr_status_line(
441 __out boolean_t *fatalp,
442 __out uint32_t *maskp);
446 efx_intr_status_message(
448 __in unsigned int message,
449 __out boolean_t *fatalp);
454 __in efx_nic_t *enp);
459 __in efx_nic_t *enp);
463 #if EFSYS_OPT_MAC_STATS
465 /* START MKCONFIG GENERATED EfxHeaderMacBlock ea466a9bc8789994 */
466 typedef enum efx_mac_stat_e {
469 EFX_MAC_RX_UNICST_PKTS,
470 EFX_MAC_RX_MULTICST_PKTS,
471 EFX_MAC_RX_BRDCST_PKTS,
472 EFX_MAC_RX_PAUSE_PKTS,
473 EFX_MAC_RX_LE_64_PKTS,
474 EFX_MAC_RX_65_TO_127_PKTS,
475 EFX_MAC_RX_128_TO_255_PKTS,
476 EFX_MAC_RX_256_TO_511_PKTS,
477 EFX_MAC_RX_512_TO_1023_PKTS,
478 EFX_MAC_RX_1024_TO_15XX_PKTS,
479 EFX_MAC_RX_GE_15XX_PKTS,
481 EFX_MAC_RX_FCS_ERRORS,
482 EFX_MAC_RX_DROP_EVENTS,
483 EFX_MAC_RX_FALSE_CARRIER_ERRORS,
484 EFX_MAC_RX_SYMBOL_ERRORS,
485 EFX_MAC_RX_ALIGN_ERRORS,
486 EFX_MAC_RX_INTERNAL_ERRORS,
487 EFX_MAC_RX_JABBER_PKTS,
488 EFX_MAC_RX_LANE0_CHAR_ERR,
489 EFX_MAC_RX_LANE1_CHAR_ERR,
490 EFX_MAC_RX_LANE2_CHAR_ERR,
491 EFX_MAC_RX_LANE3_CHAR_ERR,
492 EFX_MAC_RX_LANE0_DISP_ERR,
493 EFX_MAC_RX_LANE1_DISP_ERR,
494 EFX_MAC_RX_LANE2_DISP_ERR,
495 EFX_MAC_RX_LANE3_DISP_ERR,
496 EFX_MAC_RX_MATCH_FAULT,
497 EFX_MAC_RX_NODESC_DROP_CNT,
500 EFX_MAC_TX_UNICST_PKTS,
501 EFX_MAC_TX_MULTICST_PKTS,
502 EFX_MAC_TX_BRDCST_PKTS,
503 EFX_MAC_TX_PAUSE_PKTS,
504 EFX_MAC_TX_LE_64_PKTS,
505 EFX_MAC_TX_65_TO_127_PKTS,
506 EFX_MAC_TX_128_TO_255_PKTS,
507 EFX_MAC_TX_256_TO_511_PKTS,
508 EFX_MAC_TX_512_TO_1023_PKTS,
509 EFX_MAC_TX_1024_TO_15XX_PKTS,
510 EFX_MAC_TX_GE_15XX_PKTS,
512 EFX_MAC_TX_SGL_COL_PKTS,
513 EFX_MAC_TX_MULT_COL_PKTS,
514 EFX_MAC_TX_EX_COL_PKTS,
515 EFX_MAC_TX_LATE_COL_PKTS,
517 EFX_MAC_TX_EX_DEF_PKTS,
518 EFX_MAC_PM_TRUNC_BB_OVERFLOW,
519 EFX_MAC_PM_DISCARD_BB_OVERFLOW,
520 EFX_MAC_PM_TRUNC_VFIFO_FULL,
521 EFX_MAC_PM_DISCARD_VFIFO_FULL,
522 EFX_MAC_PM_TRUNC_QBB,
523 EFX_MAC_PM_DISCARD_QBB,
524 EFX_MAC_PM_DISCARD_MAPPING,
525 EFX_MAC_RXDP_Q_DISABLED_PKTS,
526 EFX_MAC_RXDP_DI_DROPPED_PKTS,
527 EFX_MAC_RXDP_STREAMING_PKTS,
528 EFX_MAC_RXDP_HLB_FETCH,
529 EFX_MAC_RXDP_HLB_WAIT,
530 EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
531 EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
532 EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
533 EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
534 EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
535 EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
536 EFX_MAC_VADAPTER_RX_BAD_PACKETS,
537 EFX_MAC_VADAPTER_RX_BAD_BYTES,
538 EFX_MAC_VADAPTER_RX_OVERFLOW,
539 EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
540 EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
541 EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
542 EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
543 EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
544 EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
545 EFX_MAC_VADAPTER_TX_BAD_PACKETS,
546 EFX_MAC_VADAPTER_TX_BAD_BYTES,
547 EFX_MAC_VADAPTER_TX_OVERFLOW,
548 EFX_MAC_FEC_UNCORRECTED_ERRORS,
549 EFX_MAC_FEC_CORRECTED_ERRORS,
550 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE0,
551 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE1,
552 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE2,
553 EFX_MAC_FEC_CORRECTED_SYMBOLS_LANE3,
554 EFX_MAC_CTPIO_VI_BUSY_FALLBACK,
555 EFX_MAC_CTPIO_LONG_WRITE_SUCCESS,
556 EFX_MAC_CTPIO_MISSING_DBELL_FAIL,
557 EFX_MAC_CTPIO_OVERFLOW_FAIL,
558 EFX_MAC_CTPIO_UNDERFLOW_FAIL,
559 EFX_MAC_CTPIO_TIMEOUT_FAIL,
560 EFX_MAC_CTPIO_NONCONTIG_WR_FAIL,
561 EFX_MAC_CTPIO_FRM_CLOBBER_FAIL,
562 EFX_MAC_CTPIO_INVALID_WR_FAIL,
563 EFX_MAC_CTPIO_VI_CLOBBER_FALLBACK,
564 EFX_MAC_CTPIO_UNQUALIFIED_FALLBACK,
565 EFX_MAC_CTPIO_RUNT_FALLBACK,
566 EFX_MAC_CTPIO_SUCCESS,
567 EFX_MAC_CTPIO_FALLBACK,
568 EFX_MAC_CTPIO_POISON,
570 EFX_MAC_RXDP_SCATTER_DISABLED_TRUNC,
571 EFX_MAC_RXDP_HLB_IDLE,
572 EFX_MAC_RXDP_HLB_TIMEOUT,
576 /* END MKCONFIG GENERATED EfxHeaderMacBlock */
578 #endif /* EFSYS_OPT_MAC_STATS */
580 typedef enum efx_link_mode_e {
581 EFX_LINK_UNKNOWN = 0,
597 #define EFX_MAC_ADDR_LEN 6
599 #define EFX_VNI_OR_VSID_LEN 3
601 #define EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
603 #define EFX_MAC_MULTICAST_LIST_MAX 256
605 #define EFX_MAC_SDU_MAX 9202
607 #define EFX_MAC_PDU_ADJUSTMENT \
611 + /* bug16011 */ 16) \
613 #define EFX_MAC_PDU(_sdu) \
614 EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
617 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
618 * the SDU rounded up slightly.
620 #define EFX_MAC_SDU_FROM_PDU(_pdu) ((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
622 #define EFX_MAC_PDU_MIN 60
623 #define EFX_MAC_PDU_MAX EFX_MAC_PDU(EFX_MAC_SDU_MAX)
626 extern __checkReturn efx_rc_t
632 extern __checkReturn efx_rc_t
638 extern __checkReturn efx_rc_t
644 extern __checkReturn efx_rc_t
647 __in boolean_t all_unicst,
648 __in boolean_t mulcst,
649 __in boolean_t all_mulcst,
650 __in boolean_t brdcst);
654 efx_mac_filter_get_all_ucast_mcast(
656 __out boolean_t *all_unicst,
657 __out boolean_t *all_mulcst);
660 extern __checkReturn efx_rc_t
661 efx_mac_multicast_list_set(
663 __in_ecount(6*count) uint8_t const *addrs,
667 extern __checkReturn efx_rc_t
668 efx_mac_filter_default_rxq_set(
671 __in boolean_t using_rss);
675 efx_mac_filter_default_rxq_clear(
676 __in efx_nic_t *enp);
679 extern __checkReturn efx_rc_t
682 __in boolean_t enabled);
685 extern __checkReturn efx_rc_t
688 __out boolean_t *mac_upp);
690 #define EFX_FCNTL_RESPOND 0x00000001
691 #define EFX_FCNTL_GENERATE 0x00000002
694 extern __checkReturn efx_rc_t
697 __in unsigned int fcntl,
698 __in boolean_t autoneg);
704 __out unsigned int *fcntl_wantedp,
705 __out unsigned int *fcntl_linkp);
708 #if EFSYS_OPT_MAC_STATS
713 extern __checkReturn const char *
716 __in unsigned int id);
718 #endif /* EFSYS_OPT_NAMES */
720 #define EFX_MAC_STATS_MASK_BITS_PER_PAGE (8 * sizeof (uint32_t))
722 #define EFX_MAC_STATS_MASK_NPAGES \
723 (EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS, \
724 EFX_MAC_STATS_MASK_BITS_PER_PAGE) / \
725 EFX_MAC_STATS_MASK_BITS_PER_PAGE)
728 * Get mask of MAC statistics supported by the hardware.
730 * If mask_size is insufficient to return the mask, EINVAL error is
731 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
732 * (which is sizeof (uint32_t)) is sufficient.
735 extern __checkReturn efx_rc_t
736 efx_mac_stats_get_mask(
738 __out_bcount(mask_size) uint32_t *maskp,
739 __in size_t mask_size);
741 #define EFX_MAC_STAT_SUPPORTED(_mask, _stat) \
742 ((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] & \
743 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
747 extern __checkReturn efx_rc_t
749 __in efx_nic_t *enp);
752 * Upload mac statistics supported by the hardware into the given buffer.
754 * The DMA buffer must be 4Kbyte aligned and sized to hold at least
755 * efx_nic_cfg_t::enc_mac_stats_nstats 64bit counters.
757 * The hardware will only DMA statistics that it understands (of course).
758 * Drivers should not make any assumptions about which statistics are
759 * supported, especially when the statistics are generated by firmware.
761 * Thus, drivers should zero this buffer before use, so that not-understood
762 * statistics read back as zero.
765 extern __checkReturn efx_rc_t
766 efx_mac_stats_upload(
768 __in efsys_mem_t *esmp);
771 extern __checkReturn efx_rc_t
772 efx_mac_stats_periodic(
774 __in efsys_mem_t *esmp,
775 __in uint16_t period_ms,
776 __in boolean_t events);
779 extern __checkReturn efx_rc_t
780 efx_mac_stats_update(
782 __in efsys_mem_t *esmp,
783 __inout_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat,
784 __inout_opt uint32_t *generationp);
786 #endif /* EFSYS_OPT_MAC_STATS */
790 typedef enum efx_mon_type_e {
803 __in efx_nic_t *enp);
805 #endif /* EFSYS_OPT_NAMES */
808 extern __checkReturn efx_rc_t
810 __in efx_nic_t *enp);
812 #if EFSYS_OPT_MON_STATS
814 #define EFX_MON_STATS_PAGE_SIZE 0x100
815 #define EFX_MON_MASK_ELEMENT_SIZE 32
817 /* START MKCONFIG GENERATED MonitorHeaderStatsBlock 78b65c8d5af9747b */
818 typedef enum efx_mon_stat_e {
819 EFX_MON_STAT_CONTROLLER_TEMP,
820 EFX_MON_STAT_PHY_COMMON_TEMP,
821 EFX_MON_STAT_CONTROLLER_COOLING,
822 EFX_MON_STAT_PHY0_TEMP,
823 EFX_MON_STAT_PHY0_COOLING,
824 EFX_MON_STAT_PHY1_TEMP,
825 EFX_MON_STAT_PHY1_COOLING,
831 EFX_MON_STAT_IN_12V0,
832 EFX_MON_STAT_IN_1V2A,
833 EFX_MON_STAT_IN_VREF,
834 EFX_MON_STAT_OUT_VAOE,
835 EFX_MON_STAT_AOE_TEMP,
836 EFX_MON_STAT_PSU_AOE_TEMP,
837 EFX_MON_STAT_PSU_TEMP,
843 EFX_MON_STAT_IN_VAOE,
844 EFX_MON_STAT_OUT_IAOE,
845 EFX_MON_STAT_IN_IAOE,
846 EFX_MON_STAT_NIC_POWER,
848 EFX_MON_STAT_IN_I0V9,
849 EFX_MON_STAT_IN_I1V2,
850 EFX_MON_STAT_IN_0V9_ADC,
851 EFX_MON_STAT_CONTROLLER_2_TEMP,
852 EFX_MON_STAT_VREG_INTERNAL_TEMP,
853 EFX_MON_STAT_VREG_0V9_TEMP,
854 EFX_MON_STAT_VREG_1V2_TEMP,
855 EFX_MON_STAT_CONTROLLER_VPTAT,
856 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP,
857 EFX_MON_STAT_CONTROLLER_VPTAT_EXTADC,
858 EFX_MON_STAT_CONTROLLER_INTERNAL_TEMP_EXTADC,
859 EFX_MON_STAT_AMBIENT_TEMP,
860 EFX_MON_STAT_AIRFLOW,
861 EFX_MON_STAT_VDD08D_VSS08D_CSR,
862 EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
863 EFX_MON_STAT_HOTPOINT_TEMP,
864 EFX_MON_STAT_PHY_POWER_PORT0,
865 EFX_MON_STAT_PHY_POWER_PORT1,
866 EFX_MON_STAT_MUM_VCC,
867 EFX_MON_STAT_IN_0V9_A,
868 EFX_MON_STAT_IN_I0V9_A,
869 EFX_MON_STAT_VREG_0V9_A_TEMP,
870 EFX_MON_STAT_IN_0V9_B,
871 EFX_MON_STAT_IN_I0V9_B,
872 EFX_MON_STAT_VREG_0V9_B_TEMP,
873 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
874 EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXTADC,
875 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
876 EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXTADC,
877 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
878 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
879 EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXTADC,
880 EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC,
881 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
882 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
883 EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXTADC,
884 EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC,
885 EFX_MON_STAT_SODIMM_VOUT,
886 EFX_MON_STAT_SODIMM_0_TEMP,
887 EFX_MON_STAT_SODIMM_1_TEMP,
888 EFX_MON_STAT_PHY0_VCC,
889 EFX_MON_STAT_PHY1_VCC,
890 EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
891 EFX_MON_STAT_BOARD_FRONT_TEMP,
892 EFX_MON_STAT_BOARD_BACK_TEMP,
893 EFX_MON_STAT_IN_I1V8,
894 EFX_MON_STAT_IN_I2V5,
895 EFX_MON_STAT_IN_I3V3,
896 EFX_MON_STAT_IN_I12V0,
898 EFX_MON_STAT_IN_I1V3,
902 /* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
904 typedef enum efx_mon_stat_state_e {
905 EFX_MON_STAT_STATE_OK = 0,
906 EFX_MON_STAT_STATE_WARNING = 1,
907 EFX_MON_STAT_STATE_FATAL = 2,
908 EFX_MON_STAT_STATE_BROKEN = 3,
909 EFX_MON_STAT_STATE_NO_READING = 4,
910 } efx_mon_stat_state_t;
912 typedef enum efx_mon_stat_unit_e {
913 EFX_MON_STAT_UNIT_UNKNOWN = 0,
914 EFX_MON_STAT_UNIT_BOOL,
915 EFX_MON_STAT_UNIT_TEMP_C,
916 EFX_MON_STAT_UNIT_VOLTAGE_MV,
917 EFX_MON_STAT_UNIT_CURRENT_MA,
918 EFX_MON_STAT_UNIT_POWER_W,
919 EFX_MON_STAT_UNIT_RPM,
921 } efx_mon_stat_unit_t;
923 typedef struct efx_mon_stat_value_s {
925 efx_mon_stat_state_t emsv_state;
926 efx_mon_stat_unit_t emsv_unit;
927 } efx_mon_stat_value_t;
929 typedef struct efx_mon_limit_value_s {
930 uint16_t emlv_warning_min;
931 uint16_t emlv_warning_max;
932 uint16_t emlv_fatal_min;
933 uint16_t emlv_fatal_max;
934 } efx_mon_stat_limits_t;
936 typedef enum efx_mon_stat_portmask_e {
937 EFX_MON_STAT_PORTMAP_NONE = 0,
938 EFX_MON_STAT_PORTMAP_PORT0 = 1,
939 EFX_MON_STAT_PORTMAP_PORT1 = 2,
940 EFX_MON_STAT_PORTMAP_PORT2 = 3,
941 EFX_MON_STAT_PORTMAP_PORT3 = 4,
942 EFX_MON_STAT_PORTMAP_ALL = (-1),
943 EFX_MON_STAT_PORTMAP_UNKNOWN = (-2)
944 } efx_mon_stat_portmask_t;
952 __in efx_mon_stat_t id);
956 efx_mon_stat_description(
958 __in efx_mon_stat_t id);
960 #endif /* EFSYS_OPT_NAMES */
963 extern __checkReturn boolean_t
964 efx_mon_mcdi_to_efx_stat(
966 __out efx_mon_stat_t *statp);
969 extern __checkReturn boolean_t
970 efx_mon_get_stat_unit(
971 __in efx_mon_stat_t stat,
972 __out efx_mon_stat_unit_t *unitp);
975 extern __checkReturn boolean_t
976 efx_mon_get_stat_portmap(
977 __in efx_mon_stat_t stat,
978 __out efx_mon_stat_portmask_t *maskp);
981 extern __checkReturn efx_rc_t
982 efx_mon_stats_update(
984 __in efsys_mem_t *esmp,
985 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_value_t *values);
988 extern __checkReturn efx_rc_t
989 efx_mon_limits_update(
991 __inout_ecount(EFX_MON_NSTATS) efx_mon_stat_limits_t *values);
993 #endif /* EFSYS_OPT_MON_STATS */
998 __in efx_nic_t *enp);
1003 extern __checkReturn efx_rc_t
1005 __in efx_nic_t *enp);
1007 typedef enum efx_phy_led_mode_e {
1008 EFX_PHY_LED_DEFAULT = 0,
1013 } efx_phy_led_mode_t;
1015 #if EFSYS_OPT_PHY_LED_CONTROL
1018 extern __checkReturn efx_rc_t
1020 __in efx_nic_t *enp,
1021 __in efx_phy_led_mode_t mode);
1023 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1026 extern __checkReturn efx_rc_t
1028 __in efx_nic_t *enp);
1030 #if EFSYS_OPT_LOOPBACK
1032 typedef enum efx_loopback_type_e {
1033 EFX_LOOPBACK_OFF = 0,
1034 EFX_LOOPBACK_DATA = 1,
1035 EFX_LOOPBACK_GMAC = 2,
1036 EFX_LOOPBACK_XGMII = 3,
1037 EFX_LOOPBACK_XGXS = 4,
1038 EFX_LOOPBACK_XAUI = 5,
1039 EFX_LOOPBACK_GMII = 6,
1040 EFX_LOOPBACK_SGMII = 7,
1041 EFX_LOOPBACK_XGBR = 8,
1042 EFX_LOOPBACK_XFI = 9,
1043 EFX_LOOPBACK_XAUI_FAR = 10,
1044 EFX_LOOPBACK_GMII_FAR = 11,
1045 EFX_LOOPBACK_SGMII_FAR = 12,
1046 EFX_LOOPBACK_XFI_FAR = 13,
1047 EFX_LOOPBACK_GPHY = 14,
1048 EFX_LOOPBACK_PHY_XS = 15,
1049 EFX_LOOPBACK_PCS = 16,
1050 EFX_LOOPBACK_PMA_PMD = 17,
1051 EFX_LOOPBACK_XPORT = 18,
1052 EFX_LOOPBACK_XGMII_WS = 19,
1053 EFX_LOOPBACK_XAUI_WS = 20,
1054 EFX_LOOPBACK_XAUI_WS_FAR = 21,
1055 EFX_LOOPBACK_XAUI_WS_NEAR = 22,
1056 EFX_LOOPBACK_GMII_WS = 23,
1057 EFX_LOOPBACK_XFI_WS = 24,
1058 EFX_LOOPBACK_XFI_WS_FAR = 25,
1059 EFX_LOOPBACK_PHYXS_WS = 26,
1060 EFX_LOOPBACK_PMA_INT = 27,
1061 EFX_LOOPBACK_SD_NEAR = 28,
1062 EFX_LOOPBACK_SD_FAR = 29,
1063 EFX_LOOPBACK_PMA_INT_WS = 30,
1064 EFX_LOOPBACK_SD_FEP2_WS = 31,
1065 EFX_LOOPBACK_SD_FEP1_5_WS = 32,
1066 EFX_LOOPBACK_SD_FEP_WS = 33,
1067 EFX_LOOPBACK_SD_FES_WS = 34,
1068 EFX_LOOPBACK_AOE_INT_NEAR = 35,
1069 EFX_LOOPBACK_DATA_WS = 36,
1070 EFX_LOOPBACK_FORCE_EXT_LINK = 37,
1072 } efx_loopback_type_t;
1074 typedef enum efx_loopback_kind_e {
1075 EFX_LOOPBACK_KIND_OFF = 0,
1076 EFX_LOOPBACK_KIND_ALL,
1077 EFX_LOOPBACK_KIND_MAC,
1078 EFX_LOOPBACK_KIND_PHY,
1080 } efx_loopback_kind_t;
1085 __in efx_loopback_kind_t loopback_kind,
1086 __out efx_qword_t *maskp);
1089 extern __checkReturn efx_rc_t
1090 efx_port_loopback_set(
1091 __in efx_nic_t *enp,
1092 __in efx_link_mode_t link_mode,
1093 __in efx_loopback_type_t type);
1098 extern __checkReturn const char *
1099 efx_loopback_type_name(
1100 __in efx_nic_t *enp,
1101 __in efx_loopback_type_t type);
1103 #endif /* EFSYS_OPT_NAMES */
1105 #endif /* EFSYS_OPT_LOOPBACK */
1108 extern __checkReturn efx_rc_t
1110 __in efx_nic_t *enp,
1111 __out_opt efx_link_mode_t *link_modep);
1116 __in efx_nic_t *enp);
1118 typedef enum efx_phy_cap_type_e {
1119 EFX_PHY_CAP_INVALID = 0,
1124 EFX_PHY_CAP_1000HDX,
1125 EFX_PHY_CAP_1000FDX,
1126 EFX_PHY_CAP_10000FDX,
1130 EFX_PHY_CAP_40000FDX,
1132 EFX_PHY_CAP_100000FDX,
1133 EFX_PHY_CAP_25000FDX,
1134 EFX_PHY_CAP_50000FDX,
1135 EFX_PHY_CAP_BASER_FEC,
1136 EFX_PHY_CAP_BASER_FEC_REQUESTED,
1138 EFX_PHY_CAP_RS_FEC_REQUESTED,
1139 EFX_PHY_CAP_25G_BASER_FEC,
1140 EFX_PHY_CAP_25G_BASER_FEC_REQUESTED,
1142 } efx_phy_cap_type_t;
1145 #define EFX_PHY_CAP_CURRENT 0x00000000
1146 #define EFX_PHY_CAP_DEFAULT 0x00000001
1147 #define EFX_PHY_CAP_PERM 0x00000002
1151 efx_phy_adv_cap_get(
1152 __in efx_nic_t *enp,
1154 __out uint32_t *maskp);
1157 extern __checkReturn efx_rc_t
1158 efx_phy_adv_cap_set(
1159 __in efx_nic_t *enp,
1160 __in uint32_t mask);
1165 __in efx_nic_t *enp,
1166 __out uint32_t *maskp);
1169 extern __checkReturn efx_rc_t
1171 __in efx_nic_t *enp,
1172 __out uint32_t *ouip);
1174 typedef enum efx_phy_media_type_e {
1175 EFX_PHY_MEDIA_INVALID = 0,
1180 EFX_PHY_MEDIA_SFP_PLUS,
1181 EFX_PHY_MEDIA_BASE_T,
1182 EFX_PHY_MEDIA_QSFP_PLUS,
1183 EFX_PHY_MEDIA_NTYPES
1184 } efx_phy_media_type_t;
1187 * Get the type of medium currently used. If the board has ports for
1188 * modules, a module is present, and we recognise the media type of
1189 * the module, then this will be the media type of the module.
1190 * Otherwise it will be the media type of the port.
1194 efx_phy_media_type_get(
1195 __in efx_nic_t *enp,
1196 __out efx_phy_media_type_t *typep);
1199 * 2-wire device address of the base information in accordance with SFF-8472
1200 * Diagnostic Monitoring Interface for Optical Transceivers section
1201 * 4 Memory Organization.
1203 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_BASE 0xA0
1206 * 2-wire device address of the digital diagnostics monitoring interface
1207 * in accordance with SFF-8472 Diagnostic Monitoring Interface for Optical
1208 * Transceivers section 4 Memory Organization.
1210 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_SFP_DDM 0xA2
1213 * Hard wired 2-wire device address for QSFP+ in accordance with SFF-8436
1214 * QSFP+ 10 Gbs 4X PLUGGABLE TRANSCEIVER section 7.4 Device Addressing and
1217 #define EFX_PHY_MEDIA_INFO_DEV_ADDR_QSFP 0xA0
1220 * Maximum accessible data offset for PHY module information.
1222 #define EFX_PHY_MEDIA_INFO_MAX_OFFSET 0x100
1226 extern __checkReturn efx_rc_t
1227 efx_phy_module_get_info(
1228 __in efx_nic_t *enp,
1229 __in uint8_t dev_addr,
1232 __out_bcount(len) uint8_t *data);
1234 #if EFSYS_OPT_PHY_STATS
1236 /* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
1237 typedef enum efx_phy_stat_e {
1239 EFX_PHY_STAT_PMA_PMD_LINK_UP,
1240 EFX_PHY_STAT_PMA_PMD_RX_FAULT,
1241 EFX_PHY_STAT_PMA_PMD_TX_FAULT,
1242 EFX_PHY_STAT_PMA_PMD_REV_A,
1243 EFX_PHY_STAT_PMA_PMD_REV_B,
1244 EFX_PHY_STAT_PMA_PMD_REV_C,
1245 EFX_PHY_STAT_PMA_PMD_REV_D,
1246 EFX_PHY_STAT_PCS_LINK_UP,
1247 EFX_PHY_STAT_PCS_RX_FAULT,
1248 EFX_PHY_STAT_PCS_TX_FAULT,
1249 EFX_PHY_STAT_PCS_BER,
1250 EFX_PHY_STAT_PCS_BLOCK_ERRORS,
1251 EFX_PHY_STAT_PHY_XS_LINK_UP,
1252 EFX_PHY_STAT_PHY_XS_RX_FAULT,
1253 EFX_PHY_STAT_PHY_XS_TX_FAULT,
1254 EFX_PHY_STAT_PHY_XS_ALIGN,
1255 EFX_PHY_STAT_PHY_XS_SYNC_A,
1256 EFX_PHY_STAT_PHY_XS_SYNC_B,
1257 EFX_PHY_STAT_PHY_XS_SYNC_C,
1258 EFX_PHY_STAT_PHY_XS_SYNC_D,
1259 EFX_PHY_STAT_AN_LINK_UP,
1260 EFX_PHY_STAT_AN_MASTER,
1261 EFX_PHY_STAT_AN_LOCAL_RX_OK,
1262 EFX_PHY_STAT_AN_REMOTE_RX_OK,
1263 EFX_PHY_STAT_CL22EXT_LINK_UP,
1268 EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
1269 EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
1270 EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
1271 EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
1272 EFX_PHY_STAT_AN_COMPLETE,
1273 EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
1274 EFX_PHY_STAT_PMA_PMD_REV_MINOR,
1275 EFX_PHY_STAT_PMA_PMD_REV_MICRO,
1276 EFX_PHY_STAT_PCS_FW_VERSION_0,
1277 EFX_PHY_STAT_PCS_FW_VERSION_1,
1278 EFX_PHY_STAT_PCS_FW_VERSION_2,
1279 EFX_PHY_STAT_PCS_FW_VERSION_3,
1280 EFX_PHY_STAT_PCS_FW_BUILD_YY,
1281 EFX_PHY_STAT_PCS_FW_BUILD_MM,
1282 EFX_PHY_STAT_PCS_FW_BUILD_DD,
1283 EFX_PHY_STAT_PCS_OP_MODE,
1287 /* END MKCONFIG GENERATED PhyHeaderStatsBlock */
1294 __in efx_nic_t *enp,
1295 __in efx_phy_stat_t stat);
1297 #endif /* EFSYS_OPT_NAMES */
1299 #define EFX_PHY_STATS_SIZE 0x100
1302 extern __checkReturn efx_rc_t
1303 efx_phy_stats_update(
1304 __in efx_nic_t *enp,
1305 __in efsys_mem_t *esmp,
1306 __inout_ecount(EFX_PHY_NSTATS) uint32_t *stat);
1308 #endif /* EFSYS_OPT_PHY_STATS */
1313 typedef enum efx_bist_type_e {
1314 EFX_BIST_TYPE_UNKNOWN,
1315 EFX_BIST_TYPE_PHY_NORMAL,
1316 EFX_BIST_TYPE_PHY_CABLE_SHORT,
1317 EFX_BIST_TYPE_PHY_CABLE_LONG,
1318 EFX_BIST_TYPE_MC_MEM, /* Test the MC DMEM and IMEM */
1319 EFX_BIST_TYPE_SAT_MEM, /* Test the DMEM and IMEM of satellite cpus */
1320 EFX_BIST_TYPE_REG, /* Test the register memories */
1321 EFX_BIST_TYPE_NTYPES,
1324 typedef enum efx_bist_result_e {
1325 EFX_BIST_RESULT_UNKNOWN,
1326 EFX_BIST_RESULT_RUNNING,
1327 EFX_BIST_RESULT_PASSED,
1328 EFX_BIST_RESULT_FAILED,
1329 } efx_bist_result_t;
1331 typedef enum efx_phy_cable_status_e {
1332 EFX_PHY_CABLE_STATUS_OK,
1333 EFX_PHY_CABLE_STATUS_INVALID,
1334 EFX_PHY_CABLE_STATUS_OPEN,
1335 EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1336 EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1337 EFX_PHY_CABLE_STATUS_BUSY,
1338 } efx_phy_cable_status_t;
1340 typedef enum efx_bist_value_e {
1341 EFX_BIST_PHY_CABLE_LENGTH_A,
1342 EFX_BIST_PHY_CABLE_LENGTH_B,
1343 EFX_BIST_PHY_CABLE_LENGTH_C,
1344 EFX_BIST_PHY_CABLE_LENGTH_D,
1345 EFX_BIST_PHY_CABLE_STATUS_A,
1346 EFX_BIST_PHY_CABLE_STATUS_B,
1347 EFX_BIST_PHY_CABLE_STATUS_C,
1348 EFX_BIST_PHY_CABLE_STATUS_D,
1349 EFX_BIST_FAULT_CODE,
1351 * Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1357 EFX_BIST_MEM_EXPECT,
1358 EFX_BIST_MEM_ACTUAL,
1360 EFX_BIST_MEM_ECC_PARITY,
1361 EFX_BIST_MEM_ECC_FATAL,
1366 extern __checkReturn efx_rc_t
1367 efx_bist_enable_offline(
1368 __in efx_nic_t *enp);
1371 extern __checkReturn efx_rc_t
1373 __in efx_nic_t *enp,
1374 __in efx_bist_type_t type);
1377 extern __checkReturn efx_rc_t
1379 __in efx_nic_t *enp,
1380 __in efx_bist_type_t type,
1381 __out efx_bist_result_t *resultp,
1382 __out_opt uint32_t *value_maskp,
1383 __out_ecount_opt(count) unsigned long *valuesp,
1389 __in efx_nic_t *enp,
1390 __in efx_bist_type_t type);
1392 #endif /* EFSYS_OPT_BIST */
1394 #define EFX_FEATURE_IPV6 0x00000001
1395 #define EFX_FEATURE_LFSR_HASH_INSERT 0x00000002
1396 #define EFX_FEATURE_LINK_EVENTS 0x00000004
1397 #define EFX_FEATURE_PERIODIC_MAC_STATS 0x00000008
1398 #define EFX_FEATURE_MCDI 0x00000020
1399 #define EFX_FEATURE_LOOKAHEAD_SPLIT 0x00000040
1400 #define EFX_FEATURE_MAC_HEADER_FILTERS 0x00000080
1401 #define EFX_FEATURE_TURBO 0x00000100
1402 #define EFX_FEATURE_MCDI_DMA 0x00000200
1403 #define EFX_FEATURE_TX_SRC_FILTERS 0x00000400
1404 #define EFX_FEATURE_PIO_BUFFERS 0x00000800
1405 #define EFX_FEATURE_FW_ASSISTED_TSO 0x00001000
1406 #define EFX_FEATURE_FW_ASSISTED_TSO_V2 0x00002000
1407 #define EFX_FEATURE_PACKED_STREAM 0x00004000
1408 #define EFX_FEATURE_TXQ_CKSUM_OP_DESC 0x00008000
1410 typedef enum efx_tunnel_protocol_e {
1411 EFX_TUNNEL_PROTOCOL_NONE = 0,
1412 EFX_TUNNEL_PROTOCOL_VXLAN,
1413 EFX_TUNNEL_PROTOCOL_GENEVE,
1414 EFX_TUNNEL_PROTOCOL_NVGRE,
1416 } efx_tunnel_protocol_t;
1418 typedef enum efx_vi_window_shift_e {
1419 EFX_VI_WINDOW_SHIFT_INVALID = 0,
1420 EFX_VI_WINDOW_SHIFT_8K = 13,
1421 EFX_VI_WINDOW_SHIFT_16K = 14,
1422 EFX_VI_WINDOW_SHIFT_64K = 16,
1423 } efx_vi_window_shift_t;
1425 typedef struct efx_nic_cfg_s {
1426 uint32_t enc_board_type;
1427 uint32_t enc_phy_type;
1429 char enc_phy_name[21];
1431 char enc_phy_revision[21];
1432 efx_mon_type_t enc_mon_type;
1433 #if EFSYS_OPT_MON_STATS
1434 uint32_t enc_mon_stat_dma_buf_size;
1435 uint32_t enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1437 unsigned int enc_features;
1438 efx_vi_window_shift_t enc_vi_window_shift;
1439 uint8_t enc_mac_addr[6];
1440 uint8_t enc_port; /* PHY port number */
1441 uint32_t enc_intr_vec_base;
1442 uint32_t enc_intr_limit;
1443 uint32_t enc_evq_limit;
1444 uint32_t enc_txq_limit;
1445 uint32_t enc_rxq_limit;
1446 uint32_t enc_evq_max_nevs;
1447 uint32_t enc_evq_min_nevs;
1448 uint32_t enc_rxq_max_ndescs;
1449 uint32_t enc_rxq_min_ndescs;
1450 uint32_t enc_txq_max_ndescs;
1451 uint32_t enc_txq_min_ndescs;
1452 uint32_t enc_buftbl_limit;
1453 uint32_t enc_piobuf_limit;
1454 uint32_t enc_piobuf_size;
1455 uint32_t enc_piobuf_min_alloc_size;
1456 uint32_t enc_evq_timer_quantum_ns;
1457 uint32_t enc_evq_timer_max_us;
1458 uint32_t enc_clk_mult;
1459 uint32_t enc_ev_ew_desc_size;
1460 uint32_t enc_ev_desc_size;
1461 uint32_t enc_rx_desc_size;
1462 uint32_t enc_tx_desc_size;
1463 /* Maximum Rx prefix size if many Rx prefixes are supported */
1464 uint32_t enc_rx_prefix_size;
1465 uint32_t enc_rx_buf_align_start;
1466 uint32_t enc_rx_buf_align_end;
1467 #if EFSYS_OPT_RX_SCALE
1468 uint32_t enc_rx_scale_max_exclusive_contexts;
1470 * Mask of supported hash algorithms.
1471 * Hash algorithm types are used as the bit indices.
1473 uint32_t enc_rx_scale_hash_alg_mask;
1475 * Indicates whether port numbers can be included to the
1476 * input data for hash computation.
1478 boolean_t enc_rx_scale_l4_hash_supported;
1479 boolean_t enc_rx_scale_additional_modes_supported;
1480 #endif /* EFSYS_OPT_RX_SCALE */
1481 #if EFSYS_OPT_LOOPBACK
1482 efx_qword_t enc_loopback_types[EFX_LINK_NMODES];
1483 #endif /* EFSYS_OPT_LOOPBACK */
1484 #if EFSYS_OPT_PHY_FLAGS
1485 uint32_t enc_phy_flags_mask;
1486 #endif /* EFSYS_OPT_PHY_FLAGS */
1487 #if EFSYS_OPT_PHY_LED_CONTROL
1488 uint32_t enc_led_mask;
1489 #endif /* EFSYS_OPT_PHY_LED_CONTROL */
1490 #if EFSYS_OPT_PHY_STATS
1491 uint64_t enc_phy_stat_mask;
1492 #endif /* EFSYS_OPT_PHY_STATS */
1494 uint8_t enc_mcdi_mdio_channel;
1495 #if EFSYS_OPT_PHY_STATS
1496 uint32_t enc_mcdi_phy_stat_mask;
1497 #endif /* EFSYS_OPT_PHY_STATS */
1498 #if EFSYS_OPT_MON_STATS
1499 uint32_t *enc_mcdi_sensor_maskp;
1500 uint32_t enc_mcdi_sensor_mask_size;
1501 #endif /* EFSYS_OPT_MON_STATS */
1502 #endif /* EFSYS_OPT_MCDI */
1504 uint32_t enc_bist_mask;
1505 #endif /* EFSYS_OPT_BIST */
1506 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1509 uint32_t enc_privilege_mask;
1510 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1511 boolean_t enc_evq_init_done_ev_supported;
1512 boolean_t enc_bug26807_workaround;
1513 boolean_t enc_bug35388_workaround;
1514 boolean_t enc_bug41750_workaround;
1515 boolean_t enc_bug61265_workaround;
1516 boolean_t enc_bug61297_workaround;
1517 boolean_t enc_rx_batching_enabled;
1518 /* Maximum number of descriptors completed in an rx event. */
1519 uint32_t enc_rx_batch_max;
1520 /* Number of rx descriptors the hardware requires for a push. */
1521 uint32_t enc_rx_push_align;
1522 /* Maximum amount of data in DMA descriptor */
1523 uint32_t enc_tx_dma_desc_size_max;
1525 * Boundary which DMA descriptor data must not cross or 0 if no
1528 uint32_t enc_tx_dma_desc_boundary;
1530 * Maximum number of bytes into the packet the TCP header can start for
1531 * the hardware to apply TSO packet edits.
1533 uint32_t enc_tx_tso_tcp_header_offset_limit;
1534 /* Maximum number of header DMA descriptors per TSO transaction. */
1535 uint32_t enc_tx_tso_max_header_ndescs;
1536 /* Maximum header length acceptable by TSO transaction. */
1537 uint32_t enc_tx_tso_max_header_length;
1538 /* Maximum number of payload DMA descriptors per TSO transaction. */
1539 uint32_t enc_tx_tso_max_payload_ndescs;
1540 /* Maximum payload length per TSO transaction. */
1541 uint32_t enc_tx_tso_max_payload_length;
1542 /* Maximum number of frames to be generated per TSO transaction. */
1543 uint32_t enc_tx_tso_max_nframes;
1544 boolean_t enc_fw_assisted_tso_enabled;
1545 boolean_t enc_fw_assisted_tso_v2_enabled;
1546 boolean_t enc_fw_assisted_tso_v2_encap_enabled;
1547 boolean_t enc_tso_v3_enabled;
1548 /* Number of TSO contexts on the NIC (FATSOv2) */
1549 uint32_t enc_fw_assisted_tso_v2_n_contexts;
1550 boolean_t enc_hw_tx_insert_vlan_enabled;
1551 /* Number of PFs on the NIC */
1552 uint32_t enc_hw_pf_count;
1553 /* Datapath firmware vadapter/vport/vswitch support */
1554 boolean_t enc_datapath_cap_evb;
1555 /* Datapath firmware vport reconfigure support */
1556 boolean_t enc_vport_reconfigure_supported;
1557 boolean_t enc_rx_disable_scatter_supported;
1558 boolean_t enc_allow_set_mac_with_installed_filters;
1559 boolean_t enc_enhanced_set_mac_supported;
1560 boolean_t enc_init_evq_v2_supported;
1561 boolean_t enc_init_evq_extended_width_supported;
1562 boolean_t enc_no_cont_ev_mode_supported;
1563 boolean_t enc_init_rxq_with_buffer_size;
1564 boolean_t enc_rx_packed_stream_supported;
1565 boolean_t enc_rx_var_packed_stream_supported;
1566 boolean_t enc_rx_es_super_buffer_supported;
1567 boolean_t enc_fw_subvariant_no_tx_csum_supported;
1568 boolean_t enc_pm_and_rxdp_counters;
1569 boolean_t enc_mac_stats_40g_tx_size_bins;
1570 uint32_t enc_tunnel_encapsulations_supported;
1572 * NIC global maximum for unique UDP tunnel ports shared by all
1575 uint32_t enc_tunnel_config_udp_entries_max;
1576 /* External port identifier */
1577 uint8_t enc_external_port;
1578 uint32_t enc_mcdi_max_payload_length;
1579 /* VPD may be per-PF or global */
1580 boolean_t enc_vpd_is_global;
1581 /* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1582 uint32_t enc_required_pcie_bandwidth_mbps;
1583 uint32_t enc_max_pcie_link_gen;
1584 /* Firmware verifies integrity of NVRAM updates */
1585 boolean_t enc_nvram_update_verify_result_supported;
1586 /* Firmware supports polled NVRAM updates on select partitions */
1587 boolean_t enc_nvram_update_poll_verify_result_supported;
1588 /* Firmware accepts updates via the BUNDLE partition */
1589 boolean_t enc_nvram_bundle_update_supported;
1590 /* Firmware support for extended MAC_STATS buffer */
1591 uint32_t enc_mac_stats_nstats;
1592 boolean_t enc_fec_counters;
1593 boolean_t enc_hlb_counters;
1594 /* Firmware support for "FLAG" and "MARK" filter actions */
1595 boolean_t enc_filter_action_flag_supported;
1596 boolean_t enc_filter_action_mark_supported;
1597 uint32_t enc_filter_action_mark_max;
1598 /* Port assigned to this PCI function */
1599 uint32_t enc_assigned_port;
1602 #define EFX_VPORT_PCI_FUNCTION_IS_PF(configp) \
1603 ((configp)->evc_function == 0xffff)
1605 #define EFX_PCI_FUNCTION_IS_PF(_encp) ((_encp)->enc_vf == 0xffff)
1606 #define EFX_PCI_FUNCTION_IS_VF(_encp) ((_encp)->enc_vf != 0xffff)
1608 #define EFX_PCI_FUNCTION(_encp) \
1609 (EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1611 #define EFX_PCI_VF_PARENT(_encp) ((_encp)->enc_pf)
1614 extern const efx_nic_cfg_t *
1616 __in const efx_nic_t *enp);
1618 /* RxDPCPU firmware id values by which FW variant can be identified */
1619 #define EFX_RXDP_FULL_FEATURED_FW_ID 0x0
1620 #define EFX_RXDP_LOW_LATENCY_FW_ID 0x1
1621 #define EFX_RXDP_PACKED_STREAM_FW_ID 0x2
1622 #define EFX_RXDP_RULES_ENGINE_FW_ID 0x5
1623 #define EFX_RXDP_DPDK_FW_ID 0x6
1625 typedef struct efx_nic_fw_info_s {
1626 /* Basic FW version information */
1627 uint16_t enfi_mc_fw_version[4];
1629 * If datapath capabilities can be detected,
1630 * additional FW information is to be shown
1632 boolean_t enfi_dpcpu_fw_ids_valid;
1633 /* Rx and Tx datapath CPU FW IDs */
1634 uint16_t enfi_rx_dpcpu_fw_id;
1635 uint16_t enfi_tx_dpcpu_fw_id;
1636 } efx_nic_fw_info_t;
1639 extern __checkReturn efx_rc_t
1640 efx_nic_get_fw_version(
1641 __in efx_nic_t *enp,
1642 __out efx_nic_fw_info_t *enfip);
1644 /* Driver resource limits (minimum required/maximum usable). */
1645 typedef struct efx_drv_limits_s {
1646 uint32_t edl_min_evq_count;
1647 uint32_t edl_max_evq_count;
1649 uint32_t edl_min_rxq_count;
1650 uint32_t edl_max_rxq_count;
1652 uint32_t edl_min_txq_count;
1653 uint32_t edl_max_txq_count;
1655 /* PIO blocks (sub-allocated from piobuf) */
1656 uint32_t edl_min_pio_alloc_size;
1657 uint32_t edl_max_pio_alloc_count;
1661 extern __checkReturn efx_rc_t
1662 efx_nic_set_drv_limits(
1663 __inout efx_nic_t *enp,
1664 __in efx_drv_limits_t *edlp);
1667 * Register the OS driver version string for management agents
1668 * (e.g. via NC-SI). The content length is provided (i.e. no
1669 * NUL terminator). Use length 0 to indicate no version string
1670 * should be advertised. It is valid to set the version string
1671 * only before efx_nic_probe() is called.
1674 extern __checkReturn efx_rc_t
1675 efx_nic_set_drv_version(
1676 __inout efx_nic_t *enp,
1677 __in_ecount(length) char const *verp,
1678 __in size_t length);
1680 typedef enum efx_nic_region_e {
1681 EFX_REGION_VI, /* Memory BAR UC mapping */
1682 EFX_REGION_PIO_WRITE_VI, /* Memory BAR WC mapping */
1686 extern __checkReturn efx_rc_t
1687 efx_nic_get_bar_region(
1688 __in efx_nic_t *enp,
1689 __in efx_nic_region_t region,
1690 __out uint32_t *offsetp,
1691 __out size_t *sizep);
1694 extern __checkReturn efx_rc_t
1695 efx_nic_get_vi_pool(
1696 __in efx_nic_t *enp,
1697 __out uint32_t *evq_countp,
1698 __out uint32_t *rxq_countp,
1699 __out uint32_t *txq_countp);
1704 typedef enum efx_vpd_tag_e {
1711 typedef uint16_t efx_vpd_keyword_t;
1713 typedef struct efx_vpd_value_s {
1714 efx_vpd_tag_t evv_tag;
1715 efx_vpd_keyword_t evv_keyword;
1717 uint8_t evv_value[0x100];
1721 #define EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1724 extern __checkReturn efx_rc_t
1726 __in efx_nic_t *enp);
1729 extern __checkReturn efx_rc_t
1731 __in efx_nic_t *enp,
1732 __out size_t *sizep);
1735 extern __checkReturn efx_rc_t
1737 __in efx_nic_t *enp,
1738 __out_bcount(size) caddr_t data,
1742 extern __checkReturn efx_rc_t
1744 __in efx_nic_t *enp,
1745 __in_bcount(size) caddr_t data,
1749 extern __checkReturn efx_rc_t
1751 __in efx_nic_t *enp,
1752 __in_bcount(size) caddr_t data,
1756 extern __checkReturn efx_rc_t
1758 __in efx_nic_t *enp,
1759 __in_bcount(size) caddr_t data,
1761 __inout efx_vpd_value_t *evvp);
1764 extern __checkReturn efx_rc_t
1766 __in efx_nic_t *enp,
1767 __inout_bcount(size) caddr_t data,
1769 __in efx_vpd_value_t *evvp);
1772 extern __checkReturn efx_rc_t
1774 __in efx_nic_t *enp,
1775 __inout_bcount(size) caddr_t data,
1777 __out efx_vpd_value_t *evvp,
1778 __inout unsigned int *contp);
1781 extern __checkReturn efx_rc_t
1783 __in efx_nic_t *enp,
1784 __in_bcount(size) caddr_t data,
1790 __in efx_nic_t *enp);
1792 #endif /* EFSYS_OPT_VPD */
1798 typedef enum efx_nvram_type_e {
1799 EFX_NVRAM_INVALID = 0,
1801 EFX_NVRAM_BOOTROM_CFG,
1802 EFX_NVRAM_MC_FIRMWARE,
1803 EFX_NVRAM_MC_GOLDEN,
1809 EFX_NVRAM_FPGA_BACKUP,
1810 EFX_NVRAM_DYNAMIC_CFG,
1813 EFX_NVRAM_MUM_FIRMWARE,
1814 EFX_NVRAM_DYNCONFIG_DEFAULTS,
1815 EFX_NVRAM_ROMCONFIG_DEFAULTS,
1817 EFX_NVRAM_BUNDLE_METADATA,
1821 typedef struct efx_nvram_info_s {
1823 uint32_t eni_partn_size;
1824 uint32_t eni_address;
1825 uint32_t eni_erase_size;
1826 uint32_t eni_write_size;
1829 #define EFX_NVRAM_FLAG_READ_ONLY (1 << 0)
1832 extern __checkReturn efx_rc_t
1834 __in efx_nic_t *enp);
1839 extern __checkReturn efx_rc_t
1841 __in efx_nic_t *enp);
1843 #endif /* EFSYS_OPT_DIAG */
1846 extern __checkReturn efx_rc_t
1848 __in efx_nic_t *enp,
1849 __in efx_nvram_type_t type,
1850 __out size_t *sizep);
1853 extern __checkReturn efx_rc_t
1855 __in efx_nic_t *enp,
1856 __in efx_nvram_type_t type,
1857 __out efx_nvram_info_t *enip);
1860 extern __checkReturn efx_rc_t
1862 __in efx_nic_t *enp,
1863 __in efx_nvram_type_t type,
1864 __out_opt size_t *pref_chunkp);
1867 extern __checkReturn efx_rc_t
1868 efx_nvram_rw_finish(
1869 __in efx_nic_t *enp,
1870 __in efx_nvram_type_t type,
1871 __out_opt uint32_t *verify_resultp);
1874 extern __checkReturn efx_rc_t
1875 efx_nvram_get_version(
1876 __in efx_nic_t *enp,
1877 __in efx_nvram_type_t type,
1878 __out uint32_t *subtypep,
1879 __out_ecount(4) uint16_t version[4]);
1882 extern __checkReturn efx_rc_t
1883 efx_nvram_read_chunk(
1884 __in efx_nic_t *enp,
1885 __in efx_nvram_type_t type,
1886 __in unsigned int offset,
1887 __out_bcount(size) caddr_t data,
1891 extern __checkReturn efx_rc_t
1892 efx_nvram_read_backup(
1893 __in efx_nic_t *enp,
1894 __in efx_nvram_type_t type,
1895 __in unsigned int offset,
1896 __out_bcount(size) caddr_t data,
1900 extern __checkReturn efx_rc_t
1901 efx_nvram_set_version(
1902 __in efx_nic_t *enp,
1903 __in efx_nvram_type_t type,
1904 __in_ecount(4) uint16_t version[4]);
1907 extern __checkReturn efx_rc_t
1909 __in efx_nic_t *enp,
1910 __in efx_nvram_type_t type,
1911 __in_bcount(partn_size) caddr_t partn_data,
1912 __in size_t partn_size);
1915 extern __checkReturn efx_rc_t
1917 __in efx_nic_t *enp,
1918 __in efx_nvram_type_t type);
1921 extern __checkReturn efx_rc_t
1922 efx_nvram_write_chunk(
1923 __in efx_nic_t *enp,
1924 __in efx_nvram_type_t type,
1925 __in unsigned int offset,
1926 __in_bcount(size) caddr_t data,
1932 __in efx_nic_t *enp);
1934 #endif /* EFSYS_OPT_NVRAM */
1936 #if EFSYS_OPT_BOOTCFG
1938 /* Report size and offset of bootcfg sector in NVRAM partition. */
1940 extern __checkReturn efx_rc_t
1941 efx_bootcfg_sector_info(
1942 __in efx_nic_t *enp,
1944 __out_opt uint32_t *sector_countp,
1945 __out size_t *offsetp,
1946 __out size_t *max_sizep);
1949 * Copy bootcfg sector data to a target buffer which may differ in size.
1950 * Optionally corrects format errors in source buffer.
1954 efx_bootcfg_copy_sector(
1955 __in efx_nic_t *enp,
1956 __inout_bcount(sector_length)
1958 __in size_t sector_length,
1959 __out_bcount(data_size) uint8_t *data,
1960 __in size_t data_size,
1961 __in boolean_t handle_format_errors);
1966 __in efx_nic_t *enp,
1967 __out_bcount(size) uint8_t *data,
1973 __in efx_nic_t *enp,
1974 __in_bcount(size) uint8_t *data,
1979 * Processing routines for buffers arranged in the DHCP/BOOTP option format
1980 * (see https://tools.ietf.org/html/rfc1533)
1982 * Summarising the format: the buffer is a sequence of options. All options
1983 * begin with a tag octet, which uniquely identifies the option. Fixed-
1984 * length options without data consist of only a tag octet. Only options PAD
1985 * (0) and END (255) are fixed length. All other options are variable-length
1986 * with a length octet following the tag octet. The value of the length
1987 * octet does not include the two octets specifying the tag and length. The
1988 * length octet is followed by "length" octets of data.
1990 * Option data may be a sequence of sub-options in the same format. The data
1991 * content of the encapsulating option is one or more encapsulated sub-options,
1992 * with no terminating END tag is required.
1994 * To be valid, the top-level sequence of options should be terminated by an
1995 * END tag. The buffer should be padded with the PAD byte.
1997 * When stored to NVRAM, the DHCP option format buffer is preceded by a
1998 * checksum octet. The full buffer (including after the END tag) contributes
1999 * to the checksum, hence the need to fill the buffer to the end with PAD.
2002 #define EFX_DHCP_END ((uint8_t)0xff)
2003 #define EFX_DHCP_PAD ((uint8_t)0)
2005 #define EFX_DHCP_ENCAP_OPT(encapsulator, encapsulated) \
2006 (uint16_t)(((encapsulator) << 8) | (encapsulated))
2009 extern __checkReturn uint8_t
2011 __in_bcount(size) uint8_t const *data,
2015 extern __checkReturn efx_rc_t
2017 __in_bcount(size) uint8_t const *data,
2019 __out_opt size_t *usedp);
2022 extern __checkReturn efx_rc_t
2024 __in_bcount(buffer_length) uint8_t *bufferp,
2025 __in size_t buffer_length,
2027 __deref_out uint8_t **valuepp,
2028 __out size_t *value_lengthp);
2031 extern __checkReturn efx_rc_t
2033 __in_bcount(buffer_length) uint8_t *bufferp,
2034 __in size_t buffer_length,
2035 __deref_out uint8_t **endpp);
2039 extern __checkReturn efx_rc_t
2040 efx_dhcp_delete_tag(
2041 __inout_bcount(buffer_length) uint8_t *bufferp,
2042 __in size_t buffer_length,
2046 extern __checkReturn efx_rc_t
2048 __inout_bcount(buffer_length) uint8_t *bufferp,
2049 __in size_t buffer_length,
2051 __in_bcount_opt(value_length) uint8_t *valuep,
2052 __in size_t value_length);
2055 extern __checkReturn efx_rc_t
2056 efx_dhcp_update_tag(
2057 __inout_bcount(buffer_length) uint8_t *bufferp,
2058 __in size_t buffer_length,
2060 __in uint8_t *value_locationp,
2061 __in_bcount_opt(value_length) uint8_t *valuep,
2062 __in size_t value_length);
2065 #endif /* EFSYS_OPT_BOOTCFG */
2067 #if EFSYS_OPT_IMAGE_LAYOUT
2069 #include "ef10_signed_image_layout.h"
2072 * Image header used in unsigned and signed image layouts (see SF-102785-PS).
2075 * The image header format is extensible. However, older drivers require an
2076 * exact match of image header version and header length when validating and
2077 * writing firmware images.
2079 * To avoid breaking backward compatibility, we use the upper bits of the
2080 * controller version fields to contain an extra version number used for
2081 * combined bootROM and UEFI ROM images on EF10 and later (to hold the UEFI ROM
2082 * version). See bug39254 and SF-102785-PS for details.
2084 typedef struct efx_image_header_s {
2086 uint32_t eih_version;
2088 uint32_t eih_subtype;
2089 uint32_t eih_code_size;
2092 uint32_t eih_controller_version_min;
2094 uint16_t eih_controller_version_min_short;
2095 uint8_t eih_extra_version_a;
2096 uint8_t eih_extra_version_b;
2100 uint32_t eih_controller_version_max;
2102 uint16_t eih_controller_version_max_short;
2103 uint8_t eih_extra_version_c;
2104 uint8_t eih_extra_version_d;
2107 uint16_t eih_code_version_a;
2108 uint16_t eih_code_version_b;
2109 uint16_t eih_code_version_c;
2110 uint16_t eih_code_version_d;
2111 } efx_image_header_t;
2113 #define EFX_IMAGE_HEADER_SIZE (40)
2114 #define EFX_IMAGE_HEADER_VERSION (4)
2115 #define EFX_IMAGE_HEADER_MAGIC (0x106F1A5)
2118 typedef struct efx_image_trailer_s {
2120 } efx_image_trailer_t;
2122 #define EFX_IMAGE_TRAILER_SIZE (4)
2124 typedef enum efx_image_format_e {
2125 EFX_IMAGE_FORMAT_NO_IMAGE,
2126 EFX_IMAGE_FORMAT_INVALID,
2127 EFX_IMAGE_FORMAT_UNSIGNED,
2128 EFX_IMAGE_FORMAT_SIGNED,
2129 EFX_IMAGE_FORMAT_SIGNED_PACKAGE
2130 } efx_image_format_t;
2132 typedef struct efx_image_info_s {
2133 efx_image_format_t eii_format;
2134 uint8_t * eii_imagep;
2135 size_t eii_image_size;
2136 efx_image_header_t * eii_headerp;
2140 extern __checkReturn efx_rc_t
2141 efx_check_reflash_image(
2143 __in uint32_t buffer_size,
2144 __out efx_image_info_t *infop);
2147 extern __checkReturn efx_rc_t
2148 efx_build_signed_image_write_buffer(
2149 __out_bcount(buffer_size)
2151 __in uint32_t buffer_size,
2152 __in efx_image_info_t *infop,
2153 __out efx_image_header_t **headerpp);
2155 #endif /* EFSYS_OPT_IMAGE_LAYOUT */
2159 typedef enum efx_pattern_type_t {
2160 EFX_PATTERN_BYTE_INCREMENT = 0,
2161 EFX_PATTERN_ALL_THE_SAME,
2162 EFX_PATTERN_BIT_ALTERNATE,
2163 EFX_PATTERN_BYTE_ALTERNATE,
2164 EFX_PATTERN_BYTE_CHANGING,
2165 EFX_PATTERN_BIT_SWEEP,
2167 } efx_pattern_type_t;
2170 (*efx_sram_pattern_fn_t)(
2172 __in boolean_t negate,
2173 __out efx_qword_t *eqp);
2176 extern __checkReturn efx_rc_t
2178 __in efx_nic_t *enp,
2179 __in efx_pattern_type_t type);
2181 #endif /* EFSYS_OPT_DIAG */
2184 extern __checkReturn efx_rc_t
2185 efx_sram_buf_tbl_set(
2186 __in efx_nic_t *enp,
2188 __in efsys_mem_t *esmp,
2193 efx_sram_buf_tbl_clear(
2194 __in efx_nic_t *enp,
2198 #define EFX_BUF_TBL_SIZE 0x20000
2200 #define EFX_BUF_SIZE 4096
2204 typedef struct efx_evq_s efx_evq_t;
2206 #if EFSYS_OPT_QSTATS
2208 /* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 0a147ace40844969 */
2209 typedef enum efx_ev_qstat_e {
2215 EV_RX_PAUSE_FRM_ERR,
2216 EV_RX_BUF_OWNER_ID_ERR,
2217 EV_RX_IPV4_HDR_CHKSUM_ERR,
2218 EV_RX_TCP_UDP_CHKSUM_ERR,
2222 EV_RX_MCAST_HASH_MATCH,
2239 EV_DRIVER_SRM_UPD_DONE,
2240 EV_DRIVER_TX_DESCQ_FLS_DONE,
2241 EV_DRIVER_RX_DESCQ_FLS_DONE,
2242 EV_DRIVER_RX_DESCQ_FLS_FAILED,
2243 EV_DRIVER_RX_DSC_ERROR,
2244 EV_DRIVER_TX_DSC_ERROR,
2247 EV_RX_PARSE_INCOMPLETE,
2251 /* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
2253 #endif /* EFSYS_OPT_QSTATS */
2256 extern __checkReturn efx_rc_t
2258 __in efx_nic_t *enp);
2263 __in efx_nic_t *enp);
2266 extern __checkReturn size_t
2268 __in const efx_nic_t *enp,
2269 __in unsigned int ndescs,
2270 __in uint32_t flags);
2273 extern __checkReturn unsigned int
2275 __in const efx_nic_t *enp,
2276 __in unsigned int ndescs,
2277 __in uint32_t flags);
2279 #define EFX_EVQ_FLAGS_TYPE_MASK (0x3)
2280 #define EFX_EVQ_FLAGS_TYPE_AUTO (0x0)
2281 #define EFX_EVQ_FLAGS_TYPE_THROUGHPUT (0x1)
2282 #define EFX_EVQ_FLAGS_TYPE_LOW_LATENCY (0x2)
2284 #define EFX_EVQ_FLAGS_NOTIFY_MASK (0xC)
2285 #define EFX_EVQ_FLAGS_NOTIFY_INTERRUPT (0x0) /* Interrupting (default) */
2286 #define EFX_EVQ_FLAGS_NOTIFY_DISABLED (0x4) /* Non-interrupting */
2289 * Use the NO_CONT_EV RX event format, which allows the firmware to operate more
2290 * efficiently at high data rates. See SF-109306-TC 5.11 "Events for RXQs in
2293 * NO_CONT_EV requires EVQ_RX_MERGE and RXQ_FORCED_EV_MERGING to both be set,
2294 * which is the case when an event queue is set to THROUGHPUT mode.
2296 #define EFX_EVQ_FLAGS_NO_CONT_EV (0x10)
2298 /* Configure EVQ for extended width events (EF100 only) */
2299 #define EFX_EVQ_FLAGS_EXTENDED_WIDTH (0x20)
2303 extern __checkReturn efx_rc_t
2305 __in efx_nic_t *enp,
2306 __in unsigned int index,
2307 __in efsys_mem_t *esmp,
2311 __in uint32_t flags,
2312 __deref_out efx_evq_t **eepp);
2317 __in efx_evq_t *eep,
2318 __in uint16_t data);
2320 typedef __checkReturn boolean_t
2321 (*efx_initialized_ev_t)(
2322 __in_opt void *arg);
2324 #define EFX_PKT_UNICAST 0x0004
2325 #define EFX_PKT_START 0x0008
2327 #define EFX_PKT_VLAN_TAGGED 0x0010
2328 #define EFX_CKSUM_TCPUDP 0x0020
2329 #define EFX_CKSUM_IPV4 0x0040
2330 #define EFX_PKT_CONT 0x0080
2332 #define EFX_CHECK_VLAN 0x0100
2333 #define EFX_PKT_TCP 0x0200
2334 #define EFX_PKT_UDP 0x0400
2335 #define EFX_PKT_IPV4 0x0800
2337 #define EFX_PKT_IPV6 0x1000
2338 #define EFX_PKT_PREFIX_LEN 0x2000
2339 #define EFX_ADDR_MISMATCH 0x4000
2340 #define EFX_DISCARD 0x8000
2343 * The following flags are used only for packed stream
2344 * mode. The values for the flags are reused to fit into 16 bit,
2345 * since EFX_PKT_START and EFX_PKT_CONT are never used in
2346 * packed stream mode
2348 #define EFX_PKT_PACKED_STREAM_NEW_BUFFER EFX_PKT_START
2349 #define EFX_PKT_PACKED_STREAM_PARSE_INCOMPLETE EFX_PKT_CONT
2352 #define EFX_EV_RX_NLABELS 32
2353 #define EFX_EV_TX_NLABELS 32
2355 typedef __checkReturn boolean_t
2358 __in uint32_t label,
2361 __in uint16_t flags);
2363 typedef __checkReturn boolean_t
2364 (*efx_rx_packets_ev_t)(
2366 __in uint32_t label,
2367 __in unsigned int num_packets,
2368 __in uint32_t flags);
2370 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2373 * Packed stream mode is documented in SF-112241-TC.
2374 * The general idea is that, instead of putting each incoming
2375 * packet into a separate buffer which is specified in a RX
2376 * descriptor, a large buffer is provided to the hardware and
2377 * packets are put there in a continuous stream.
2378 * The main advantage of such an approach is that RX queue refilling
2379 * happens much less frequently.
2381 * Equal stride packed stream mode is documented in SF-119419-TC.
2382 * The general idea is to utilize advantages of the packed stream,
2383 * but avoid indirection in packets representation.
2384 * The main advantage of such an approach is that RX queue refilling
2385 * happens much less frequently and packets buffers are independent
2386 * from upper layers point of view.
2389 typedef __checkReturn boolean_t
2392 __in uint32_t label,
2394 __in uint32_t pkt_count,
2395 __in uint16_t flags);
2399 typedef __checkReturn boolean_t
2402 __in uint32_t label,
2405 typedef __checkReturn boolean_t
2406 (*efx_tx_ndescs_ev_t)(
2408 __in uint32_t label,
2409 __in unsigned int ndescs);
2411 #define EFX_EXCEPTION_RX_RECOVERY 0x00000001
2412 #define EFX_EXCEPTION_RX_DSC_ERROR 0x00000002
2413 #define EFX_EXCEPTION_TX_DSC_ERROR 0x00000003
2414 #define EFX_EXCEPTION_UNKNOWN_SENSOREVT 0x00000004
2415 #define EFX_EXCEPTION_FWALERT_SRAM 0x00000005
2416 #define EFX_EXCEPTION_UNKNOWN_FWALERT 0x00000006
2417 #define EFX_EXCEPTION_RX_ERROR 0x00000007
2418 #define EFX_EXCEPTION_TX_ERROR 0x00000008
2419 #define EFX_EXCEPTION_EV_ERROR 0x00000009
2421 typedef __checkReturn boolean_t
2422 (*efx_exception_ev_t)(
2424 __in uint32_t label,
2425 __in uint32_t data);
2427 typedef __checkReturn boolean_t
2428 (*efx_rxq_flush_done_ev_t)(
2430 __in uint32_t rxq_index);
2432 typedef __checkReturn boolean_t
2433 (*efx_rxq_flush_failed_ev_t)(
2435 __in uint32_t rxq_index);
2437 typedef __checkReturn boolean_t
2438 (*efx_txq_flush_done_ev_t)(
2440 __in uint32_t txq_index);
2442 typedef __checkReturn boolean_t
2443 (*efx_software_ev_t)(
2445 __in uint16_t magic);
2447 typedef __checkReturn boolean_t
2450 __in uint32_t code);
2452 #define EFX_SRAM_CLEAR 0
2453 #define EFX_SRAM_UPDATE 1
2454 #define EFX_SRAM_ILLEGAL_CLEAR 2
2456 typedef __checkReturn boolean_t
2457 (*efx_wake_up_ev_t)(
2459 __in uint32_t label);
2461 typedef __checkReturn boolean_t
2464 __in uint32_t label);
2466 typedef __checkReturn boolean_t
2467 (*efx_link_change_ev_t)(
2469 __in efx_link_mode_t link_mode);
2471 #if EFSYS_OPT_MON_STATS
2473 typedef __checkReturn boolean_t
2474 (*efx_monitor_ev_t)(
2476 __in efx_mon_stat_t id,
2477 __in efx_mon_stat_value_t value);
2479 #endif /* EFSYS_OPT_MON_STATS */
2481 #if EFSYS_OPT_MAC_STATS
2483 typedef __checkReturn boolean_t
2484 (*efx_mac_stats_ev_t)(
2486 __in uint32_t generation);
2488 #endif /* EFSYS_OPT_MAC_STATS */
2490 #if EFSYS_OPT_DESC_PROXY
2493 * NOTE: This callback returns the raw descriptor data, which has not been
2494 * converted to host endian. The callback must use the EFX_OWORD macros
2495 * to extract the descriptor fields as host endian values.
2497 typedef __checkReturn boolean_t
2498 (*efx_desc_proxy_txq_desc_ev_t)(
2500 __in uint16_t vi_id,
2501 __in efx_oword_t txq_desc);
2504 * NOTE: This callback returns the raw descriptor data, which has not been
2505 * converted to host endian. The callback must use the EFX_OWORD macros
2506 * to extract the descriptor fields as host endian values.
2508 typedef __checkReturn boolean_t
2509 (*efx_desc_proxy_virtq_desc_ev_t)(
2511 __in uint16_t vi_id,
2512 __in uint16_t avail,
2513 __in efx_oword_t virtq_desc);
2515 #endif /* EFSYS_OPT_DESC_PROXY */
2517 typedef struct efx_ev_callbacks_s {
2518 efx_initialized_ev_t eec_initialized;
2520 efx_rx_packets_ev_t eec_rx_packets;
2521 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
2522 efx_rx_ps_ev_t eec_rx_ps;
2525 efx_tx_ndescs_ev_t eec_tx_ndescs;
2526 efx_exception_ev_t eec_exception;
2527 efx_rxq_flush_done_ev_t eec_rxq_flush_done;
2528 efx_rxq_flush_failed_ev_t eec_rxq_flush_failed;
2529 efx_txq_flush_done_ev_t eec_txq_flush_done;
2530 efx_software_ev_t eec_software;
2531 efx_sram_ev_t eec_sram;
2532 efx_wake_up_ev_t eec_wake_up;
2533 efx_timer_ev_t eec_timer;
2534 efx_link_change_ev_t eec_link_change;
2535 #if EFSYS_OPT_MON_STATS
2536 efx_monitor_ev_t eec_monitor;
2537 #endif /* EFSYS_OPT_MON_STATS */
2538 #if EFSYS_OPT_MAC_STATS
2539 efx_mac_stats_ev_t eec_mac_stats;
2540 #endif /* EFSYS_OPT_MAC_STATS */
2541 #if EFSYS_OPT_DESC_PROXY
2542 efx_desc_proxy_txq_desc_ev_t eec_desc_proxy_txq_desc;
2543 efx_desc_proxy_virtq_desc_ev_t eec_desc_proxy_virtq_desc;
2544 #endif /* EFSYS_OPT_DESC_PROXY */
2546 } efx_ev_callbacks_t;
2549 extern __checkReturn boolean_t
2551 __in efx_evq_t *eep,
2552 __in unsigned int count);
2554 #if EFSYS_OPT_EV_PREFETCH
2559 __in efx_evq_t *eep,
2560 __in unsigned int count);
2562 #endif /* EFSYS_OPT_EV_PREFETCH */
2566 efx_ev_qcreate_check_init_done(
2567 __in efx_evq_t *eep,
2568 __in const efx_ev_callbacks_t *eecp,
2569 __in_opt void *arg);
2574 __in efx_evq_t *eep,
2575 __inout unsigned int *countp,
2576 __in const efx_ev_callbacks_t *eecp,
2577 __in_opt void *arg);
2580 extern __checkReturn efx_rc_t
2581 efx_ev_usecs_to_ticks(
2582 __in efx_nic_t *enp,
2583 __in unsigned int usecs,
2584 __out unsigned int *ticksp);
2587 extern __checkReturn efx_rc_t
2589 __in efx_evq_t *eep,
2590 __in unsigned int us);
2593 extern __checkReturn efx_rc_t
2595 __in efx_evq_t *eep,
2596 __in unsigned int count);
2598 #if EFSYS_OPT_QSTATS
2605 __in efx_nic_t *enp,
2606 __in unsigned int id);
2608 #endif /* EFSYS_OPT_NAMES */
2612 efx_ev_qstats_update(
2613 __in efx_evq_t *eep,
2614 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat);
2616 #endif /* EFSYS_OPT_QSTATS */
2621 __in efx_evq_t *eep);
2626 extern __checkReturn efx_rc_t
2628 __inout efx_nic_t *enp);
2633 __in efx_nic_t *enp);
2635 #if EFSYS_OPT_RX_SCATTER
2637 extern __checkReturn efx_rc_t
2638 efx_rx_scatter_enable(
2639 __in efx_nic_t *enp,
2640 __in unsigned int buf_size);
2641 #endif /* EFSYS_OPT_RX_SCATTER */
2643 /* Handle to represent use of the default RSS context. */
2644 #define EFX_RSS_CONTEXT_DEFAULT 0xffffffff
2646 #if EFSYS_OPT_RX_SCALE
2648 typedef enum efx_rx_hash_alg_e {
2649 EFX_RX_HASHALG_LFSR = 0,
2650 EFX_RX_HASHALG_TOEPLITZ,
2651 EFX_RX_HASHALG_PACKED_STREAM,
2653 } efx_rx_hash_alg_t;
2656 * Legacy hash type flags.
2658 * They represent standard tuples for distinct traffic classes.
2660 #define EFX_RX_HASH_IPV4 (1U << 0)
2661 #define EFX_RX_HASH_TCPIPV4 (1U << 1)
2662 #define EFX_RX_HASH_IPV6 (1U << 2)
2663 #define EFX_RX_HASH_TCPIPV6 (1U << 3)
2665 #define EFX_RX_HASH_LEGACY_MASK \
2666 (EFX_RX_HASH_IPV4 | \
2667 EFX_RX_HASH_TCPIPV4 | \
2668 EFX_RX_HASH_IPV6 | \
2669 EFX_RX_HASH_TCPIPV6)
2672 * The type of the argument used by efx_rx_scale_mode_set() to
2673 * provide a means for the client drivers to configure hashing.
2675 * A properly constructed value can either be:
2676 * - a combination of legacy flags
2677 * - a combination of EFX_RX_HASH() flags
2679 typedef uint32_t efx_rx_hash_type_t;
2681 typedef enum efx_rx_hash_support_e {
2682 EFX_RX_HASH_UNAVAILABLE = 0, /* Hardware hash not inserted */
2683 EFX_RX_HASH_AVAILABLE /* Insert hash with/without RSS */
2684 } efx_rx_hash_support_t;
2686 #define EFX_RSS_KEY_SIZE 40 /* RSS key size (bytes) */
2687 #define EFX_RSS_TBL_SIZE 128 /* Rows in RX indirection table */
2688 #define EFX_MAXRSS 64 /* RX indirection entry range */
2689 #define EFX_MAXRSS_LEGACY 16 /* See bug16611 and bug17213 */
2691 typedef enum efx_rx_scale_context_type_e {
2692 EFX_RX_SCALE_UNAVAILABLE = 0, /* No RX scale context */
2693 EFX_RX_SCALE_EXCLUSIVE, /* Writable key/indirection table */
2694 EFX_RX_SCALE_SHARED /* Read-only key/indirection table */
2695 } efx_rx_scale_context_type_t;
2698 * Traffic classes eligible for hash computation.
2700 * Select packet headers used in computing the receive hash.
2701 * This uses the same encoding as the RSS_MODES field of
2702 * MC_CMD_RSS_CONTEXT_SET_FLAGS.
2704 #define EFX_RX_CLASS_IPV4_TCP_LBN 8
2705 #define EFX_RX_CLASS_IPV4_TCP_WIDTH 4
2706 #define EFX_RX_CLASS_IPV4_UDP_LBN 12
2707 #define EFX_RX_CLASS_IPV4_UDP_WIDTH 4
2708 #define EFX_RX_CLASS_IPV4_LBN 16
2709 #define EFX_RX_CLASS_IPV4_WIDTH 4
2710 #define EFX_RX_CLASS_IPV6_TCP_LBN 20
2711 #define EFX_RX_CLASS_IPV6_TCP_WIDTH 4
2712 #define EFX_RX_CLASS_IPV6_UDP_LBN 24
2713 #define EFX_RX_CLASS_IPV6_UDP_WIDTH 4
2714 #define EFX_RX_CLASS_IPV6_LBN 28
2715 #define EFX_RX_CLASS_IPV6_WIDTH 4
2717 #define EFX_RX_NCLASSES 6
2720 * Ancillary flags used to construct generic hash tuples.
2721 * This uses the same encoding as RSS_MODE_HASH_SELECTOR.
2723 #define EFX_RX_CLASS_HASH_SRC_ADDR (1U << 0)
2724 #define EFX_RX_CLASS_HASH_DST_ADDR (1U << 1)
2725 #define EFX_RX_CLASS_HASH_SRC_PORT (1U << 2)
2726 #define EFX_RX_CLASS_HASH_DST_PORT (1U << 3)
2729 * Generic hash tuples.
2731 * They express combinations of packet fields
2732 * which can contribute to the hash value for
2733 * a particular traffic class.
2735 #define EFX_RX_CLASS_HASH_DISABLE 0
2737 #define EFX_RX_CLASS_HASH_1TUPLE_SRC EFX_RX_CLASS_HASH_SRC_ADDR
2738 #define EFX_RX_CLASS_HASH_1TUPLE_DST EFX_RX_CLASS_HASH_DST_ADDR
2740 #define EFX_RX_CLASS_HASH_2TUPLE \
2741 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2742 EFX_RX_CLASS_HASH_DST_ADDR)
2744 #define EFX_RX_CLASS_HASH_2TUPLE_SRC \
2745 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2746 EFX_RX_CLASS_HASH_SRC_PORT)
2748 #define EFX_RX_CLASS_HASH_2TUPLE_DST \
2749 (EFX_RX_CLASS_HASH_DST_ADDR | \
2750 EFX_RX_CLASS_HASH_DST_PORT)
2752 #define EFX_RX_CLASS_HASH_4TUPLE \
2753 (EFX_RX_CLASS_HASH_SRC_ADDR | \
2754 EFX_RX_CLASS_HASH_DST_ADDR | \
2755 EFX_RX_CLASS_HASH_SRC_PORT | \
2756 EFX_RX_CLASS_HASH_DST_PORT)
2758 #define EFX_RX_CLASS_HASH_NTUPLES 7
2761 * Hash flag constructor.
2763 * Resulting flags encode hash tuples for specific traffic classes.
2764 * The client drivers are encouraged to use these flags to form
2765 * a hash type value.
2767 #define EFX_RX_HASH(_class, _tuple) \
2768 EFX_INSERT_FIELD_NATIVE32(0, 31, \
2769 EFX_RX_CLASS_##_class, EFX_RX_CLASS_HASH_##_tuple)
2772 * The maximum number of EFX_RX_HASH() flags.
2774 #define EFX_RX_HASH_NFLAGS (EFX_RX_NCLASSES * EFX_RX_CLASS_HASH_NTUPLES)
2777 extern __checkReturn efx_rc_t
2778 efx_rx_scale_hash_flags_get(
2779 __in efx_nic_t *enp,
2780 __in efx_rx_hash_alg_t hash_alg,
2781 __out_ecount_part(max_nflags, *nflagsp) unsigned int *flagsp,
2782 __in unsigned int max_nflags,
2783 __out unsigned int *nflagsp);
2786 extern __checkReturn efx_rc_t
2787 efx_rx_hash_default_support_get(
2788 __in efx_nic_t *enp,
2789 __out efx_rx_hash_support_t *supportp);
2793 extern __checkReturn efx_rc_t
2794 efx_rx_scale_default_support_get(
2795 __in efx_nic_t *enp,
2796 __out efx_rx_scale_context_type_t *typep);
2799 extern __checkReturn efx_rc_t
2800 efx_rx_scale_context_alloc(
2801 __in efx_nic_t *enp,
2802 __in efx_rx_scale_context_type_t type,
2803 __in uint32_t num_queues,
2804 __out uint32_t *rss_contextp);
2807 extern __checkReturn efx_rc_t
2808 efx_rx_scale_context_free(
2809 __in efx_nic_t *enp,
2810 __in uint32_t rss_context);
2813 extern __checkReturn efx_rc_t
2814 efx_rx_scale_mode_set(
2815 __in efx_nic_t *enp,
2816 __in uint32_t rss_context,
2817 __in efx_rx_hash_alg_t alg,
2818 __in efx_rx_hash_type_t type,
2819 __in boolean_t insert);
2822 extern __checkReturn efx_rc_t
2823 efx_rx_scale_tbl_set(
2824 __in efx_nic_t *enp,
2825 __in uint32_t rss_context,
2826 __in_ecount(n) unsigned int *table,
2830 extern __checkReturn efx_rc_t
2831 efx_rx_scale_key_set(
2832 __in efx_nic_t *enp,
2833 __in uint32_t rss_context,
2834 __in_ecount(n) uint8_t *key,
2838 extern __checkReturn uint32_t
2839 efx_pseudo_hdr_hash_get(
2840 __in efx_rxq_t *erp,
2841 __in efx_rx_hash_alg_t func,
2842 __in uint8_t *buffer);
2844 #endif /* EFSYS_OPT_RX_SCALE */
2847 extern __checkReturn efx_rc_t
2848 efx_pseudo_hdr_pkt_length_get(
2849 __in efx_rxq_t *erp,
2850 __in uint8_t *buffer,
2851 __out uint16_t *pkt_lengthp);
2854 extern __checkReturn size_t
2856 __in const efx_nic_t *enp,
2857 __in unsigned int ndescs);
2860 extern __checkReturn unsigned int
2862 __in const efx_nic_t *enp,
2863 __in unsigned int ndescs);
2865 #define EFX_RXQ_LIMIT(_ndescs) ((_ndescs) - 16)
2868 * libefx representation of the Rx prefix layout information.
2870 * The information may be used inside libefx to implement Rx prefix fields
2871 * accessors and by drivers which process Rx prefix itself.
2875 * All known Rx prefix fields.
2877 * An Rx prefix may have a subset of these fields.
2879 typedef enum efx_rx_prefix_field_e {
2880 EFX_RX_PREFIX_FIELD_LENGTH = 0,
2881 EFX_RX_PREFIX_FIELD_ORIG_LENGTH,
2882 EFX_RX_PREFIX_FIELD_CLASS,
2883 EFX_RX_PREFIX_FIELD_RSS_HASH,
2884 EFX_RX_PREFIX_FIELD_RSS_HASH_VALID,
2885 EFX_RX_PREFIX_FIELD_PARTIAL_TSTAMP,
2886 EFX_RX_PREFIX_FIELD_VLAN_STRIP_TCI,
2887 EFX_RX_PREFIX_FIELD_INNER_VLAN_STRIP_TCI,
2888 EFX_RX_PREFIX_FIELD_USER_FLAG,
2889 EFX_RX_PREFIX_FIELD_USER_MARK,
2890 EFX_RX_PREFIX_FIELD_USER_MARK_VALID,
2891 EFX_RX_PREFIX_FIELD_CSUM_FRAME,
2892 EFX_RX_PREFIX_FIELD_INGRESS_VPORT,
2893 EFX_RX_PREFIX_NFIELDS
2894 } efx_rx_prefix_field_t;
2897 * Location and endianness of a field in Rx prefix.
2899 * If width is zero, the field is not present.
2901 typedef struct efx_rx_prefix_field_info_s {
2902 uint16_t erpfi_offset_bits;
2903 uint8_t erpfi_width_bits;
2904 boolean_t erpfi_big_endian;
2905 } efx_rx_prefix_field_info_t;
2907 /* Helper macro to define Rx prefix fields */
2908 #define EFX_RX_PREFIX_FIELD(_efx, _field, _big_endian) \
2909 [EFX_RX_PREFIX_FIELD_ ## _efx] = { \
2910 .erpfi_offset_bits = EFX_LOW_BIT(_field), \
2911 .erpfi_width_bits = EFX_WIDTH(_field), \
2912 .erpfi_big_endian = (_big_endian), \
2915 typedef struct efx_rx_prefix_layout_s {
2917 uint8_t erpl_length;
2918 efx_rx_prefix_field_info_t erpl_fields[EFX_RX_PREFIX_NFIELDS];
2919 } efx_rx_prefix_layout_t;
2922 extern __checkReturn efx_rc_t
2923 efx_rx_prefix_get_layout(
2924 __in const efx_rxq_t *erp,
2925 __out efx_rx_prefix_layout_t *erplp);
2927 typedef enum efx_rxq_type_e {
2928 EFX_RXQ_TYPE_DEFAULT,
2929 EFX_RXQ_TYPE_PACKED_STREAM,
2930 EFX_RXQ_TYPE_ES_SUPER_BUFFER,
2935 * Dummy flag to be used instead of 0 to make it clear that the argument
2936 * is receive queue flags.
2938 #define EFX_RXQ_FLAG_NONE 0x0
2939 #define EFX_RXQ_FLAG_SCATTER 0x1
2941 * If tunnels are supported and Rx event can provide information about
2942 * either outer or inner packet classes (e.g. SFN8xxx adapters with
2943 * full-feature firmware variant running), outer classes are requested by
2944 * default. However, if the driver supports tunnels, the flag allows to
2945 * request inner classes which are required to be able to interpret inner
2946 * Rx checksum offload results.
2948 #define EFX_RXQ_FLAG_INNER_CLASSES 0x2
2951 extern __checkReturn efx_rc_t
2953 __in efx_nic_t *enp,
2954 __in unsigned int index,
2955 __in unsigned int label,
2956 __in efx_rxq_type_t type,
2957 __in size_t buf_size,
2958 __in efsys_mem_t *esmp,
2961 __in unsigned int flags,
2962 __in efx_evq_t *eep,
2963 __deref_out efx_rxq_t **erpp);
2965 #if EFSYS_OPT_RX_PACKED_STREAM
2967 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_1M (1U * 1024 * 1024)
2968 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_512K (512U * 1024)
2969 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_256K (256U * 1024)
2970 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_128K (128U * 1024)
2971 #define EFX_RXQ_PACKED_STREAM_BUF_SIZE_64K (64U * 1024)
2974 extern __checkReturn efx_rc_t
2975 efx_rx_qcreate_packed_stream(
2976 __in efx_nic_t *enp,
2977 __in unsigned int index,
2978 __in unsigned int label,
2979 __in uint32_t ps_buf_size,
2980 __in efsys_mem_t *esmp,
2982 __in efx_evq_t *eep,
2983 __deref_out efx_rxq_t **erpp);
2987 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
2989 /* Maximum head-of-line block timeout in nanoseconds */
2990 #define EFX_RXQ_ES_SUPER_BUFFER_HOL_BLOCK_MAX (400U * 1000 * 1000)
2993 extern __checkReturn efx_rc_t
2994 efx_rx_qcreate_es_super_buffer(
2995 __in efx_nic_t *enp,
2996 __in unsigned int index,
2997 __in unsigned int label,
2998 __in uint32_t n_bufs_per_desc,
2999 __in uint32_t max_dma_len,
3000 __in uint32_t buf_stride,
3001 __in uint32_t hol_block_timeout,
3002 __in efsys_mem_t *esmp,
3004 __in unsigned int flags,
3005 __in efx_evq_t *eep,
3006 __deref_out efx_rxq_t **erpp);
3010 typedef struct efx_buffer_s {
3011 efsys_dma_addr_t eb_addr;
3016 typedef struct efx_desc_s {
3023 __in efx_rxq_t *erp,
3024 __in_ecount(ndescs) efsys_dma_addr_t *addrp,
3026 __in unsigned int ndescs,
3027 __in unsigned int completed,
3028 __in unsigned int added);
3033 __in efx_rxq_t *erp,
3034 __in unsigned int added,
3035 __inout unsigned int *pushedp);
3037 #if EFSYS_OPT_RX_PACKED_STREAM
3041 efx_rx_qpush_ps_credits(
3042 __in efx_rxq_t *erp);
3045 extern __checkReturn uint8_t *
3046 efx_rx_qps_packet_info(
3047 __in efx_rxq_t *erp,
3048 __in uint8_t *buffer,
3049 __in uint32_t buffer_length,
3050 __in uint32_t current_offset,
3051 __out uint16_t *lengthp,
3052 __out uint32_t *next_offsetp,
3053 __out uint32_t *timestamp);
3057 extern __checkReturn efx_rc_t
3059 __in efx_rxq_t *erp);
3064 __in efx_rxq_t *erp);
3069 __in efx_rxq_t *erp);
3073 typedef struct efx_txq_s efx_txq_t;
3075 #if EFSYS_OPT_QSTATS
3077 /* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
3078 typedef enum efx_tx_qstat_e {
3084 /* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
3086 #endif /* EFSYS_OPT_QSTATS */
3089 extern __checkReturn efx_rc_t
3091 __in efx_nic_t *enp);
3096 __in efx_nic_t *enp);
3099 extern __checkReturn size_t
3101 __in const efx_nic_t *enp,
3102 __in unsigned int ndescs);
3105 extern __checkReturn unsigned int
3107 __in const efx_nic_t *enp,
3108 __in unsigned int ndescs);
3110 #define EFX_TXQ_LIMIT(_ndescs) ((_ndescs) - 16)
3112 #define EFX_TXQ_CKSUM_IPV4 0x0001
3113 #define EFX_TXQ_CKSUM_TCPUDP 0x0002
3114 #define EFX_TXQ_FATSOV2 0x0004
3115 #define EFX_TXQ_CKSUM_INNER_IPV4 0x0008
3116 #define EFX_TXQ_CKSUM_INNER_TCPUDP 0x0010
3119 extern __checkReturn efx_rc_t
3121 __in efx_nic_t *enp,
3122 __in unsigned int index,
3123 __in unsigned int label,
3124 __in efsys_mem_t *esmp,
3127 __in uint16_t flags,
3128 __in efx_evq_t *eep,
3129 __deref_out efx_txq_t **etpp,
3130 __out unsigned int *addedp);
3133 extern __checkReturn efx_rc_t
3135 __in efx_txq_t *etp,
3136 __in_ecount(ndescs) efx_buffer_t *eb,
3137 __in unsigned int ndescs,
3138 __in unsigned int completed,
3139 __inout unsigned int *addedp);
3142 extern __checkReturn efx_rc_t
3144 __in efx_txq_t *etp,
3145 __in unsigned int ns);
3150 __in efx_txq_t *etp,
3151 __in unsigned int added,
3152 __in unsigned int pushed);
3155 extern __checkReturn efx_rc_t
3157 __in efx_txq_t *etp);
3162 __in efx_txq_t *etp);
3165 extern __checkReturn efx_rc_t
3167 __in efx_txq_t *etp);
3171 efx_tx_qpio_disable(
3172 __in efx_txq_t *etp);
3175 extern __checkReturn efx_rc_t
3177 __in efx_txq_t *etp,
3178 __in_ecount(buf_length) uint8_t *buffer,
3179 __in size_t buf_length,
3180 __in size_t pio_buf_offset);
3183 extern __checkReturn efx_rc_t
3185 __in efx_txq_t *etp,
3186 __in size_t pkt_length,
3187 __in unsigned int completed,
3188 __inout unsigned int *addedp);
3191 extern __checkReturn efx_rc_t
3193 __in efx_txq_t *etp,
3194 __in_ecount(n) efx_desc_t *ed,
3195 __in unsigned int n,
3196 __in unsigned int completed,
3197 __inout unsigned int *addedp);
3201 efx_tx_qdesc_dma_create(
3202 __in efx_txq_t *etp,
3203 __in efsys_dma_addr_t addr,
3206 __out efx_desc_t *edp);
3210 efx_tx_qdesc_tso_create(
3211 __in efx_txq_t *etp,
3212 __in uint16_t ipv4_id,
3213 __in uint32_t tcp_seq,
3214 __in uint8_t tcp_flags,
3215 __out efx_desc_t *edp);
3217 /* Number of FATSOv2 option descriptors */
3218 #define EFX_TX_FATSOV2_OPT_NDESCS 2
3220 /* Maximum number of DMA segments per TSO packet (not superframe) */
3221 #define EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX 24
3225 efx_tx_qdesc_tso2_create(
3226 __in efx_txq_t *etp,
3227 __in uint16_t ipv4_id,
3228 __in uint16_t outer_ipv4_id,
3229 __in uint32_t tcp_seq,
3230 __in uint16_t tcp_mss,
3231 __out_ecount(count) efx_desc_t *edp,
3236 efx_tx_qdesc_vlantci_create(
3237 __in efx_txq_t *etp,
3239 __out efx_desc_t *edp);
3243 efx_tx_qdesc_checksum_create(
3244 __in efx_txq_t *etp,
3245 __in uint16_t flags,
3246 __out efx_desc_t *edp);
3248 #if EFSYS_OPT_QSTATS
3255 __in efx_nic_t *etp,
3256 __in unsigned int id);
3258 #endif /* EFSYS_OPT_NAMES */
3262 efx_tx_qstats_update(
3263 __in efx_txq_t *etp,
3264 __inout_ecount(TX_NQSTATS) efsys_stat_t *stat);
3266 #endif /* EFSYS_OPT_QSTATS */
3271 __in efx_txq_t *etp);
3276 #if EFSYS_OPT_FILTER
3278 #define EFX_ETHER_TYPE_IPV4 0x0800
3279 #define EFX_ETHER_TYPE_IPV6 0x86DD
3281 #define EFX_IPPROTO_TCP 6
3282 #define EFX_IPPROTO_UDP 17
3283 #define EFX_IPPROTO_GRE 47
3285 /* Use RSS to spread across multiple queues */
3286 #define EFX_FILTER_FLAG_RX_RSS 0x01
3287 /* Enable RX scatter */
3288 #define EFX_FILTER_FLAG_RX_SCATTER 0x02
3290 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
3291 * May only be set by the filter implementation for each type.
3292 * A removal request will restore the automatic filter in its place.
3294 #define EFX_FILTER_FLAG_RX_OVER_AUTO 0x04
3295 /* Filter is for RX */
3296 #define EFX_FILTER_FLAG_RX 0x08
3297 /* Filter is for TX */
3298 #define EFX_FILTER_FLAG_TX 0x10
3299 /* Set match flag on the received packet */
3300 #define EFX_FILTER_FLAG_ACTION_FLAG 0x20
3301 /* Set match mark on the received packet */
3302 #define EFX_FILTER_FLAG_ACTION_MARK 0x40
3304 typedef uint8_t efx_filter_flags_t;
3307 * Flags which specify the fields to match on. The values are the same as in the
3308 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
3311 /* Match by remote IP host address */
3312 #define EFX_FILTER_MATCH_REM_HOST 0x00000001
3313 /* Match by local IP host address */
3314 #define EFX_FILTER_MATCH_LOC_HOST 0x00000002
3315 /* Match by remote MAC address */
3316 #define EFX_FILTER_MATCH_REM_MAC 0x00000004
3317 /* Match by remote TCP/UDP port */
3318 #define EFX_FILTER_MATCH_REM_PORT 0x00000008
3319 /* Match by remote TCP/UDP port */
3320 #define EFX_FILTER_MATCH_LOC_MAC 0x00000010
3321 /* Match by local TCP/UDP port */
3322 #define EFX_FILTER_MATCH_LOC_PORT 0x00000020
3323 /* Match by Ether-type */
3324 #define EFX_FILTER_MATCH_ETHER_TYPE 0x00000040
3325 /* Match by inner VLAN ID */
3326 #define EFX_FILTER_MATCH_INNER_VID 0x00000080
3327 /* Match by outer VLAN ID */
3328 #define EFX_FILTER_MATCH_OUTER_VID 0x00000100
3329 /* Match by IP transport protocol */
3330 #define EFX_FILTER_MATCH_IP_PROTO 0x00000200
3331 /* Match by VNI or VSID */
3332 #define EFX_FILTER_MATCH_VNI_OR_VSID 0x00000800
3333 /* For encapsulated packets, match by inner frame local MAC address */
3334 #define EFX_FILTER_MATCH_IFRM_LOC_MAC 0x00010000
3335 /* For encapsulated packets, match all multicast inner frames */
3336 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST 0x01000000
3337 /* For encapsulated packets, match all unicast inner frames */
3338 #define EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST 0x02000000
3340 * Match by encap type, this flag does not correspond to
3341 * the MCDI match flags and any unoccupied value may be used
3343 #define EFX_FILTER_MATCH_ENCAP_TYPE 0x20000000
3344 /* Match otherwise-unmatched multicast and broadcast packets */
3345 #define EFX_FILTER_MATCH_UNKNOWN_MCAST_DST 0x40000000
3346 /* Match otherwise-unmatched unicast packets */
3347 #define EFX_FILTER_MATCH_UNKNOWN_UCAST_DST 0x80000000
3349 typedef uint32_t efx_filter_match_flags_t;
3351 /* Filter priority from lowest to highest */
3352 typedef enum efx_filter_priority_s {
3353 EFX_FILTER_PRI_AUTO = 0, /* Automatic filter based on device
3354 * address list or hardware
3355 * requirements. This may only be used
3356 * by the filter implementation for
3358 EFX_FILTER_PRI_MANUAL, /* Manually configured filter */
3360 } efx_filter_priority_t;
3363 * FIXME: All these fields are assumed to be in little-endian byte order.
3364 * It may be better for some to be big-endian. See bug42804.
3367 typedef struct efx_filter_spec_s {
3368 efx_filter_match_flags_t efs_match_flags;
3369 uint8_t efs_priority;
3370 efx_filter_flags_t efs_flags;
3371 uint16_t efs_dmaq_id;
3372 uint32_t efs_rss_context;
3375 * Saved lower-priority filter. If it is set, it is restored on
3376 * filter delete operation.
3378 struct efx_filter_spec_s *efs_overridden_spec;
3379 /* Fields below here are hashed for software filter lookup */
3380 uint16_t efs_outer_vid;
3381 uint16_t efs_inner_vid;
3382 uint8_t efs_loc_mac[EFX_MAC_ADDR_LEN];
3383 uint8_t efs_rem_mac[EFX_MAC_ADDR_LEN];
3384 uint16_t efs_ether_type;
3385 uint8_t efs_ip_proto;
3386 efx_tunnel_protocol_t efs_encap_type;
3387 uint16_t efs_loc_port;
3388 uint16_t efs_rem_port;
3389 efx_oword_t efs_rem_host;
3390 efx_oword_t efs_loc_host;
3391 uint8_t efs_vni_or_vsid[EFX_VNI_OR_VSID_LEN];
3392 uint8_t efs_ifrm_loc_mac[EFX_MAC_ADDR_LEN];
3393 } efx_filter_spec_t;
3396 /* Default values for use in filter specifications */
3397 #define EFX_FILTER_SPEC_RX_DMAQ_ID_DROP 0xfff
3398 #define EFX_FILTER_SPEC_VID_UNSPEC 0xffff
3401 extern __checkReturn efx_rc_t
3403 __in efx_nic_t *enp);
3408 __in efx_nic_t *enp);
3411 extern __checkReturn efx_rc_t
3413 __in efx_nic_t *enp,
3414 __inout efx_filter_spec_t *spec);
3417 extern __checkReturn efx_rc_t
3419 __in efx_nic_t *enp,
3420 __inout efx_filter_spec_t *spec);
3423 extern __checkReturn efx_rc_t
3425 __in efx_nic_t *enp);
3428 extern __checkReturn efx_rc_t
3429 efx_filter_supported_filters(
3430 __in efx_nic_t *enp,
3431 __out_ecount(buffer_length) uint32_t *buffer,
3432 __in size_t buffer_length,
3433 __out size_t *list_lengthp);
3437 efx_filter_spec_init_rx(
3438 __out efx_filter_spec_t *spec,
3439 __in efx_filter_priority_t priority,
3440 __in efx_filter_flags_t flags,
3441 __in efx_rxq_t *erp);
3445 efx_filter_spec_init_tx(
3446 __out efx_filter_spec_t *spec,
3447 __in efx_txq_t *etp);
3450 extern __checkReturn efx_rc_t
3451 efx_filter_spec_set_ipv4_local(
3452 __inout efx_filter_spec_t *spec,
3455 __in uint16_t port);
3458 extern __checkReturn efx_rc_t
3459 efx_filter_spec_set_ipv4_full(
3460 __inout efx_filter_spec_t *spec,
3462 __in uint32_t lhost,
3463 __in uint16_t lport,
3464 __in uint32_t rhost,
3465 __in uint16_t rport);
3468 extern __checkReturn efx_rc_t
3469 efx_filter_spec_set_eth_local(
3470 __inout efx_filter_spec_t *spec,
3472 __in const uint8_t *addr);
3476 efx_filter_spec_set_ether_type(
3477 __inout efx_filter_spec_t *spec,
3478 __in uint16_t ether_type);
3481 extern __checkReturn efx_rc_t
3482 efx_filter_spec_set_uc_def(
3483 __inout efx_filter_spec_t *spec);
3486 extern __checkReturn efx_rc_t
3487 efx_filter_spec_set_mc_def(
3488 __inout efx_filter_spec_t *spec);
3490 typedef enum efx_filter_inner_frame_match_e {
3491 EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
3492 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
3493 EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
3494 } efx_filter_inner_frame_match_t;
3497 extern __checkReturn efx_rc_t
3498 efx_filter_spec_set_encap_type(
3499 __inout efx_filter_spec_t *spec,
3500 __in efx_tunnel_protocol_t encap_type,
3501 __in efx_filter_inner_frame_match_t inner_frame_match);
3504 extern __checkReturn efx_rc_t
3505 efx_filter_spec_set_vxlan(
3506 __inout efx_filter_spec_t *spec,
3507 __in const uint8_t *vni,
3508 __in const uint8_t *inner_addr,
3509 __in const uint8_t *outer_addr);
3512 extern __checkReturn efx_rc_t
3513 efx_filter_spec_set_geneve(
3514 __inout efx_filter_spec_t *spec,
3515 __in const uint8_t *vni,
3516 __in const uint8_t *inner_addr,
3517 __in const uint8_t *outer_addr);
3520 extern __checkReturn efx_rc_t
3521 efx_filter_spec_set_nvgre(
3522 __inout efx_filter_spec_t *spec,
3523 __in const uint8_t *vsid,
3524 __in const uint8_t *inner_addr,
3525 __in const uint8_t *outer_addr);
3527 #if EFSYS_OPT_RX_SCALE
3529 extern __checkReturn efx_rc_t
3530 efx_filter_spec_set_rss_context(
3531 __inout efx_filter_spec_t *spec,
3532 __in uint32_t rss_context);
3534 #endif /* EFSYS_OPT_FILTER */
3539 extern __checkReturn uint32_t
3541 __in_ecount(count) uint32_t const *input,
3543 __in uint32_t init);
3546 extern __checkReturn uint32_t
3548 __in_ecount(length) uint8_t const *input,
3550 __in uint32_t init);
3552 #if EFSYS_OPT_LICENSING
3556 typedef struct efx_key_stats_s {
3558 uint32_t eks_invalid;
3559 uint32_t eks_blacklisted;
3560 uint32_t eks_unverifiable;
3561 uint32_t eks_wrong_node;
3562 uint32_t eks_licensed_apps_lo;
3563 uint32_t eks_licensed_apps_hi;
3564 uint32_t eks_licensed_features_lo;
3565 uint32_t eks_licensed_features_hi;
3569 extern __checkReturn efx_rc_t
3571 __in efx_nic_t *enp);
3576 __in efx_nic_t *enp);
3579 extern __checkReturn boolean_t
3580 efx_lic_check_support(
3581 __in efx_nic_t *enp);
3584 extern __checkReturn efx_rc_t
3585 efx_lic_update_licenses(
3586 __in efx_nic_t *enp);
3589 extern __checkReturn efx_rc_t
3590 efx_lic_get_key_stats(
3591 __in efx_nic_t *enp,
3592 __out efx_key_stats_t *ksp);
3595 extern __checkReturn efx_rc_t
3597 __in efx_nic_t *enp,
3598 __in uint64_t app_id,
3599 __out boolean_t *licensedp);
3602 extern __checkReturn efx_rc_t
3604 __in efx_nic_t *enp,
3605 __in size_t buffer_size,
3606 __out uint32_t *typep,
3607 __out size_t *lengthp,
3608 __out_opt uint8_t *bufferp);
3612 extern __checkReturn efx_rc_t
3614 __in efx_nic_t *enp,
3615 __in_bcount(buffer_size)
3617 __in size_t buffer_size,
3618 __out uint32_t *startp);
3621 extern __checkReturn efx_rc_t
3623 __in efx_nic_t *enp,
3624 __in_bcount(buffer_size)
3626 __in size_t buffer_size,
3627 __in uint32_t offset,
3628 __out uint32_t *endp);
3631 extern __checkReturn __success(return != B_FALSE) boolean_t
3633 __in efx_nic_t *enp,
3634 __in_bcount(buffer_size)
3636 __in size_t buffer_size,
3637 __in uint32_t offset,
3638 __out uint32_t *startp,
3639 __out uint32_t *lengthp);
3642 extern __checkReturn __success(return != B_FALSE) boolean_t
3643 efx_lic_validate_key(
3644 __in efx_nic_t *enp,
3645 __in_bcount(length) caddr_t keyp,
3646 __in uint32_t length);
3649 extern __checkReturn efx_rc_t
3651 __in efx_nic_t *enp,
3652 __in_bcount(buffer_size)
3654 __in size_t buffer_size,
3655 __in uint32_t offset,
3656 __in uint32_t length,
3657 __out_bcount_part(key_max_size, *lengthp)
3659 __in size_t key_max_size,
3660 __out uint32_t *lengthp);
3663 extern __checkReturn efx_rc_t
3665 __in efx_nic_t *enp,
3666 __in_bcount(buffer_size)
3668 __in size_t buffer_size,
3669 __in uint32_t offset,
3670 __in_bcount(length) caddr_t keyp,
3671 __in uint32_t length,
3672 __out uint32_t *lengthp);
3675 extern __checkReturn efx_rc_t
3677 __in efx_nic_t *enp,
3678 __in_bcount(buffer_size)
3680 __in size_t buffer_size,
3681 __in uint32_t offset,
3682 __in uint32_t length,
3684 __out uint32_t *deltap);
3687 extern __checkReturn efx_rc_t
3688 efx_lic_create_partition(
3689 __in efx_nic_t *enp,
3690 __in_bcount(buffer_size)
3692 __in size_t buffer_size);
3694 extern __checkReturn efx_rc_t
3695 efx_lic_finish_partition(
3696 __in efx_nic_t *enp,
3697 __in_bcount(buffer_size)
3699 __in size_t buffer_size);
3701 #endif /* EFSYS_OPT_LICENSING */
3705 #if EFSYS_OPT_TUNNEL
3708 extern __checkReturn efx_rc_t
3710 __in efx_nic_t *enp);
3715 __in efx_nic_t *enp);
3718 * For overlay network encapsulation using UDP, the firmware needs to know
3719 * the configured UDP port for the overlay so it can decode encapsulated
3721 * The UDP port/protocol list is global.
3725 extern __checkReturn efx_rc_t
3726 efx_tunnel_config_udp_add(
3727 __in efx_nic_t *enp,
3728 __in uint16_t port /* host/cpu-endian */,
3729 __in efx_tunnel_protocol_t protocol);
3732 * Returns EBUSY if reconfiguration of the port is in progress in other thread.
3735 extern __checkReturn efx_rc_t
3736 efx_tunnel_config_udp_remove(
3737 __in efx_nic_t *enp,
3738 __in uint16_t port /* host/cpu-endian */,
3739 __in efx_tunnel_protocol_t protocol);
3742 * Returns EBUSY if reconfiguration of any of the tunnel entries
3743 * is in progress in other thread.
3746 extern __checkReturn efx_rc_t
3747 efx_tunnel_config_clear(
3748 __in efx_nic_t *enp);
3751 * Apply tunnel UDP ports configuration to hardware.
3753 * EAGAIN is returned if hardware will be reset (datapath and managment CPU
3757 extern __checkReturn efx_rc_t
3758 efx_tunnel_reconfigure(
3759 __in efx_nic_t *enp);
3761 #endif /* EFSYS_OPT_TUNNEL */
3763 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
3766 * Firmware subvariant choice options.
3768 * It may be switched to no Tx checksum if attached drivers are either
3769 * preboot or firmware subvariant aware and no VIS are allocated.
3770 * If may be always switched to default explicitly using set request or
3771 * implicitly if unaware driver is attaching. If switching is done when
3772 * a driver is attached, it gets MC_REBOOT event and should recreate its
3775 * See SF-119419-TC DPDK Firmware Driver Interface and
3776 * SF-109306-TC EF10 for Driver Writers for details.
3778 typedef enum efx_nic_fw_subvariant_e {
3779 EFX_NIC_FW_SUBVARIANT_DEFAULT = 0,
3780 EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM = 1,
3781 EFX_NIC_FW_SUBVARIANT_NTYPES
3782 } efx_nic_fw_subvariant_t;
3785 extern __checkReturn efx_rc_t
3786 efx_nic_get_fw_subvariant(
3787 __in efx_nic_t *enp,
3788 __out efx_nic_fw_subvariant_t *subvariantp);
3791 extern __checkReturn efx_rc_t
3792 efx_nic_set_fw_subvariant(
3793 __in efx_nic_t *enp,
3794 __in efx_nic_fw_subvariant_t subvariant);
3796 #endif /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
3798 typedef enum efx_phy_fec_type_e {
3799 EFX_PHY_FEC_NONE = 0,
3802 } efx_phy_fec_type_t;
3805 extern __checkReturn efx_rc_t
3806 efx_phy_fec_type_get(
3807 __in efx_nic_t *enp,
3808 __out efx_phy_fec_type_t *typep);
3810 typedef struct efx_phy_link_state_s {
3811 uint32_t epls_adv_cap_mask;
3812 uint32_t epls_lp_cap_mask;
3813 uint32_t epls_ld_cap_mask;
3814 unsigned int epls_fcntl;
3815 efx_phy_fec_type_t epls_fec;
3816 efx_link_mode_t epls_link_mode;
3817 } efx_phy_link_state_t;
3820 extern __checkReturn efx_rc_t
3821 efx_phy_link_state_get(
3822 __in efx_nic_t *enp,
3823 __out efx_phy_link_state_t *eplsp);
3828 typedef uint32_t efx_vswitch_id_t;
3829 typedef uint32_t efx_vport_id_t;
3831 typedef enum efx_vswitch_type_e {
3832 EFX_VSWITCH_TYPE_VLAN = 1,
3833 EFX_VSWITCH_TYPE_VEB,
3834 /* VSWITCH_TYPE_VEPA: obsolete */
3835 EFX_VSWITCH_TYPE_MUX = 4,
3836 } efx_vswitch_type_t;
3838 typedef enum efx_vport_type_e {
3839 EFX_VPORT_TYPE_NORMAL = 4,
3840 EFX_VPORT_TYPE_EXPANSION,
3841 EFX_VPORT_TYPE_TEST,
3844 /* Unspecified VLAN ID to support disabling of VLAN filtering */
3845 #define EFX_FILTER_VID_UNSPEC 0xffff
3846 #define EFX_DEFAULT_VSWITCH_ID 1
3848 /* Default VF VLAN ID on creation */
3849 #define EFX_VF_VID_DEFAULT EFX_FILTER_VID_UNSPEC
3850 #define EFX_VPORT_ID_INVALID 0
3852 typedef struct efx_vport_config_s {
3853 /* Either VF index or 0xffff for PF */
3854 uint16_t evc_function;
3855 /* VLAN ID of the associated function */
3857 /* vport id shared with client driver */
3858 efx_vport_id_t evc_vport_id;
3859 /* MAC address of the associated function */
3860 uint8_t evc_mac_addr[EFX_MAC_ADDR_LEN];
3862 * vports created with this flag set may only transfer traffic on the
3863 * VLANs permitted by the vport. Also, an attempt to install filter with
3864 * VLAN will be refused unless requesting function has VLAN privilege.
3866 boolean_t evc_vlan_restrict;
3867 /* Whether this function is assigned or not */
3868 boolean_t evc_vport_assigned;
3869 } efx_vport_config_t;
3871 typedef struct efx_vswitch_s efx_vswitch_t;
3874 extern __checkReturn efx_rc_t
3876 __in efx_nic_t *enp);
3881 __in efx_nic_t *enp);
3884 extern __checkReturn efx_rc_t
3885 efx_evb_vswitch_create(
3886 __in efx_nic_t *enp,
3887 __in uint32_t num_vports,
3888 __inout_ecount(num_vports) efx_vport_config_t *vport_configp,
3889 __deref_out efx_vswitch_t **evpp);
3892 extern __checkReturn efx_rc_t
3893 efx_evb_vswitch_destroy(
3894 __in efx_nic_t *enp,
3895 __in efx_vswitch_t *evp);
3898 extern __checkReturn efx_rc_t
3899 efx_evb_vport_mac_set(
3900 __in efx_nic_t *enp,
3901 __in efx_vswitch_t *evp,
3902 __in efx_vport_id_t vport_id,
3903 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp);
3906 extern __checkReturn efx_rc_t
3907 efx_evb_vport_vlan_set(
3908 __in efx_nic_t *enp,
3909 __in efx_vswitch_t *evp,
3910 __in efx_vport_id_t vport_id,
3914 extern __checkReturn efx_rc_t
3915 efx_evb_vport_reset(
3916 __in efx_nic_t *enp,
3917 __in efx_vswitch_t *evp,
3918 __in efx_vport_id_t vport_id,
3919 __in_bcount(EFX_MAC_ADDR_LEN) uint8_t *addrp,
3921 __out boolean_t *is_fn_resetp);
3924 extern __checkReturn efx_rc_t
3925 efx_evb_vport_stats(
3926 __in efx_nic_t *enp,
3927 __in efx_vswitch_t *evp,
3928 __in efx_vport_id_t vport_id,
3929 __out efsys_mem_t *stats_bufferp);
3931 #endif /* EFSYS_OPT_EVB */
3933 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
3935 typedef struct efx_proxy_auth_config_s {
3936 efsys_mem_t *request_bufferp;
3937 efsys_mem_t *response_bufferp;
3938 efsys_mem_t *status_bufferp;
3942 uint32_t handled_privileges;
3943 } efx_proxy_auth_config_t;
3945 typedef struct efx_proxy_cmd_params_s {
3948 uint8_t *request_bufferp;
3949 size_t request_size;
3950 uint8_t *response_bufferp;
3951 size_t response_size;
3952 size_t *response_size_actualp;
3953 } efx_proxy_cmd_params_t;
3956 extern __checkReturn efx_rc_t
3957 efx_proxy_auth_init(
3958 __in efx_nic_t *enp);
3962 efx_proxy_auth_fini(
3963 __in efx_nic_t *enp);
3966 extern __checkReturn efx_rc_t
3967 efx_proxy_auth_configure(
3968 __in efx_nic_t *enp,
3969 __in efx_proxy_auth_config_t *configp);
3972 extern __checkReturn efx_rc_t
3973 efx_proxy_auth_destroy(
3974 __in efx_nic_t *enp,
3975 __in uint32_t handled_privileges);
3978 extern __checkReturn efx_rc_t
3979 efx_proxy_auth_complete_request(
3980 __in efx_nic_t *enp,
3981 __in uint32_t fn_index,
3982 __in uint32_t proxy_result,
3983 __in uint32_t handle);
3986 extern __checkReturn efx_rc_t
3987 efx_proxy_auth_exec_cmd(
3988 __in efx_nic_t *enp,
3989 __inout efx_proxy_cmd_params_t *paramsp);
3992 extern __checkReturn efx_rc_t
3993 efx_proxy_auth_set_privilege_mask(
3994 __in efx_nic_t *enp,
3995 __in uint32_t vf_index,
3997 __in uint32_t value);
4000 extern __checkReturn efx_rc_t
4001 efx_proxy_auth_privilege_mask_get(
4002 __in efx_nic_t *enp,
4003 __in uint32_t pf_index,
4004 __in uint32_t vf_index,
4005 __out uint32_t *maskp);
4008 extern __checkReturn efx_rc_t
4009 efx_proxy_auth_privilege_modify(
4010 __in efx_nic_t *enp,
4011 __in uint32_t pf_index,
4012 __in uint32_t vf_index,
4013 __in uint32_t add_privileges_mask,
4014 __in uint32_t remove_privileges_mask);
4016 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
4022 #endif /* _SYS_EFX_H */