drivers/common/sfc_efx/base/efx_ev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9 #if EFSYS_OPT_MON_MCDI
  10 #include "mcdi_mon.h"
  11 #endif
  12
  13 #define EFX_EV_PRESENT(_qword)                                          \
  14         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
  15         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
  16
  17
  18
  19 #if EFSYS_OPT_SIENA
  20
  21 static  __checkReturn   efx_rc_t
  22 siena_ev_init(
  23         __in            efx_nic_t *enp);
  24
  25 static                  void
  26 siena_ev_fini(
  27         __in            efx_nic_t *enp);
  28
  29 static  __checkReturn   efx_rc_t
  30 siena_ev_qcreate(
  31         __in            efx_nic_t *enp,
  32         __in            unsigned int index,
  33         __in            efsys_mem_t *esmp,
  34         __in            size_t ndescs,
  35         __in            uint32_t id,
  36         __in            uint32_t us,
  37         __in            uint32_t flags,
  38         __in            efx_evq_t *eep);
  39
  40 static                  void
  41 siena_ev_qdestroy(
  42         __in            efx_evq_t *eep);
  43
  44 static  __checkReturn   efx_rc_t
  45 siena_ev_qprime(
  46         __in            efx_evq_t *eep,
  47         __in            unsigned int count);
  48
  49 static                  void
  50 siena_ev_qpost(
  51         __in    efx_evq_t *eep,
  52         __in    uint16_t data);
  53
  54 static  __checkReturn   efx_rc_t
  55 siena_ev_qmoderate(
  56         __in            efx_evq_t *eep,
  57         __in            unsigned int us);
  58
  59 #if EFSYS_OPT_QSTATS
  60 static                  void
  61 siena_ev_qstats_update(
  62         __in                            efx_evq_t *eep,
  63         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
  64
  65 #endif
  66
  67 #endif /* EFSYS_OPT_SIENA */
  68
  69 #if EFX_OPTS_EF10() || EFSYS_OPT_SIENA
  70
  71 static                  void
  72 siena_ef10_ev_qpoll(
  73         __in            efx_evq_t *eep,
  74         __inout         unsigned int *countp,
  75         __in            const efx_ev_callbacks_t *eecp,
  76         __in_opt        void *arg);
  77
  78 #endif  /* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */
  79
  80 #if EFSYS_OPT_SIENA
  81 static const efx_ev_ops_t       __efx_ev_siena_ops = {
  82         siena_ev_init,                          /* eevo_init */
  83         siena_ev_fini,                          /* eevo_fini */
  84         siena_ev_qcreate,                       /* eevo_qcreate */
  85         siena_ev_qdestroy,                      /* eevo_qdestroy */
  86         siena_ev_qprime,                        /* eevo_qprime */
  87         siena_ev_qpost,                         /* eevo_qpost */
  88         siena_ef10_ev_qpoll,                    /* eevo_qpoll */
  89         siena_ev_qmoderate,                     /* eevo_qmoderate */
  90 #if EFSYS_OPT_QSTATS
  91         siena_ev_qstats_update,                 /* eevo_qstats_update */
  92 #endif
  93 };
  94 #endif /* EFSYS_OPT_SIENA */
  95
  96 #if EFX_OPTS_EF10()
  97 static const efx_ev_ops_t       __efx_ev_ef10_ops = {
  98         ef10_ev_init,                           /* eevo_init */
  99         ef10_ev_fini,                           /* eevo_fini */
 100         ef10_ev_qcreate,                        /* eevo_qcreate */
 101         ef10_ev_qdestroy,                       /* eevo_qdestroy */
 102         ef10_ev_qprime,                         /* eevo_qprime */
 103         ef10_ev_qpost,                          /* eevo_qpost */
 104         siena_ef10_ev_qpoll,                    /* eevo_qpoll */
 105         ef10_ev_qmoderate,                      /* eevo_qmoderate */
 106 #if EFSYS_OPT_QSTATS
 107         ef10_ev_qstats_update,                  /* eevo_qstats_update */
 108 #endif
 109 };
 110 #endif /* EFX_OPTS_EF10() */
 111
 112 #if EFSYS_OPT_RIVERHEAD
 113 static const efx_ev_ops_t       __efx_ev_rhead_ops = {
 114         rhead_ev_init,                          /* eevo_init */
 115         rhead_ev_fini,                          /* eevo_fini */
 116         rhead_ev_qcreate,                       /* eevo_qcreate */
 117         rhead_ev_qdestroy,                      /* eevo_qdestroy */
 118         rhead_ev_qprime,                        /* eevo_qprime */
 119         rhead_ev_qpost,                         /* eevo_qpost */
 120         rhead_ev_qpoll,                         /* eevo_qpoll */
 121         rhead_ev_qmoderate,                     /* eevo_qmoderate */
 122 #if EFSYS_OPT_QSTATS
 123         rhead_ev_qstats_update,                 /* eevo_qstats_update */
 124 #endif
 125 };
 126 #endif /* EFSYS_OPT_RIVERHEAD */
 127
 128
 129         __checkReturn   efx_rc_t
 130 efx_ev_init(
 131         __in            efx_nic_t *enp)
 132 {
 133         const efx_ev_ops_t *eevop;
 134         efx_rc_t rc;
 135
 136         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 137         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 138
 139         if (enp->en_mod_flags & EFX_MOD_EV) {
 140                 rc = EINVAL;
 141                 goto fail1;
 142         }
 143
 144         switch (enp->en_family) {
 145 #if EFSYS_OPT_SIENA
 146         case EFX_FAMILY_SIENA:
 147                 eevop = &__efx_ev_siena_ops;
 148                 break;
 149 #endif /* EFSYS_OPT_SIENA */
 150
 151 #if EFSYS_OPT_HUNTINGTON
 152         case EFX_FAMILY_HUNTINGTON:
 153                 eevop = &__efx_ev_ef10_ops;
 154                 break;
 155 #endif /* EFSYS_OPT_HUNTINGTON */
 156
 157 #if EFSYS_OPT_MEDFORD
 158         case EFX_FAMILY_MEDFORD:
 159                 eevop = &__efx_ev_ef10_ops;
 160                 break;
 161 #endif /* EFSYS_OPT_MEDFORD */
 162
 163 #if EFSYS_OPT_MEDFORD2
 164         case EFX_FAMILY_MEDFORD2:
 165                 eevop = &__efx_ev_ef10_ops;
 166                 break;
 167 #endif /* EFSYS_OPT_MEDFORD2 */
 168
 169 #if EFSYS_OPT_RIVERHEAD
 170         case EFX_FAMILY_RIVERHEAD:
 171                 eevop = &__efx_ev_rhead_ops;
 172                 break;
 173 #endif /* EFSYS_OPT_RIVERHEAD */
 174
 175         default:
 176                 EFSYS_ASSERT(0);
 177                 rc = ENOTSUP;
 178                 goto fail1;
 179         }
 180
 181         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 182
 183         if ((rc = eevop->eevo_init(enp)) != 0)
 184                 goto fail2;
 185
 186         enp->en_eevop = eevop;
 187         enp->en_mod_flags |= EFX_MOD_EV;
 188         return (0);
 189
 190 fail2:
 191         EFSYS_PROBE(fail2);
 192
 193 fail1:
 194         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 195
 196         enp->en_eevop = NULL;
 197         enp->en_mod_flags &= ~EFX_MOD_EV;
 198         return (rc);
 199 }
 200
 201         __checkReturn   size_t
 202 efx_evq_size(
 203         __in    const efx_nic_t *enp,
 204         __in    unsigned int ndescs)
 205 {
 206         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 207
 208         return (ndescs * encp->enc_ev_desc_size);
 209 }
 210
 211         __checkReturn   unsigned int
 212 efx_evq_nbufs(
 213         __in    const efx_nic_t *enp,
 214         __in    unsigned int ndescs)
 215 {
 216         return (EFX_DIV_ROUND_UP(efx_evq_size(enp, ndescs), EFX_BUF_SIZE));
 217 }
 218
 219                 void
 220 efx_ev_fini(
 221         __in    efx_nic_t *enp)
 222 {
 223         const efx_ev_ops_t *eevop = enp->en_eevop;
 224
 225         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 226         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 227         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 228         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 229         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 230         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 231
 232         eevop->eevo_fini(enp);
 233
 234         enp->en_eevop = NULL;
 235         enp->en_mod_flags &= ~EFX_MOD_EV;
 236 }
 237
 238
 239         __checkReturn   efx_rc_t
 240 efx_ev_qcreate(
 241         __in            efx_nic_t *enp,
 242         __in            unsigned int index,
 243         __in            efsys_mem_t *esmp,
 244         __in            size_t ndescs,
 245         __in            uint32_t id,
 246         __in            uint32_t us,
 247         __in            uint32_t flags,
 248         __deref_out     efx_evq_t **eepp)
 249 {
 250         const efx_ev_ops_t *eevop = enp->en_eevop;
 251         efx_evq_t *eep;
 252         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 253         efx_rc_t rc;
 254
 255         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 256         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 257
 258         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <,
 259             enp->en_nic_cfg.enc_evq_limit);
 260
 261         if (index >= encp->enc_evq_limit) {
 262                 rc = EINVAL;
 263                 goto fail1;
 264         }
 265
 266         if (us > encp->enc_evq_timer_max_us) {
 267                 rc = EINVAL;
 268                 goto fail2;
 269         }
 270
 271         switch (flags & EFX_EVQ_FLAGS_NOTIFY_MASK) {
 272         case EFX_EVQ_FLAGS_NOTIFY_INTERRUPT:
 273                 break;
 274         case EFX_EVQ_FLAGS_NOTIFY_DISABLED:
 275                 if (us != 0) {
 276                         rc = EINVAL;
 277                         goto fail3;
 278                 }
 279                 break;
 280         default:
 281                 rc = EINVAL;
 282                 goto fail4;
 283         }
 284
 285         EFSYS_ASSERT(ISP2(encp->enc_evq_max_nevs));
 286         EFSYS_ASSERT(ISP2(encp->enc_evq_min_nevs));
 287
 288         if (!ISP2(ndescs) ||
 289             ndescs < encp->enc_evq_min_nevs ||
 290             ndescs > encp->enc_evq_max_nevs) {
 291                 rc = EINVAL;
 292                 goto fail5;
 293         }
 294
 295         /* Allocate an EVQ object */
 296         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
 297         if (eep == NULL) {
 298                 rc = ENOMEM;
 299                 goto fail6;
 300         }
 301
 302         eep->ee_magic = EFX_EVQ_MAGIC;
 303         eep->ee_enp = enp;
 304         eep->ee_index = index;
 305         eep->ee_mask = ndescs - 1;
 306         eep->ee_flags = flags;
 307         eep->ee_esmp = esmp;
 308
 309         /*
 310          * Set outputs before the queue is created because interrupts may be
 311          * raised for events immediately after the queue is created, before the
 312          * function call below returns. See bug58606.
 313          *
 314          * The eepp pointer passed in by the client must therefore point to data
 315          * shared with the client's event processing context.
 316          */
 317         enp->en_ev_qcount++;
 318         *eepp = eep;
 319
 320         if ((rc = eevop->eevo_qcreate(enp, index, esmp, ndescs, id, us, flags,
 321             eep)) != 0)
 322                 goto fail7;
 323
 324         return (0);
 325
 326 fail7:
 327         EFSYS_PROBE(fail7);
 328
 329         *eepp = NULL;
 330         enp->en_ev_qcount--;
 331         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 332 fail6:
 333         EFSYS_PROBE(fail6);
 334 fail5:
 335         EFSYS_PROBE(fail5);
 336 fail4:
 337         EFSYS_PROBE(fail4);
 338 fail3:
 339         EFSYS_PROBE(fail3);
 340 fail2:
 341         EFSYS_PROBE(fail2);
 342 fail1:
 343         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 344         return (rc);
 345 }
 346
 347                 void
 348 efx_ev_qdestroy(
 349         __in    efx_evq_t *eep)
 350 {
 351         efx_nic_t *enp = eep->ee_enp;
 352         const efx_ev_ops_t *eevop = enp->en_eevop;
 353
 354         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 355
 356         EFSYS_ASSERT(enp->en_ev_qcount != 0);
 357         --enp->en_ev_qcount;
 358
 359         eevop->eevo_qdestroy(eep);
 360
 361         /* Free the EVQ object */
 362         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 363 }
 364
 365         __checkReturn   efx_rc_t
 366 efx_ev_qprime(
 367         __in            efx_evq_t *eep,
 368         __in            unsigned int count)
 369 {
 370         efx_nic_t *enp = eep->ee_enp;
 371         const efx_ev_ops_t *eevop = enp->en_eevop;
 372         efx_rc_t rc;
 373
 374         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 375
 376         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
 377                 rc = EINVAL;
 378                 goto fail1;
 379         }
 380
 381         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
 382                 goto fail2;
 383
 384         return (0);
 385
 386 fail2:
 387         EFSYS_PROBE(fail2);
 388 fail1:
 389         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 390         return (rc);
 391 }
 392
 393         __checkReturn   boolean_t
 394 efx_ev_qpending(
 395         __in            efx_evq_t *eep,
 396         __in            unsigned int count)
 397 {
 398         size_t offset;
 399         efx_qword_t qword;
 400
 401         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 402
 403         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 404         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
 405
 406         return (EFX_EV_PRESENT(qword));
 407 }
 408
 409 #if EFSYS_OPT_EV_PREFETCH
 410
 411                         void
 412 efx_ev_qprefetch(
 413         __in            efx_evq_t *eep,
 414         __in            unsigned int count)
 415 {
 416         unsigned int offset;
 417
 418         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 419
 420         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 421         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 422 }
 423
 424 #endif  /* EFSYS_OPT_EV_PREFETCH */
 425
 426 /*
 427  * This method is needed to ensure that eec_initialized callback
 428  * is invoked after queue creation. The callback will be invoked
 429  * on Riverhead boards which have no support for INIT_DONE events
 430  * and will do nothing on other boards.
 431  *
 432  * The client drivers must call this method after calling efx_ev_create().
 433  * The call must be done with the same locks being held (if any) which are
 434  * normally acquired around efx_ev_qpoll() calls to ensure that
 435  * eec_initialized callback is invoked within the same locking context.
 436  */
 437                         void
 438 efx_ev_qcreate_check_init_done(
 439         __in            efx_evq_t *eep,
 440         __in            const efx_ev_callbacks_t *eecp,
 441         __in_opt        void *arg)
 442 {
 443         const efx_nic_cfg_t *encp;
 444
 445         EFSYS_ASSERT(eep != NULL);
 446         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 447         EFSYS_ASSERT(eecp != NULL);
 448         EFSYS_ASSERT(eecp->eec_initialized != NULL);
 449
 450         encp = efx_nic_cfg_get(eep->ee_enp);
 451
 452         if (encp->enc_evq_init_done_ev_supported == B_FALSE)
 453                 (void) eecp->eec_initialized(arg);
 454 }
 455
 456                         void
 457 efx_ev_qpoll(
 458         __in            efx_evq_t *eep,
 459         __inout         unsigned int *countp,
 460         __in            const efx_ev_callbacks_t *eecp,
 461         __in_opt        void *arg)
 462 {
 463         efx_nic_t *enp = eep->ee_enp;
 464         const efx_ev_ops_t *eevop = enp->en_eevop;
 465
 466         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 467
 468         EFSYS_ASSERT(eevop != NULL &&
 469             eevop->eevo_qpoll != NULL);
 470
 471         eevop->eevo_qpoll(eep, countp, eecp, arg);
 472 }
 473
 474                         void
 475 efx_ev_qpost(
 476         __in    efx_evq_t *eep,
 477         __in    uint16_t data)
 478 {
 479         efx_nic_t *enp = eep->ee_enp;
 480         const efx_ev_ops_t *eevop = enp->en_eevop;
 481
 482         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 483
 484         EFSYS_ASSERT(eevop != NULL &&
 485             eevop->eevo_qpost != NULL);
 486
 487         eevop->eevo_qpost(eep, data);
 488 }
 489
 490         __checkReturn   efx_rc_t
 491 efx_ev_usecs_to_ticks(
 492         __in            efx_nic_t *enp,
 493         __in            unsigned int us,
 494         __out           unsigned int *ticksp)
 495 {
 496         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 497         unsigned int ticks;
 498         efx_rc_t rc;
 499
 500         if (encp->enc_evq_timer_quantum_ns == 0) {
 501                 rc = ENOTSUP;
 502                 goto fail1;
 503         }
 504
 505         /* Convert microseconds to a timer tick count */
 506         if (us == 0)
 507                 ticks = 0;
 508         else if (us * 1000 < encp->enc_evq_timer_quantum_ns)
 509                 ticks = 1;      /* Never round down to zero */
 510         else
 511                 ticks = us * 1000 / encp->enc_evq_timer_quantum_ns;
 512
 513         *ticksp = ticks;
 514         return (0);
 515
 516 fail1:
 517         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 518         return (rc);
 519 }
 520
 521         __checkReturn   efx_rc_t
 522 efx_ev_qmoderate(
 523         __in            efx_evq_t *eep,
 524         __in            unsigned int us)
 525 {
 526         efx_nic_t *enp = eep->ee_enp;
 527         const efx_ev_ops_t *eevop = enp->en_eevop;
 528         efx_rc_t rc;
 529
 530         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 531
 532         if ((eep->ee_flags & EFX_EVQ_FLAGS_NOTIFY_MASK) ==
 533             EFX_EVQ_FLAGS_NOTIFY_DISABLED) {
 534                 rc = EINVAL;
 535                 goto fail1;
 536         }
 537
 538         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
 539                 goto fail2;
 540
 541         return (0);
 542
 543 fail2:
 544         EFSYS_PROBE(fail2);
 545 fail1:
 546         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 547         return (rc);
 548 }
 549
 550 #if EFSYS_OPT_QSTATS
 551                                         void
 552 efx_ev_qstats_update(
 553         __in                            efx_evq_t *eep,
 554         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
 555
 556 {       efx_nic_t *enp = eep->ee_enp;
 557         const efx_ev_ops_t *eevop = enp->en_eevop;
 558
 559         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 560
 561         eevop->eevo_qstats_update(eep, stat);
 562 }
 563
 564 #endif  /* EFSYS_OPT_QSTATS */
 565
 566 #if EFSYS_OPT_SIENA
 567
 568 static  __checkReturn   efx_rc_t
 569 siena_ev_init(
 570         __in            efx_nic_t *enp)
 571 {
 572         efx_oword_t oword;
 573
 574         /*
 575          * Program the event queue for receive and transmit queue
 576          * flush events.
 577          */
 578         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
 579         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 580         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 581
 582         return (0);
 583
 584 }
 585
 586 static  __checkReturn   boolean_t
 587 siena_ev_rx_not_ok(
 588         __in            efx_evq_t *eep,
 589         __in            efx_qword_t *eqp,
 590         __in            uint32_t label,
 591         __in            uint32_t id,
 592         __inout         uint16_t *flagsp)
 593 {
 594         boolean_t ignore = B_FALSE;
 595
 596         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
 597                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
 598                 EFSYS_PROBE(tobe_disc);
 599                 /*
 600                  * Assume this is a unicast address mismatch, unless below
 601                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
 602                  * EV_RX_PAUSE_FRM_ERR is set.
 603                  */
 604                 (*flagsp) |= EFX_ADDR_MISMATCH;
 605         }
 606
 607         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
 608                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
 609                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
 610                 (*flagsp) |= EFX_DISCARD;
 611
 612 #if EFSYS_OPT_RX_SCATTER
 613                 /*
 614                  * Lookout for payload queue ran dry errors and ignore them.
 615                  *
 616                  * Sadly for the header/data split cases, the descriptor
 617                  * pointer in this event refers to the header queue and
 618                  * therefore cannot be easily detected as duplicate.
 619                  * So we drop these and rely on the receive processing seeing
 620                  * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
 621                  * the partially received packet.
 622                  */
 623                 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
 624                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
 625                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
 626                         ignore = B_TRUE;
 627 #endif  /* EFSYS_OPT_RX_SCATTER */
 628         }
 629
 630         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
 631                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
 632                 EFSYS_PROBE(crc_err);
 633                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 634                 (*flagsp) |= EFX_DISCARD;
 635         }
 636
 637         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
 638                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
 639                 EFSYS_PROBE(pause_frm_err);
 640                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 641                 (*flagsp) |= EFX_DISCARD;
 642         }
 643
 644         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
 645                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
 646                 EFSYS_PROBE(owner_id_err);
 647                 (*flagsp) |= EFX_DISCARD;
 648         }
 649
 650         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
 651                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
 652                 EFSYS_PROBE(ipv4_err);
 653                 (*flagsp) &= ~EFX_CKSUM_IPV4;
 654         }
 655
 656         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
 657                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
 658                 EFSYS_PROBE(udp_chk_err);
 659                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
 660         }
 661
 662         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
 663                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
 664
 665                 /*
 666                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
 667                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
 668                  * condition.
 669                  */
 670                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
 671         }
 672
 673         return (ignore);
 674 }
 675
 676 static  __checkReturn   boolean_t
 677 siena_ev_rx(
 678         __in            efx_evq_t *eep,
 679         __in            efx_qword_t *eqp,
 680         __in            const efx_ev_callbacks_t *eecp,
 681         __in_opt        void *arg)
 682 {
 683         uint32_t id;
 684         uint32_t size;
 685         uint32_t label;
 686         boolean_t ok;
 687 #if EFSYS_OPT_RX_SCATTER
 688         boolean_t sop;
 689         boolean_t jumbo_cont;
 690 #endif  /* EFSYS_OPT_RX_SCATTER */
 691         uint32_t hdr_type;
 692         boolean_t is_v6;
 693         uint16_t flags;
 694         boolean_t ignore;
 695         boolean_t should_abort;
 696
 697         EFX_EV_QSTAT_INCR(eep, EV_RX);
 698
 699         /* Basic packet information */
 700         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
 701         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
 702         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
 703         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
 704
 705 #if EFSYS_OPT_RX_SCATTER
 706         sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
 707         jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
 708 #endif  /* EFSYS_OPT_RX_SCATTER */
 709
 710         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
 711
 712         is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
 713
 714         /*
 715          * If packet is marked as OK and packet type is TCP/IP or
 716          * UDP/IP or other IP, then we can rely on the hardware checksums.
 717          */
 718         switch (hdr_type) {
 719         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
 720                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
 721                 if (is_v6) {
 722                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
 723                         flags |= EFX_PKT_IPV6;
 724                 } else {
 725                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
 726                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 727                 }
 728                 break;
 729
 730         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
 731                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
 732                 if (is_v6) {
 733                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
 734                         flags |= EFX_PKT_IPV6;
 735                 } else {
 736                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
 737                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 738                 }
 739                 break;
 740
 741         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
 742                 if (is_v6) {
 743                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
 744                         flags = EFX_PKT_IPV6;
 745                 } else {
 746                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
 747                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 748                 }
 749                 break;
 750
 751         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
 752                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
 753                 flags = 0;
 754                 break;
 755
 756         default:
 757                 EFSYS_ASSERT(B_FALSE);
 758                 flags = 0;
 759                 break;
 760         }
 761
 762 #if EFSYS_OPT_RX_SCATTER
 763         /* Report scatter and header/lookahead split buffer flags */
 764         if (sop)
 765                 flags |= EFX_PKT_START;
 766         if (jumbo_cont)
 767                 flags |= EFX_PKT_CONT;
 768 #endif  /* EFSYS_OPT_RX_SCATTER */
 769
 770         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 771         if (!ok) {
 772                 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 773                 if (ignore) {
 774                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 775                             uint32_t, size, uint16_t, flags);
 776
 777                         return (B_FALSE);
 778                 }
 779         }
 780
 781         /* If we're not discarding the packet then it is ok */
 782         if (~flags & EFX_DISCARD)
 783                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
 784
 785         /* Detect multicast packets that didn't match the filter */
 786         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
 787                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
 788
 789                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
 790                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
 791                 } else {
 792                         EFSYS_PROBE(mcast_mismatch);
 793                         flags |= EFX_ADDR_MISMATCH;
 794                 }
 795         } else {
 796                 flags |= EFX_PKT_UNICAST;
 797         }
 798
 799         /*
 800          * The packet parser in Siena can abort parsing packets under
 801          * certain error conditions, setting the PKT_NOT_PARSED bit
 802          * (which clears PKT_OK). If this is set, then don't trust
 803          * the PKT_TYPE field.
 804          */
 805         if (!ok) {
 806                 uint32_t parse_err;
 807
 808                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
 809                 if (parse_err != 0)
 810                         flags |= EFX_CHECK_VLAN;
 811         }
 812
 813         if (~flags & EFX_CHECK_VLAN) {
 814                 uint32_t pkt_type;
 815
 816                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
 817                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
 818                         flags |= EFX_PKT_VLAN_TAGGED;
 819         }
 820
 821         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 822             uint32_t, size, uint16_t, flags);
 823
 824         EFSYS_ASSERT(eecp->eec_rx != NULL);
 825         should_abort = eecp->eec_rx(arg, label, id, size, flags);
 826
 827         return (should_abort);
 828 }
 829
 830 static  __checkReturn   boolean_t
 831 siena_ev_tx(
 832         __in            efx_evq_t *eep,
 833         __in            efx_qword_t *eqp,
 834         __in            const efx_ev_callbacks_t *eecp,
 835         __in_opt        void *arg)
 836 {
 837         uint32_t id;
 838         uint32_t label;
 839         boolean_t should_abort;
 840
 841         EFX_EV_QSTAT_INCR(eep, EV_TX);
 842
 843         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
 844             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
 845             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
 846             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
 847
 848                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
 849                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
 850
 851                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
 852
 853                 EFSYS_ASSERT(eecp->eec_tx != NULL);
 854                 should_abort = eecp->eec_tx(arg, label, id);
 855
 856                 return (should_abort);
 857         }
 858
 859         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
 860                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 861                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 862                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 863
 864         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
 865                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
 866
 867         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
 868                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
 869
 870         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
 871                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
 872
 873         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
 874         return (B_FALSE);
 875 }
 876
 877 static  __checkReturn   boolean_t
 878 siena_ev_global(
 879         __in            efx_evq_t *eep,
 880         __in            efx_qword_t *eqp,
 881         __in            const efx_ev_callbacks_t *eecp,
 882         __in_opt        void *arg)
 883 {
 884         _NOTE(ARGUNUSED(eqp, eecp, arg))
 885
 886         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
 887
 888         return (B_FALSE);
 889 }
 890
 891 static  __checkReturn   boolean_t
 892 siena_ev_driver(
 893         __in            efx_evq_t *eep,
 894         __in            efx_qword_t *eqp,
 895         __in            const efx_ev_callbacks_t *eecp,
 896         __in_opt        void *arg)
 897 {
 898         boolean_t should_abort;
 899
 900         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
 901         should_abort = B_FALSE;
 902
 903         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
 904         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
 905                 uint32_t txq_index;
 906
 907                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
 908
 909                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 910
 911                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
 912
 913                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
 914                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
 915
 916                 break;
 917         }
 918         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
 919                 uint32_t rxq_index;
 920                 uint32_t failed;
 921
 922                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
 923                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
 924
 925                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
 926                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
 927
 928                 if (failed) {
 929                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
 930
 931                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 932
 933                         should_abort = eecp->eec_rxq_flush_failed(arg,
 934                                                                     rxq_index);
 935                 } else {
 936                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 937
 938                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
 939
 940                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
 941                 }
 942
 943                 break;
 944         }
 945         case FSE_AZ_EVQ_INIT_DONE_EV:
 946                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
 947                 should_abort = eecp->eec_initialized(arg);
 948
 949                 break;
 950
 951         case FSE_AZ_EVQ_NOT_EN_EV:
 952                 EFSYS_PROBE(evq_not_en);
 953                 break;
 954
 955         case FSE_AZ_SRM_UPD_DONE_EV: {
 956                 uint32_t code;
 957
 958                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
 959
 960                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 961
 962                 EFSYS_ASSERT(eecp->eec_sram != NULL);
 963                 should_abort = eecp->eec_sram(arg, code);
 964
 965                 break;
 966         }
 967         case FSE_AZ_WAKE_UP_EV: {
 968                 uint32_t id;
 969
 970                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 971
 972                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
 973                 should_abort = eecp->eec_wake_up(arg, id);
 974
 975                 break;
 976         }
 977         case FSE_AZ_TX_PKT_NON_TCP_UDP:
 978                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
 979                 break;
 980
 981         case FSE_AZ_TIMER_EV: {
 982                 uint32_t id;
 983
 984                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 985
 986                 EFSYS_ASSERT(eecp->eec_timer != NULL);
 987                 should_abort = eecp->eec_timer(arg, id);
 988
 989                 break;
 990         }
 991         case FSE_AZ_RX_DSC_ERROR_EV:
 992                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
 993
 994                 EFSYS_PROBE(rx_dsc_error);
 995
 996                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 997                 should_abort = eecp->eec_exception(arg,
 998                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
 999
1000                 break;
1001
1002         case FSE_AZ_TX_DSC_ERROR_EV:
1003                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
1004
1005                 EFSYS_PROBE(tx_dsc_error);
1006
1007                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1008                 should_abort = eecp->eec_exception(arg,
1009                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
1010
1011                 break;
1012
1013         default:
1014                 break;
1015         }
1016
1017         return (should_abort);
1018 }
1019
1020 static  __checkReturn   boolean_t
1021 siena_ev_drv_gen(
1022         __in            efx_evq_t *eep,
1023         __in            efx_qword_t *eqp,
1024         __in            const efx_ev_callbacks_t *eecp,
1025         __in_opt        void *arg)
1026 {
1027         uint32_t data;
1028         boolean_t should_abort;
1029
1030         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
1031
1032         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
1033         if (data >= ((uint32_t)1 << 16)) {
1034                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1035                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1036                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1037                 return (B_TRUE);
1038         }
1039
1040         EFSYS_ASSERT(eecp->eec_software != NULL);
1041         should_abort = eecp->eec_software(arg, (uint16_t)data);
1042
1043         return (should_abort);
1044 }
1045
1046 #if EFSYS_OPT_MCDI
1047
1048 static  __checkReturn   boolean_t
1049 siena_ev_mcdi(
1050         __in            efx_evq_t *eep,
1051         __in            efx_qword_t *eqp,
1052         __in            const efx_ev_callbacks_t *eecp,
1053         __in_opt        void *arg)
1054 {
1055         efx_nic_t *enp = eep->ee_enp;
1056         unsigned int code;
1057         boolean_t should_abort = B_FALSE;
1058
1059         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
1060
1061         if (enp->en_family != EFX_FAMILY_SIENA)
1062                 goto out;
1063
1064         EFSYS_ASSERT(eecp->eec_link_change != NULL);
1065         EFSYS_ASSERT(eecp->eec_exception != NULL);
1066 #if EFSYS_OPT_MON_STATS
1067         EFSYS_ASSERT(eecp->eec_monitor != NULL);
1068 #endif
1069
1070         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
1071
1072         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
1073         switch (code) {
1074         case MCDI_EVENT_CODE_BADSSERT:
1075                 efx_mcdi_ev_death(enp, EINTR);
1076                 break;
1077
1078         case MCDI_EVENT_CODE_CMDDONE:
1079                 efx_mcdi_ev_cpl(enp,
1080                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
1081                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
1082                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
1083                 break;
1084
1085         case MCDI_EVENT_CODE_LINKCHANGE: {
1086                 efx_link_mode_t link_mode;
1087
1088                 siena_phy_link_ev(enp, eqp, &link_mode);
1089                 should_abort = eecp->eec_link_change(arg, link_mode);
1090                 break;
1091         }
1092         case MCDI_EVENT_CODE_SENSOREVT: {
1093 #if EFSYS_OPT_MON_STATS
1094                 efx_mon_stat_t id;
1095                 efx_mon_stat_value_t value;
1096                 efx_rc_t rc;
1097
1098                 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
1099                         should_abort = eecp->eec_monitor(arg, id, value);
1100                 else if (rc == ENOTSUP) {
1101                         should_abort = eecp->eec_exception(arg,
1102                                 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
1103                                 MCDI_EV_FIELD(eqp, DATA));
1104                 } else
1105                         EFSYS_ASSERT(rc == ENODEV);     /* Wrong port */
1106 #else
1107                 should_abort = B_FALSE;
1108 #endif
1109                 break;
1110         }
1111         case MCDI_EVENT_CODE_SCHEDERR:
1112                 /* Informational only */
1113                 break;
1114
1115         case MCDI_EVENT_CODE_REBOOT:
1116                 efx_mcdi_ev_death(enp, EIO);
1117                 break;
1118
1119         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1120 #if EFSYS_OPT_MAC_STATS
1121                 if (eecp->eec_mac_stats != NULL) {
1122                         eecp->eec_mac_stats(arg,
1123                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1124                 }
1125 #endif
1126                 break;
1127
1128         case MCDI_EVENT_CODE_FWALERT: {
1129                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1130
1131                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1132                         should_abort = eecp->eec_exception(arg,
1133                                 EFX_EXCEPTION_FWALERT_SRAM,
1134                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1135                 else
1136                         should_abort = eecp->eec_exception(arg,
1137                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1138                                 MCDI_EV_FIELD(eqp, DATA));
1139                 break;
1140         }
1141
1142         default:
1143                 EFSYS_PROBE1(mc_pcol_error, int, code);
1144                 break;
1145         }
1146
1147 out:
1148         return (should_abort);
1149 }
1150
1151 #endif  /* EFSYS_OPT_MCDI */
1152
1153 static  __checkReturn   efx_rc_t
1154 siena_ev_qprime(
1155         __in            efx_evq_t *eep,
1156         __in            unsigned int count)
1157 {
1158         efx_nic_t *enp = eep->ee_enp;
1159         uint32_t rptr;
1160         efx_dword_t dword;
1161
1162         rptr = count & eep->ee_mask;
1163
1164         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1165
1166         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1167                             &dword, B_FALSE);
1168
1169         return (0);
1170 }
1171
1172 static          void
1173 siena_ev_qpost(
1174         __in    efx_evq_t *eep,
1175         __in    uint16_t data)
1176 {
1177         efx_nic_t *enp = eep->ee_enp;
1178         efx_qword_t ev;
1179         efx_oword_t oword;
1180
1181         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1182             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1183
1184         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1185             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1186             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1187
1188         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1189 }
1190
1191 static  __checkReturn   efx_rc_t
1192 siena_ev_qmoderate(
1193         __in            efx_evq_t *eep,
1194         __in            unsigned int us)
1195 {
1196         efx_nic_t *enp = eep->ee_enp;
1197         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1198         unsigned int locked;
1199         efx_dword_t dword;
1200         efx_rc_t rc;
1201
1202         if (us > encp->enc_evq_timer_max_us) {
1203                 rc = EINVAL;
1204                 goto fail1;
1205         }
1206
1207         /* If the value is zero then disable the timer */
1208         if (us == 0) {
1209                 EFX_POPULATE_DWORD_2(dword,
1210                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1211                     FRF_CZ_TC_TIMER_VAL, 0);
1212         } else {
1213                 unsigned int ticks;
1214
1215                 if ((rc = efx_ev_usecs_to_ticks(enp, us, &ticks)) != 0)
1216                         goto fail2;
1217
1218                 EFSYS_ASSERT(ticks > 0);
1219                 EFX_POPULATE_DWORD_2(dword,
1220                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1221                     FRF_CZ_TC_TIMER_VAL, ticks - 1);
1222         }
1223
1224         locked = (eep->ee_index == 0) ? 1 : 0;
1225
1226         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1227             eep->ee_index, &dword, locked);
1228
1229         return (0);
1230
1231 fail2:
1232         EFSYS_PROBE(fail2);
1233 fail1:
1234         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1235
1236         return (rc);
1237 }
1238
1239 static  __checkReturn   efx_rc_t
1240 siena_ev_qcreate(
1241         __in            efx_nic_t *enp,
1242         __in            unsigned int index,
1243         __in            efsys_mem_t *esmp,
1244         __in            size_t ndescs,
1245         __in            uint32_t id,
1246         __in            uint32_t us,
1247         __in            uint32_t flags,
1248         __in            efx_evq_t *eep)
1249 {
1250         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1251         uint32_t size;
1252         efx_oword_t oword;
1253         efx_rc_t rc;
1254         boolean_t notify_mode;
1255
1256         _NOTE(ARGUNUSED(esmp))
1257
1258 #if EFSYS_OPT_RX_SCALE
1259         if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1260             index >= EFX_MAXRSS_LEGACY) {
1261                 rc = EINVAL;
1262                 goto fail1;
1263         }
1264 #endif
1265         for (size = 0;
1266             (1U << size) <= encp->enc_evq_max_nevs / encp->enc_evq_min_nevs;
1267             size++)
1268                 if ((1U << size) == (uint32_t)ndescs / encp->enc_evq_min_nevs)
1269                         break;
1270         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1271                 rc = EINVAL;
1272                 goto fail2;
1273         }
1274
1275         /* Set up the handler table */
1276         eep->ee_rx      = siena_ev_rx;
1277         eep->ee_tx      = siena_ev_tx;
1278         eep->ee_driver  = siena_ev_driver;
1279         eep->ee_global  = siena_ev_global;
1280         eep->ee_drv_gen = siena_ev_drv_gen;
1281 #if EFSYS_OPT_MCDI
1282         eep->ee_mcdi    = siena_ev_mcdi;
1283 #endif  /* EFSYS_OPT_MCDI */
1284
1285         notify_mode = ((flags & EFX_EVQ_FLAGS_NOTIFY_MASK) !=
1286             EFX_EVQ_FLAGS_NOTIFY_INTERRUPT);
1287
1288         /* Set up the new event queue */
1289         EFX_POPULATE_OWORD_3(oword, FRF_CZ_TIMER_Q_EN, 1,
1290             FRF_CZ_HOST_NOTIFY_MODE, notify_mode,
1291             FRF_CZ_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS);
1292         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1293
1294         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1295             FRF_AZ_EVQ_BUF_BASE_ID, id);
1296
1297         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1298
1299         /* Set initial interrupt moderation */
1300         siena_ev_qmoderate(eep, us);
1301
1302         return (0);
1303
1304 fail2:
1305         EFSYS_PROBE(fail2);
1306 #if EFSYS_OPT_RX_SCALE
1307 fail1:
1308 #endif
1309         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1310
1311         return (rc);
1312 }
1313
1314 #endif /* EFSYS_OPT_SIENA */
1315
1316 #if EFSYS_OPT_QSTATS
1317 #if EFSYS_OPT_NAMES
1318 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock ac223f7134058b4f */
1319 static const char * const __efx_ev_qstat_name[] = {
1320         "all",
1321         "rx",
1322         "rx_ok",
1323         "rx_frm_trunc",
1324         "rx_tobe_disc",
1325         "rx_pause_frm_err",
1326         "rx_buf_owner_id_err",
1327         "rx_ipv4_hdr_chksum_err",
1328         "rx_tcp_udp_chksum_err",
1329         "rx_eth_crc_err",
1330         "rx_ip_frag_err",
1331         "rx_mcast_pkt",
1332         "rx_mcast_hash_match",
1333         "rx_tcp_ipv4",
1334         "rx_tcp_ipv6",
1335         "rx_udp_ipv4",
1336         "rx_udp_ipv6",
1337         "rx_other_ipv4",
1338         "rx_other_ipv6",
1339         "rx_non_ip",
1340         "rx_batch",
1341         "tx",
1342         "tx_wq_ff_full",
1343         "tx_pkt_err",
1344         "tx_pkt_too_big",
1345         "tx_unexpected",
1346         "global",
1347         "global_mnt",
1348         "driver",
1349         "driver_srm_upd_done",
1350         "driver_tx_descq_fls_done",
1351         "driver_rx_descq_fls_done",
1352         "driver_rx_descq_fls_failed",
1353         "driver_rx_dsc_error",
1354         "driver_tx_dsc_error",
1355         "drv_gen",
1356         "mcdi_response",
1357         "rx_parse_incomplete",
1358 };
1359 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1360
1361                 const char *
1362 efx_ev_qstat_name(
1363         __in    efx_nic_t *enp,
1364         __in    unsigned int id)
1365 {
1366         _NOTE(ARGUNUSED(enp))
1367
1368         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1369         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1370
1371         return (__efx_ev_qstat_name[id]);
1372 }
1373 #endif  /* EFSYS_OPT_NAMES */
1374 #endif  /* EFSYS_OPT_QSTATS */
1375
1376 #if EFSYS_OPT_SIENA
1377
1378 #if EFSYS_OPT_QSTATS
1379 static                                  void
1380 siena_ev_qstats_update(
1381         __in                            efx_evq_t *eep,
1382         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1383 {
1384         unsigned int id;
1385
1386         for (id = 0; id < EV_NQSTATS; id++) {
1387                 efsys_stat_t *essp = &stat[id];
1388
1389                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1390                 eep->ee_stat[id] = 0;
1391         }
1392 }
1393 #endif  /* EFSYS_OPT_QSTATS */
1394
1395 static          void
1396 siena_ev_qdestroy(
1397         __in    efx_evq_t *eep)
1398 {
1399         efx_nic_t *enp = eep->ee_enp;
1400         efx_oword_t oword;
1401
1402         /* Purge event queue */
1403         EFX_ZERO_OWORD(oword);
1404
1405         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1406             eep->ee_index, &oword, B_TRUE);
1407
1408         EFX_ZERO_OWORD(oword);
1409         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1410 }
1411
1412 static          void
1413 siena_ev_fini(
1414         __in    efx_nic_t *enp)
1415 {
1416         _NOTE(ARGUNUSED(enp))
1417 }
1418
1419 #endif /* EFSYS_OPT_SIENA */
1420
1421 #if EFX_OPTS_EF10() || EFSYS_OPT_SIENA
1422
1423 #define EFX_EV_BATCH    8
1424
1425 static                  void
1426 siena_ef10_ev_qpoll(
1427         __in            efx_evq_t *eep,
1428         __inout         unsigned int *countp,
1429         __in            const efx_ev_callbacks_t *eecp,
1430         __in_opt        void *arg)
1431 {
1432         efx_qword_t ev[EFX_EV_BATCH];
1433         unsigned int batch;
1434         unsigned int total;
1435         unsigned int count;
1436         unsigned int index;
1437         size_t offset;
1438
1439         /* Ensure events codes match for EF10 (Huntington/Medford) and Siena */
1440         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
1441         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
1442
1443         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
1444         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
1445         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
1446         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
1447             FSE_AZ_EV_CODE_DRV_GEN_EV);
1448 #if EFSYS_OPT_MCDI
1449         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
1450             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
1451 #endif
1452
1453         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
1454         EFSYS_ASSERT(countp != NULL);
1455         EFSYS_ASSERT(eecp != NULL);
1456
1457         count = *countp;
1458         do {
1459                 /* Read up until the end of the batch period */
1460                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
1461                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1462                 for (total = 0; total < batch; ++total) {
1463                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
1464
1465                         if (!EFX_EV_PRESENT(ev[total]))
1466                                 break;
1467
1468                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
1469                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
1470                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
1471
1472                         offset += sizeof (efx_qword_t);
1473                 }
1474
1475 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
1476                 /*
1477                  * Prefetch the next batch when we get within PREFETCH_PERIOD
1478                  * of a completed batch. If the batch is smaller, then prefetch
1479                  * immediately.
1480                  */
1481                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
1482                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1483 #endif  /* EFSYS_OPT_EV_PREFETCH */
1484
1485                 /* Process the batch of events */
1486                 for (index = 0; index < total; ++index) {
1487                         boolean_t should_abort;
1488                         uint32_t code;
1489
1490 #if EFSYS_OPT_EV_PREFETCH
1491                         /* Prefetch if we've now reached the batch period */
1492                         if (total == batch &&
1493                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
1494                                 offset = (count + batch) & eep->ee_mask;
1495                                 offset *= sizeof (efx_qword_t);
1496
1497                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1498                         }
1499 #endif  /* EFSYS_OPT_EV_PREFETCH */
1500
1501                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
1502
1503                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
1504                         switch (code) {
1505                         case FSE_AZ_EV_CODE_RX_EV:
1506                                 should_abort = eep->ee_rx(eep,
1507                                     &(ev[index]), eecp, arg);
1508                                 break;
1509                         case FSE_AZ_EV_CODE_TX_EV:
1510                                 should_abort = eep->ee_tx(eep,
1511                                     &(ev[index]), eecp, arg);
1512                                 break;
1513                         case FSE_AZ_EV_CODE_DRIVER_EV:
1514                                 should_abort = eep->ee_driver(eep,
1515                                     &(ev[index]), eecp, arg);
1516                                 break;
1517                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
1518                                 should_abort = eep->ee_drv_gen(eep,
1519                                     &(ev[index]), eecp, arg);
1520                                 break;
1521 #if EFSYS_OPT_MCDI
1522                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
1523                                 should_abort = eep->ee_mcdi(eep,
1524                                     &(ev[index]), eecp, arg);
1525                                 break;
1526 #endif
1527                         case FSE_AZ_EV_CODE_GLOBAL_EV:
1528                                 if (eep->ee_global) {
1529                                         should_abort = eep->ee_global(eep,
1530                                             &(ev[index]), eecp, arg);
1531                                         break;
1532                                 }
1533                                 /* else fallthrough */
1534                         default:
1535                                 EFSYS_PROBE3(bad_event,
1536                                     unsigned int, eep->ee_index,
1537                                     uint32_t,
1538                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
1539                                     uint32_t,
1540                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
1541
1542                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1543                                 (void) eecp->eec_exception(arg,
1544                                         EFX_EXCEPTION_EV_ERROR, code);
1545                                 should_abort = B_TRUE;
1546                         }
1547                         if (should_abort) {
1548                                 /* Ignore subsequent events */
1549                                 total = index + 1;
1550
1551                                 /*
1552                                  * Poison batch to ensure the outer
1553                                  * loop is broken out of.
1554                                  */
1555                                 EFSYS_ASSERT(batch <= EFX_EV_BATCH);
1556                                 batch += (EFX_EV_BATCH << 1);
1557                                 EFSYS_ASSERT(total != batch);
1558                                 break;
1559                         }
1560                 }
1561
1562                 /*
1563                  * Now that the hardware has most likely moved onto dma'ing
1564                  * into the next cache line, clear the processed events. Take
1565                  * care to only clear out events that we've processed
1566                  */
1567                 EFX_SET_QWORD(ev[0]);
1568                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1569                 for (index = 0; index < total; ++index) {
1570                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
1571                         offset += sizeof (efx_qword_t);
1572                 }
1573
1574                 count += total;
1575
1576         } while (total == batch);
1577
1578         *countp = count;
1579 }
1580
1581 #endif  /* EFX_OPTS_EF10() || EFSYS_OPT_SIENA */