drivers/common/sfc_efx/base/efx_impl.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2021 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #ifndef _SYS_EFX_IMPL_H
   8 #define _SYS_EFX_IMPL_H
   9
  10 #include "efx.h"
  11 #include "efx_regs.h"
  12 #include "efx_regs_ef10.h"
  13 #include "efx_regs_ef100.h"
  14 #if EFSYS_OPT_MCDI
  15 #include "efx_mcdi.h"
  16 #endif  /* EFSYS_OPT_MCDI */
  17
  18 /* FIXME: Add definition for driver generated software events */
  19 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  20 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  21 #endif
  22
  23
  24 #if EFSYS_OPT_SIENA
  25 #include "siena_impl.h"
  26 #endif  /* EFSYS_OPT_SIENA */
  27
  28 #if EFSYS_OPT_HUNTINGTON
  29 #include "hunt_impl.h"
  30 #endif  /* EFSYS_OPT_HUNTINGTON */
  31
  32 #if EFSYS_OPT_MEDFORD
  33 #include "medford_impl.h"
  34 #endif  /* EFSYS_OPT_MEDFORD */
  35
  36 #if EFSYS_OPT_MEDFORD2
  37 #include "medford2_impl.h"
  38 #endif  /* EFSYS_OPT_MEDFORD2 */
  39
  40 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
  41 #include "ef10_impl.h"
  42 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
  43
  44 #if EFSYS_OPT_RIVERHEAD
  45 #include "rhead_impl.h"
  46 #endif  /* EFSYS_OPT_RIVERHEAD */
  47
  48 #ifdef  __cplusplus
  49 extern "C" {
  50 #endif
  51
  52 #define EFX_MOD_MCDI            0x00000001
  53 #define EFX_MOD_PROBE           0x00000002
  54 #define EFX_MOD_NVRAM           0x00000004
  55 #define EFX_MOD_VPD             0x00000008
  56 #define EFX_MOD_NIC             0x00000010
  57 #define EFX_MOD_INTR            0x00000020
  58 #define EFX_MOD_EV              0x00000040
  59 #define EFX_MOD_RX              0x00000080
  60 #define EFX_MOD_TX              0x00000100
  61 #define EFX_MOD_PORT            0x00000200
  62 #define EFX_MOD_MON             0x00000400
  63 #define EFX_MOD_FILTER          0x00001000
  64 #define EFX_MOD_LIC             0x00002000
  65 #define EFX_MOD_TUNNEL          0x00004000
  66 #define EFX_MOD_EVB             0x00008000
  67 #define EFX_MOD_PROXY           0x00010000
  68 #define EFX_MOD_VIRTIO          0x00020000
  69
  70 #define EFX_RESET_PHY           0x00000001
  71 #define EFX_RESET_RXQ_ERR       0x00000002
  72 #define EFX_RESET_TXQ_ERR       0x00000004
  73 #define EFX_RESET_HW_UNAVAIL    0x00000008
  74
  75 typedef enum efx_mac_type_e {
  76         EFX_MAC_INVALID = 0,
  77         EFX_MAC_SIENA,
  78         EFX_MAC_HUNTINGTON,
  79         EFX_MAC_MEDFORD,
  80         EFX_MAC_MEDFORD2,
  81         EFX_MAC_RIVERHEAD,
  82         EFX_MAC_NTYPES
  83 } efx_mac_type_t;
  84
  85 typedef struct efx_ev_ops_s {
  86         efx_rc_t        (*eevo_init)(efx_nic_t *);
  87         void            (*eevo_fini)(efx_nic_t *);
  88         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  89                                           efsys_mem_t *, size_t, uint32_t,
  90                                           uint32_t, uint32_t, efx_evq_t *);
  91         void            (*eevo_qdestroy)(efx_evq_t *);
  92         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
  93         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
  94         void            (*eevo_qpoll)(efx_evq_t *, unsigned int *,
  95                                         const efx_ev_callbacks_t *, void *);
  96         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
  97 #if EFSYS_OPT_QSTATS
  98         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
  99 #endif
 100 } efx_ev_ops_t;
 101
 102 typedef struct efx_tx_ops_s {
 103         efx_rc_t        (*etxo_init)(efx_nic_t *);
 104         void            (*etxo_fini)(efx_nic_t *);
 105         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 106                                         unsigned int, unsigned int,
 107                                         efsys_mem_t *, size_t,
 108                                         uint32_t, uint16_t,
 109                                         efx_evq_t *, efx_txq_t *,
 110                                         unsigned int *);
 111         void            (*etxo_qdestroy)(efx_txq_t *);
 112         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 113                                       unsigned int, unsigned int,
 114                                       unsigned int *);
 115         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 116         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 117         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 118         void            (*etxo_qenable)(efx_txq_t *);
 119         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 120         void            (*etxo_qpio_disable)(efx_txq_t *);
 121         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
 122                                            size_t);
 123         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 124                                            unsigned int *);
 125         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 126                                       unsigned int, unsigned int,
 127                                       unsigned int *);
 128         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 129                                                 size_t, boolean_t,
 130                                                 efx_desc_t *);
 131         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 132                                                 uint32_t, uint8_t,
 133                                                 efx_desc_t *);
 134         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 135                                                 uint16_t, uint32_t, uint16_t,
 136                                                 efx_desc_t *, int);
 137         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 138                                                 efx_desc_t *);
 139         void            (*etxo_qdesc_checksum_create)(efx_txq_t *, uint16_t,
 140                                                 efx_desc_t *);
 141 #if EFSYS_OPT_QSTATS
 142         void            (*etxo_qstats_update)(efx_txq_t *,
 143                                               efsys_stat_t *);
 144 #endif
 145 } efx_tx_ops_t;
 146
 147 typedef union efx_rxq_type_data_u {
 148         struct {
 149                 size_t          ed_buf_size;
 150         } ertd_default;
 151 #if EFSYS_OPT_RX_PACKED_STREAM
 152         struct {
 153                 uint32_t        eps_buf_size;
 154         } ertd_packed_stream;
 155 #endif
 156 #if EFSYS_OPT_RX_ES_SUPER_BUFFER
 157         struct {
 158                 uint32_t        eessb_bufs_per_desc;
 159                 uint32_t        eessb_max_dma_len;
 160                 uint32_t        eessb_buf_stride;
 161                 uint32_t        eessb_hol_block_timeout;
 162         } ertd_es_super_buffer;
 163 #endif
 164 } efx_rxq_type_data_t;
 165
 166 typedef struct efx_rx_ops_s {
 167         efx_rc_t        (*erxo_init)(efx_nic_t *);
 168         void            (*erxo_fini)(efx_nic_t *);
 169 #if EFSYS_OPT_RX_SCATTER
 170         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 171 #endif
 172 #if EFSYS_OPT_RX_SCALE
 173         efx_rc_t        (*erxo_scale_context_alloc)(efx_nic_t *,
 174                                                     efx_rx_scale_context_type_t,
 175                                                     uint32_t, uint32_t *);
 176         efx_rc_t        (*erxo_scale_context_free)(efx_nic_t *, uint32_t);
 177         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, uint32_t,
 178                                                efx_rx_hash_alg_t,
 179                                                efx_rx_hash_type_t, boolean_t);
 180         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint32_t,
 181                                               uint8_t *, size_t);
 182         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, uint32_t,
 183                                               unsigned int *, size_t);
 184         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 185                                             uint8_t *);
 186 #endif /* EFSYS_OPT_RX_SCALE */
 187         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 188                                               uint16_t *);
 189         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 190                                       unsigned int, unsigned int,
 191                                       unsigned int);
 192         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 193 #if EFSYS_OPT_RX_PACKED_STREAM
 194         void            (*erxo_qpush_ps_credits)(efx_rxq_t *);
 195         uint8_t *       (*erxo_qps_packet_info)(efx_rxq_t *, uint8_t *,
 196                                                 uint32_t, uint32_t,
 197                                                 uint16_t *, uint32_t *, uint32_t *);
 198 #endif
 199         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 200         void            (*erxo_qenable)(efx_rxq_t *);
 201         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 202                                         unsigned int, efx_rxq_type_t,
 203                                         const efx_rxq_type_data_t *,
 204                                         efsys_mem_t *, size_t, uint32_t,
 205                                         unsigned int,
 206                                         efx_evq_t *, efx_rxq_t *);
 207         void            (*erxo_qdestroy)(efx_rxq_t *);
 208 } efx_rx_ops_t;
 209
 210 typedef struct efx_mac_ops_s {
 211         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 212         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 213         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 214         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 215         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 216         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 217         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 218         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 219                                                       efx_rxq_t *, boolean_t);
 220         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 221 #if EFSYS_OPT_LOOPBACK
 222         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 223                                             efx_loopback_type_t);
 224 #endif  /* EFSYS_OPT_LOOPBACK */
 225 #if EFSYS_OPT_MAC_STATS
 226         efx_rc_t        (*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
 227         efx_rc_t        (*emo_stats_clear)(efx_nic_t *);
 228         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 229         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 230                                               uint16_t, boolean_t);
 231         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 232                                             efsys_stat_t *, uint32_t *);
 233 #endif  /* EFSYS_OPT_MAC_STATS */
 234 } efx_mac_ops_t;
 235
 236 typedef struct efx_phy_ops_s {
 237         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 238         efx_rc_t        (*epo_reset)(efx_nic_t *);
 239         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 240         efx_rc_t        (*epo_verify)(efx_nic_t *);
 241         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 242         efx_rc_t        (*epo_link_state_get)(efx_nic_t *, efx_phy_link_state_t *);
 243 #if EFSYS_OPT_PHY_STATS
 244         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 245                                             uint32_t *);
 246 #endif  /* EFSYS_OPT_PHY_STATS */
 247 #if EFSYS_OPT_BIST
 248         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 249         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 250         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 251                                          efx_bist_result_t *, uint32_t *,
 252                                          unsigned long *, size_t);
 253         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 254 #endif  /* EFSYS_OPT_BIST */
 255 } efx_phy_ops_t;
 256
 257 #if EFSYS_OPT_FILTER
 258
 259 /*
 260  * Policy for replacing existing filter when inserting a new one.
 261  * Note that all policies allow for storing the new lower priority
 262  * filters as overridden by existing higher priority ones. It is needed
 263  * to restore the lower priority filters on higher priority ones removal.
 264  */
 265 typedef enum efx_filter_replacement_policy_e {
 266         /* Cannot replace existing filter */
 267         EFX_FILTER_REPLACEMENT_NEVER,
 268         /* Higher priority filters can replace lower priotiry ones */
 269         EFX_FILTER_REPLACEMENT_HIGHER_PRIORITY,
 270         /*
 271          * Higher priority filters can replace lower priority ones and
 272          * equal priority filters can replace each other.
 273          */
 274         EFX_FILTER_REPLACEMENT_HIGHER_OR_EQUAL_PRIORITY,
 275 } efx_filter_replacement_policy_t;
 276
 277 typedef struct efx_filter_ops_s {
 278         efx_rc_t        (*efo_init)(efx_nic_t *);
 279         void            (*efo_fini)(efx_nic_t *);
 280         efx_rc_t        (*efo_restore)(efx_nic_t *);
 281         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 282                                    efx_filter_replacement_policy_t policy);
 283         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 284         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *,
 285                                    size_t, size_t *);
 286         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 287                                    boolean_t, boolean_t, boolean_t,
 288                                    uint8_t const *, uint32_t);
 289 } efx_filter_ops_t;
 290
 291 LIBEFX_INTERNAL
 292 extern  __checkReturn   efx_rc_t
 293 efx_filter_reconfigure(
 294         __in                            efx_nic_t *enp,
 295         __in_ecount(6)                  uint8_t const *mac_addr,
 296         __in                            boolean_t all_unicst,
 297         __in                            boolean_t mulcst,
 298         __in                            boolean_t all_mulcst,
 299         __in                            boolean_t brdcst,
 300         __in_ecount(6*count)            uint8_t const *addrs,
 301         __in                            uint32_t count);
 302
 303 #endif /* EFSYS_OPT_FILTER */
 304
 305 #if EFSYS_OPT_TUNNEL
 306 typedef struct efx_tunnel_ops_s {
 307         efx_rc_t        (*eto_reconfigure)(efx_nic_t *);
 308         void            (*eto_fini)(efx_nic_t *);
 309 } efx_tunnel_ops_t;
 310 #endif /* EFSYS_OPT_TUNNEL */
 311
 312 #if EFSYS_OPT_VIRTIO
 313 typedef struct efx_virtio_ops_s {
 314         efx_rc_t        (*evo_virtio_qstart)(efx_virtio_vq_t *,
 315                                 efx_virtio_vq_cfg_t *,
 316                                 efx_virtio_vq_dyncfg_t *);
 317         efx_rc_t        (*evo_virtio_qstop)(efx_virtio_vq_t *,
 318                                 efx_virtio_vq_dyncfg_t *);
 319         efx_rc_t        (*evo_get_doorbell_offset)(efx_virtio_vq_t *,
 320                                 uint32_t *);
 321         efx_rc_t        (*evo_get_features)(efx_nic_t *,
 322                                 efx_virtio_device_type_t, uint64_t *);
 323         efx_rc_t        (*evo_verify_features)(efx_nic_t *,
 324                                 efx_virtio_device_type_t, uint64_t);
 325 } efx_virtio_ops_t;
 326 #endif /* EFSYS_OPT_VIRTIO */
 327
 328 typedef struct efx_port_s {
 329         efx_mac_type_t          ep_mac_type;
 330         uint32_t                ep_phy_type;
 331         uint8_t                 ep_port;
 332         uint32_t                ep_mac_pdu;
 333         uint8_t                 ep_mac_addr[6];
 334         efx_link_mode_t         ep_link_mode;
 335         boolean_t               ep_all_unicst;
 336         boolean_t               ep_all_unicst_inserted;
 337         boolean_t               ep_mulcst;
 338         boolean_t               ep_all_mulcst;
 339         boolean_t               ep_all_mulcst_inserted;
 340         boolean_t               ep_brdcst;
 341         unsigned int            ep_fcntl;
 342         boolean_t               ep_fcntl_autoneg;
 343         efx_oword_t             ep_multicst_hash[2];
 344         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 345                                                     EFX_MAC_MULTICAST_LIST_MAX];
 346         uint32_t                ep_mulcst_addr_count;
 347 #if EFSYS_OPT_LOOPBACK
 348         efx_loopback_type_t     ep_loopback_type;
 349         efx_link_mode_t         ep_loopback_link_mode;
 350 #endif  /* EFSYS_OPT_LOOPBACK */
 351 #if EFSYS_OPT_PHY_FLAGS
 352         uint32_t                ep_phy_flags;
 353 #endif  /* EFSYS_OPT_PHY_FLAGS */
 354 #if EFSYS_OPT_PHY_LED_CONTROL
 355         efx_phy_led_mode_t      ep_phy_led_mode;
 356 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 357         efx_phy_media_type_t    ep_fixed_port_type;
 358         efx_phy_media_type_t    ep_module_type;
 359         uint32_t                ep_adv_cap_mask;
 360         uint32_t                ep_lp_cap_mask;
 361         uint32_t                ep_default_adv_cap_mask;
 362         uint32_t                ep_phy_cap_mask;
 363         boolean_t               ep_mac_drain;
 364 #if EFSYS_OPT_BIST
 365         efx_bist_type_t         ep_current_bist;
 366 #endif
 367         const efx_mac_ops_t     *ep_emop;
 368         const efx_phy_ops_t     *ep_epop;
 369 } efx_port_t;
 370
 371 typedef struct efx_mon_ops_s {
 372 #if EFSYS_OPT_MON_STATS
 373         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 374                                             efx_mon_stat_value_t *);
 375         efx_rc_t        (*emo_limits_update)(efx_nic_t *,
 376                                              efx_mon_stat_limits_t *);
 377 #endif  /* EFSYS_OPT_MON_STATS */
 378 } efx_mon_ops_t;
 379
 380 typedef struct efx_mon_s {
 381         efx_mon_type_t          em_type;
 382         const efx_mon_ops_t     *em_emop;
 383 } efx_mon_t;
 384
 385 typedef struct efx_intr_ops_s {
 386         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 387         void            (*eio_enable)(efx_nic_t *);
 388         void            (*eio_disable)(efx_nic_t *);
 389         void            (*eio_disable_unlocked)(efx_nic_t *);
 390         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 391         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 392         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 393                                  boolean_t *);
 394         void            (*eio_fatal)(efx_nic_t *);
 395         void            (*eio_fini)(efx_nic_t *);
 396 } efx_intr_ops_t;
 397
 398 typedef struct efx_intr_s {
 399         const efx_intr_ops_t    *ei_eiop;
 400         efsys_mem_t             *ei_esmp;
 401         efx_intr_type_t         ei_type;
 402         unsigned int            ei_level;
 403 } efx_intr_t;
 404
 405 typedef struct efx_nic_ops_s {
 406         efx_rc_t        (*eno_probe)(efx_nic_t *);
 407         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 408         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 409         efx_rc_t        (*eno_reset)(efx_nic_t *);
 410         efx_rc_t        (*eno_init)(efx_nic_t *);
 411         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 412         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 413                                         uint32_t *, size_t *);
 414         boolean_t       (*eno_hw_unavailable)(efx_nic_t *);
 415         void            (*eno_set_hw_unavailable)(efx_nic_t *);
 416 #if EFSYS_OPT_DIAG
 417         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 418 #endif  /* EFSYS_OPT_DIAG */
 419         void            (*eno_fini)(efx_nic_t *);
 420         void            (*eno_unprobe)(efx_nic_t *);
 421 } efx_nic_ops_t;
 422
 423 #ifndef EFX_TXQ_LIMIT_TARGET
 424 #define EFX_TXQ_LIMIT_TARGET 259
 425 #endif
 426 #ifndef EFX_RXQ_LIMIT_TARGET
 427 #define EFX_RXQ_LIMIT_TARGET 512
 428 #endif
 429
 430
 431 #if EFSYS_OPT_FILTER
 432
 433 #if EFSYS_OPT_SIENA
 434
 435 typedef struct siena_filter_spec_s {
 436         uint8_t         sfs_type;
 437         uint32_t        sfs_flags;
 438         uint32_t        sfs_dmaq_id;
 439         uint32_t        sfs_dword[3];
 440 } siena_filter_spec_t;
 441
 442 typedef enum siena_filter_type_e {
 443         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 444         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 445         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 446         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 447         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 448         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 449
 450         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 451         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 452         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 453         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 454         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 455         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 456
 457         EFX_SIENA_FILTER_NTYPES
 458 } siena_filter_type_t;
 459
 460 typedef enum siena_filter_tbl_id_e {
 461         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 462         EFX_SIENA_FILTER_TBL_RX_MAC,
 463         EFX_SIENA_FILTER_TBL_TX_IP,
 464         EFX_SIENA_FILTER_TBL_TX_MAC,
 465         EFX_SIENA_FILTER_NTBLS
 466 } siena_filter_tbl_id_t;
 467
 468 typedef struct siena_filter_tbl_s {
 469         int                     sft_size;       /* number of entries */
 470         int                     sft_used;       /* active count */
 471         uint32_t                *sft_bitmap;    /* active bitmap */
 472         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 473 } siena_filter_tbl_t;
 474
 475 typedef struct siena_filter_s {
 476         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 477         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 478 } siena_filter_t;
 479
 480 #endif  /* EFSYS_OPT_SIENA */
 481
 482 typedef struct efx_filter_s {
 483 #if EFSYS_OPT_SIENA
 484         siena_filter_t          *ef_siena_filter;
 485 #endif /* EFSYS_OPT_SIENA */
 486 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 487         ef10_filter_table_t     *ef_ef10_filter_table;
 488 #endif /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 489 } efx_filter_t;
 490
 491 #if EFSYS_OPT_SIENA
 492
 493 LIBEFX_INTERNAL
 494 extern                  void
 495 siena_filter_tbl_clear(
 496         __in            efx_nic_t *enp,
 497         __in            siena_filter_tbl_id_t tbl);
 498
 499 #endif  /* EFSYS_OPT_SIENA */
 500
 501 #endif  /* EFSYS_OPT_FILTER */
 502
 503 #if EFSYS_OPT_MCDI
 504
 505 #define EFX_TUNNEL_MAXNENTRIES  (16)
 506
 507 #if EFSYS_OPT_TUNNEL
 508
 509 /* State of a UDP tunnel table entry */
 510 typedef enum efx_tunnel_udp_entry_state_e {
 511         EFX_TUNNEL_UDP_ENTRY_ADDED, /* Tunnel addition is requested */
 512         EFX_TUNNEL_UDP_ENTRY_REMOVED, /* Tunnel removal is requested */
 513         EFX_TUNNEL_UDP_ENTRY_APPLIED, /* Tunnel is applied by HW */
 514 } efx_tunnel_udp_entry_state_t;
 515
 516 #if EFSYS_OPT_RIVERHEAD
 517 typedef uint32_t        efx_vnic_encap_rule_handle_t;
 518 #endif /* EFSYS_OPT_RIVERHEAD */
 519
 520 typedef struct efx_tunnel_udp_entry_s {
 521         uint16_t                        etue_port; /* host/cpu-endian */
 522         uint16_t                        etue_protocol;
 523         boolean_t                       etue_busy;
 524         efx_tunnel_udp_entry_state_t    etue_state;
 525 #if EFSYS_OPT_RIVERHEAD
 526         efx_vnic_encap_rule_handle_t    etue_handle;
 527 #endif /* EFSYS_OPT_RIVERHEAD */
 528 } efx_tunnel_udp_entry_t;
 529
 530 typedef struct efx_tunnel_cfg_s {
 531         efx_tunnel_udp_entry_t  etc_udp_entries[EFX_TUNNEL_MAXNENTRIES];
 532         unsigned int            etc_udp_entries_num;
 533 } efx_tunnel_cfg_t;
 534
 535 #endif /* EFSYS_OPT_TUNNEL */
 536
 537 typedef struct efx_mcdi_ops_s {
 538         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 539         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 540                                         void *, size_t);
 541         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 542         boolean_t       (*emco_poll_response)(efx_nic_t *);
 543         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 544         void            (*emco_fini)(efx_nic_t *);
 545         efx_rc_t        (*emco_feature_supported)(efx_nic_t *,
 546                                             efx_mcdi_feature_id_t, boolean_t *);
 547         void            (*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
 548                                             uint32_t *);
 549 } efx_mcdi_ops_t;
 550
 551 typedef struct efx_mcdi_s {
 552         const efx_mcdi_ops_t            *em_emcop;
 553         const efx_mcdi_transport_t      *em_emtp;
 554         efx_mcdi_iface_t                em_emip;
 555 } efx_mcdi_t;
 556
 557 #endif /* EFSYS_OPT_MCDI */
 558
 559 #if EFSYS_OPT_NVRAM
 560
 561 /* Invalid partition ID for en_nvram_partn_locked field of efx_nc_t */
 562 #define EFX_NVRAM_PARTN_INVALID         (0xffffffffu)
 563
 564 typedef struct efx_nvram_ops_s {
 565 #if EFSYS_OPT_DIAG
 566         efx_rc_t        (*envo_test)(efx_nic_t *);
 567 #endif  /* EFSYS_OPT_DIAG */
 568         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 569                                             uint32_t *);
 570         efx_rc_t        (*envo_partn_info)(efx_nic_t *, uint32_t,
 571                                             efx_nvram_info_t *);
 572         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 573         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 574                                             unsigned int, caddr_t, size_t);
 575         efx_rc_t        (*envo_partn_read_backup)(efx_nic_t *, uint32_t,
 576                                             unsigned int, caddr_t, size_t);
 577         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 578                                             unsigned int, size_t);
 579         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 580                                             unsigned int, caddr_t, size_t);
 581         efx_rc_t        (*envo_partn_rw_finish)(efx_nic_t *, uint32_t,
 582                                             uint32_t *);
 583         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 584                                             uint32_t *, uint16_t *);
 585         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 586                                             uint16_t *);
 587         efx_rc_t        (*envo_buffer_validate)(uint32_t,
 588                                             caddr_t, size_t);
 589 } efx_nvram_ops_t;
 590 #endif /* EFSYS_OPT_NVRAM */
 591
 592 #if EFSYS_OPT_VPD
 593 typedef struct efx_vpd_ops_s {
 594         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 595         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 596         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 597         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 598         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 599         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 600                                         efx_vpd_value_t *);
 601         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 602                                         efx_vpd_value_t *);
 603         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 604                                         efx_vpd_value_t *, unsigned int *);
 605         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 606         void            (*evpdo_fini)(efx_nic_t *);
 607 } efx_vpd_ops_t;
 608 #endif  /* EFSYS_OPT_VPD */
 609
 610 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 611
 612 LIBEFX_INTERNAL
 613 extern  __checkReturn           efx_rc_t
 614 efx_mcdi_nvram_partitions(
 615         __in                    efx_nic_t *enp,
 616         __out_bcount(size)      caddr_t data,
 617         __in                    size_t size,
 618         __out                   unsigned int *npartnp);
 619
 620 LIBEFX_INTERNAL
 621 extern  __checkReturn           efx_rc_t
 622 efx_mcdi_nvram_metadata(
 623         __in                    efx_nic_t *enp,
 624         __in                    uint32_t partn,
 625         __out                   uint32_t *subtypep,
 626         __out_ecount(4)         uint16_t version[4],
 627         __out_bcount_opt(size)  char *descp,
 628         __in                    size_t size);
 629
 630 LIBEFX_INTERNAL
 631 extern  __checkReturn           efx_rc_t
 632 efx_mcdi_nvram_info(
 633         __in                    efx_nic_t *enp,
 634         __in                    uint32_t partn,
 635         __out                   efx_nvram_info_t *eni);
 636
 637 LIBEFX_INTERNAL
 638 extern  __checkReturn           efx_rc_t
 639 efx_mcdi_nvram_update_start(
 640         __in                    efx_nic_t *enp,
 641         __in                    uint32_t partn);
 642
 643 LIBEFX_INTERNAL
 644 extern  __checkReturn           efx_rc_t
 645 efx_mcdi_nvram_read(
 646         __in                    efx_nic_t *enp,
 647         __in                    uint32_t partn,
 648         __in                    uint32_t offset,
 649         __out_bcount(size)      caddr_t data,
 650         __in                    size_t size,
 651         __in                    uint32_t mode);
 652
 653 LIBEFX_INTERNAL
 654 extern  __checkReturn           efx_rc_t
 655 efx_mcdi_nvram_erase(
 656         __in                    efx_nic_t *enp,
 657         __in                    uint32_t partn,
 658         __in                    uint32_t offset,
 659         __in                    size_t size);
 660
 661 LIBEFX_INTERNAL
 662 extern  __checkReturn           efx_rc_t
 663 efx_mcdi_nvram_write(
 664         __in                    efx_nic_t *enp,
 665         __in                    uint32_t partn,
 666         __in                    uint32_t offset,
 667         __in_bcount(size)       caddr_t data,
 668         __in                    size_t size);
 669
 670 #define EFX_NVRAM_UPDATE_FLAGS_BACKGROUND       0x00000001
 671 #define EFX_NVRAM_UPDATE_FLAGS_POLL             0x00000002
 672
 673 LIBEFX_INTERNAL
 674 extern  __checkReturn           efx_rc_t
 675 efx_mcdi_nvram_update_finish(
 676         __in                    efx_nic_t *enp,
 677         __in                    uint32_t partn,
 678         __in                    boolean_t reboot,
 679         __in                    uint32_t flags,
 680         __out_opt               uint32_t *verify_resultp);
 681
 682 #if EFSYS_OPT_DIAG
 683
 684 LIBEFX_INTERNAL
 685 extern  __checkReturn           efx_rc_t
 686 efx_mcdi_nvram_test(
 687         __in                    efx_nic_t *enp,
 688         __in                    uint32_t partn);
 689
 690 #endif  /* EFSYS_OPT_DIAG */
 691
 692 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 693
 694 #if EFSYS_OPT_LICENSING
 695
 696 typedef struct efx_lic_ops_s {
 697         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 698         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 699         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 700         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 701                                       size_t *, uint8_t *);
 702         efx_rc_t        (*elo_find_start)
 703                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 704         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 705                                 uint32_t, uint32_t *);
 706         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 707                                 uint32_t, uint32_t *, uint32_t *);
 708         boolean_t       (*elo_validate_key)(efx_nic_t *,
 709                                 caddr_t, uint32_t);
 710         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 711                                 caddr_t, size_t, uint32_t, uint32_t,
 712                                 caddr_t, size_t, uint32_t *);
 713         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 714                                 caddr_t, size_t, uint32_t,
 715                                 caddr_t, uint32_t, uint32_t *);
 716         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 717                                 caddr_t, size_t, uint32_t,
 718                                 uint32_t, uint32_t, uint32_t *);
 719         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 720                                 caddr_t, size_t);
 721         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 722                                 caddr_t, size_t);
 723 } efx_lic_ops_t;
 724
 725 #endif
 726
 727 #if EFSYS_OPT_EVB
 728
 729 struct efx_vswitch_s {
 730         efx_nic_t               *ev_enp;
 731         efx_vswitch_id_t        ev_vswitch_id;
 732         uint32_t                ev_num_vports;
 733         /*
 734          * Vport configuration array: index 0 to store PF configuration
 735          * and next ev_num_vports-1 entries hold VFs configuration.
 736          */
 737         efx_vport_config_t      *ev_evcp;
 738 };
 739
 740 typedef struct efx_evb_ops_s {
 741         efx_rc_t        (*eeo_init)(efx_nic_t *);
 742         void            (*eeo_fini)(efx_nic_t *);
 743         efx_rc_t        (*eeo_vswitch_alloc)(efx_nic_t *, efx_vswitch_id_t *);
 744         efx_rc_t        (*eeo_vswitch_free)(efx_nic_t *, efx_vswitch_id_t);
 745         efx_rc_t        (*eeo_vport_alloc)(efx_nic_t *, efx_vswitch_id_t,
 746                                                 efx_vport_type_t, uint16_t,
 747                                                 boolean_t, efx_vport_id_t *);
 748         efx_rc_t        (*eeo_vport_free)(efx_nic_t *, efx_vswitch_id_t,
 749                                                 efx_vport_id_t);
 750         efx_rc_t        (*eeo_vport_mac_addr_add)(efx_nic_t *, efx_vswitch_id_t,
 751                                                 efx_vport_id_t, uint8_t *);
 752         efx_rc_t        (*eeo_vport_mac_addr_del)(efx_nic_t *, efx_vswitch_id_t,
 753                                                 efx_vport_id_t, uint8_t *);
 754         efx_rc_t        (*eeo_vadaptor_alloc)(efx_nic_t *, efx_vswitch_id_t,
 755                                                 efx_vport_id_t);
 756         efx_rc_t        (*eeo_vadaptor_free)(efx_nic_t *, efx_vswitch_id_t,
 757                                                 efx_vport_id_t);
 758         efx_rc_t        (*eeo_vport_assign)(efx_nic_t *, efx_vswitch_id_t,
 759                                                 efx_vport_id_t, uint32_t);
 760         efx_rc_t        (*eeo_vport_reconfigure)(efx_nic_t *, efx_vswitch_id_t,
 761                                                         efx_vport_id_t,
 762                                                         uint16_t *, uint8_t *,
 763                                                         boolean_t *);
 764         efx_rc_t        (*eeo_vport_stats)(efx_nic_t *, efx_vswitch_id_t,
 765                                                 efx_vport_id_t, efsys_mem_t *);
 766 } efx_evb_ops_t;
 767
 768 LIBEFX_INTERNAL
 769 extern __checkReturn    boolean_t
 770 efx_is_zero_eth_addr(
 771         __in_bcount(EFX_MAC_ADDR_LEN)   const uint8_t *addrp);
 772
 773 #endif /* EFSYS_OPT_EVB */
 774
 775 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 776
 777 #define EFX_PROXY_CONFIGURE_MAGIC       0xAB2015EF
 778
 779
 780 typedef struct efx_proxy_ops_s {
 781         efx_rc_t        (*epo_init)(efx_nic_t *);
 782         void            (*epo_fini)(efx_nic_t *);
 783         efx_rc_t        (*epo_mc_config)(efx_nic_t *, efsys_mem_t *,
 784                                         efsys_mem_t *, efsys_mem_t *,
 785                                         uint32_t, uint32_t *, size_t);
 786         efx_rc_t        (*epo_disable)(efx_nic_t *);
 787         efx_rc_t        (*epo_privilege_modify)(efx_nic_t *, uint32_t, uint32_t,
 788                                         uint32_t, uint32_t, uint32_t);
 789         efx_rc_t        (*epo_set_privilege_mask)(efx_nic_t *, uint32_t,
 790                                         uint32_t, uint32_t);
 791         efx_rc_t        (*epo_complete_request)(efx_nic_t *, uint32_t,
 792                                         uint32_t, uint32_t);
 793         efx_rc_t        (*epo_exec_cmd)(efx_nic_t *, efx_proxy_cmd_params_t *);
 794         efx_rc_t        (*epo_get_privilege_mask)(efx_nic_t *, uint32_t,
 795                                         uint32_t, uint32_t *);
 796 } efx_proxy_ops_t;
 797
 798 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 799
 800 #if EFSYS_OPT_MAE
 801
 802 typedef struct efx_mae_field_cap_s {
 803         uint32_t                        emfc_support;
 804         boolean_t                       emfc_mask_affects_class;
 805         boolean_t                       emfc_match_affects_class;
 806 } efx_mae_field_cap_t;
 807
 808 typedef struct efx_mae_s {
 809         uint32_t                        em_max_n_action_prios;
 810         /*
 811          * The number of MAE field IDs recognised by the FW implementation.
 812          * Any field ID greater than or equal to this value is unsupported.
 813          */
 814         uint32_t                        em_max_nfields;
 815         /** Action rule match field capabilities. */
 816         efx_mae_field_cap_t             *em_action_rule_field_caps;
 817         size_t                          em_action_rule_field_caps_size;
 818         uint32_t                        em_max_n_outer_prios;
 819         uint32_t                        em_encap_types_supported;
 820         /** Outer rule match field capabilities. */
 821         efx_mae_field_cap_t             *em_outer_rule_field_caps;
 822         size_t                          em_outer_rule_field_caps_size;
 823 } efx_mae_t;
 824
 825 #endif /* EFSYS_OPT_MAE */
 826
 827 #define EFX_DRV_VER_MAX         20
 828
 829 typedef struct efx_drv_cfg_s {
 830         uint32_t                edc_min_vi_count;
 831         uint32_t                edc_max_vi_count;
 832
 833         uint32_t                edc_max_piobuf_count;
 834         uint32_t                edc_pio_alloc_size;
 835 } efx_drv_cfg_t;
 836
 837 struct efx_nic_s {
 838         uint32_t                en_magic;
 839         efx_family_t            en_family;
 840         uint32_t                en_features;
 841         efsys_identifier_t      *en_esip;
 842         efsys_lock_t            *en_eslp;
 843         efsys_bar_t             *en_esbp;
 844         unsigned int            en_mod_flags;
 845         unsigned int            en_reset_flags;
 846         efx_nic_cfg_t           en_nic_cfg;
 847         efx_drv_cfg_t           en_drv_cfg;
 848         efx_port_t              en_port;
 849         efx_mon_t               en_mon;
 850         efx_intr_t              en_intr;
 851         uint32_t                en_ev_qcount;
 852         uint32_t                en_rx_qcount;
 853         uint32_t                en_tx_qcount;
 854         const efx_nic_ops_t     *en_enop;
 855         const efx_ev_ops_t      *en_eevop;
 856         const efx_tx_ops_t      *en_etxop;
 857         const efx_rx_ops_t      *en_erxop;
 858         efx_fw_variant_t        efv;
 859         char                    en_drv_version[EFX_DRV_VER_MAX];
 860 #if EFSYS_OPT_FILTER
 861         efx_filter_t            en_filter;
 862         const efx_filter_ops_t  *en_efop;
 863 #endif  /* EFSYS_OPT_FILTER */
 864 #if EFSYS_OPT_TUNNEL
 865         efx_tunnel_cfg_t        en_tunnel_cfg;
 866         const efx_tunnel_ops_t  *en_etop;
 867 #endif /* EFSYS_OPT_TUNNEL */
 868 #if EFSYS_OPT_MCDI
 869         efx_mcdi_t              en_mcdi;
 870 #endif  /* EFSYS_OPT_MCDI */
 871 #if EFSYS_OPT_NVRAM
 872         uint32_t                en_nvram_partn_locked;
 873         const efx_nvram_ops_t   *en_envop;
 874 #endif  /* EFSYS_OPT_NVRAM */
 875 #if EFSYS_OPT_VPD
 876         const efx_vpd_ops_t     *en_evpdop;
 877 #endif  /* EFSYS_OPT_VPD */
 878 #if EFSYS_OPT_VIRTIO
 879         const efx_virtio_ops_t  *en_evop;
 880 #endif  /* EFSYS_OPT_VPD */
 881 #if EFSYS_OPT_RX_SCALE
 882         efx_rx_hash_support_t           en_hash_support;
 883         efx_rx_scale_context_type_t     en_rss_context_type;
 884         uint32_t                        en_rss_context;
 885 #endif  /* EFSYS_OPT_RX_SCALE */
 886         uint32_t                en_vport_id;
 887 #if EFSYS_OPT_LICENSING
 888         const efx_lic_ops_t     *en_elop;
 889         boolean_t               en_licensing_supported;
 890 #endif
 891         union {
 892 #if EFSYS_OPT_SIENA
 893                 struct {
 894 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 895                         unsigned int            enu_partn_mask;
 896 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 897 #if EFSYS_OPT_VPD
 898                         caddr_t                 enu_svpd;
 899                         size_t                  enu_svpd_length;
 900 #endif  /* EFSYS_OPT_VPD */
 901                         int                     enu_unused;
 902                 } siena;
 903 #endif  /* EFSYS_OPT_SIENA */
 904                 int     enu_unused;
 905         } en_u;
 906 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
 907         union en_arch {
 908                 struct {
 909                         int                     ena_vi_base;
 910                         int                     ena_vi_count;
 911                         int                     ena_vi_shift;
 912                         uint32_t                ena_fcw_base;
 913 #if EFSYS_OPT_VPD
 914                         caddr_t                 ena_svpd;
 915                         size_t                  ena_svpd_length;
 916 #endif  /* EFSYS_OPT_VPD */
 917                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 918                         uint32_t                ena_piobuf_count;
 919                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 920                         uint32_t                ena_pio_write_vi_base;
 921                         /* Memory BAR mapping regions */
 922                         uint32_t                ena_uc_mem_map_offset;
 923                         size_t                  ena_uc_mem_map_size;
 924                         uint32_t                ena_wc_mem_map_offset;
 925                         size_t                  ena_wc_mem_map_size;
 926                 } ef10;
 927         } en_arch;
 928 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
 929 #if EFSYS_OPT_EVB
 930         const efx_evb_ops_t     *en_eeop;
 931         struct efx_vswitch_s    *en_vswitchp;
 932 #endif  /* EFSYS_OPT_EVB */
 933 #if EFSYS_OPT_MCDI_PROXY_AUTH_SERVER
 934         const efx_proxy_ops_t   *en_epop;
 935 #endif  /* EFSYS_OPT_MCDI_PROXY_AUTH_SERVER */
 936 #if EFSYS_OPT_MAE
 937         efx_mae_t               *en_maep;
 938 #endif  /* EFSYS_OPT_MAE */
 939 };
 940
 941 #define EFX_FAMILY_IS_EF10(_enp) \
 942         ((_enp)->en_family == EFX_FAMILY_MEDFORD2 || \
 943          (_enp)->en_family == EFX_FAMILY_MEDFORD || \
 944          (_enp)->en_family == EFX_FAMILY_HUNTINGTON)
 945
 946 #define EFX_FAMILY_IS_EF100(_enp) \
 947         ((_enp)->en_family == EFX_FAMILY_RIVERHEAD)
 948
 949
 950 #define EFX_NIC_MAGIC   0x02121996
 951
 952 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 953     const efx_ev_callbacks_t *, void *);
 954
 955 #if EFSYS_OPT_EV_EXTENDED_WIDTH
 956 typedef boolean_t (*efx_ev_ew_handler_t)(efx_evq_t *, efx_xword_t *,
 957     const efx_ev_callbacks_t *, void *);
 958 #endif /* EFSYS_OPT_EV_EXTENDED_WIDTH */
 959
 960 typedef struct efx_evq_rxq_state_s {
 961         unsigned int                    eers_rx_read_ptr;
 962         unsigned int                    eers_rx_mask;
 963 #if EFSYS_OPT_RX_PACKED_STREAM || EFSYS_OPT_RX_ES_SUPER_BUFFER
 964         unsigned int                    eers_rx_stream_npackets;
 965         boolean_t                       eers_rx_packed_stream;
 966 #endif
 967 #if EFSYS_OPT_RX_PACKED_STREAM
 968         unsigned int                    eers_rx_packed_stream_credits;
 969 #endif
 970 } efx_evq_rxq_state_t;
 971
 972 struct efx_evq_s {
 973         uint32_t                        ee_magic;
 974         uint32_t                        ee_flags;
 975         efx_nic_t                       *ee_enp;
 976         unsigned int                    ee_index;
 977         unsigned int                    ee_mask;
 978         efsys_mem_t                     *ee_esmp;
 979 #if EFSYS_OPT_QSTATS
 980         uint32_t                        ee_stat[EV_NQSTATS];
 981 #endif  /* EFSYS_OPT_QSTATS */
 982
 983         efx_ev_handler_t                ee_rx;
 984         efx_ev_handler_t                ee_tx;
 985         efx_ev_handler_t                ee_driver;
 986         efx_ev_handler_t                ee_global;
 987         efx_ev_handler_t                ee_drv_gen;
 988 #if EFSYS_OPT_MCDI
 989         efx_ev_handler_t                ee_mcdi;
 990 #endif  /* EFSYS_OPT_MCDI */
 991
 992 #if EFSYS_OPT_DESC_PROXY
 993         efx_ev_ew_handler_t             ee_ew_txq_desc;
 994         efx_ev_ew_handler_t             ee_ew_virtq_desc;
 995 #endif /* EFSYS_OPT_DESC_PROXY */
 996
 997         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 998 };
 999
1000 #define EFX_EVQ_MAGIC   0x08081997
1001
1002 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
1003
1004 #if EFSYS_OPT_QSTATS
1005 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
1006         do {                                                            \
1007                 (_eep)->ee_stat[_stat]++;                               \
1008         _NOTE(CONSTANTCONDITION)                                        \
1009         } while (B_FALSE)
1010 #else
1011 #define EFX_EV_QSTAT_INCR(_eep, _stat)
1012 #endif
1013
1014 struct efx_rxq_s {
1015         uint32_t                        er_magic;
1016         efx_nic_t                       *er_enp;
1017         efx_evq_t                       *er_eep;
1018         unsigned int                    er_index;
1019         unsigned int                    er_label;
1020         unsigned int                    er_mask;
1021         size_t                          er_buf_size;
1022         efsys_mem_t                     *er_esmp;
1023         efx_evq_rxq_state_t             *er_ev_qstate;
1024         efx_rx_prefix_layout_t          er_prefix_layout;
1025 };
1026
1027 #define EFX_RXQ_MAGIC   0x15022005
1028
1029 struct efx_txq_s {
1030         uint32_t                        et_magic;
1031         efx_nic_t                       *et_enp;
1032         unsigned int                    et_index;
1033         unsigned int                    et_mask;
1034         efsys_mem_t                     *et_esmp;
1035 #if EFSYS_OPT_HUNTINGTON
1036         uint32_t                        et_pio_bufnum;
1037         uint32_t                        et_pio_blknum;
1038         uint32_t                        et_pio_write_offset;
1039         uint32_t                        et_pio_offset;
1040         size_t                          et_pio_size;
1041 #endif
1042 #if EFSYS_OPT_QSTATS
1043         uint32_t                        et_stat[TX_NQSTATS];
1044 #endif  /* EFSYS_OPT_QSTATS */
1045 };
1046
1047 #define EFX_TXQ_MAGIC   0x05092005
1048
1049 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
1050         do {                                                            \
1051                 (_dst)[0] = (_src)[0];                                  \
1052                 (_dst)[1] = (_src)[1];                                  \
1053                 (_dst)[2] = (_src)[2];                                  \
1054                 (_dst)[3] = (_src)[3];                                  \
1055                 (_dst)[4] = (_src)[4];                                  \
1056                 (_dst)[5] = (_src)[5];                                  \
1057         _NOTE(CONSTANTCONDITION)                                        \
1058         } while (B_FALSE)
1059
1060 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
1061         do {                                                            \
1062                 uint16_t *_d = (uint16_t *)(_dst);                      \
1063                 _d[0] = 0xffff;                                         \
1064                 _d[1] = 0xffff;                                         \
1065                 _d[2] = 0xffff;                                         \
1066         _NOTE(CONSTANTCONDITION)                                        \
1067         } while (B_FALSE)
1068
1069 #if EFSYS_OPT_CHECK_REG
1070 #define EFX_CHECK_REG(_enp, _reg)                                       \
1071         do {                                                            \
1072                 const char *name = #_reg;                               \
1073                 char min = name[4];                                     \
1074                 char max = name[5];                                     \
1075                 char rev;                                               \
1076                                                                         \
1077                 switch ((_enp)->en_family) {                            \
1078                 case EFX_FAMILY_SIENA:                                  \
1079                         rev = 'C';                                      \
1080                         break;                                          \
1081                                                                         \
1082                 case EFX_FAMILY_HUNTINGTON:                             \
1083                         rev = 'D';                                      \
1084                         break;                                          \
1085                                                                         \
1086                 case EFX_FAMILY_MEDFORD:                                \
1087                         rev = 'E';                                      \
1088                         break;                                          \
1089                                                                         \
1090                 case EFX_FAMILY_MEDFORD2:                               \
1091                         rev = 'F';                                      \
1092                         break;                                          \
1093                                                                         \
1094                 case EFX_FAMILY_RIVERHEAD:                              \
1095                         rev = 'G';                                      \
1096                         break;                                          \
1097                                                                         \
1098                 default:                                                \
1099                         rev = '?';                                      \
1100                         break;                                          \
1101                 }                                                       \
1102                                                                         \
1103                 EFSYS_ASSERT3S(rev, >=, min);                           \
1104                 EFSYS_ASSERT3S(rev, <=, max);                           \
1105                                                                         \
1106         _NOTE(CONSTANTCONDITION)                                        \
1107         } while (B_FALSE)
1108 #else
1109 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
1110         _NOTE(CONSTANTCONDITION)                                        \
1111         } while (B_FALSE)
1112 #endif
1113
1114 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
1115         do {                                                            \
1116                 EFX_CHECK_REG((_enp), (_reg));                          \
1117                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
1118                     (_edp), (_lock));                                   \
1119                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
1120                     uint32_t, _reg ## _OFST,                            \
1121                     uint32_t, (_edp)->ed_u32[0]);                       \
1122         _NOTE(CONSTANTCONDITION)                                        \
1123         } while (B_FALSE)
1124
1125 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
1126         do {                                                            \
1127                 EFX_CHECK_REG((_enp), (_reg));                          \
1128                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
1129                     uint32_t, _reg ## _OFST,                            \
1130                     uint32_t, (_edp)->ed_u32[0]);                       \
1131                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
1132                     (_edp), (_lock));                                   \
1133         _NOTE(CONSTANTCONDITION)                                        \
1134         } while (B_FALSE)
1135
1136 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
1137         do {                                                            \
1138                 EFX_CHECK_REG((_enp), (_reg));                          \
1139                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
1140                     (_eqp));                                            \
1141                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
1142                     uint32_t, _reg ## _OFST,                            \
1143                     uint32_t, (_eqp)->eq_u32[1],                        \
1144                     uint32_t, (_eqp)->eq_u32[0]);                       \
1145         _NOTE(CONSTANTCONDITION)                                        \
1146         } while (B_FALSE)
1147
1148 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
1149         do {                                                            \
1150                 EFX_CHECK_REG((_enp), (_reg));                          \
1151                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
1152                     uint32_t, _reg ## _OFST,                            \
1153                     uint32_t, (_eqp)->eq_u32[1],                        \
1154                     uint32_t, (_eqp)->eq_u32[0]);                       \
1155                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
1156                     (_eqp));                                            \
1157         _NOTE(CONSTANTCONDITION)                                        \
1158         } while (B_FALSE)
1159
1160 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
1161         do {                                                            \
1162                 EFX_CHECK_REG((_enp), (_reg));                          \
1163                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
1164                     (_eop), B_TRUE);                                    \
1165                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
1166                     uint32_t, _reg ## _OFST,                            \
1167                     uint32_t, (_eop)->eo_u32[3],                        \
1168                     uint32_t, (_eop)->eo_u32[2],                        \
1169                     uint32_t, (_eop)->eo_u32[1],                        \
1170                     uint32_t, (_eop)->eo_u32[0]);                       \
1171         _NOTE(CONSTANTCONDITION)                                        \
1172         } while (B_FALSE)
1173
1174 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
1175         do {                                                            \
1176                 EFX_CHECK_REG((_enp), (_reg));                          \
1177                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
1178                     uint32_t, _reg ## _OFST,                            \
1179                     uint32_t, (_eop)->eo_u32[3],                        \
1180                     uint32_t, (_eop)->eo_u32[2],                        \
1181                     uint32_t, (_eop)->eo_u32[1],                        \
1182                     uint32_t, (_eop)->eo_u32[0]);                       \
1183                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
1184                     (_eop), B_TRUE);                                    \
1185         _NOTE(CONSTANTCONDITION)                                        \
1186         } while (B_FALSE)
1187
1188 /*
1189  * Accessors for memory BAR non-VI tables.
1190  *
1191  * Code used on EF10 *must* use EFX_BAR_VI_*() macros for per-VI registers,
1192  * to ensure the correct runtime VI window size is used on Medford2.
1193  *
1194  * Code used on EF100 *must* use EFX_BAR_FCW_* macros for function control
1195  * window registers, to ensure the correct starting offset is used.
1196  *
1197  * Siena-only code may continue using EFX_BAR_TBL_*() macros for VI registers.
1198  */
1199
1200 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
1201         do {                                                            \
1202                 EFX_CHECK_REG((_enp), (_reg));                          \
1203                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1204                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1205                     (_edp), (_lock));                                   \
1206                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
1207                     uint32_t, (_index),                                 \
1208                     uint32_t, _reg ## _OFST,                            \
1209                     uint32_t, (_edp)->ed_u32[0]);                       \
1210         _NOTE(CONSTANTCONDITION)                                        \
1211         } while (B_FALSE)
1212
1213 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
1214         do {                                                            \
1215                 EFX_CHECK_REG((_enp), (_reg));                          \
1216                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1217                     uint32_t, (_index),                                 \
1218                     uint32_t, _reg ## _OFST,                            \
1219                     uint32_t, (_edp)->ed_u32[0]);                       \
1220                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1221                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1222                     (_edp), (_lock));                                   \
1223         _NOTE(CONSTANTCONDITION)                                        \
1224         } while (B_FALSE)
1225
1226 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
1227         do {                                                            \
1228                 EFX_CHECK_REG((_enp), (_reg));                          \
1229                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
1230                     uint32_t, (_index),                                 \
1231                     uint32_t, _reg ## _OFST,                            \
1232                     uint32_t, (_edp)->ed_u32[0]);                       \
1233                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1234                     (_reg ## _OFST +                                    \
1235                     (3 * sizeof (efx_dword_t)) +                        \
1236                     ((_index) * _reg ## _STEP)),                        \
1237                     (_edp), (_lock));                                   \
1238         _NOTE(CONSTANTCONDITION)                                        \
1239         } while (B_FALSE)
1240
1241 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
1242         do {                                                            \
1243                 EFX_CHECK_REG((_enp), (_reg));                          \
1244                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
1245                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1246                     (_eqp));                                            \
1247                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
1248                     uint32_t, (_index),                                 \
1249                     uint32_t, _reg ## _OFST,                            \
1250                     uint32_t, (_eqp)->eq_u32[1],                        \
1251                     uint32_t, (_eqp)->eq_u32[0]);                       \
1252         _NOTE(CONSTANTCONDITION)                                        \
1253         } while (B_FALSE)
1254
1255 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
1256         do {                                                            \
1257                 EFX_CHECK_REG((_enp), (_reg));                          \
1258                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
1259                     uint32_t, (_index),                                 \
1260                     uint32_t, _reg ## _OFST,                            \
1261                     uint32_t, (_eqp)->eq_u32[1],                        \
1262                     uint32_t, (_eqp)->eq_u32[0]);                       \
1263                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
1264                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1265                     (_eqp));                                            \
1266         _NOTE(CONSTANTCONDITION)                                        \
1267         } while (B_FALSE)
1268
1269 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
1270         do {                                                            \
1271                 EFX_CHECK_REG((_enp), (_reg));                          \
1272                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
1273                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1274                     (_eop), (_lock));                                   \
1275                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
1276                     uint32_t, (_index),                                 \
1277                     uint32_t, _reg ## _OFST,                            \
1278                     uint32_t, (_eop)->eo_u32[3],                        \
1279                     uint32_t, (_eop)->eo_u32[2],                        \
1280                     uint32_t, (_eop)->eo_u32[1],                        \
1281                     uint32_t, (_eop)->eo_u32[0]);                       \
1282         _NOTE(CONSTANTCONDITION)                                        \
1283         } while (B_FALSE)
1284
1285 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
1286         do {                                                            \
1287                 EFX_CHECK_REG((_enp), (_reg));                          \
1288                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
1289                     uint32_t, (_index),                                 \
1290                     uint32_t, _reg ## _OFST,                            \
1291                     uint32_t, (_eop)->eo_u32[3],                        \
1292                     uint32_t, (_eop)->eo_u32[2],                        \
1293                     uint32_t, (_eop)->eo_u32[1],                        \
1294                     uint32_t, (_eop)->eo_u32[0]);                       \
1295                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
1296                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1297                     (_eop), (_lock));                                   \
1298         _NOTE(CONSTANTCONDITION)                                        \
1299         } while (B_FALSE)
1300
1301 /*
1302  * Accessors for memory BAR function control window registers.
1303  *
1304  * The function control window is located at an offset which can be
1305  * non-zero in case of Riverhead.
1306  */
1307
1308 #if EFSYS_OPT_RIVERHEAD
1309
1310 #define EFX_BAR_FCW_READD(_enp, _reg, _edp)                             \
1311         do {                                                            \
1312                 EFX_CHECK_REG((_enp), (_reg));                          \
1313                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST +        \
1314                     (_enp)->en_arch.ef10.ena_fcw_base,                  \
1315                     (_edp), B_FALSE);                                   \
1316                 EFSYS_PROBE3(efx_bar_fcw_readd, const char *, #_reg,    \
1317                     uint32_t, _reg ## _OFST,                            \
1318                     uint32_t, (_edp)->ed_u32[0]);                       \
1319         _NOTE(CONSTANTCONDITION)                                        \
1320         } while (B_FALSE)
1321
1322 #define EFX_BAR_FCW_WRITED(_enp, _reg, _edp)                            \
1323         do {                                                            \
1324                 EFX_CHECK_REG((_enp), (_reg));                          \
1325                 EFSYS_PROBE3(efx_bar_fcw_writed, const char *, #_reg,   \
1326                     uint32_t, _reg ## _OFST,                            \
1327                     uint32_t, (_edp)->ed_u32[0]);                       \
1328                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST +       \
1329                     (_enp)->en_arch.ef10.ena_fcw_base,                  \
1330                     (_edp), B_FALSE);                                   \
1331         _NOTE(CONSTANTCONDITION)                                        \
1332         } while (B_FALSE)
1333
1334 #endif  /* EFSYS_OPT_RIVERHEAD */
1335
1336 /*
1337  * Accessors for memory BAR per-VI registers.
1338  *
1339  * The VI window size is 8KB for Medford and all earlier controllers.
1340  * For Medford2, the VI window size can be 8KB, 16KB or 64KB.
1341  */
1342
1343 #define EFX_BAR_VI_READD(_enp, _reg, _index, _edp, _lock)               \
1344         do {                                                            \
1345                 EFX_CHECK_REG((_enp), (_reg));                          \
1346                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
1347                     ((_reg ## _OFST) +                                  \
1348                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1349                     (_edp), (_lock));                                   \
1350                 EFSYS_PROBE4(efx_bar_vi_readd, const char *, #_reg,     \
1351                     uint32_t, (_index),                                 \
1352                     uint32_t, _reg ## _OFST,                            \
1353                     uint32_t, (_edp)->ed_u32[0]);                       \
1354         _NOTE(CONSTANTCONDITION)                                        \
1355         } while (B_FALSE)
1356
1357 #define EFX_BAR_VI_WRITED(_enp, _reg, _index, _edp, _lock)              \
1358         do {                                                            \
1359                 EFX_CHECK_REG((_enp), (_reg));                          \
1360                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1361                     uint32_t, (_index),                                 \
1362                     uint32_t, _reg ## _OFST,                            \
1363                     uint32_t, (_edp)->ed_u32[0]);                       \
1364                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1365                     ((_reg ## _OFST) +                                  \
1366                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1367                     (_edp), (_lock));                                   \
1368         _NOTE(CONSTANTCONDITION)                                        \
1369         } while (B_FALSE)
1370
1371 #define EFX_BAR_VI_WRITED2(_enp, _reg, _index, _edp, _lock)             \
1372         do {                                                            \
1373                 EFX_CHECK_REG((_enp), (_reg));                          \
1374                 EFSYS_PROBE4(efx_bar_vi_writed, const char *, #_reg,    \
1375                     uint32_t, (_index),                                 \
1376                     uint32_t, _reg ## _OFST,                            \
1377                     uint32_t, (_edp)->ed_u32[0]);                       \
1378                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
1379                     ((_reg ## _OFST) +                                  \
1380                     (2 * sizeof (efx_dword_t)) +                        \
1381                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1382                     (_edp), (_lock));                                   \
1383         _NOTE(CONSTANTCONDITION)                                        \
1384         } while (B_FALSE)
1385
1386 /*
1387  * Allow drivers to perform optimised 128-bit VI doorbell writes.
1388  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1389  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1390  * the need for locking in the host, and are the only ones known to be safe to
1391  * use 128-bites write with.
1392  */
1393 #define EFX_BAR_VI_DOORBELL_WRITEO(_enp, _reg, _index, _eop)            \
1394         do {                                                            \
1395                 EFX_CHECK_REG((_enp), (_reg));                          \
1396                 EFSYS_PROBE7(efx_bar_vi_doorbell_writeo,                \
1397                     const char *, #_reg,                                \
1398                     uint32_t, (_index),                                 \
1399                     uint32_t, _reg ## _OFST,                            \
1400                     uint32_t, (_eop)->eo_u32[3],                        \
1401                     uint32_t, (_eop)->eo_u32[2],                        \
1402                     uint32_t, (_eop)->eo_u32[1],                        \
1403                     uint32_t, (_eop)->eo_u32[0]);                       \
1404                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1405                     (_reg ## _OFST +                                    \
1406                     ((_index) << (_enp)->en_nic_cfg.enc_vi_window_shift)), \
1407                     (_eop));                                            \
1408         _NOTE(CONSTANTCONDITION)                                        \
1409         } while (B_FALSE)
1410
1411 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _desc_size,      \
1412                                       _wptr, _owptr)                    \
1413         do {                                                            \
1414                 unsigned int _new = (_wptr);                            \
1415                 unsigned int _old = (_owptr);                           \
1416                                                                         \
1417                 if ((_new) >= (_old))                                   \
1418                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1419                             (_old) * (_desc_size),                      \
1420                             ((_new) - (_old)) * (_desc_size));          \
1421                 else                                                    \
1422                         /*                                              \
1423                          * It is cheaper to sync entire map than sync   \
1424                          * two parts especially when offset/size are    \
1425                          * ignored and entire map is synced in any case.\
1426                          */                                             \
1427                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1428                             0,                                          \
1429                             (_entries) * (_desc_size));                 \
1430         _NOTE(CONSTANTCONDITION)                                        \
1431         } while (B_FALSE)
1432
1433 LIBEFX_INTERNAL
1434 extern  __checkReturn   efx_rc_t
1435 efx_mac_select(
1436         __in            efx_nic_t *enp);
1437
1438 LIBEFX_INTERNAL
1439 extern  void
1440 efx_mac_multicast_hash_compute(
1441         __in_ecount(6*count)            uint8_t const *addrs,
1442         __in                            int count,
1443         __out                           efx_oword_t *hash_low,
1444         __out                           efx_oword_t *hash_high);
1445
1446 LIBEFX_INTERNAL
1447 extern  __checkReturn   efx_rc_t
1448 efx_phy_probe(
1449         __in            efx_nic_t *enp);
1450
1451 LIBEFX_INTERNAL
1452 extern                  void
1453 efx_phy_unprobe(
1454         __in            efx_nic_t *enp);
1455
1456 #if EFSYS_OPT_VPD
1457
1458 /* VPD utility functions */
1459
1460 LIBEFX_INTERNAL
1461 extern  __checkReturn           efx_rc_t
1462 efx_vpd_hunk_length(
1463         __in_bcount(size)       caddr_t data,
1464         __in                    size_t size,
1465         __out                   size_t *lengthp);
1466
1467 LIBEFX_INTERNAL
1468 extern  __checkReturn           efx_rc_t
1469 efx_vpd_hunk_verify(
1470         __in_bcount(size)       caddr_t data,
1471         __in                    size_t size,
1472         __out_opt               boolean_t *cksummedp);
1473
1474 LIBEFX_INTERNAL
1475 extern  __checkReturn           efx_rc_t
1476 efx_vpd_hunk_reinit(
1477         __in_bcount(size)       caddr_t data,
1478         __in                    size_t size,
1479         __in                    boolean_t wantpid);
1480
1481 LIBEFX_INTERNAL
1482 extern  __checkReturn           efx_rc_t
1483 efx_vpd_hunk_get(
1484         __in_bcount(size)       caddr_t data,
1485         __in                    size_t size,
1486         __in                    efx_vpd_tag_t tag,
1487         __in                    efx_vpd_keyword_t keyword,
1488         __out                   unsigned int *payloadp,
1489         __out                   uint8_t *paylenp);
1490
1491 LIBEFX_INTERNAL
1492 extern  __checkReturn                   efx_rc_t
1493 efx_vpd_hunk_next(
1494         __in_bcount(size)               caddr_t data,
1495         __in                            size_t size,
1496         __out                           efx_vpd_tag_t *tagp,
1497         __out                           efx_vpd_keyword_t *keyword,
1498         __out_opt                       unsigned int *payloadp,
1499         __out_opt                       uint8_t *paylenp,
1500         __inout                         unsigned int *contp);
1501
1502 LIBEFX_INTERNAL
1503 extern  __checkReturn           efx_rc_t
1504 efx_vpd_hunk_set(
1505         __in_bcount(size)       caddr_t data,
1506         __in                    size_t size,
1507         __in                    efx_vpd_value_t *evvp);
1508
1509 #endif  /* EFSYS_OPT_VPD */
1510
1511 #if EFSYS_OPT_MCDI
1512
1513 LIBEFX_INTERNAL
1514 extern  __checkReturn           efx_rc_t
1515 efx_mcdi_set_workaround(
1516         __in                    efx_nic_t *enp,
1517         __in                    uint32_t type,
1518         __in                    boolean_t enabled,
1519         __out_opt               uint32_t *flagsp);
1520
1521 LIBEFX_INTERNAL
1522 extern  __checkReturn           efx_rc_t
1523 efx_mcdi_get_workarounds(
1524         __in                    efx_nic_t *enp,
1525         __out_opt               uint32_t *implementedp,
1526         __out_opt               uint32_t *enabledp);
1527
1528 #if EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10()
1529
1530 LIBEFX_INTERNAL
1531 extern  __checkReturn   efx_rc_t
1532 efx_mcdi_init_evq(
1533         __in            efx_nic_t *enp,
1534         __in            unsigned int instance,
1535         __in            efsys_mem_t *esmp,
1536         __in            size_t nevs,
1537         __in            uint32_t irq,
1538         __in            uint32_t target_evq,
1539         __in            uint32_t us,
1540         __in            uint32_t flags,
1541         __in            boolean_t low_latency);
1542
1543 LIBEFX_INTERNAL
1544 extern  __checkReturn   efx_rc_t
1545 efx_mcdi_fini_evq(
1546         __in            efx_nic_t *enp,
1547         __in            uint32_t instance);
1548
1549 typedef struct efx_mcdi_init_rxq_params_s {
1550         boolean_t       disable_scatter;
1551         boolean_t       want_inner_classes;
1552         uint32_t        buf_size;
1553         uint32_t        ps_buf_size;
1554         uint32_t        es_bufs_per_desc;
1555         uint32_t        es_max_dma_len;
1556         uint32_t        es_buf_stride;
1557         uint32_t        hol_block_timeout;
1558         uint32_t        prefix_id;
1559 } efx_mcdi_init_rxq_params_t;
1560
1561 LIBEFX_INTERNAL
1562 extern  __checkReturn   efx_rc_t
1563 efx_mcdi_init_rxq(
1564         __in            efx_nic_t *enp,
1565         __in            uint32_t ndescs,
1566         __in            efx_evq_t *eep,
1567         __in            uint32_t label,
1568         __in            uint32_t instance,
1569         __in            efsys_mem_t *esmp,
1570         __in            const efx_mcdi_init_rxq_params_t *params);
1571
1572 LIBEFX_INTERNAL
1573 extern  __checkReturn   efx_rc_t
1574 efx_mcdi_fini_rxq(
1575         __in            efx_nic_t *enp,
1576         __in            uint32_t instance);
1577
1578 LIBEFX_INTERNAL
1579 extern  __checkReturn   efx_rc_t
1580 efx_mcdi_init_txq(
1581         __in            efx_nic_t *enp,
1582         __in            uint32_t ndescs,
1583         __in            uint32_t target_evq,
1584         __in            uint32_t label,
1585         __in            uint32_t instance,
1586         __in            uint16_t flags,
1587         __in            efsys_mem_t *esmp);
1588
1589 LIBEFX_INTERNAL
1590 extern  __checkReturn   efx_rc_t
1591 efx_mcdi_fini_txq(
1592         __in            efx_nic_t *enp,
1593         __in            uint32_t instance);
1594
1595 #endif  /* EFSYS_OPT_RIVERHEAD || EFX_OPTS_EF10() */
1596
1597 #endif /* EFSYS_OPT_MCDI */
1598
1599 #if EFSYS_OPT_MAC_STATS
1600
1601 /*
1602  * Closed range of stats (i.e. the first and the last are included).
1603  * The last must be greater or equal (if the range is one item only) to
1604  * the first.
1605  */
1606 struct efx_mac_stats_range {
1607         efx_mac_stat_t          first;
1608         efx_mac_stat_t          last;
1609 };
1610
1611 typedef enum efx_stats_action_e {
1612         EFX_STATS_CLEAR,
1613         EFX_STATS_UPLOAD,
1614         EFX_STATS_ENABLE_NOEVENTS,
1615         EFX_STATS_ENABLE_EVENTS,
1616         EFX_STATS_DISABLE,
1617 } efx_stats_action_t;
1618
1619 LIBEFX_INTERNAL
1620 extern                                  efx_rc_t
1621 efx_mac_stats_mask_add_ranges(
1622         __inout_bcount(mask_size)       uint32_t *maskp,
1623         __in                            size_t mask_size,
1624         __in_ecount(rng_count)          const struct efx_mac_stats_range *rngp,
1625         __in                            unsigned int rng_count);
1626
1627 LIBEFX_INTERNAL
1628 extern  __checkReturn   efx_rc_t
1629 efx_mcdi_mac_stats(
1630         __in            efx_nic_t *enp,
1631         __in            uint32_t vport_id,
1632         __in_opt        efsys_mem_t *esmp,
1633         __in            efx_stats_action_t action,
1634         __in            uint16_t period_ms);
1635
1636 #endif  /* EFSYS_OPT_MAC_STATS */
1637
1638 #if EFSYS_OPT_PCI
1639
1640 /*
1641  * Find the next extended capability in a PCI device's config space
1642  * with specified capability id.
1643  * Passing 0 offset makes the function search from the start.
1644  * If search succeeds, found capability is in modified offset.
1645  *
1646  * Returns ENOENT if a capability is not found.
1647  */
1648 LIBEFX_INTERNAL
1649 extern  __checkReturn                   efx_rc_t
1650 efx_pci_config_find_next_ext_cap(
1651         __in                            efsys_pci_config_t *espcp,
1652         __in                            const efx_pci_ops_t *epop,
1653         __in                            uint16_t cap_id,
1654         __inout                         size_t *offsetp);
1655
1656 /*
1657  * Get the next extended capability in a PCI device's config space.
1658  * Passing 0 offset makes the function get the first capability.
1659  * If search succeeds, the capability is in modified offset.
1660  *
1661  * Returns ENOENT if there is no next capability.
1662  */
1663 LIBEFX_INTERNAL
1664 extern  __checkReturn                   efx_rc_t
1665 efx_pci_config_next_ext_cap(
1666         __in                            efsys_pci_config_t *espcp,
1667         __in                            const efx_pci_ops_t *epop,
1668         __inout                         size_t *offsetp);
1669
1670 /*
1671  * Find the next Xilinx capabilities table location by searching
1672  * PCI extended capabilities.
1673  *
1674  * Returns ENOENT if a table location is not found.
1675  */
1676 LIBEFX_INTERNAL
1677 extern  __checkReturn                   efx_rc_t
1678 efx_pci_find_next_xilinx_cap_table(
1679         __in                            efsys_pci_config_t *espcp,
1680         __in                            const efx_pci_ops_t *epop,
1681         __inout                         size_t *pci_cap_offsetp,
1682         __out                           unsigned int *xilinx_tbl_barp,
1683         __out                           efsys_dma_addr_t *xilinx_tbl_offsetp);
1684
1685 /*
1686  * Read a Xilinx extended PCI capability that gives the location
1687  * of a Xilinx capabilities table.
1688  *
1689  * Returns ENOENT if the extended PCI capability does not contain
1690  * Xilinx capabilities table locator.
1691  */
1692 LIBEFX_INTERNAL
1693 extern  __checkReturn                   efx_rc_t
1694 efx_pci_read_ext_cap_xilinx_table(
1695         __in                            efsys_pci_config_t *espcp,
1696         __in                            const efx_pci_ops_t *epop,
1697         __in                            size_t cap_offset,
1698         __out                           unsigned int *barp,
1699         __out                           efsys_dma_addr_t *offsetp);
1700
1701 /*
1702  * Find a capability with specified format_id in a Xilinx capabilities table.
1703  * Searching is started from provided offset, taking skip_first into account.
1704  * If search succeeds, found capability is in modified offset.
1705  *
1706  * Returns ENOENT if an entry with specified format id is not found.
1707  */
1708 LIBEFX_INTERNAL
1709 extern  __checkReturn                   efx_rc_t
1710 efx_pci_xilinx_cap_tbl_find(
1711         __in                            efsys_bar_t *esbp,
1712         __in                            uint32_t format_id,
1713         __in                            boolean_t skip_first,
1714         __inout                         efsys_dma_addr_t *entry_offsetp);
1715
1716 #endif /* EFSYS_OPT_PCI */
1717
1718 #if EFSYS_OPT_MAE
1719
1720 struct efx_mae_match_spec_s {
1721         efx_mae_rule_type_t             emms_type;
1722         uint32_t                        emms_prio;
1723         union emms_mask_value_pairs {
1724                 uint8_t                 action[
1725                                             MAE_FIELD_MASK_VALUE_PAIRS_V2_LEN];
1726                 uint8_t                 outer[MAE_ENC_FIELD_PAIRS_LEN];
1727         } emms_mask_value_pairs;
1728 };
1729
1730 typedef enum efx_mae_action_e {
1731         /* These actions are strictly ordered. */
1732         EFX_MAE_ACTION_DECAP,
1733         EFX_MAE_ACTION_VLAN_POP,
1734         EFX_MAE_ACTION_VLAN_PUSH,
1735         EFX_MAE_ACTION_ENCAP,
1736
1737         /*
1738          * These actions are not strictly ordered and can
1739          * be passed by a client in any order (before DELIVER).
1740          * However, these enumerants must be kept compactly
1741          * in the end of the enumeration (before DELIVER).
1742          */
1743         EFX_MAE_ACTION_FLAG,
1744         EFX_MAE_ACTION_MARK,
1745
1746         /* DELIVER is always the last action. */
1747         EFX_MAE_ACTION_DELIVER,
1748
1749         EFX_MAE_NACTIONS
1750 } efx_mae_action_t;
1751
1752 /* MAE VLAN_POP action can handle 1 or 2 tags. */
1753 #define EFX_MAE_VLAN_POP_MAX_NTAGS      (2)
1754
1755 /* MAE VLAN_PUSH action can handle 1 or 2 tags. */
1756 #define EFX_MAE_VLAN_PUSH_MAX_NTAGS     (2)
1757
1758 typedef struct efx_mae_action_vlan_push_s {
1759         uint16_t                        emavp_tpid_be;
1760         uint16_t                        emavp_tci_be;
1761 } efx_mae_action_vlan_push_t;
1762
1763 typedef struct efx_mae_actions_rsrc_s {
1764         efx_mae_eh_id_t                 emar_eh_id;
1765 } efx_mae_actions_rsrc_t;
1766
1767 struct efx_mae_actions_s {
1768         /* Bitmap of actions in spec, indexed by action type */
1769         uint32_t                        ema_actions;
1770
1771         unsigned int                    ema_n_vlan_tags_to_pop;
1772         unsigned int                    ema_n_vlan_tags_to_push;
1773         efx_mae_action_vlan_push_t      ema_vlan_push_descs[
1774             EFX_MAE_VLAN_PUSH_MAX_NTAGS];
1775         uint32_t                        ema_mark_value;
1776         efx_mport_sel_t                 ema_deliver_mport;
1777
1778         /*
1779          * Always keep this at the end of the struct since
1780          * efx_mae_action_set_specs_equal() relies on that
1781          * to make sure that resource IDs are not compared.
1782          */
1783         efx_mae_actions_rsrc_t          ema_rsrc;
1784 };
1785
1786 #endif /* EFSYS_OPT_MAE */
1787
1788 #if EFSYS_OPT_VIRTIO
1789
1790 #define EFX_VQ_MAGIC    0x026011950
1791
1792 typedef enum efx_virtio_vq_state_e {
1793         EFX_VIRTIO_VQ_STATE_UNKNOWN = 0,
1794         EFX_VIRTIO_VQ_STATE_INITIALIZED,
1795         EFX_VIRTIO_VQ_STATE_STARTED,
1796         EFX_VIRTIO_VQ_NSTATES
1797 } efx_virtio_vq_state_t;
1798
1799 struct efx_virtio_vq_s {
1800         uint32_t                evv_magic;
1801         efx_nic_t               *evv_enp;
1802         efx_virtio_vq_state_t   evv_state;
1803         uint32_t                evv_vi_index;
1804         efx_virtio_vq_type_t    evv_type;
1805         uint16_t                evv_target_vf;
1806 };
1807
1808 #endif /* EFSYS_OPT_VIRTIO */
1809
1810 #ifdef  __cplusplus
1811 }
1812 #endif
1813
1814 #endif  /* _SYS_EFX_IMPL_H */