drivers/common/sfc_efx/base/efx_mae.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_MAE
  12
  13 static  __checkReturn                   efx_rc_t
  14 efx_mae_get_capabilities(
  15         __in                            efx_nic_t *enp)
  16 {
  17         efx_mcdi_req_t req;
  18         EFX_MCDI_DECLARE_BUF(payload,
  19             MC_CMD_MAE_GET_CAPS_IN_LEN,
  20             MC_CMD_MAE_GET_CAPS_OUT_LEN);
  21         struct efx_mae_s *maep = enp->en_maep;
  22         efx_rc_t rc;
  23
  24         req.emr_cmd = MC_CMD_MAE_GET_CAPS;
  25         req.emr_in_buf = payload;
  26         req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
  27         req.emr_out_buf = payload;
  28         req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
  29
  30         efx_mcdi_execute(enp, &req);
  31
  32         if (req.emr_rc != 0) {
  33                 rc = req.emr_rc;
  34                 goto fail1;
  35         }
  36
  37         if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
  38                 rc = EMSGSIZE;
  39                 goto fail2;
  40         }
  41
  42         maep->em_max_n_outer_prios =
  43             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
  44
  45         maep->em_max_n_action_prios =
  46             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
  47
  48         maep->em_encap_types_supported = 0;
  49
  50         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
  51                 maep->em_encap_types_supported |=
  52                     (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
  53         }
  54
  55         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
  56                 maep->em_encap_types_supported |=
  57                     (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
  58         }
  59
  60         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
  61                 maep->em_encap_types_supported |=
  62                     (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
  63         }
  64
  65         maep->em_max_nfields =
  66             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
  67
  68         return (0);
  69
  70 fail2:
  71         EFSYS_PROBE(fail2);
  72 fail1:
  73         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  74         return (rc);
  75 }
  76
  77 static  __checkReturn                   efx_rc_t
  78 efx_mae_get_action_rule_caps(
  79         __in                            efx_nic_t *enp,
  80         __in                            unsigned int field_ncaps,
  81         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
  82 {
  83         efx_mcdi_req_t req;
  84         EFX_MCDI_DECLARE_BUF(payload,
  85             MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
  86             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
  87         unsigned int mcdi_field_ncaps;
  88         unsigned int i;
  89         efx_rc_t rc;
  90
  91         if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
  92             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
  93                 rc = EINVAL;
  94                 goto fail1;
  95         }
  96
  97         req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
  98         req.emr_in_buf = payload;
  99         req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
 100         req.emr_out_buf = payload;
 101         req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
 102
 103         efx_mcdi_execute(enp, &req);
 104
 105         if (req.emr_rc != 0) {
 106                 rc = req.emr_rc;
 107                 goto fail2;
 108         }
 109
 110         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 111
 112         if (req.emr_out_length_used <
 113             MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 114                 rc = EMSGSIZE;
 115                 goto fail3;
 116         }
 117
 118         if (mcdi_field_ncaps > field_ncaps) {
 119                 rc = EMSGSIZE;
 120                 goto fail4;
 121         }
 122
 123         for (i = 0; i < mcdi_field_ncaps; ++i) {
 124                 uint32_t match_flag;
 125                 uint32_t mask_flag;
 126
 127                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 128                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 129                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 130
 131                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 132                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 133                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 134
 135                 field_caps[i].emfc_match_affects_class =
 136                     (match_flag != 0) ? B_TRUE : B_FALSE;
 137
 138                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 139                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 140                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 141
 142                 field_caps[i].emfc_mask_affects_class =
 143                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 144         }
 145
 146         return (0);
 147
 148 fail4:
 149         EFSYS_PROBE(fail4);
 150 fail3:
 151         EFSYS_PROBE(fail3);
 152 fail2:
 153         EFSYS_PROBE(fail2);
 154 fail1:
 155         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 156         return (rc);
 157 }
 158
 159         __checkReturn                   efx_rc_t
 160 efx_mae_init(
 161         __in                            efx_nic_t *enp)
 162 {
 163         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 164         efx_mae_field_cap_t *ar_fcaps;
 165         size_t ar_fcaps_size;
 166         efx_mae_t *maep;
 167         efx_rc_t rc;
 168
 169         if (encp->enc_mae_supported == B_FALSE) {
 170                 rc = ENOTSUP;
 171                 goto fail1;
 172         }
 173
 174         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
 175         if (maep == NULL) {
 176                 rc = ENOMEM;
 177                 goto fail2;
 178         }
 179
 180         enp->en_maep = maep;
 181
 182         rc = efx_mae_get_capabilities(enp);
 183         if (rc != 0)
 184                 goto fail3;
 185
 186         ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
 187         EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
 188         if (ar_fcaps == NULL) {
 189                 rc = ENOMEM;
 190                 goto fail4;
 191         }
 192
 193         maep->em_action_rule_field_caps_size = ar_fcaps_size;
 194         maep->em_action_rule_field_caps = ar_fcaps;
 195
 196         rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
 197         if (rc != 0)
 198                 goto fail5;
 199
 200         return (0);
 201
 202 fail5:
 203         EFSYS_PROBE(fail5);
 204         EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
 205 fail4:
 206         EFSYS_PROBE(fail4);
 207 fail3:
 208         EFSYS_PROBE(fail3);
 209         EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
 210         enp->en_maep = NULL;
 211 fail2:
 212         EFSYS_PROBE(fail2);
 213 fail1:
 214         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 215         return (rc);
 216 }
 217
 218                                         void
 219 efx_mae_fini(
 220         __in                            efx_nic_t *enp)
 221 {
 222         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 223         efx_mae_t *maep = enp->en_maep;
 224
 225         if (encp->enc_mae_supported == B_FALSE)
 226                 return;
 227
 228         EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
 229             maep->em_action_rule_field_caps);
 230         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
 231         enp->en_maep = NULL;
 232 }
 233
 234         __checkReturn                   efx_rc_t
 235 efx_mae_get_limits(
 236         __in                            efx_nic_t *enp,
 237         __out                           efx_mae_limits_t *emlp)
 238 {
 239         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 240         struct efx_mae_s *maep = enp->en_maep;
 241         efx_rc_t rc;
 242
 243         if (encp->enc_mae_supported == B_FALSE) {
 244                 rc = ENOTSUP;
 245                 goto fail1;
 246         }
 247
 248         emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
 249         emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
 250         emlp->eml_encap_types_supported = maep->em_encap_types_supported;
 251
 252         return (0);
 253
 254 fail1:
 255         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 256         return (rc);
 257 }
 258
 259         __checkReturn                   efx_rc_t
 260 efx_mae_match_spec_init(
 261         __in                            efx_nic_t *enp,
 262         __in                            efx_mae_rule_type_t type,
 263         __in                            uint32_t prio,
 264         __out                           efx_mae_match_spec_t **specp)
 265 {
 266         efx_mae_match_spec_t *spec;
 267         efx_rc_t rc;
 268
 269         switch (type) {
 270         case EFX_MAE_RULE_OUTER:
 271                 break;
 272         case EFX_MAE_RULE_ACTION:
 273                 break;
 274         default:
 275                 rc = ENOTSUP;
 276                 goto fail1;
 277         }
 278
 279         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 280         if (spec == NULL) {
 281                 rc = ENOMEM;
 282                 goto fail2;
 283         }
 284
 285         spec->emms_type = type;
 286         spec->emms_prio = prio;
 287
 288         *specp = spec;
 289
 290         return (0);
 291
 292 fail2:
 293         EFSYS_PROBE(fail2);
 294 fail1:
 295         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 296         return (rc);
 297 }
 298
 299                                         void
 300 efx_mae_match_spec_fini(
 301         __in                            efx_nic_t *enp,
 302         __in                            efx_mae_match_spec_t *spec)
 303 {
 304         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 305 }
 306
 307 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
 308 typedef enum efx_mae_field_cap_id_e {
 309         EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
 310         EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
 311         EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
 312         EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
 313         EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
 314         EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
 315         EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
 316         EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
 317         EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
 318         EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
 319         EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
 320         EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
 321         EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
 322         EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
 323         EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
 324         EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
 325         EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
 326         EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
 327         EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
 328         EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
 329         EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
 330         EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
 331         EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
 332         EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
 333         EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
 334         EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
 335         EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
 336         EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
 337         EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
 338         EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
 339         EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
 340         EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
 341         EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
 342         EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
 343         EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
 344
 345         EFX_MAE_FIELD_CAP_NIDS
 346 } efx_mae_field_cap_id_t;
 347
 348 typedef enum efx_mae_field_endianness_e {
 349         EFX_MAE_FIELD_LE = 0,
 350         EFX_MAE_FIELD_BE,
 351
 352         EFX_MAE_FIELD_ENDIANNESS_NTYPES
 353 } efx_mae_field_endianness_t;
 354
 355 /*
 356  * The following structure is a means to describe an MAE field.
 357  * The information in it is meant to be used internally by
 358  * APIs for addressing a given field in a mask-value pairs
 359  * structure and for validation purposes.
 360  */
 361 typedef struct efx_mae_mv_desc_s {
 362         efx_mae_field_cap_id_t          emmd_field_cap_id;
 363
 364         size_t                          emmd_value_size;
 365         size_t                          emmd_value_offset;
 366         size_t                          emmd_mask_size;
 367         size_t                          emmd_mask_offset;
 368
 369         efx_mae_field_endianness_t      emmd_endianness;
 370 } efx_mae_mv_desc_t;
 371
 372 /* Indices to this array are provided by efx_mae_field_id_t */
 373 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
 374 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 375         [EFX_MAE_FIELD_##_name] =                                       \
 376         {                                                               \
 377                 EFX_MAE_FIELD_ID_##_name,                               \
 378                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN,               \
 379                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,              \
 380                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,          \
 381                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,         \
 382                 _endianness                                             \
 383         }
 384
 385         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 386         EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 387         EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 388         EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 389         EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 390         EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 391         EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 392         EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 393         EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
 394         EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
 395         EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
 396         EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
 397         EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
 398         EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
 399         EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
 400         EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
 401         EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
 402         EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
 403         EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
 404
 405 #undef EFX_MAE_MV_DESC
 406 };
 407
 408 /* Indices to this array are provided by efx_mae_field_id_t */
 409 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 410 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 411         [EFX_MAE_FIELD_##_name] =                                       \
 412         {                                                               \
 413                 EFX_MAE_FIELD_ID_##_name,                               \
 414                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 415                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 416                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 417                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 418                 _endianness                                             \
 419         }
 420
 421         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 422         EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 423         EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 424         EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 425         EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 426         EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 427         EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 428         EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 429         EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
 430         EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
 431         EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
 432         EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
 433         EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
 434         EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
 435         EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
 436         EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
 437         EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
 438
 439 #undef EFX_MAE_MV_DESC
 440 };
 441
 442         __checkReturn                   efx_rc_t
 443 efx_mae_mport_by_phy_port(
 444         __in                            uint32_t phy_port,
 445         __out                           efx_mport_sel_t *mportp)
 446 {
 447         efx_dword_t dword;
 448         efx_rc_t rc;
 449
 450         if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
 451                 rc = EINVAL;
 452                 goto fail1;
 453         }
 454
 455         EFX_POPULATE_DWORD_2(dword,
 456             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
 457             MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
 458
 459         memset(mportp, 0, sizeof (*mportp));
 460         mportp->sel = dword.ed_u32[0];
 461
 462         return (0);
 463
 464 fail1:
 465         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 466         return (rc);
 467 }
 468
 469         __checkReturn                   efx_rc_t
 470 efx_mae_mport_by_pcie_function(
 471         __in                            uint32_t pf,
 472         __in                            uint32_t vf,
 473         __out                           efx_mport_sel_t *mportp)
 474 {
 475         efx_dword_t dword;
 476         efx_rc_t rc;
 477
 478         EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
 479             MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
 480
 481         if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
 482                 rc = EINVAL;
 483                 goto fail1;
 484         }
 485
 486         if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
 487                 rc = EINVAL;
 488                 goto fail2;
 489         }
 490
 491         EFX_POPULATE_DWORD_3(dword,
 492             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
 493             MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
 494             MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
 495
 496         memset(mportp, 0, sizeof (*mportp));
 497         mportp->sel = dword.ed_u32[0];
 498
 499         return (0);
 500
 501 fail2:
 502         EFSYS_PROBE(fail2);
 503 fail1:
 504         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 505         return (rc);
 506 }
 507
 508         __checkReturn                   efx_rc_t
 509 efx_mae_match_spec_field_set(
 510         __in                            efx_mae_match_spec_t *spec,
 511         __in                            efx_mae_field_id_t field_id,
 512         __in                            size_t value_size,
 513         __in_bcount(value_size)         const uint8_t *value,
 514         __in                            size_t mask_size,
 515         __in_bcount(mask_size)          const uint8_t *mask)
 516 {
 517         const efx_mae_mv_desc_t *descp;
 518         uint8_t *mvp;
 519         efx_rc_t rc;
 520
 521         if (field_id >= EFX_MAE_FIELD_NIDS) {
 522                 rc = EINVAL;
 523                 goto fail1;
 524         }
 525
 526         switch (spec->emms_type) {
 527         case EFX_MAE_RULE_OUTER:
 528                 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
 529                 mvp = spec->emms_mask_value_pairs.outer;
 530                 break;
 531         case EFX_MAE_RULE_ACTION:
 532                 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
 533                 mvp = spec->emms_mask_value_pairs.action;
 534                 break;
 535         default:
 536                 rc = ENOTSUP;
 537                 goto fail2;
 538         }
 539
 540         if (value_size != descp->emmd_value_size) {
 541                 rc = EINVAL;
 542                 goto fail3;
 543         }
 544
 545         if (mask_size != descp->emmd_mask_size) {
 546                 rc = EINVAL;
 547                 goto fail4;
 548         }
 549
 550         if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
 551                 /*
 552                  * The mask/value are in network (big endian) order.
 553                  * The MCDI request field is also big endian.
 554                  */
 555                 memcpy(mvp + descp->emmd_value_offset, value, value_size);
 556                 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
 557         } else {
 558                 efx_dword_t dword;
 559
 560                 /*
 561                  * The mask/value are in host byte order.
 562                  * The MCDI request field is little endian.
 563                  */
 564                 switch (value_size) {
 565                 case 4:
 566                         EFX_POPULATE_DWORD_1(dword,
 567                             EFX_DWORD_0, *(const uint32_t *)value);
 568
 569                         memcpy(mvp + descp->emmd_value_offset,
 570                             &dword, sizeof (dword));
 571                         break;
 572                 default:
 573                         EFSYS_ASSERT(B_FALSE);
 574                 }
 575
 576                 switch (mask_size) {
 577                 case 4:
 578                         EFX_POPULATE_DWORD_1(dword,
 579                             EFX_DWORD_0, *(const uint32_t *)mask);
 580
 581                         memcpy(mvp + descp->emmd_mask_offset,
 582                             &dword, sizeof (dword));
 583                         break;
 584                 default:
 585                         EFSYS_ASSERT(B_FALSE);
 586                 }
 587         }
 588
 589         return (0);
 590
 591 fail4:
 592         EFSYS_PROBE(fail4);
 593 fail3:
 594         EFSYS_PROBE(fail3);
 595 fail2:
 596         EFSYS_PROBE(fail2);
 597 fail1:
 598         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 599         return (rc);
 600 }
 601
 602         __checkReturn                   efx_rc_t
 603 efx_mae_match_spec_mport_set(
 604         __in                            efx_mae_match_spec_t *spec,
 605         __in                            const efx_mport_sel_t *valuep,
 606         __in_opt                        const efx_mport_sel_t *maskp)
 607 {
 608         uint32_t full_mask = UINT32_MAX;
 609         const uint8_t *vp;
 610         const uint8_t *mp;
 611         efx_rc_t rc;
 612
 613         if (valuep == NULL) {
 614                 rc = EINVAL;
 615                 goto fail1;
 616         }
 617
 618         vp = (const uint8_t *)&valuep->sel;
 619         if (maskp != NULL)
 620                 mp = (const uint8_t *)&maskp->sel;
 621         else
 622                 mp = (const uint8_t *)&full_mask;
 623
 624         rc = efx_mae_match_spec_field_set(spec,
 625             EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
 626             sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
 627         if (rc != 0)
 628                 goto fail2;
 629
 630         return (0);
 631
 632 fail2:
 633         EFSYS_PROBE(fail2);
 634 fail1:
 635         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 636         return (rc);
 637 }
 638
 639 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)              \
 640             ((_mask)[(_bit) / (_mask_page_nbits)] &                     \
 641                     (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
 642
 643 static inline                           boolean_t
 644 efx_mask_is_prefix(
 645         __in                            size_t mask_nbytes,
 646         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 647 {
 648         boolean_t prev_bit_is_set = B_TRUE;
 649         unsigned int i;
 650
 651         for (i = 0; i < 8 * mask_nbytes; ++i) {
 652                 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
 653
 654                 if (!prev_bit_is_set && bit_is_set)
 655                         return B_FALSE;
 656
 657                 prev_bit_is_set = bit_is_set;
 658         }
 659
 660         return B_TRUE;
 661 }
 662
 663 static inline                           boolean_t
 664 efx_mask_is_all_ones(
 665         __in                            size_t mask_nbytes,
 666         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 667 {
 668         unsigned int i;
 669         uint8_t t = ~0;
 670
 671         for (i = 0; i < mask_nbytes; ++i)
 672                 t &= maskp[i];
 673
 674         return (t == (uint8_t)(~0));
 675 }
 676
 677 static inline                           boolean_t
 678 efx_mask_is_all_zeros(
 679         __in                            size_t mask_nbytes,
 680         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 681 {
 682         unsigned int i;
 683         uint8_t t = 0;
 684
 685         for (i = 0; i < mask_nbytes; ++i)
 686                 t |= maskp[i];
 687
 688         return (t == 0);
 689 }
 690
 691         __checkReturn                   boolean_t
 692 efx_mae_match_spec_is_valid(
 693         __in                            efx_nic_t *enp,
 694         __in                            const efx_mae_match_spec_t *spec)
 695 {
 696         efx_mae_t *maep = enp->en_maep;
 697         unsigned int field_ncaps = maep->em_max_nfields;
 698         const efx_mae_field_cap_t *field_caps;
 699         const efx_mae_mv_desc_t *desc_setp;
 700         unsigned int desc_set_nentries;
 701         boolean_t is_valid = B_TRUE;
 702         efx_mae_field_id_t field_id;
 703         const uint8_t *mvp;
 704
 705         switch (spec->emms_type) {
 706         case EFX_MAE_RULE_ACTION:
 707                 field_caps = maep->em_action_rule_field_caps;
 708                 desc_setp = __efx_mae_action_rule_mv_desc_set;
 709                 desc_set_nentries =
 710                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 711                 mvp = spec->emms_mask_value_pairs.action;
 712                 break;
 713         default:
 714                 return (B_FALSE);
 715         }
 716
 717         if (field_caps == NULL)
 718                 return (B_FALSE);
 719
 720         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
 721                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
 722                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
 723                 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
 724                 size_t m_size = descp->emmd_mask_size;
 725
 726                 if (m_size == 0)
 727                         continue; /* Skip array gap */
 728
 729                 if (field_cap_id >= field_ncaps)
 730                         break;
 731
 732                 switch (field_caps[field_cap_id].emfc_support) {
 733                 case MAE_FIELD_SUPPORTED_MATCH_MASK:
 734                         is_valid = B_TRUE;
 735                         break;
 736                 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
 737                         is_valid = efx_mask_is_prefix(m_size, m_buf);
 738                         break;
 739                 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
 740                         is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
 741                             efx_mask_is_all_zeros(m_size, m_buf));
 742                         break;
 743                 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
 744                         is_valid = efx_mask_is_all_ones(m_size, m_buf);
 745                         break;
 746                 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
 747                 case MAE_FIELD_UNSUPPORTED:
 748                 default:
 749                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
 750                         break;
 751                 }
 752
 753                 if (is_valid == B_FALSE)
 754                         break;
 755         }
 756
 757         return (is_valid);
 758 }
 759
 760         __checkReturn                   efx_rc_t
 761 efx_mae_action_set_spec_init(
 762         __in                            efx_nic_t *enp,
 763         __out                           efx_mae_actions_t **specp)
 764 {
 765         efx_mae_actions_t *spec;
 766         efx_rc_t rc;
 767
 768         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 769         if (spec == NULL) {
 770                 rc = ENOMEM;
 771                 goto fail1;
 772         }
 773
 774         *specp = spec;
 775
 776         return (0);
 777
 778 fail1:
 779         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 780         return (rc);
 781 }
 782
 783                                         void
 784 efx_mae_action_set_spec_fini(
 785         __in                            efx_nic_t *enp,
 786         __in                            efx_mae_actions_t *spec)
 787 {
 788         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 789 }
 790
 791 static  __checkReturn                   efx_rc_t
 792 efx_mae_action_set_add_vlan_pop(
 793         __in                            efx_mae_actions_t *spec,
 794         __in                            size_t arg_size,
 795         __in_bcount(arg_size)           const uint8_t *arg)
 796 {
 797         efx_rc_t rc;
 798
 799         if (arg_size != 0) {
 800                 rc = EINVAL;
 801                 goto fail1;
 802         }
 803
 804         if (arg != NULL) {
 805                 rc = EINVAL;
 806                 goto fail2;
 807         }
 808
 809         if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
 810                 rc = ENOTSUP;
 811                 goto fail3;
 812         }
 813
 814         ++spec->ema_n_vlan_tags_to_pop;
 815
 816         return (0);
 817
 818 fail3:
 819         EFSYS_PROBE(fail3);
 820 fail2:
 821         EFSYS_PROBE(fail2);
 822 fail1:
 823         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 824         return (rc);
 825 }
 826
 827 static  __checkReturn                   efx_rc_t
 828 efx_mae_action_set_add_vlan_push(
 829         __in                            efx_mae_actions_t *spec,
 830         __in                            size_t arg_size,
 831         __in_bcount(arg_size)           const uint8_t *arg)
 832 {
 833         unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
 834         efx_rc_t rc;
 835
 836         if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
 837                 rc = EINVAL;
 838                 goto fail1;
 839         }
 840
 841         if (arg == NULL) {
 842                 rc = EINVAL;
 843                 goto fail2;
 844         }
 845
 846         if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
 847                 rc = ENOTSUP;
 848                 goto fail3;
 849         }
 850
 851         memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
 852         ++(spec->ema_n_vlan_tags_to_push);
 853
 854         return (0);
 855
 856 fail3:
 857         EFSYS_PROBE(fail3);
 858 fail2:
 859         EFSYS_PROBE(fail2);
 860 fail1:
 861         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 862         return (rc);
 863 }
 864
 865 static  __checkReturn                   efx_rc_t
 866 efx_mae_action_set_add_flag(
 867         __in                            efx_mae_actions_t *spec,
 868         __in                            size_t arg_size,
 869         __in_bcount(arg_size)           const uint8_t *arg)
 870 {
 871         efx_rc_t rc;
 872
 873         _NOTE(ARGUNUSED(spec))
 874
 875         if (arg_size != 0) {
 876                 rc = EINVAL;
 877                 goto fail1;
 878         }
 879
 880         if (arg != NULL) {
 881                 rc = EINVAL;
 882                 goto fail2;
 883         }
 884
 885         /* This action does not have any arguments, so do nothing here. */
 886
 887         return (0);
 888
 889 fail2:
 890         EFSYS_PROBE(fail2);
 891 fail1:
 892         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 893         return (rc);
 894 }
 895
 896 static  __checkReturn                   efx_rc_t
 897 efx_mae_action_set_add_mark(
 898         __in                            efx_mae_actions_t *spec,
 899         __in                            size_t arg_size,
 900         __in_bcount(arg_size)           const uint8_t *arg)
 901 {
 902         efx_rc_t rc;
 903
 904         if (arg_size != sizeof (spec->ema_mark_value)) {
 905                 rc = EINVAL;
 906                 goto fail1;
 907         }
 908
 909         if (arg == NULL) {
 910                 rc = EINVAL;
 911                 goto fail2;
 912         }
 913
 914         memcpy(&spec->ema_mark_value, arg, arg_size);
 915
 916         return (0);
 917
 918 fail2:
 919         EFSYS_PROBE(fail2);
 920 fail1:
 921         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 922         return (rc);
 923 }
 924
 925 static  __checkReturn                   efx_rc_t
 926 efx_mae_action_set_add_deliver(
 927         __in                            efx_mae_actions_t *spec,
 928         __in                            size_t arg_size,
 929         __in_bcount(arg_size)           const uint8_t *arg)
 930 {
 931         efx_rc_t rc;
 932
 933         if (arg_size != sizeof (spec->ema_deliver_mport)) {
 934                 rc = EINVAL;
 935                 goto fail1;
 936         }
 937
 938         if (arg == NULL) {
 939                 rc = EINVAL;
 940                 goto fail2;
 941         }
 942
 943         memcpy(&spec->ema_deliver_mport, arg, arg_size);
 944
 945         return (0);
 946
 947 fail2:
 948         EFSYS_PROBE(fail2);
 949 fail1:
 950         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 951         return (rc);
 952 }
 953
 954 typedef struct efx_mae_action_desc_s {
 955         /* Action specific handler */
 956         efx_rc_t        (*emad_add)(efx_mae_actions_t *,
 957                                     size_t, const uint8_t *);
 958 } efx_mae_action_desc_t;
 959
 960 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
 961         [EFX_MAE_ACTION_VLAN_POP] = {
 962                 .emad_add = efx_mae_action_set_add_vlan_pop
 963         },
 964         [EFX_MAE_ACTION_VLAN_PUSH] = {
 965                 .emad_add = efx_mae_action_set_add_vlan_push
 966         },
 967         [EFX_MAE_ACTION_FLAG] = {
 968                 .emad_add = efx_mae_action_set_add_flag
 969         },
 970         [EFX_MAE_ACTION_MARK] = {
 971                 .emad_add = efx_mae_action_set_add_mark
 972         },
 973         [EFX_MAE_ACTION_DELIVER] = {
 974                 .emad_add = efx_mae_action_set_add_deliver
 975         }
 976 };
 977
 978 static const uint32_t efx_mae_action_ordered_map =
 979         (1U << EFX_MAE_ACTION_VLAN_POP) |
 980         (1U << EFX_MAE_ACTION_VLAN_PUSH) |
 981         (1U << EFX_MAE_ACTION_FLAG) |
 982         (1U << EFX_MAE_ACTION_MARK) |
 983         (1U << EFX_MAE_ACTION_DELIVER);
 984
 985 /*
 986  * These actions must not be added after DELIVER, but
 987  * they can have any place among the rest of
 988  * strictly ordered actions.
 989  */
 990 static const uint32_t efx_mae_action_nonstrict_map =
 991         (1U << EFX_MAE_ACTION_FLAG) |
 992         (1U << EFX_MAE_ACTION_MARK);
 993
 994 static const uint32_t efx_mae_action_repeat_map =
 995         (1U << EFX_MAE_ACTION_VLAN_POP) |
 996         (1U << EFX_MAE_ACTION_VLAN_PUSH);
 997
 998 /*
 999  * Add an action to an action set.
1000  *
1001  * This has to be invoked in the desired action order.
1002  * An out-of-order action request will be turned down.
1003  */
1004 static  __checkReturn                   efx_rc_t
1005 efx_mae_action_set_spec_populate(
1006         __in                            efx_mae_actions_t *spec,
1007         __in                            efx_mae_action_t type,
1008         __in                            size_t arg_size,
1009         __in_bcount(arg_size)           const uint8_t *arg)
1010 {
1011         uint32_t action_mask;
1012         efx_rc_t rc;
1013
1014         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1015             (sizeof (efx_mae_action_ordered_map) * 8));
1016         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1017             (sizeof (efx_mae_action_repeat_map) * 8));
1018
1019         EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1020         EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1021         EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1022
1023         if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1024                 rc = EINVAL;
1025                 goto fail1;
1026         }
1027
1028         action_mask = (1U << type);
1029
1030         if ((spec->ema_actions & action_mask) != 0) {
1031                 /* The action set already contains this action. */
1032                 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1033                         /* Cannot add another non-repeatable action. */
1034                         rc = ENOTSUP;
1035                         goto fail2;
1036                 }
1037         }
1038
1039         if ((efx_mae_action_ordered_map & action_mask) != 0) {
1040                 uint32_t strict_ordered_map =
1041                     efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1042                 uint32_t later_actions_mask =
1043                     strict_ordered_map & ~(action_mask | (action_mask - 1));
1044
1045                 if ((spec->ema_actions & later_actions_mask) != 0) {
1046                         /* Cannot add an action after later ordered actions. */
1047                         rc = ENOTSUP;
1048                         goto fail3;
1049                 }
1050         }
1051
1052         if (efx_mae_actions[type].emad_add != NULL) {
1053                 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1054                 if (rc != 0)
1055                         goto fail4;
1056         }
1057
1058         spec->ema_actions |= action_mask;
1059
1060         return (0);
1061
1062 fail4:
1063         EFSYS_PROBE(fail4);
1064 fail3:
1065         EFSYS_PROBE(fail3);
1066 fail2:
1067         EFSYS_PROBE(fail2);
1068 fail1:
1069         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1070         return (rc);
1071 }
1072
1073         __checkReturn                   efx_rc_t
1074 efx_mae_action_set_populate_vlan_pop(
1075         __in                            efx_mae_actions_t *spec)
1076 {
1077         return (efx_mae_action_set_spec_populate(spec,
1078             EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1079 }
1080
1081         __checkReturn                   efx_rc_t
1082 efx_mae_action_set_populate_vlan_push(
1083         __in                            efx_mae_actions_t *spec,
1084         __in                            uint16_t tpid_be,
1085         __in                            uint16_t tci_be)
1086 {
1087         efx_mae_action_vlan_push_t action;
1088         const uint8_t *arg = (const uint8_t *)&action;
1089
1090         action.emavp_tpid_be = tpid_be;
1091         action.emavp_tci_be = tci_be;
1092
1093         return (efx_mae_action_set_spec_populate(spec,
1094             EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1095 }
1096
1097         __checkReturn                   efx_rc_t
1098 efx_mae_action_set_populate_flag(
1099         __in                            efx_mae_actions_t *spec)
1100 {
1101         return (efx_mae_action_set_spec_populate(spec,
1102             EFX_MAE_ACTION_FLAG, 0, NULL));
1103 }
1104
1105         __checkReturn                   efx_rc_t
1106 efx_mae_action_set_populate_mark(
1107         __in                            efx_mae_actions_t *spec,
1108         __in                            uint32_t mark_value)
1109 {
1110         const uint8_t *arg = (const uint8_t *)&mark_value;
1111
1112         return (efx_mae_action_set_spec_populate(spec,
1113             EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1114 }
1115
1116         __checkReturn                   efx_rc_t
1117 efx_mae_action_set_populate_deliver(
1118         __in                            efx_mae_actions_t *spec,
1119         __in                            const efx_mport_sel_t *mportp)
1120 {
1121         const uint8_t *arg;
1122         efx_rc_t rc;
1123
1124         if (mportp == NULL) {
1125                 rc = EINVAL;
1126                 goto fail1;
1127         }
1128
1129         arg = (const uint8_t *)&mportp->sel;
1130
1131         return (efx_mae_action_set_spec_populate(spec,
1132             EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1133
1134 fail1:
1135         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1136         return (rc);
1137 }
1138
1139         __checkReturn                   efx_rc_t
1140 efx_mae_action_set_populate_drop(
1141         __in                            efx_mae_actions_t *spec)
1142 {
1143         efx_mport_sel_t mport;
1144         const uint8_t *arg;
1145         efx_dword_t dword;
1146
1147         EFX_POPULATE_DWORD_1(dword,
1148             MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1149
1150         mport.sel = dword.ed_u32[0];
1151
1152         arg = (const uint8_t *)&mport.sel;
1153
1154         return (efx_mae_action_set_spec_populate(spec,
1155             EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1156 }
1157
1158         __checkReturn                   boolean_t
1159 efx_mae_action_set_specs_equal(
1160         __in                            const efx_mae_actions_t *left,
1161         __in                            const efx_mae_actions_t *right)
1162 {
1163         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1164 }
1165
1166         __checkReturn                   efx_rc_t
1167 efx_mae_match_specs_class_cmp(
1168         __in                            efx_nic_t *enp,
1169         __in                            const efx_mae_match_spec_t *left,
1170         __in                            const efx_mae_match_spec_t *right,
1171         __out                           boolean_t *have_same_classp)
1172 {
1173         efx_mae_t *maep = enp->en_maep;
1174         unsigned int field_ncaps = maep->em_max_nfields;
1175         const efx_mae_field_cap_t *field_caps;
1176         const efx_mae_mv_desc_t *desc_setp;
1177         unsigned int desc_set_nentries;
1178         boolean_t have_same_class = B_TRUE;
1179         efx_mae_field_id_t field_id;
1180         const uint8_t *mvpl;
1181         const uint8_t *mvpr;
1182         efx_rc_t rc;
1183
1184         switch (left->emms_type) {
1185         case EFX_MAE_RULE_ACTION:
1186                 field_caps = maep->em_action_rule_field_caps;
1187                 desc_setp = __efx_mae_action_rule_mv_desc_set;
1188                 desc_set_nentries =
1189                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1190                 mvpl = left->emms_mask_value_pairs.action;
1191                 mvpr = right->emms_mask_value_pairs.action;
1192                 break;
1193         default:
1194                 rc = ENOTSUP;
1195                 goto fail1;
1196         }
1197
1198         if (field_caps == NULL) {
1199                 rc = EAGAIN;
1200                 goto fail2;
1201         }
1202
1203         if (left->emms_type != right->emms_type ||
1204             left->emms_prio != right->emms_prio) {
1205                 /*
1206                  * Rules of different types can never map to the same class.
1207                  *
1208                  * The FW can support some set of match criteria for one
1209                  * priority and not support the very same set for
1210                  * another priority. Thus, two rules which have
1211                  * different priorities can never map to
1212                  * the same class.
1213                  */
1214                 *have_same_classp = B_FALSE;
1215                 return (0);
1216         }
1217
1218         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
1219                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1220                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1221
1222                 if (descp->emmd_mask_size == 0)
1223                         continue; /* Skip array gap */
1224
1225                 if (field_cap_id >= field_ncaps)
1226                         break;
1227
1228                 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1229                         const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1230                         const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1231                         size_t mask_size = descp->emmd_mask_size;
1232
1233                         if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1234                                 have_same_class = B_FALSE;
1235                                 break;
1236                         }
1237                 }
1238
1239                 if (field_caps[field_cap_id].emfc_match_affects_class) {
1240                         const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1241                         const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1242                         size_t value_size = descp->emmd_value_size;
1243
1244                         if (memcmp(lvalp, rvalp, value_size) != 0) {
1245                                 have_same_class = B_FALSE;
1246                                 break;
1247                         }
1248                 }
1249         }
1250
1251         *have_same_classp = have_same_class;
1252
1253         return (0);
1254
1255 fail2:
1256         EFSYS_PROBE(fail2);
1257 fail1:
1258         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1259         return (rc);
1260 }
1261
1262         __checkReturn                   efx_rc_t
1263 efx_mae_action_set_alloc(
1264         __in                            efx_nic_t *enp,
1265         __in                            const efx_mae_actions_t *spec,
1266         __out                           efx_mae_aset_id_t *aset_idp)
1267 {
1268         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1269         efx_mcdi_req_t req;
1270         EFX_MCDI_DECLARE_BUF(payload,
1271             MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1272             MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1273         efx_mae_aset_id_t aset_id;
1274         efx_rc_t rc;
1275
1276         if (encp->enc_mae_supported == B_FALSE) {
1277                 rc = ENOTSUP;
1278                 goto fail1;
1279         }
1280
1281         req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1282         req.emr_in_buf = payload;
1283         req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1284         req.emr_out_buf = payload;
1285         req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1286
1287         /*
1288          * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1289          * corresponding resource types are supported by the implementation.
1290          * Use proper resource ID assignments instead.
1291          */
1292         MCDI_IN_SET_DWORD(req,
1293             MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1294         MCDI_IN_SET_DWORD(req,
1295             MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1296         MCDI_IN_SET_DWORD(req,
1297             MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1298
1299         MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1300             MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1301
1302         if (spec->ema_n_vlan_tags_to_push > 0) {
1303                 unsigned int outer_tag_idx;
1304
1305                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1306                     MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1307                     spec->ema_n_vlan_tags_to_push);
1308
1309                 if (spec->ema_n_vlan_tags_to_push ==
1310                     EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1311                         MCDI_IN_SET_WORD(req,
1312                             MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1313                             spec->ema_vlan_push_descs[0].emavp_tpid_be);
1314                         MCDI_IN_SET_WORD(req,
1315                             MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1316                             spec->ema_vlan_push_descs[0].emavp_tci_be);
1317                 }
1318
1319                 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1320
1321                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1322                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1323                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1324                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1325         }
1326
1327         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1328                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1329                     MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1330         }
1331
1332         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1333                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1334                     MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1335
1336                 MCDI_IN_SET_DWORD(req,
1337                     MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1338         }
1339
1340         MCDI_IN_SET_DWORD(req,
1341             MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1342
1343         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1344             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1345         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1346             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1347
1348         efx_mcdi_execute(enp, &req);
1349
1350         if (req.emr_rc != 0) {
1351                 rc = req.emr_rc;
1352                 goto fail2;
1353         }
1354
1355         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1356                 rc = EMSGSIZE;
1357                 goto fail3;
1358         }
1359
1360         aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1361         if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1362                 rc = ENOENT;
1363                 goto fail4;
1364         }
1365
1366         aset_idp->id = aset_id.id;
1367
1368         return (0);
1369
1370 fail4:
1371         EFSYS_PROBE(fail4);
1372 fail3:
1373         EFSYS_PROBE(fail3);
1374 fail2:
1375         EFSYS_PROBE(fail2);
1376 fail1:
1377         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1378         return (rc);
1379 }
1380
1381         __checkReturn                   efx_rc_t
1382 efx_mae_action_set_free(
1383         __in                            efx_nic_t *enp,
1384         __in                            const efx_mae_aset_id_t *aset_idp)
1385 {
1386         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1387         efx_mcdi_req_t req;
1388         EFX_MCDI_DECLARE_BUF(payload,
1389             MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1390             MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1391         efx_rc_t rc;
1392
1393         if (encp->enc_mae_supported == B_FALSE) {
1394                 rc = ENOTSUP;
1395                 goto fail1;
1396         }
1397
1398         req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1399         req.emr_in_buf = payload;
1400         req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1401         req.emr_out_buf = payload;
1402         req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1403
1404         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1405
1406         efx_mcdi_execute(enp, &req);
1407
1408         if (req.emr_rc != 0) {
1409                 rc = req.emr_rc;
1410                 goto fail2;
1411         }
1412
1413         if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1414             aset_idp->id) {
1415                 /* Firmware failed to free the action set. */
1416                 rc = EAGAIN;
1417                 goto fail3;
1418         }
1419
1420         return (0);
1421
1422 fail3:
1423         EFSYS_PROBE(fail3);
1424 fail2:
1425         EFSYS_PROBE(fail2);
1426 fail1:
1427         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1428         return (rc);
1429 }
1430
1431         __checkReturn                   efx_rc_t
1432 efx_mae_action_rule_insert(
1433         __in                            efx_nic_t *enp,
1434         __in                            const efx_mae_match_spec_t *spec,
1435         __in                            const efx_mae_aset_list_id_t *asl_idp,
1436         __in                            const efx_mae_aset_id_t *as_idp,
1437         __out                           efx_mae_rule_id_t *ar_idp)
1438 {
1439         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1440         efx_mcdi_req_t req;
1441         EFX_MCDI_DECLARE_BUF(payload,
1442             MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1443             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1444         efx_oword_t *rule_response;
1445         efx_mae_rule_id_t ar_id;
1446         size_t offset;
1447         efx_rc_t rc;
1448
1449         EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1450             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1451
1452         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1453             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1454
1455         if (encp->enc_mae_supported == B_FALSE) {
1456                 rc = ENOTSUP;
1457                 goto fail1;
1458         }
1459
1460         if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1461             (asl_idp != NULL && as_idp != NULL) ||
1462             (asl_idp == NULL && as_idp == NULL)) {
1463                 rc = EINVAL;
1464                 goto fail2;
1465         }
1466
1467         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1468         req.emr_in_buf = payload;
1469         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1470         req.emr_out_buf = payload;
1471         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1472
1473         EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1474             MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1475         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1476         rule_response = (efx_oword_t *)(payload + offset);
1477         EFX_POPULATE_OWORD_3(*rule_response,
1478             MAE_ACTION_RULE_RESPONSE_ASL_ID,
1479             (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1480             MAE_ACTION_RULE_RESPONSE_AS_ID,
1481             (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1482             MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1483
1484         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1485
1486         /*
1487          * Mask-value pairs have been stored in the byte order needed for the
1488          * MCDI request and are thus safe to be copied directly to the buffer.
1489          */
1490         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1491             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1492         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1493         memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1494             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1495
1496         efx_mcdi_execute(enp, &req);
1497
1498         if (req.emr_rc != 0) {
1499                 rc = req.emr_rc;
1500                 goto fail3;
1501         }
1502
1503         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1504                 rc = EMSGSIZE;
1505                 goto fail4;
1506         }
1507
1508         ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1509         if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1510                 rc = ENOENT;
1511                 goto fail5;
1512         }
1513
1514         ar_idp->id = ar_id.id;
1515
1516         return (0);
1517
1518 fail5:
1519         EFSYS_PROBE(fail5);
1520 fail4:
1521         EFSYS_PROBE(fail4);
1522 fail3:
1523         EFSYS_PROBE(fail3);
1524 fail2:
1525         EFSYS_PROBE(fail2);
1526 fail1:
1527         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1528         return (rc);
1529 }
1530
1531         __checkReturn                   efx_rc_t
1532 efx_mae_action_rule_remove(
1533         __in                            efx_nic_t *enp,
1534         __in                            const efx_mae_rule_id_t *ar_idp)
1535 {
1536         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1537         efx_mcdi_req_t req;
1538         EFX_MCDI_DECLARE_BUF(payload,
1539             MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1540             MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1541         efx_rc_t rc;
1542
1543         if (encp->enc_mae_supported == B_FALSE) {
1544                 rc = ENOTSUP;
1545                 goto fail1;
1546         }
1547
1548         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1549         req.emr_in_buf = payload;
1550         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1551         req.emr_out_buf = payload;
1552         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1553
1554         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1555
1556         efx_mcdi_execute(enp, &req);
1557
1558         if (req.emr_rc != 0) {
1559                 rc = req.emr_rc;
1560                 goto fail2;
1561         }
1562
1563         if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1564             ar_idp->id) {
1565                 /* Firmware failed to delete the action rule. */
1566                 rc = EAGAIN;
1567                 goto fail3;
1568         }
1569
1570         return (0);
1571
1572 fail3:
1573         EFSYS_PROBE(fail3);
1574 fail2:
1575         EFSYS_PROBE(fail2);
1576 fail1:
1577         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1578         return (rc);
1579 }
1580
1581 #endif /* EFSYS_OPT_MAE */