drivers/common/sfc_efx/base/efx_mae.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_MAE
  12
  13 static  __checkReturn                   efx_rc_t
  14 efx_mae_get_capabilities(
  15         __in                            efx_nic_t *enp)
  16 {
  17         efx_mcdi_req_t req;
  18         EFX_MCDI_DECLARE_BUF(payload,
  19             MC_CMD_MAE_GET_CAPS_IN_LEN,
  20             MC_CMD_MAE_GET_CAPS_OUT_LEN);
  21         struct efx_mae_s *maep = enp->en_maep;
  22         efx_rc_t rc;
  23
  24         req.emr_cmd = MC_CMD_MAE_GET_CAPS;
  25         req.emr_in_buf = payload;
  26         req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
  27         req.emr_out_buf = payload;
  28         req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
  29
  30         efx_mcdi_execute(enp, &req);
  31
  32         if (req.emr_rc != 0) {
  33                 rc = req.emr_rc;
  34                 goto fail1;
  35         }
  36
  37         if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
  38                 rc = EMSGSIZE;
  39                 goto fail2;
  40         }
  41
  42         maep->em_max_n_outer_prios =
  43             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
  44
  45         maep->em_max_n_action_prios =
  46             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
  47
  48         maep->em_encap_types_supported = 0;
  49
  50         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
  51                 maep->em_encap_types_supported |=
  52                     (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
  53         }
  54
  55         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
  56                 maep->em_encap_types_supported |=
  57                     (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
  58         }
  59
  60         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
  61                 maep->em_encap_types_supported |=
  62                     (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
  63         }
  64
  65         maep->em_max_nfields =
  66             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
  67
  68         return (0);
  69
  70 fail2:
  71         EFSYS_PROBE(fail2);
  72 fail1:
  73         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  74         return (rc);
  75 }
  76
  77 static  __checkReturn                   efx_rc_t
  78 efx_mae_get_outer_rule_caps(
  79         __in                            efx_nic_t *enp,
  80         __in                            unsigned int field_ncaps,
  81         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
  82 {
  83         efx_mcdi_req_t req;
  84         EFX_MCDI_DECLARE_BUF(payload,
  85             MC_CMD_MAE_GET_OR_CAPS_IN_LEN,
  86             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2);
  87         unsigned int mcdi_field_ncaps;
  88         unsigned int i;
  89         efx_rc_t rc;
  90
  91         if (MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps) >
  92             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2) {
  93                 rc = EINVAL;
  94                 goto fail1;
  95         }
  96
  97         req.emr_cmd = MC_CMD_MAE_GET_OR_CAPS;
  98         req.emr_in_buf = payload;
  99         req.emr_in_length = MC_CMD_MAE_GET_OR_CAPS_IN_LEN;
 100         req.emr_out_buf = payload;
 101         req.emr_out_length = MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps);
 102
 103         efx_mcdi_execute(enp, &req);
 104
 105         if (req.emr_rc != 0) {
 106                 rc = req.emr_rc;
 107                 goto fail2;
 108         }
 109
 110         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 111
 112         if (req.emr_out_length_used <
 113             MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 114                 rc = EMSGSIZE;
 115                 goto fail3;
 116         }
 117
 118         if (mcdi_field_ncaps > field_ncaps) {
 119                 rc = EMSGSIZE;
 120                 goto fail4;
 121         }
 122
 123         for (i = 0; i < mcdi_field_ncaps; ++i) {
 124                 uint32_t match_flag;
 125                 uint32_t mask_flag;
 126
 127                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 128                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 129                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 130
 131                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 132                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 133                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 134
 135                 field_caps[i].emfc_match_affects_class =
 136                     (match_flag != 0) ? B_TRUE : B_FALSE;
 137
 138                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 139                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 140                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 141
 142                 field_caps[i].emfc_mask_affects_class =
 143                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 144         }
 145
 146         return (0);
 147
 148 fail4:
 149         EFSYS_PROBE(fail4);
 150 fail3:
 151         EFSYS_PROBE(fail3);
 152 fail2:
 153         EFSYS_PROBE(fail2);
 154 fail1:
 155         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 156         return (rc);
 157 }
 158
 159 static  __checkReturn                   efx_rc_t
 160 efx_mae_get_action_rule_caps(
 161         __in                            efx_nic_t *enp,
 162         __in                            unsigned int field_ncaps,
 163         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
 164 {
 165         efx_mcdi_req_t req;
 166         EFX_MCDI_DECLARE_BUF(payload,
 167             MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
 168             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
 169         unsigned int mcdi_field_ncaps;
 170         unsigned int i;
 171         efx_rc_t rc;
 172
 173         if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
 174             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
 175                 rc = EINVAL;
 176                 goto fail1;
 177         }
 178
 179         req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
 180         req.emr_in_buf = payload;
 181         req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
 182         req.emr_out_buf = payload;
 183         req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
 184
 185         efx_mcdi_execute(enp, &req);
 186
 187         if (req.emr_rc != 0) {
 188                 rc = req.emr_rc;
 189                 goto fail2;
 190         }
 191
 192         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 193
 194         if (req.emr_out_length_used <
 195             MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 196                 rc = EMSGSIZE;
 197                 goto fail3;
 198         }
 199
 200         if (mcdi_field_ncaps > field_ncaps) {
 201                 rc = EMSGSIZE;
 202                 goto fail4;
 203         }
 204
 205         for (i = 0; i < mcdi_field_ncaps; ++i) {
 206                 uint32_t match_flag;
 207                 uint32_t mask_flag;
 208
 209                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 210                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 211                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 212
 213                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 214                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 215                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 216
 217                 field_caps[i].emfc_match_affects_class =
 218                     (match_flag != 0) ? B_TRUE : B_FALSE;
 219
 220                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 221                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 222                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 223
 224                 field_caps[i].emfc_mask_affects_class =
 225                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 226         }
 227
 228         return (0);
 229
 230 fail4:
 231         EFSYS_PROBE(fail4);
 232 fail3:
 233         EFSYS_PROBE(fail3);
 234 fail2:
 235         EFSYS_PROBE(fail2);
 236 fail1:
 237         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 238         return (rc);
 239 }
 240
 241         __checkReturn                   efx_rc_t
 242 efx_mae_init(
 243         __in                            efx_nic_t *enp)
 244 {
 245         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 246         efx_mae_field_cap_t *or_fcaps;
 247         size_t or_fcaps_size;
 248         efx_mae_field_cap_t *ar_fcaps;
 249         size_t ar_fcaps_size;
 250         efx_mae_t *maep;
 251         efx_rc_t rc;
 252
 253         if (encp->enc_mae_supported == B_FALSE) {
 254                 rc = ENOTSUP;
 255                 goto fail1;
 256         }
 257
 258         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
 259         if (maep == NULL) {
 260                 rc = ENOMEM;
 261                 goto fail2;
 262         }
 263
 264         enp->en_maep = maep;
 265
 266         rc = efx_mae_get_capabilities(enp);
 267         if (rc != 0)
 268                 goto fail3;
 269
 270         or_fcaps_size = maep->em_max_nfields * sizeof (*or_fcaps);
 271         EFSYS_KMEM_ALLOC(enp->en_esip, or_fcaps_size, or_fcaps);
 272         if (or_fcaps == NULL) {
 273                 rc = ENOMEM;
 274                 goto fail4;
 275         }
 276
 277         maep->em_outer_rule_field_caps_size = or_fcaps_size;
 278         maep->em_outer_rule_field_caps = or_fcaps;
 279
 280         rc = efx_mae_get_outer_rule_caps(enp, maep->em_max_nfields, or_fcaps);
 281         if (rc != 0)
 282                 goto fail5;
 283
 284         ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
 285         EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
 286         if (ar_fcaps == NULL) {
 287                 rc = ENOMEM;
 288                 goto fail6;
 289         }
 290
 291         maep->em_action_rule_field_caps_size = ar_fcaps_size;
 292         maep->em_action_rule_field_caps = ar_fcaps;
 293
 294         rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
 295         if (rc != 0)
 296                 goto fail7;
 297
 298         return (0);
 299
 300 fail7:
 301         EFSYS_PROBE(fail5);
 302         EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
 303 fail6:
 304         EFSYS_PROBE(fail4);
 305 fail5:
 306         EFSYS_PROBE(fail5);
 307         EFSYS_KMEM_FREE(enp->en_esip, or_fcaps_size, or_fcaps);
 308 fail4:
 309         EFSYS_PROBE(fail4);
 310 fail3:
 311         EFSYS_PROBE(fail3);
 312         EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
 313         enp->en_maep = NULL;
 314 fail2:
 315         EFSYS_PROBE(fail2);
 316 fail1:
 317         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 318         return (rc);
 319 }
 320
 321                                         void
 322 efx_mae_fini(
 323         __in                            efx_nic_t *enp)
 324 {
 325         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 326         efx_mae_t *maep = enp->en_maep;
 327
 328         if (encp->enc_mae_supported == B_FALSE)
 329                 return;
 330
 331         EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
 332             maep->em_action_rule_field_caps);
 333         EFSYS_KMEM_FREE(enp->en_esip, maep->em_outer_rule_field_caps_size,
 334             maep->em_outer_rule_field_caps);
 335         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
 336         enp->en_maep = NULL;
 337 }
 338
 339         __checkReturn                   efx_rc_t
 340 efx_mae_get_limits(
 341         __in                            efx_nic_t *enp,
 342         __out                           efx_mae_limits_t *emlp)
 343 {
 344         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 345         struct efx_mae_s *maep = enp->en_maep;
 346         efx_rc_t rc;
 347
 348         if (encp->enc_mae_supported == B_FALSE) {
 349                 rc = ENOTSUP;
 350                 goto fail1;
 351         }
 352
 353         emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
 354         emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
 355         emlp->eml_encap_types_supported = maep->em_encap_types_supported;
 356
 357         return (0);
 358
 359 fail1:
 360         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 361         return (rc);
 362 }
 363
 364         __checkReturn                   efx_rc_t
 365 efx_mae_match_spec_init(
 366         __in                            efx_nic_t *enp,
 367         __in                            efx_mae_rule_type_t type,
 368         __in                            uint32_t prio,
 369         __out                           efx_mae_match_spec_t **specp)
 370 {
 371         efx_mae_match_spec_t *spec;
 372         efx_rc_t rc;
 373
 374         switch (type) {
 375         case EFX_MAE_RULE_OUTER:
 376                 break;
 377         case EFX_MAE_RULE_ACTION:
 378                 break;
 379         default:
 380                 rc = ENOTSUP;
 381                 goto fail1;
 382         }
 383
 384         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 385         if (spec == NULL) {
 386                 rc = ENOMEM;
 387                 goto fail2;
 388         }
 389
 390         spec->emms_type = type;
 391         spec->emms_prio = prio;
 392
 393         *specp = spec;
 394
 395         return (0);
 396
 397 fail2:
 398         EFSYS_PROBE(fail2);
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401         return (rc);
 402 }
 403
 404                                         void
 405 efx_mae_match_spec_fini(
 406         __in                            efx_nic_t *enp,
 407         __in                            efx_mae_match_spec_t *spec)
 408 {
 409         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 410 }
 411
 412 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
 413 typedef enum efx_mae_field_cap_id_e {
 414         EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
 415         EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
 416         EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
 417         EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
 418         EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
 419         EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
 420         EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
 421         EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
 422         EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
 423         EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
 424         EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
 425         EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
 426         EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
 427         EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
 428         EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
 429         EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
 430         EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
 431         EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
 432         EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
 433         EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
 434         EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
 435         EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
 436         EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
 437         EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
 438         EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
 439         EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
 440         EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
 441         EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
 442         EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
 443         EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
 444         EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
 445         EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
 446         EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
 447         EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
 448         EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
 449         EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
 450
 451         EFX_MAE_FIELD_CAP_NIDS
 452 } efx_mae_field_cap_id_t;
 453
 454 typedef enum efx_mae_field_endianness_e {
 455         EFX_MAE_FIELD_LE = 0,
 456         EFX_MAE_FIELD_BE,
 457
 458         EFX_MAE_FIELD_ENDIANNESS_NTYPES
 459 } efx_mae_field_endianness_t;
 460
 461 /*
 462  * The following structure is a means to describe an MAE field.
 463  * The information in it is meant to be used internally by
 464  * APIs for addressing a given field in a mask-value pairs
 465  * structure and for validation purposes.
 466  *
 467  * A field may have an alternative one. This structure
 468  * has additional members to reference the alternative
 469  * field's mask. See efx_mae_match_spec_is_valid().
 470  */
 471 typedef struct efx_mae_mv_desc_s {
 472         efx_mae_field_cap_id_t          emmd_field_cap_id;
 473
 474         size_t                          emmd_value_size;
 475         size_t                          emmd_value_offset;
 476         size_t                          emmd_mask_size;
 477         size_t                          emmd_mask_offset;
 478
 479         /*
 480          * Having the alternative field's mask size set to 0
 481          * means that there's no alternative field specified.
 482          */
 483         size_t                          emmd_alt_mask_size;
 484         size_t                          emmd_alt_mask_offset;
 485
 486         /* Primary field and the alternative one are of the same endianness. */
 487         efx_mae_field_endianness_t      emmd_endianness;
 488 } efx_mae_mv_desc_t;
 489
 490 /* Indices to this array are provided by efx_mae_field_id_t */
 491 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
 492 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 493         [EFX_MAE_FIELD_##_name] =                                       \
 494         {                                                               \
 495                 EFX_MAE_FIELD_ID_##_name,                               \
 496                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN,               \
 497                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,              \
 498                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,          \
 499                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,         \
 500                 0, 0 /* no alternative field */,                        \
 501                 _endianness                                             \
 502         }
 503
 504         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 505         EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 506         EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 507         EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 508         EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 509         EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 510         EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 511         EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 512         EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
 513         EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
 514         EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
 515         EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
 516         EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
 517         EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
 518         EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
 519         EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
 520         EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
 521         EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
 522         EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
 523         EFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),
 524
 525 #undef EFX_MAE_MV_DESC
 526 };
 527
 528 /* Indices to this array are provided by efx_mae_field_id_t */
 529 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 530 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 531         [EFX_MAE_FIELD_##_name] =                                       \
 532         {                                                               \
 533                 EFX_MAE_FIELD_ID_##_name,                               \
 534                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 535                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 536                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 537                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 538                 0, 0 /* no alternative field */,                        \
 539                 _endianness                                             \
 540         }
 541
 542 /* Same as EFX_MAE_MV_DESC(), but also indicates an alternative field. */
 543 #define EFX_MAE_MV_DESC_ALT(_name, _alt_name, _endianness)              \
 544         [EFX_MAE_FIELD_##_name] =                                       \
 545         {                                                               \
 546                 EFX_MAE_FIELD_ID_##_name,                               \
 547                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 548                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 549                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 550                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 551                 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_LEN,             \
 552                 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_OFST,            \
 553                 _endianness                                             \
 554         }
 555
 556         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 557         EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 558         EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 559         EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 560         EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 561         EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 562         EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 563         EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 564         EFX_MAE_MV_DESC_ALT(ENC_SRC_IP4_BE, ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
 565         EFX_MAE_MV_DESC_ALT(ENC_DST_IP4_BE, ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
 566         EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
 567         EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
 568         EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
 569         EFX_MAE_MV_DESC_ALT(ENC_SRC_IP6_BE, ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
 570         EFX_MAE_MV_DESC_ALT(ENC_DST_IP6_BE, ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
 571         EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
 572         EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
 573
 574 #undef EFX_MAE_MV_DESC_ALT
 575 #undef EFX_MAE_MV_DESC
 576 };
 577
 578         __checkReturn                   efx_rc_t
 579 efx_mae_mport_by_phy_port(
 580         __in                            uint32_t phy_port,
 581         __out                           efx_mport_sel_t *mportp)
 582 {
 583         efx_dword_t dword;
 584         efx_rc_t rc;
 585
 586         if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
 587                 rc = EINVAL;
 588                 goto fail1;
 589         }
 590
 591         EFX_POPULATE_DWORD_2(dword,
 592             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
 593             MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
 594
 595         memset(mportp, 0, sizeof (*mportp));
 596         /*
 597          * The constructed DWORD is little-endian,
 598          * but the resulting value is meant to be
 599          * passed to MCDIs, where it will undergo
 600          * host-order to little endian conversion.
 601          */
 602         mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
 603
 604         return (0);
 605
 606 fail1:
 607         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 608         return (rc);
 609 }
 610
 611         __checkReturn                   efx_rc_t
 612 efx_mae_mport_by_pcie_function(
 613         __in                            uint32_t pf,
 614         __in                            uint32_t vf,
 615         __out                           efx_mport_sel_t *mportp)
 616 {
 617         efx_dword_t dword;
 618         efx_rc_t rc;
 619
 620         EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
 621             MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
 622
 623         if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
 624                 rc = EINVAL;
 625                 goto fail1;
 626         }
 627
 628         if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
 629                 rc = EINVAL;
 630                 goto fail2;
 631         }
 632
 633         EFX_POPULATE_DWORD_3(dword,
 634             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
 635             MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
 636             MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
 637
 638         memset(mportp, 0, sizeof (*mportp));
 639         /*
 640          * The constructed DWORD is little-endian,
 641          * but the resulting value is meant to be
 642          * passed to MCDIs, where it will undergo
 643          * host-order to little endian conversion.
 644          */
 645         mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
 646
 647         return (0);
 648
 649 fail2:
 650         EFSYS_PROBE(fail2);
 651 fail1:
 652         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 653         return (rc);
 654 }
 655
 656         __checkReturn                   efx_rc_t
 657 efx_mae_match_spec_field_set(
 658         __in                            efx_mae_match_spec_t *spec,
 659         __in                            efx_mae_field_id_t field_id,
 660         __in                            size_t value_size,
 661         __in_bcount(value_size)         const uint8_t *value,
 662         __in                            size_t mask_size,
 663         __in_bcount(mask_size)          const uint8_t *mask)
 664 {
 665         const efx_mae_mv_desc_t *descp;
 666         unsigned int desc_set_nentries;
 667         uint8_t *mvp;
 668         efx_rc_t rc;
 669
 670         switch (spec->emms_type) {
 671         case EFX_MAE_RULE_OUTER:
 672                 desc_set_nentries =
 673                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
 674                 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
 675                 mvp = spec->emms_mask_value_pairs.outer;
 676                 break;
 677         case EFX_MAE_RULE_ACTION:
 678                 desc_set_nentries =
 679                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 680                 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
 681                 mvp = spec->emms_mask_value_pairs.action;
 682                 break;
 683         default:
 684                 rc = ENOTSUP;
 685                 goto fail1;
 686         }
 687
 688         if ((unsigned int)field_id >= desc_set_nentries) {
 689                 rc = EINVAL;
 690                 goto fail2;
 691         }
 692
 693         if (value_size != descp->emmd_value_size) {
 694                 rc = EINVAL;
 695                 goto fail3;
 696         }
 697
 698         if (mask_size != descp->emmd_mask_size) {
 699                 rc = EINVAL;
 700                 goto fail4;
 701         }
 702
 703         if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
 704                 /*
 705                  * The mask/value are in network (big endian) order.
 706                  * The MCDI request field is also big endian.
 707                  */
 708                 memcpy(mvp + descp->emmd_value_offset, value, value_size);
 709                 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
 710         } else {
 711                 efx_dword_t dword;
 712
 713                 /*
 714                  * The mask/value are in host byte order.
 715                  * The MCDI request field is little endian.
 716                  */
 717                 switch (value_size) {
 718                 case 4:
 719                         EFX_POPULATE_DWORD_1(dword,
 720                             EFX_DWORD_0, *(const uint32_t *)value);
 721
 722                         memcpy(mvp + descp->emmd_value_offset,
 723                             &dword, sizeof (dword));
 724                         break;
 725                 default:
 726                         EFSYS_ASSERT(B_FALSE);
 727                 }
 728
 729                 switch (mask_size) {
 730                 case 4:
 731                         EFX_POPULATE_DWORD_1(dword,
 732                             EFX_DWORD_0, *(const uint32_t *)mask);
 733
 734                         memcpy(mvp + descp->emmd_mask_offset,
 735                             &dword, sizeof (dword));
 736                         break;
 737                 default:
 738                         EFSYS_ASSERT(B_FALSE);
 739                 }
 740         }
 741
 742         return (0);
 743
 744 fail4:
 745         EFSYS_PROBE(fail4);
 746 fail3:
 747         EFSYS_PROBE(fail3);
 748 fail2:
 749         EFSYS_PROBE(fail2);
 750 fail1:
 751         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 752         return (rc);
 753 }
 754
 755         __checkReturn                   efx_rc_t
 756 efx_mae_match_spec_mport_set(
 757         __in                            efx_mae_match_spec_t *spec,
 758         __in                            const efx_mport_sel_t *valuep,
 759         __in_opt                        const efx_mport_sel_t *maskp)
 760 {
 761         uint32_t full_mask = UINT32_MAX;
 762         const uint8_t *vp;
 763         const uint8_t *mp;
 764         efx_rc_t rc;
 765
 766         if (valuep == NULL) {
 767                 rc = EINVAL;
 768                 goto fail1;
 769         }
 770
 771         vp = (const uint8_t *)&valuep->sel;
 772         if (maskp != NULL)
 773                 mp = (const uint8_t *)&maskp->sel;
 774         else
 775                 mp = (const uint8_t *)&full_mask;
 776
 777         rc = efx_mae_match_spec_field_set(spec,
 778             EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
 779             sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
 780         if (rc != 0)
 781                 goto fail2;
 782
 783         return (0);
 784
 785 fail2:
 786         EFSYS_PROBE(fail2);
 787 fail1:
 788         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 789         return (rc);
 790 }
 791
 792         __checkReturn                   boolean_t
 793 efx_mae_match_specs_equal(
 794         __in                            const efx_mae_match_spec_t *left,
 795         __in                            const efx_mae_match_spec_t *right)
 796 {
 797         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
 798 }
 799
 800 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)              \
 801             ((_mask)[(_bit) / (_mask_page_nbits)] &                     \
 802                     (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
 803
 804 static                                  boolean_t
 805 efx_mask_is_prefix(
 806         __in                            size_t mask_nbytes,
 807         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 808 {
 809         boolean_t prev_bit_is_set = B_TRUE;
 810         unsigned int i;
 811
 812         for (i = 0; i < 8 * mask_nbytes; ++i) {
 813                 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
 814
 815                 if (!prev_bit_is_set && bit_is_set)
 816                         return B_FALSE;
 817
 818                 prev_bit_is_set = bit_is_set;
 819         }
 820
 821         return B_TRUE;
 822 }
 823
 824 static                                  boolean_t
 825 efx_mask_is_all_ones(
 826         __in                            size_t mask_nbytes,
 827         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 828 {
 829         unsigned int i;
 830         uint8_t t = ~0;
 831
 832         for (i = 0; i < mask_nbytes; ++i)
 833                 t &= maskp[i];
 834
 835         return (t == (uint8_t)(~0));
 836 }
 837
 838 static                                  boolean_t
 839 efx_mask_is_all_zeros(
 840         __in                            size_t mask_nbytes,
 841         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 842 {
 843         unsigned int i;
 844         uint8_t t = 0;
 845
 846         for (i = 0; i < mask_nbytes; ++i)
 847                 t |= maskp[i];
 848
 849         return (t == 0);
 850 }
 851
 852         __checkReturn                   boolean_t
 853 efx_mae_match_spec_is_valid(
 854         __in                            efx_nic_t *enp,
 855         __in                            const efx_mae_match_spec_t *spec)
 856 {
 857         efx_mae_t *maep = enp->en_maep;
 858         unsigned int field_ncaps = maep->em_max_nfields;
 859         const efx_mae_field_cap_t *field_caps;
 860         const efx_mae_mv_desc_t *desc_setp;
 861         unsigned int desc_set_nentries;
 862         boolean_t is_valid = B_TRUE;
 863         efx_mae_field_id_t field_id;
 864         const uint8_t *mvp;
 865
 866         switch (spec->emms_type) {
 867         case EFX_MAE_RULE_OUTER:
 868                 field_caps = maep->em_outer_rule_field_caps;
 869                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
 870                 desc_set_nentries =
 871                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
 872                 mvp = spec->emms_mask_value_pairs.outer;
 873                 break;
 874         case EFX_MAE_RULE_ACTION:
 875                 field_caps = maep->em_action_rule_field_caps;
 876                 desc_setp = __efx_mae_action_rule_mv_desc_set;
 877                 desc_set_nentries =
 878                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 879                 mvp = spec->emms_mask_value_pairs.action;
 880                 break;
 881         default:
 882                 return (B_FALSE);
 883         }
 884
 885         if (field_caps == NULL)
 886                 return (B_FALSE);
 887
 888         for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
 889              ++field_id) {
 890                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
 891                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
 892                 const uint8_t *alt_m_buf = mvp + descp->emmd_alt_mask_offset;
 893                 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
 894                 size_t alt_m_size = descp->emmd_alt_mask_size;
 895                 size_t m_size = descp->emmd_mask_size;
 896
 897                 if (m_size == 0)
 898                         continue; /* Skip array gap */
 899
 900                 if ((unsigned int)field_cap_id >= field_ncaps)
 901                         break;
 902
 903                 switch (field_caps[field_cap_id].emfc_support) {
 904                 case MAE_FIELD_SUPPORTED_MATCH_MASK:
 905                         is_valid = B_TRUE;
 906                         break;
 907                 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
 908                         is_valid = efx_mask_is_prefix(m_size, m_buf);
 909                         break;
 910                 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
 911                         is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
 912                             efx_mask_is_all_zeros(m_size, m_buf));
 913                         break;
 914                 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
 915                         is_valid = efx_mask_is_all_ones(m_size, m_buf);
 916
 917                         if ((is_valid == B_FALSE) && (alt_m_size != 0)) {
 918                                 /*
 919                                  * This field has an alternative one. The FW
 920                                  * reports ALWAYS for both implying that one
 921                                  * of them is required to have all-ones mask.
 922                                  *
 923                                  * The primary field's mask is incorrect; go
 924                                  * on to check that of the alternative field.
 925                                  */
 926                                 is_valid = efx_mask_is_all_ones(alt_m_size,
 927                                                                 alt_m_buf);
 928                         }
 929                         break;
 930                 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
 931                 case MAE_FIELD_UNSUPPORTED:
 932                 default:
 933                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
 934                         break;
 935                 }
 936
 937                 if (is_valid == B_FALSE)
 938                         break;
 939         }
 940
 941         return (is_valid);
 942 }
 943
 944         __checkReturn                   efx_rc_t
 945 efx_mae_action_set_spec_init(
 946         __in                            efx_nic_t *enp,
 947         __out                           efx_mae_actions_t **specp)
 948 {
 949         efx_mae_actions_t *spec;
 950         efx_rc_t rc;
 951
 952         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 953         if (spec == NULL) {
 954                 rc = ENOMEM;
 955                 goto fail1;
 956         }
 957
 958         *specp = spec;
 959
 960         return (0);
 961
 962 fail1:
 963         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 964         return (rc);
 965 }
 966
 967                                         void
 968 efx_mae_action_set_spec_fini(
 969         __in                            efx_nic_t *enp,
 970         __in                            efx_mae_actions_t *spec)
 971 {
 972         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 973 }
 974
 975 static  __checkReturn                   efx_rc_t
 976 efx_mae_action_set_add_vlan_pop(
 977         __in                            efx_mae_actions_t *spec,
 978         __in                            size_t arg_size,
 979         __in_bcount(arg_size)           const uint8_t *arg)
 980 {
 981         efx_rc_t rc;
 982
 983         if (arg_size != 0) {
 984                 rc = EINVAL;
 985                 goto fail1;
 986         }
 987
 988         if (arg != NULL) {
 989                 rc = EINVAL;
 990                 goto fail2;
 991         }
 992
 993         if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
 994                 rc = ENOTSUP;
 995                 goto fail3;
 996         }
 997
 998         ++spec->ema_n_vlan_tags_to_pop;
 999
1000         return (0);
1001
1002 fail3:
1003         EFSYS_PROBE(fail3);
1004 fail2:
1005         EFSYS_PROBE(fail2);
1006 fail1:
1007         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1008         return (rc);
1009 }
1010
1011 static  __checkReturn                   efx_rc_t
1012 efx_mae_action_set_add_vlan_push(
1013         __in                            efx_mae_actions_t *spec,
1014         __in                            size_t arg_size,
1015         __in_bcount(arg_size)           const uint8_t *arg)
1016 {
1017         unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
1018         efx_rc_t rc;
1019
1020         if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
1021                 rc = EINVAL;
1022                 goto fail1;
1023         }
1024
1025         if (arg == NULL) {
1026                 rc = EINVAL;
1027                 goto fail2;
1028         }
1029
1030         if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1031                 rc = ENOTSUP;
1032                 goto fail3;
1033         }
1034
1035         memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
1036         ++(spec->ema_n_vlan_tags_to_push);
1037
1038         return (0);
1039
1040 fail3:
1041         EFSYS_PROBE(fail3);
1042 fail2:
1043         EFSYS_PROBE(fail2);
1044 fail1:
1045         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1046         return (rc);
1047 }
1048
1049 static  __checkReturn                   efx_rc_t
1050 efx_mae_action_set_add_flag(
1051         __in                            efx_mae_actions_t *spec,
1052         __in                            size_t arg_size,
1053         __in_bcount(arg_size)           const uint8_t *arg)
1054 {
1055         efx_rc_t rc;
1056
1057         _NOTE(ARGUNUSED(spec))
1058
1059         if (arg_size != 0) {
1060                 rc = EINVAL;
1061                 goto fail1;
1062         }
1063
1064         if (arg != NULL) {
1065                 rc = EINVAL;
1066                 goto fail2;
1067         }
1068
1069         /* This action does not have any arguments, so do nothing here. */
1070
1071         return (0);
1072
1073 fail2:
1074         EFSYS_PROBE(fail2);
1075 fail1:
1076         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1077         return (rc);
1078 }
1079
1080 static  __checkReturn                   efx_rc_t
1081 efx_mae_action_set_add_mark(
1082         __in                            efx_mae_actions_t *spec,
1083         __in                            size_t arg_size,
1084         __in_bcount(arg_size)           const uint8_t *arg)
1085 {
1086         efx_rc_t rc;
1087
1088         if (arg_size != sizeof (spec->ema_mark_value)) {
1089                 rc = EINVAL;
1090                 goto fail1;
1091         }
1092
1093         if (arg == NULL) {
1094                 rc = EINVAL;
1095                 goto fail2;
1096         }
1097
1098         memcpy(&spec->ema_mark_value, arg, arg_size);
1099
1100         return (0);
1101
1102 fail2:
1103         EFSYS_PROBE(fail2);
1104 fail1:
1105         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1106         return (rc);
1107 }
1108
1109 static  __checkReturn                   efx_rc_t
1110 efx_mae_action_set_add_deliver(
1111         __in                            efx_mae_actions_t *spec,
1112         __in                            size_t arg_size,
1113         __in_bcount(arg_size)           const uint8_t *arg)
1114 {
1115         efx_rc_t rc;
1116
1117         if (arg_size != sizeof (spec->ema_deliver_mport)) {
1118                 rc = EINVAL;
1119                 goto fail1;
1120         }
1121
1122         if (arg == NULL) {
1123                 rc = EINVAL;
1124                 goto fail2;
1125         }
1126
1127         memcpy(&spec->ema_deliver_mport, arg, arg_size);
1128
1129         return (0);
1130
1131 fail2:
1132         EFSYS_PROBE(fail2);
1133 fail1:
1134         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1135         return (rc);
1136 }
1137
1138 typedef struct efx_mae_action_desc_s {
1139         /* Action specific handler */
1140         efx_rc_t        (*emad_add)(efx_mae_actions_t *,
1141                                     size_t, const uint8_t *);
1142 } efx_mae_action_desc_t;
1143
1144 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
1145         [EFX_MAE_ACTION_VLAN_POP] = {
1146                 .emad_add = efx_mae_action_set_add_vlan_pop
1147         },
1148         [EFX_MAE_ACTION_VLAN_PUSH] = {
1149                 .emad_add = efx_mae_action_set_add_vlan_push
1150         },
1151         [EFX_MAE_ACTION_FLAG] = {
1152                 .emad_add = efx_mae_action_set_add_flag
1153         },
1154         [EFX_MAE_ACTION_MARK] = {
1155                 .emad_add = efx_mae_action_set_add_mark
1156         },
1157         [EFX_MAE_ACTION_DELIVER] = {
1158                 .emad_add = efx_mae_action_set_add_deliver
1159         }
1160 };
1161
1162 static const uint32_t efx_mae_action_ordered_map =
1163         (1U << EFX_MAE_ACTION_VLAN_POP) |
1164         (1U << EFX_MAE_ACTION_VLAN_PUSH) |
1165         (1U << EFX_MAE_ACTION_FLAG) |
1166         (1U << EFX_MAE_ACTION_MARK) |
1167         (1U << EFX_MAE_ACTION_DELIVER);
1168
1169 /*
1170  * These actions must not be added after DELIVER, but
1171  * they can have any place among the rest of
1172  * strictly ordered actions.
1173  */
1174 static const uint32_t efx_mae_action_nonstrict_map =
1175         (1U << EFX_MAE_ACTION_FLAG) |
1176         (1U << EFX_MAE_ACTION_MARK);
1177
1178 static const uint32_t efx_mae_action_repeat_map =
1179         (1U << EFX_MAE_ACTION_VLAN_POP) |
1180         (1U << EFX_MAE_ACTION_VLAN_PUSH);
1181
1182 /*
1183  * Add an action to an action set.
1184  *
1185  * This has to be invoked in the desired action order.
1186  * An out-of-order action request will be turned down.
1187  */
1188 static  __checkReturn                   efx_rc_t
1189 efx_mae_action_set_spec_populate(
1190         __in                            efx_mae_actions_t *spec,
1191         __in                            efx_mae_action_t type,
1192         __in                            size_t arg_size,
1193         __in_bcount(arg_size)           const uint8_t *arg)
1194 {
1195         uint32_t action_mask;
1196         efx_rc_t rc;
1197
1198         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1199             (sizeof (efx_mae_action_ordered_map) * 8));
1200         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1201             (sizeof (efx_mae_action_repeat_map) * 8));
1202
1203         EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1204         EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1205         EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1206
1207         if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1208                 rc = EINVAL;
1209                 goto fail1;
1210         }
1211
1212         action_mask = (1U << type);
1213
1214         if ((spec->ema_actions & action_mask) != 0) {
1215                 /* The action set already contains this action. */
1216                 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1217                         /* Cannot add another non-repeatable action. */
1218                         rc = ENOTSUP;
1219                         goto fail2;
1220                 }
1221         }
1222
1223         if ((efx_mae_action_ordered_map & action_mask) != 0) {
1224                 uint32_t strict_ordered_map =
1225                     efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1226                 uint32_t later_actions_mask =
1227                     strict_ordered_map & ~(action_mask | (action_mask - 1));
1228
1229                 if ((spec->ema_actions & later_actions_mask) != 0) {
1230                         /* Cannot add an action after later ordered actions. */
1231                         rc = ENOTSUP;
1232                         goto fail3;
1233                 }
1234         }
1235
1236         if (efx_mae_actions[type].emad_add != NULL) {
1237                 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1238                 if (rc != 0)
1239                         goto fail4;
1240         }
1241
1242         spec->ema_actions |= action_mask;
1243
1244         return (0);
1245
1246 fail4:
1247         EFSYS_PROBE(fail4);
1248 fail3:
1249         EFSYS_PROBE(fail3);
1250 fail2:
1251         EFSYS_PROBE(fail2);
1252 fail1:
1253         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1254         return (rc);
1255 }
1256
1257         __checkReturn                   efx_rc_t
1258 efx_mae_action_set_populate_vlan_pop(
1259         __in                            efx_mae_actions_t *spec)
1260 {
1261         return (efx_mae_action_set_spec_populate(spec,
1262             EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1263 }
1264
1265         __checkReturn                   efx_rc_t
1266 efx_mae_action_set_populate_vlan_push(
1267         __in                            efx_mae_actions_t *spec,
1268         __in                            uint16_t tpid_be,
1269         __in                            uint16_t tci_be)
1270 {
1271         efx_mae_action_vlan_push_t action;
1272         const uint8_t *arg = (const uint8_t *)&action;
1273
1274         action.emavp_tpid_be = tpid_be;
1275         action.emavp_tci_be = tci_be;
1276
1277         return (efx_mae_action_set_spec_populate(spec,
1278             EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1279 }
1280
1281         __checkReturn                   efx_rc_t
1282 efx_mae_action_set_populate_flag(
1283         __in                            efx_mae_actions_t *spec)
1284 {
1285         return (efx_mae_action_set_spec_populate(spec,
1286             EFX_MAE_ACTION_FLAG, 0, NULL));
1287 }
1288
1289         __checkReturn                   efx_rc_t
1290 efx_mae_action_set_populate_mark(
1291         __in                            efx_mae_actions_t *spec,
1292         __in                            uint32_t mark_value)
1293 {
1294         const uint8_t *arg = (const uint8_t *)&mark_value;
1295
1296         return (efx_mae_action_set_spec_populate(spec,
1297             EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1298 }
1299
1300         __checkReturn                   efx_rc_t
1301 efx_mae_action_set_populate_deliver(
1302         __in                            efx_mae_actions_t *spec,
1303         __in                            const efx_mport_sel_t *mportp)
1304 {
1305         const uint8_t *arg;
1306         efx_rc_t rc;
1307
1308         if (mportp == NULL) {
1309                 rc = EINVAL;
1310                 goto fail1;
1311         }
1312
1313         arg = (const uint8_t *)&mportp->sel;
1314
1315         return (efx_mae_action_set_spec_populate(spec,
1316             EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1317
1318 fail1:
1319         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1320         return (rc);
1321 }
1322
1323         __checkReturn                   efx_rc_t
1324 efx_mae_action_set_populate_drop(
1325         __in                            efx_mae_actions_t *spec)
1326 {
1327         efx_mport_sel_t mport;
1328         const uint8_t *arg;
1329         efx_dword_t dword;
1330
1331         EFX_POPULATE_DWORD_1(dword,
1332             MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1333
1334         /*
1335          * The constructed DWORD is little-endian,
1336          * but the resulting value is meant to be
1337          * passed to MCDIs, where it will undergo
1338          * host-order to little endian conversion.
1339          */
1340         mport.sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
1341
1342         arg = (const uint8_t *)&mport.sel;
1343
1344         return (efx_mae_action_set_spec_populate(spec,
1345             EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1346 }
1347
1348         __checkReturn                   boolean_t
1349 efx_mae_action_set_specs_equal(
1350         __in                            const efx_mae_actions_t *left,
1351         __in                            const efx_mae_actions_t *right)
1352 {
1353         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1354 }
1355
1356         __checkReturn                   efx_rc_t
1357 efx_mae_match_specs_class_cmp(
1358         __in                            efx_nic_t *enp,
1359         __in                            const efx_mae_match_spec_t *left,
1360         __in                            const efx_mae_match_spec_t *right,
1361         __out                           boolean_t *have_same_classp)
1362 {
1363         efx_mae_t *maep = enp->en_maep;
1364         unsigned int field_ncaps = maep->em_max_nfields;
1365         const efx_mae_field_cap_t *field_caps;
1366         const efx_mae_mv_desc_t *desc_setp;
1367         unsigned int desc_set_nentries;
1368         boolean_t have_same_class = B_TRUE;
1369         efx_mae_field_id_t field_id;
1370         const uint8_t *mvpl;
1371         const uint8_t *mvpr;
1372         efx_rc_t rc;
1373
1374         switch (left->emms_type) {
1375         case EFX_MAE_RULE_OUTER:
1376                 field_caps = maep->em_outer_rule_field_caps;
1377                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
1378                 desc_set_nentries =
1379                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
1380                 mvpl = left->emms_mask_value_pairs.outer;
1381                 mvpr = right->emms_mask_value_pairs.outer;
1382                 break;
1383         case EFX_MAE_RULE_ACTION:
1384                 field_caps = maep->em_action_rule_field_caps;
1385                 desc_setp = __efx_mae_action_rule_mv_desc_set;
1386                 desc_set_nentries =
1387                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1388                 mvpl = left->emms_mask_value_pairs.action;
1389                 mvpr = right->emms_mask_value_pairs.action;
1390                 break;
1391         default:
1392                 rc = ENOTSUP;
1393                 goto fail1;
1394         }
1395
1396         if (field_caps == NULL) {
1397                 rc = EAGAIN;
1398                 goto fail2;
1399         }
1400
1401         if (left->emms_type != right->emms_type ||
1402             left->emms_prio != right->emms_prio) {
1403                 /*
1404                  * Rules of different types can never map to the same class.
1405                  *
1406                  * The FW can support some set of match criteria for one
1407                  * priority and not support the very same set for
1408                  * another priority. Thus, two rules which have
1409                  * different priorities can never map to
1410                  * the same class.
1411                  */
1412                 *have_same_classp = B_FALSE;
1413                 return (0);
1414         }
1415
1416         for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
1417              ++field_id) {
1418                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1419                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1420
1421                 if (descp->emmd_mask_size == 0)
1422                         continue; /* Skip array gap */
1423
1424                 if ((unsigned int)field_cap_id >= field_ncaps)
1425                         break;
1426
1427                 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1428                         const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1429                         const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1430                         size_t mask_size = descp->emmd_mask_size;
1431
1432                         if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1433                                 have_same_class = B_FALSE;
1434                                 break;
1435                         }
1436                 }
1437
1438                 if (field_caps[field_cap_id].emfc_match_affects_class) {
1439                         const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1440                         const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1441                         size_t value_size = descp->emmd_value_size;
1442
1443                         if (memcmp(lvalp, rvalp, value_size) != 0) {
1444                                 have_same_class = B_FALSE;
1445                                 break;
1446                         }
1447                 }
1448         }
1449
1450         *have_same_classp = have_same_class;
1451
1452         return (0);
1453
1454 fail2:
1455         EFSYS_PROBE(fail2);
1456 fail1:
1457         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1458         return (rc);
1459 }
1460
1461         __checkReturn           efx_rc_t
1462 efx_mae_outer_rule_insert(
1463         __in                    efx_nic_t *enp,
1464         __in                    const efx_mae_match_spec_t *spec,
1465         __in                    efx_tunnel_protocol_t encap_type,
1466         __out                   efx_mae_rule_id_t *or_idp)
1467 {
1468         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1469         efx_mcdi_req_t req;
1470         EFX_MCDI_DECLARE_BUF(payload,
1471             MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,
1472             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);
1473         uint32_t encap_type_mcdi;
1474         efx_mae_rule_id_t or_id;
1475         size_t offset;
1476         efx_rc_t rc;
1477
1478         EFX_STATIC_ASSERT(sizeof (or_idp->id) ==
1479             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);
1480
1481         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1482             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);
1483
1484         if (encp->enc_mae_supported == B_FALSE) {
1485                 rc = ENOTSUP;
1486                 goto fail1;
1487         }
1488
1489         if (spec->emms_type != EFX_MAE_RULE_OUTER) {
1490                 rc = EINVAL;
1491                 goto fail2;
1492         }
1493
1494         switch (encap_type) {
1495         case EFX_TUNNEL_PROTOCOL_NONE:
1496                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
1497                 break;
1498         case EFX_TUNNEL_PROTOCOL_VXLAN:
1499                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
1500                 break;
1501         case EFX_TUNNEL_PROTOCOL_GENEVE:
1502                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
1503                 break;
1504         case EFX_TUNNEL_PROTOCOL_NVGRE:
1505                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
1506                 break;
1507         default:
1508                 rc = ENOTSUP;
1509                 goto fail3;
1510         }
1511
1512         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;
1513         req.emr_in_buf = payload;
1514         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;
1515         req.emr_out_buf = payload;
1516         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;
1517
1518         MCDI_IN_SET_DWORD(req,
1519             MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);
1520
1521         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);
1522
1523         /*
1524          * Mask-value pairs have been stored in the byte order needed for the
1525          * MCDI request and are thus safe to be copied directly to the buffer.
1526          * The library cares about byte order in efx_mae_match_spec_field_set().
1527          */
1528         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=
1529             MAE_ENC_FIELD_PAIRS_LEN);
1530         offset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;
1531         memcpy(payload + offset, spec->emms_mask_value_pairs.outer,
1532             MAE_ENC_FIELD_PAIRS_LEN);
1533
1534         efx_mcdi_execute(enp, &req);
1535
1536         if (req.emr_rc != 0) {
1537                 rc = req.emr_rc;
1538                 goto fail4;
1539         }
1540
1541         if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {
1542                 rc = EMSGSIZE;
1543                 goto fail5;
1544         }
1545
1546         or_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);
1547         if (or_id.id == EFX_MAE_RSRC_ID_INVALID) {
1548                 rc = ENOENT;
1549                 goto fail6;
1550         }
1551
1552         or_idp->id = or_id.id;
1553
1554         return (0);
1555
1556 fail6:
1557         EFSYS_PROBE(fail6);
1558 fail5:
1559         EFSYS_PROBE(fail5);
1560 fail4:
1561         EFSYS_PROBE(fail4);
1562 fail3:
1563         EFSYS_PROBE(fail3);
1564 fail2:
1565         EFSYS_PROBE(fail2);
1566 fail1:
1567         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1568         return (rc);
1569 }
1570
1571         __checkReturn           efx_rc_t
1572 efx_mae_outer_rule_remove(
1573         __in                    efx_nic_t *enp,
1574         __in                    const efx_mae_rule_id_t *or_idp)
1575 {
1576         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1577         efx_mcdi_req_t req;
1578         EFX_MCDI_DECLARE_BUF(payload,
1579             MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),
1580             MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));
1581         efx_rc_t rc;
1582
1583         if (encp->enc_mae_supported == B_FALSE) {
1584                 rc = ENOTSUP;
1585                 goto fail1;
1586         }
1587
1588         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;
1589         req.emr_in_buf = payload;
1590         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);
1591         req.emr_out_buf = payload;
1592         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);
1593
1594         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);
1595
1596         efx_mcdi_execute(enp, &req);
1597
1598         if (req.emr_rc != 0) {
1599                 rc = req.emr_rc;
1600                 goto fail2;
1601         }
1602
1603         if (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=
1604             or_idp->id) {
1605                 /* Firmware failed to remove the outer rule. */
1606                 rc = EAGAIN;
1607                 goto fail3;
1608         }
1609
1610         return (0);
1611
1612 fail3:
1613         EFSYS_PROBE(fail3);
1614 fail2:
1615         EFSYS_PROBE(fail2);
1616 fail1:
1617         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1618         return (rc);
1619 }
1620
1621         __checkReturn                   efx_rc_t
1622 efx_mae_match_spec_outer_rule_id_set(
1623         __in                            efx_mae_match_spec_t *spec,
1624         __in                            const efx_mae_rule_id_t *or_idp)
1625 {
1626         uint32_t full_mask = UINT32_MAX;
1627         efx_rc_t rc;
1628
1629         if (spec->emms_type != EFX_MAE_RULE_ACTION) {
1630                 rc = EINVAL;
1631                 goto fail1;
1632         }
1633
1634         if (or_idp == NULL) {
1635                 rc = EINVAL;
1636                 goto fail2;
1637         }
1638
1639         rc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,
1640             sizeof (or_idp->id), (const uint8_t *)&or_idp->id,
1641             sizeof (full_mask), (const uint8_t *)&full_mask);
1642         if (rc != 0)
1643                 goto fail3;
1644
1645         return (0);
1646
1647 fail3:
1648         EFSYS_PROBE(fail3);
1649 fail2:
1650         EFSYS_PROBE(fail2);
1651 fail1:
1652         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1653         return (rc);
1654 }
1655
1656         __checkReturn                   efx_rc_t
1657 efx_mae_action_set_alloc(
1658         __in                            efx_nic_t *enp,
1659         __in                            const efx_mae_actions_t *spec,
1660         __out                           efx_mae_aset_id_t *aset_idp)
1661 {
1662         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1663         efx_mcdi_req_t req;
1664         EFX_MCDI_DECLARE_BUF(payload,
1665             MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1666             MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1667         efx_mae_aset_id_t aset_id;
1668         efx_rc_t rc;
1669
1670         if (encp->enc_mae_supported == B_FALSE) {
1671                 rc = ENOTSUP;
1672                 goto fail1;
1673         }
1674
1675         req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1676         req.emr_in_buf = payload;
1677         req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1678         req.emr_out_buf = payload;
1679         req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1680
1681         /*
1682          * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1683          * corresponding resource types are supported by the implementation.
1684          * Use proper resource ID assignments instead.
1685          */
1686         MCDI_IN_SET_DWORD(req,
1687             MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1688         MCDI_IN_SET_DWORD(req,
1689             MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1690         MCDI_IN_SET_DWORD(req,
1691             MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1692
1693         MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1694             MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1695
1696         if (spec->ema_n_vlan_tags_to_push > 0) {
1697                 unsigned int outer_tag_idx;
1698
1699                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1700                     MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1701                     spec->ema_n_vlan_tags_to_push);
1702
1703                 if (spec->ema_n_vlan_tags_to_push ==
1704                     EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1705                         MCDI_IN_SET_WORD(req,
1706                             MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1707                             spec->ema_vlan_push_descs[0].emavp_tpid_be);
1708                         MCDI_IN_SET_WORD(req,
1709                             MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1710                             spec->ema_vlan_push_descs[0].emavp_tci_be);
1711                 }
1712
1713                 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1714
1715                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1716                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1717                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1718                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1719         }
1720
1721         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1722                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1723                     MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1724         }
1725
1726         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1727                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1728                     MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1729
1730                 MCDI_IN_SET_DWORD(req,
1731                     MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1732         }
1733
1734         MCDI_IN_SET_DWORD(req,
1735             MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1736
1737         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1738             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1739         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1740             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1741
1742         efx_mcdi_execute(enp, &req);
1743
1744         if (req.emr_rc != 0) {
1745                 rc = req.emr_rc;
1746                 goto fail2;
1747         }
1748
1749         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1750                 rc = EMSGSIZE;
1751                 goto fail3;
1752         }
1753
1754         aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1755         if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1756                 rc = ENOENT;
1757                 goto fail4;
1758         }
1759
1760         aset_idp->id = aset_id.id;
1761
1762         return (0);
1763
1764 fail4:
1765         EFSYS_PROBE(fail4);
1766 fail3:
1767         EFSYS_PROBE(fail3);
1768 fail2:
1769         EFSYS_PROBE(fail2);
1770 fail1:
1771         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1772         return (rc);
1773 }
1774
1775         __checkReturn                   efx_rc_t
1776 efx_mae_action_set_free(
1777         __in                            efx_nic_t *enp,
1778         __in                            const efx_mae_aset_id_t *aset_idp)
1779 {
1780         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1781         efx_mcdi_req_t req;
1782         EFX_MCDI_DECLARE_BUF(payload,
1783             MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1784             MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1785         efx_rc_t rc;
1786
1787         if (encp->enc_mae_supported == B_FALSE) {
1788                 rc = ENOTSUP;
1789                 goto fail1;
1790         }
1791
1792         req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1793         req.emr_in_buf = payload;
1794         req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1795         req.emr_out_buf = payload;
1796         req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1797
1798         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1799
1800         efx_mcdi_execute(enp, &req);
1801
1802         if (req.emr_rc != 0) {
1803                 rc = req.emr_rc;
1804                 goto fail2;
1805         }
1806
1807         if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1808             aset_idp->id) {
1809                 /* Firmware failed to free the action set. */
1810                 rc = EAGAIN;
1811                 goto fail3;
1812         }
1813
1814         return (0);
1815
1816 fail3:
1817         EFSYS_PROBE(fail3);
1818 fail2:
1819         EFSYS_PROBE(fail2);
1820 fail1:
1821         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1822         return (rc);
1823 }
1824
1825         __checkReturn                   efx_rc_t
1826 efx_mae_action_rule_insert(
1827         __in                            efx_nic_t *enp,
1828         __in                            const efx_mae_match_spec_t *spec,
1829         __in                            const efx_mae_aset_list_id_t *asl_idp,
1830         __in                            const efx_mae_aset_id_t *as_idp,
1831         __out                           efx_mae_rule_id_t *ar_idp)
1832 {
1833         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1834         efx_mcdi_req_t req;
1835         EFX_MCDI_DECLARE_BUF(payload,
1836             MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1837             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1838         efx_oword_t *rule_response;
1839         efx_mae_rule_id_t ar_id;
1840         size_t offset;
1841         efx_rc_t rc;
1842
1843         EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1844             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1845
1846         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1847             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1848
1849         if (encp->enc_mae_supported == B_FALSE) {
1850                 rc = ENOTSUP;
1851                 goto fail1;
1852         }
1853
1854         if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1855             (asl_idp != NULL && as_idp != NULL) ||
1856             (asl_idp == NULL && as_idp == NULL)) {
1857                 rc = EINVAL;
1858                 goto fail2;
1859         }
1860
1861         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1862         req.emr_in_buf = payload;
1863         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1864         req.emr_out_buf = payload;
1865         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1866
1867         EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1868             MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1869         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1870         rule_response = (efx_oword_t *)(payload + offset);
1871         EFX_POPULATE_OWORD_3(*rule_response,
1872             MAE_ACTION_RULE_RESPONSE_ASL_ID,
1873             (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1874             MAE_ACTION_RULE_RESPONSE_AS_ID,
1875             (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1876             MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1877
1878         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1879
1880         /*
1881          * Mask-value pairs have been stored in the byte order needed for the
1882          * MCDI request and are thus safe to be copied directly to the buffer.
1883          */
1884         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1885             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1886         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1887         memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1888             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1889
1890         efx_mcdi_execute(enp, &req);
1891
1892         if (req.emr_rc != 0) {
1893                 rc = req.emr_rc;
1894                 goto fail3;
1895         }
1896
1897         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1898                 rc = EMSGSIZE;
1899                 goto fail4;
1900         }
1901
1902         ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1903         if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1904                 rc = ENOENT;
1905                 goto fail5;
1906         }
1907
1908         ar_idp->id = ar_id.id;
1909
1910         return (0);
1911
1912 fail5:
1913         EFSYS_PROBE(fail5);
1914 fail4:
1915         EFSYS_PROBE(fail4);
1916 fail3:
1917         EFSYS_PROBE(fail3);
1918 fail2:
1919         EFSYS_PROBE(fail2);
1920 fail1:
1921         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1922         return (rc);
1923 }
1924
1925         __checkReturn                   efx_rc_t
1926 efx_mae_action_rule_remove(
1927         __in                            efx_nic_t *enp,
1928         __in                            const efx_mae_rule_id_t *ar_idp)
1929 {
1930         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1931         efx_mcdi_req_t req;
1932         EFX_MCDI_DECLARE_BUF(payload,
1933             MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1934             MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1935         efx_rc_t rc;
1936
1937         if (encp->enc_mae_supported == B_FALSE) {
1938                 rc = ENOTSUP;
1939                 goto fail1;
1940         }
1941
1942         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1943         req.emr_in_buf = payload;
1944         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1945         req.emr_out_buf = payload;
1946         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1947
1948         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1949
1950         efx_mcdi_execute(enp, &req);
1951
1952         if (req.emr_rc != 0) {
1953                 rc = req.emr_rc;
1954                 goto fail2;
1955         }
1956
1957         if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1958             ar_idp->id) {
1959                 /* Firmware failed to delete the action rule. */
1960                 rc = EAGAIN;
1961                 goto fail3;
1962         }
1963
1964         return (0);
1965
1966 fail3:
1967         EFSYS_PROBE(fail3);
1968 fail2:
1969         EFSYS_PROBE(fail2);
1970 fail1:
1971         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1972         return (rc);
1973 }
1974
1975 #endif /* EFSYS_OPT_MAE */