drivers/common/sfc_efx/base/efx_mae.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_MAE
  12
  13 static  __checkReturn                   efx_rc_t
  14 efx_mae_get_capabilities(
  15         __in                            efx_nic_t *enp)
  16 {
  17         efx_mcdi_req_t req;
  18         EFX_MCDI_DECLARE_BUF(payload,
  19             MC_CMD_MAE_GET_CAPS_IN_LEN,
  20             MC_CMD_MAE_GET_CAPS_OUT_LEN);
  21         struct efx_mae_s *maep = enp->en_maep;
  22         efx_rc_t rc;
  23
  24         req.emr_cmd = MC_CMD_MAE_GET_CAPS;
  25         req.emr_in_buf = payload;
  26         req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
  27         req.emr_out_buf = payload;
  28         req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
  29
  30         efx_mcdi_execute(enp, &req);
  31
  32         if (req.emr_rc != 0) {
  33                 rc = req.emr_rc;
  34                 goto fail1;
  35         }
  36
  37         if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
  38                 rc = EMSGSIZE;
  39                 goto fail2;
  40         }
  41
  42         maep->em_max_n_outer_prios =
  43             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
  44
  45         maep->em_max_n_action_prios =
  46             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
  47
  48         maep->em_encap_types_supported = 0;
  49
  50         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
  51                 maep->em_encap_types_supported |=
  52                     (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
  53         }
  54
  55         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
  56                 maep->em_encap_types_supported |=
  57                     (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
  58         }
  59
  60         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
  61                 maep->em_encap_types_supported |=
  62                     (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
  63         }
  64
  65         maep->em_max_nfields =
  66             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
  67
  68         return (0);
  69
  70 fail2:
  71         EFSYS_PROBE(fail2);
  72 fail1:
  73         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  74         return (rc);
  75 }
  76
  77 static  __checkReturn                   efx_rc_t
  78 efx_mae_get_outer_rule_caps(
  79         __in                            efx_nic_t *enp,
  80         __in                            unsigned int field_ncaps,
  81         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
  82 {
  83         efx_mcdi_req_t req;
  84         EFX_MCDI_DECLARE_BUF(payload,
  85             MC_CMD_MAE_GET_OR_CAPS_IN_LEN,
  86             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2);
  87         unsigned int mcdi_field_ncaps;
  88         unsigned int i;
  89         efx_rc_t rc;
  90
  91         if (MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps) >
  92             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2) {
  93                 rc = EINVAL;
  94                 goto fail1;
  95         }
  96
  97         req.emr_cmd = MC_CMD_MAE_GET_OR_CAPS;
  98         req.emr_in_buf = payload;
  99         req.emr_in_length = MC_CMD_MAE_GET_OR_CAPS_IN_LEN;
 100         req.emr_out_buf = payload;
 101         req.emr_out_length = MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps);
 102
 103         efx_mcdi_execute(enp, &req);
 104
 105         if (req.emr_rc != 0) {
 106                 rc = req.emr_rc;
 107                 goto fail2;
 108         }
 109
 110         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 111
 112         if (req.emr_out_length_used <
 113             MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 114                 rc = EMSGSIZE;
 115                 goto fail3;
 116         }
 117
 118         if (mcdi_field_ncaps > field_ncaps) {
 119                 rc = EMSGSIZE;
 120                 goto fail4;
 121         }
 122
 123         for (i = 0; i < mcdi_field_ncaps; ++i) {
 124                 uint32_t match_flag;
 125                 uint32_t mask_flag;
 126
 127                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 128                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 129                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 130
 131                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 132                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 133                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 134
 135                 field_caps[i].emfc_match_affects_class =
 136                     (match_flag != 0) ? B_TRUE : B_FALSE;
 137
 138                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 139                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 140                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 141
 142                 field_caps[i].emfc_mask_affects_class =
 143                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 144         }
 145
 146         return (0);
 147
 148 fail4:
 149         EFSYS_PROBE(fail4);
 150 fail3:
 151         EFSYS_PROBE(fail3);
 152 fail2:
 153         EFSYS_PROBE(fail2);
 154 fail1:
 155         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 156         return (rc);
 157 }
 158
 159 static  __checkReturn                   efx_rc_t
 160 efx_mae_get_action_rule_caps(
 161         __in                            efx_nic_t *enp,
 162         __in                            unsigned int field_ncaps,
 163         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
 164 {
 165         efx_mcdi_req_t req;
 166         EFX_MCDI_DECLARE_BUF(payload,
 167             MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
 168             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
 169         unsigned int mcdi_field_ncaps;
 170         unsigned int i;
 171         efx_rc_t rc;
 172
 173         if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
 174             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
 175                 rc = EINVAL;
 176                 goto fail1;
 177         }
 178
 179         req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
 180         req.emr_in_buf = payload;
 181         req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
 182         req.emr_out_buf = payload;
 183         req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
 184
 185         efx_mcdi_execute(enp, &req);
 186
 187         if (req.emr_rc != 0) {
 188                 rc = req.emr_rc;
 189                 goto fail2;
 190         }
 191
 192         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 193
 194         if (req.emr_out_length_used <
 195             MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 196                 rc = EMSGSIZE;
 197                 goto fail3;
 198         }
 199
 200         if (mcdi_field_ncaps > field_ncaps) {
 201                 rc = EMSGSIZE;
 202                 goto fail4;
 203         }
 204
 205         for (i = 0; i < mcdi_field_ncaps; ++i) {
 206                 uint32_t match_flag;
 207                 uint32_t mask_flag;
 208
 209                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 210                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 211                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 212
 213                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 214                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 215                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 216
 217                 field_caps[i].emfc_match_affects_class =
 218                     (match_flag != 0) ? B_TRUE : B_FALSE;
 219
 220                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 221                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 222                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 223
 224                 field_caps[i].emfc_mask_affects_class =
 225                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 226         }
 227
 228         return (0);
 229
 230 fail4:
 231         EFSYS_PROBE(fail4);
 232 fail3:
 233         EFSYS_PROBE(fail3);
 234 fail2:
 235         EFSYS_PROBE(fail2);
 236 fail1:
 237         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 238         return (rc);
 239 }
 240
 241         __checkReturn                   efx_rc_t
 242 efx_mae_init(
 243         __in                            efx_nic_t *enp)
 244 {
 245         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 246         efx_mae_field_cap_t *or_fcaps;
 247         size_t or_fcaps_size;
 248         efx_mae_field_cap_t *ar_fcaps;
 249         size_t ar_fcaps_size;
 250         efx_mae_t *maep;
 251         efx_rc_t rc;
 252
 253         if (encp->enc_mae_supported == B_FALSE) {
 254                 rc = ENOTSUP;
 255                 goto fail1;
 256         }
 257
 258         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
 259         if (maep == NULL) {
 260                 rc = ENOMEM;
 261                 goto fail2;
 262         }
 263
 264         enp->en_maep = maep;
 265
 266         rc = efx_mae_get_capabilities(enp);
 267         if (rc != 0)
 268                 goto fail3;
 269
 270         or_fcaps_size = maep->em_max_nfields * sizeof (*or_fcaps);
 271         EFSYS_KMEM_ALLOC(enp->en_esip, or_fcaps_size, or_fcaps);
 272         if (or_fcaps == NULL) {
 273                 rc = ENOMEM;
 274                 goto fail4;
 275         }
 276
 277         maep->em_outer_rule_field_caps_size = or_fcaps_size;
 278         maep->em_outer_rule_field_caps = or_fcaps;
 279
 280         rc = efx_mae_get_outer_rule_caps(enp, maep->em_max_nfields, or_fcaps);
 281         if (rc != 0)
 282                 goto fail5;
 283
 284         ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
 285         EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
 286         if (ar_fcaps == NULL) {
 287                 rc = ENOMEM;
 288                 goto fail6;
 289         }
 290
 291         maep->em_action_rule_field_caps_size = ar_fcaps_size;
 292         maep->em_action_rule_field_caps = ar_fcaps;
 293
 294         rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
 295         if (rc != 0)
 296                 goto fail7;
 297
 298         return (0);
 299
 300 fail7:
 301         EFSYS_PROBE(fail5);
 302         EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
 303 fail6:
 304         EFSYS_PROBE(fail4);
 305 fail5:
 306         EFSYS_PROBE(fail5);
 307         EFSYS_KMEM_FREE(enp->en_esip, or_fcaps_size, or_fcaps);
 308 fail4:
 309         EFSYS_PROBE(fail4);
 310 fail3:
 311         EFSYS_PROBE(fail3);
 312         EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
 313         enp->en_maep = NULL;
 314 fail2:
 315         EFSYS_PROBE(fail2);
 316 fail1:
 317         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 318         return (rc);
 319 }
 320
 321                                         void
 322 efx_mae_fini(
 323         __in                            efx_nic_t *enp)
 324 {
 325         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 326         efx_mae_t *maep = enp->en_maep;
 327
 328         if (encp->enc_mae_supported == B_FALSE)
 329                 return;
 330
 331         EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
 332             maep->em_action_rule_field_caps);
 333         EFSYS_KMEM_FREE(enp->en_esip, maep->em_outer_rule_field_caps_size,
 334             maep->em_outer_rule_field_caps);
 335         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
 336         enp->en_maep = NULL;
 337 }
 338
 339         __checkReturn                   efx_rc_t
 340 efx_mae_get_limits(
 341         __in                            efx_nic_t *enp,
 342         __out                           efx_mae_limits_t *emlp)
 343 {
 344         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 345         struct efx_mae_s *maep = enp->en_maep;
 346         efx_rc_t rc;
 347
 348         if (encp->enc_mae_supported == B_FALSE) {
 349                 rc = ENOTSUP;
 350                 goto fail1;
 351         }
 352
 353         emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
 354         emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
 355         emlp->eml_encap_types_supported = maep->em_encap_types_supported;
 356
 357         return (0);
 358
 359 fail1:
 360         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 361         return (rc);
 362 }
 363
 364         __checkReturn                   efx_rc_t
 365 efx_mae_match_spec_init(
 366         __in                            efx_nic_t *enp,
 367         __in                            efx_mae_rule_type_t type,
 368         __in                            uint32_t prio,
 369         __out                           efx_mae_match_spec_t **specp)
 370 {
 371         efx_mae_match_spec_t *spec;
 372         efx_rc_t rc;
 373
 374         switch (type) {
 375         case EFX_MAE_RULE_OUTER:
 376                 break;
 377         case EFX_MAE_RULE_ACTION:
 378                 break;
 379         default:
 380                 rc = ENOTSUP;
 381                 goto fail1;
 382         }
 383
 384         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 385         if (spec == NULL) {
 386                 rc = ENOMEM;
 387                 goto fail2;
 388         }
 389
 390         spec->emms_type = type;
 391         spec->emms_prio = prio;
 392
 393         *specp = spec;
 394
 395         return (0);
 396
 397 fail2:
 398         EFSYS_PROBE(fail2);
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401         return (rc);
 402 }
 403
 404                                         void
 405 efx_mae_match_spec_fini(
 406         __in                            efx_nic_t *enp,
 407         __in                            efx_mae_match_spec_t *spec)
 408 {
 409         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 410 }
 411
 412 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
 413 typedef enum efx_mae_field_cap_id_e {
 414         EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
 415         EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
 416         EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
 417         EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
 418         EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
 419         EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
 420         EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
 421         EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
 422         EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
 423         EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
 424         EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
 425         EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
 426         EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
 427         EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
 428         EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
 429         EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
 430         EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
 431         EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
 432         EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
 433         EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
 434         EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
 435         EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
 436         EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
 437         EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
 438         EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
 439         EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
 440         EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
 441         EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
 442         EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
 443         EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
 444         EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
 445         EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
 446         EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
 447         EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
 448         EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
 449         EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
 450
 451         EFX_MAE_FIELD_CAP_NIDS
 452 } efx_mae_field_cap_id_t;
 453
 454 typedef enum efx_mae_field_endianness_e {
 455         EFX_MAE_FIELD_LE = 0,
 456         EFX_MAE_FIELD_BE,
 457
 458         EFX_MAE_FIELD_ENDIANNESS_NTYPES
 459 } efx_mae_field_endianness_t;
 460
 461 /*
 462  * The following structure is a means to describe an MAE field.
 463  * The information in it is meant to be used internally by
 464  * APIs for addressing a given field in a mask-value pairs
 465  * structure and for validation purposes.
 466  */
 467 typedef struct efx_mae_mv_desc_s {
 468         efx_mae_field_cap_id_t          emmd_field_cap_id;
 469
 470         size_t                          emmd_value_size;
 471         size_t                          emmd_value_offset;
 472         size_t                          emmd_mask_size;
 473         size_t                          emmd_mask_offset;
 474
 475         efx_mae_field_endianness_t      emmd_endianness;
 476 } efx_mae_mv_desc_t;
 477
 478 /* Indices to this array are provided by efx_mae_field_id_t */
 479 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
 480 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 481         [EFX_MAE_FIELD_##_name] =                                       \
 482         {                                                               \
 483                 EFX_MAE_FIELD_ID_##_name,                               \
 484                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN,               \
 485                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,              \
 486                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,          \
 487                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,         \
 488                 _endianness                                             \
 489         }
 490
 491         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 492         EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 493         EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 494         EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 495         EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 496         EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 497         EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 498         EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 499         EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
 500         EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
 501         EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
 502         EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
 503         EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
 504         EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
 505         EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
 506         EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
 507         EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
 508         EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
 509         EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
 510         EFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),
 511
 512 #undef EFX_MAE_MV_DESC
 513 };
 514
 515 /* Indices to this array are provided by efx_mae_field_id_t */
 516 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 517 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 518         [EFX_MAE_FIELD_##_name] =                                       \
 519         {                                                               \
 520                 EFX_MAE_FIELD_ID_##_name,                               \
 521                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 522                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 523                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 524                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 525                 _endianness                                             \
 526         }
 527
 528         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 529         EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 530         EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 531         EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 532         EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 533         EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 534         EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 535         EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 536         EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
 537         EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
 538         EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
 539         EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
 540         EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
 541         EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
 542         EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
 543         EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
 544         EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
 545
 546 #undef EFX_MAE_MV_DESC
 547 };
 548
 549         __checkReturn                   efx_rc_t
 550 efx_mae_mport_by_phy_port(
 551         __in                            uint32_t phy_port,
 552         __out                           efx_mport_sel_t *mportp)
 553 {
 554         efx_dword_t dword;
 555         efx_rc_t rc;
 556
 557         if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
 558                 rc = EINVAL;
 559                 goto fail1;
 560         }
 561
 562         EFX_POPULATE_DWORD_2(dword,
 563             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
 564             MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
 565
 566         memset(mportp, 0, sizeof (*mportp));
 567         mportp->sel = dword.ed_u32[0];
 568
 569         return (0);
 570
 571 fail1:
 572         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 573         return (rc);
 574 }
 575
 576         __checkReturn                   efx_rc_t
 577 efx_mae_mport_by_pcie_function(
 578         __in                            uint32_t pf,
 579         __in                            uint32_t vf,
 580         __out                           efx_mport_sel_t *mportp)
 581 {
 582         efx_dword_t dword;
 583         efx_rc_t rc;
 584
 585         EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
 586             MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
 587
 588         if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
 589                 rc = EINVAL;
 590                 goto fail1;
 591         }
 592
 593         if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
 594                 rc = EINVAL;
 595                 goto fail2;
 596         }
 597
 598         EFX_POPULATE_DWORD_3(dword,
 599             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
 600             MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
 601             MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
 602
 603         memset(mportp, 0, sizeof (*mportp));
 604         mportp->sel = dword.ed_u32[0];
 605
 606         return (0);
 607
 608 fail2:
 609         EFSYS_PROBE(fail2);
 610 fail1:
 611         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 612         return (rc);
 613 }
 614
 615         __checkReturn                   efx_rc_t
 616 efx_mae_match_spec_field_set(
 617         __in                            efx_mae_match_spec_t *spec,
 618         __in                            efx_mae_field_id_t field_id,
 619         __in                            size_t value_size,
 620         __in_bcount(value_size)         const uint8_t *value,
 621         __in                            size_t mask_size,
 622         __in_bcount(mask_size)          const uint8_t *mask)
 623 {
 624         const efx_mae_mv_desc_t *descp;
 625         unsigned int desc_set_nentries;
 626         uint8_t *mvp;
 627         efx_rc_t rc;
 628
 629         switch (spec->emms_type) {
 630         case EFX_MAE_RULE_OUTER:
 631                 desc_set_nentries =
 632                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
 633                 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
 634                 mvp = spec->emms_mask_value_pairs.outer;
 635                 break;
 636         case EFX_MAE_RULE_ACTION:
 637                 desc_set_nentries =
 638                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 639                 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
 640                 mvp = spec->emms_mask_value_pairs.action;
 641                 break;
 642         default:
 643                 rc = ENOTSUP;
 644                 goto fail1;
 645         }
 646
 647         if (field_id >= desc_set_nentries) {
 648                 rc = EINVAL;
 649                 goto fail2;
 650         }
 651
 652         if (value_size != descp->emmd_value_size) {
 653                 rc = EINVAL;
 654                 goto fail3;
 655         }
 656
 657         if (mask_size != descp->emmd_mask_size) {
 658                 rc = EINVAL;
 659                 goto fail4;
 660         }
 661
 662         if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
 663                 /*
 664                  * The mask/value are in network (big endian) order.
 665                  * The MCDI request field is also big endian.
 666                  */
 667                 memcpy(mvp + descp->emmd_value_offset, value, value_size);
 668                 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
 669         } else {
 670                 efx_dword_t dword;
 671
 672                 /*
 673                  * The mask/value are in host byte order.
 674                  * The MCDI request field is little endian.
 675                  */
 676                 switch (value_size) {
 677                 case 4:
 678                         EFX_POPULATE_DWORD_1(dword,
 679                             EFX_DWORD_0, *(const uint32_t *)value);
 680
 681                         memcpy(mvp + descp->emmd_value_offset,
 682                             &dword, sizeof (dword));
 683                         break;
 684                 default:
 685                         EFSYS_ASSERT(B_FALSE);
 686                 }
 687
 688                 switch (mask_size) {
 689                 case 4:
 690                         EFX_POPULATE_DWORD_1(dword,
 691                             EFX_DWORD_0, *(const uint32_t *)mask);
 692
 693                         memcpy(mvp + descp->emmd_mask_offset,
 694                             &dword, sizeof (dword));
 695                         break;
 696                 default:
 697                         EFSYS_ASSERT(B_FALSE);
 698                 }
 699         }
 700
 701         return (0);
 702
 703 fail4:
 704         EFSYS_PROBE(fail4);
 705 fail3:
 706         EFSYS_PROBE(fail3);
 707 fail2:
 708         EFSYS_PROBE(fail2);
 709 fail1:
 710         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 711         return (rc);
 712 }
 713
 714         __checkReturn                   efx_rc_t
 715 efx_mae_match_spec_mport_set(
 716         __in                            efx_mae_match_spec_t *spec,
 717         __in                            const efx_mport_sel_t *valuep,
 718         __in_opt                        const efx_mport_sel_t *maskp)
 719 {
 720         uint32_t full_mask = UINT32_MAX;
 721         const uint8_t *vp;
 722         const uint8_t *mp;
 723         efx_rc_t rc;
 724
 725         if (valuep == NULL) {
 726                 rc = EINVAL;
 727                 goto fail1;
 728         }
 729
 730         vp = (const uint8_t *)&valuep->sel;
 731         if (maskp != NULL)
 732                 mp = (const uint8_t *)&maskp->sel;
 733         else
 734                 mp = (const uint8_t *)&full_mask;
 735
 736         rc = efx_mae_match_spec_field_set(spec,
 737             EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
 738             sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
 739         if (rc != 0)
 740                 goto fail2;
 741
 742         return (0);
 743
 744 fail2:
 745         EFSYS_PROBE(fail2);
 746 fail1:
 747         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 748         return (rc);
 749 }
 750
 751         __checkReturn                   boolean_t
 752 efx_mae_match_specs_equal(
 753         __in                            const efx_mae_match_spec_t *left,
 754         __in                            const efx_mae_match_spec_t *right)
 755 {
 756         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
 757 }
 758
 759 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)              \
 760             ((_mask)[(_bit) / (_mask_page_nbits)] &                     \
 761                     (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
 762
 763 static                                  boolean_t
 764 efx_mask_is_prefix(
 765         __in                            size_t mask_nbytes,
 766         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 767 {
 768         boolean_t prev_bit_is_set = B_TRUE;
 769         unsigned int i;
 770
 771         for (i = 0; i < 8 * mask_nbytes; ++i) {
 772                 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
 773
 774                 if (!prev_bit_is_set && bit_is_set)
 775                         return B_FALSE;
 776
 777                 prev_bit_is_set = bit_is_set;
 778         }
 779
 780         return B_TRUE;
 781 }
 782
 783 static                                  boolean_t
 784 efx_mask_is_all_ones(
 785         __in                            size_t mask_nbytes,
 786         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 787 {
 788         unsigned int i;
 789         uint8_t t = ~0;
 790
 791         for (i = 0; i < mask_nbytes; ++i)
 792                 t &= maskp[i];
 793
 794         return (t == (uint8_t)(~0));
 795 }
 796
 797 static                                  boolean_t
 798 efx_mask_is_all_zeros(
 799         __in                            size_t mask_nbytes,
 800         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 801 {
 802         unsigned int i;
 803         uint8_t t = 0;
 804
 805         for (i = 0; i < mask_nbytes; ++i)
 806                 t |= maskp[i];
 807
 808         return (t == 0);
 809 }
 810
 811         __checkReturn                   boolean_t
 812 efx_mae_match_spec_is_valid(
 813         __in                            efx_nic_t *enp,
 814         __in                            const efx_mae_match_spec_t *spec)
 815 {
 816         efx_mae_t *maep = enp->en_maep;
 817         unsigned int field_ncaps = maep->em_max_nfields;
 818         const efx_mae_field_cap_t *field_caps;
 819         const efx_mae_mv_desc_t *desc_setp;
 820         unsigned int desc_set_nentries;
 821         boolean_t is_valid = B_TRUE;
 822         efx_mae_field_id_t field_id;
 823         const uint8_t *mvp;
 824
 825         switch (spec->emms_type) {
 826         case EFX_MAE_RULE_OUTER:
 827                 field_caps = maep->em_outer_rule_field_caps;
 828                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
 829                 desc_set_nentries =
 830                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
 831                 mvp = spec->emms_mask_value_pairs.outer;
 832                 break;
 833         case EFX_MAE_RULE_ACTION:
 834                 field_caps = maep->em_action_rule_field_caps;
 835                 desc_setp = __efx_mae_action_rule_mv_desc_set;
 836                 desc_set_nentries =
 837                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 838                 mvp = spec->emms_mask_value_pairs.action;
 839                 break;
 840         default:
 841                 return (B_FALSE);
 842         }
 843
 844         if (field_caps == NULL)
 845                 return (B_FALSE);
 846
 847         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
 848                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
 849                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
 850                 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
 851                 size_t m_size = descp->emmd_mask_size;
 852
 853                 if (m_size == 0)
 854                         continue; /* Skip array gap */
 855
 856                 if (field_cap_id >= field_ncaps)
 857                         break;
 858
 859                 switch (field_caps[field_cap_id].emfc_support) {
 860                 case MAE_FIELD_SUPPORTED_MATCH_MASK:
 861                         is_valid = B_TRUE;
 862                         break;
 863                 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
 864                         is_valid = efx_mask_is_prefix(m_size, m_buf);
 865                         break;
 866                 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
 867                         is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
 868                             efx_mask_is_all_zeros(m_size, m_buf));
 869                         break;
 870                 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
 871                         is_valid = efx_mask_is_all_ones(m_size, m_buf);
 872                         break;
 873                 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
 874                 case MAE_FIELD_UNSUPPORTED:
 875                 default:
 876                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
 877                         break;
 878                 }
 879
 880                 if (is_valid == B_FALSE)
 881                         break;
 882         }
 883
 884         return (is_valid);
 885 }
 886
 887         __checkReturn                   efx_rc_t
 888 efx_mae_action_set_spec_init(
 889         __in                            efx_nic_t *enp,
 890         __out                           efx_mae_actions_t **specp)
 891 {
 892         efx_mae_actions_t *spec;
 893         efx_rc_t rc;
 894
 895         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 896         if (spec == NULL) {
 897                 rc = ENOMEM;
 898                 goto fail1;
 899         }
 900
 901         *specp = spec;
 902
 903         return (0);
 904
 905 fail1:
 906         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 907         return (rc);
 908 }
 909
 910                                         void
 911 efx_mae_action_set_spec_fini(
 912         __in                            efx_nic_t *enp,
 913         __in                            efx_mae_actions_t *spec)
 914 {
 915         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 916 }
 917
 918 static  __checkReturn                   efx_rc_t
 919 efx_mae_action_set_add_vlan_pop(
 920         __in                            efx_mae_actions_t *spec,
 921         __in                            size_t arg_size,
 922         __in_bcount(arg_size)           const uint8_t *arg)
 923 {
 924         efx_rc_t rc;
 925
 926         if (arg_size != 0) {
 927                 rc = EINVAL;
 928                 goto fail1;
 929         }
 930
 931         if (arg != NULL) {
 932                 rc = EINVAL;
 933                 goto fail2;
 934         }
 935
 936         if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
 937                 rc = ENOTSUP;
 938                 goto fail3;
 939         }
 940
 941         ++spec->ema_n_vlan_tags_to_pop;
 942
 943         return (0);
 944
 945 fail3:
 946         EFSYS_PROBE(fail3);
 947 fail2:
 948         EFSYS_PROBE(fail2);
 949 fail1:
 950         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 951         return (rc);
 952 }
 953
 954 static  __checkReturn                   efx_rc_t
 955 efx_mae_action_set_add_vlan_push(
 956         __in                            efx_mae_actions_t *spec,
 957         __in                            size_t arg_size,
 958         __in_bcount(arg_size)           const uint8_t *arg)
 959 {
 960         unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
 961         efx_rc_t rc;
 962
 963         if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
 964                 rc = EINVAL;
 965                 goto fail1;
 966         }
 967
 968         if (arg == NULL) {
 969                 rc = EINVAL;
 970                 goto fail2;
 971         }
 972
 973         if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
 974                 rc = ENOTSUP;
 975                 goto fail3;
 976         }
 977
 978         memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
 979         ++(spec->ema_n_vlan_tags_to_push);
 980
 981         return (0);
 982
 983 fail3:
 984         EFSYS_PROBE(fail3);
 985 fail2:
 986         EFSYS_PROBE(fail2);
 987 fail1:
 988         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 989         return (rc);
 990 }
 991
 992 static  __checkReturn                   efx_rc_t
 993 efx_mae_action_set_add_flag(
 994         __in                            efx_mae_actions_t *spec,
 995         __in                            size_t arg_size,
 996         __in_bcount(arg_size)           const uint8_t *arg)
 997 {
 998         efx_rc_t rc;
 999
1000         _NOTE(ARGUNUSED(spec))
1001
1002         if (arg_size != 0) {
1003                 rc = EINVAL;
1004                 goto fail1;
1005         }
1006
1007         if (arg != NULL) {
1008                 rc = EINVAL;
1009                 goto fail2;
1010         }
1011
1012         /* This action does not have any arguments, so do nothing here. */
1013
1014         return (0);
1015
1016 fail2:
1017         EFSYS_PROBE(fail2);
1018 fail1:
1019         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1020         return (rc);
1021 }
1022
1023 static  __checkReturn                   efx_rc_t
1024 efx_mae_action_set_add_mark(
1025         __in                            efx_mae_actions_t *spec,
1026         __in                            size_t arg_size,
1027         __in_bcount(arg_size)           const uint8_t *arg)
1028 {
1029         efx_rc_t rc;
1030
1031         if (arg_size != sizeof (spec->ema_mark_value)) {
1032                 rc = EINVAL;
1033                 goto fail1;
1034         }
1035
1036         if (arg == NULL) {
1037                 rc = EINVAL;
1038                 goto fail2;
1039         }
1040
1041         memcpy(&spec->ema_mark_value, arg, arg_size);
1042
1043         return (0);
1044
1045 fail2:
1046         EFSYS_PROBE(fail2);
1047 fail1:
1048         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1049         return (rc);
1050 }
1051
1052 static  __checkReturn                   efx_rc_t
1053 efx_mae_action_set_add_deliver(
1054         __in                            efx_mae_actions_t *spec,
1055         __in                            size_t arg_size,
1056         __in_bcount(arg_size)           const uint8_t *arg)
1057 {
1058         efx_rc_t rc;
1059
1060         if (arg_size != sizeof (spec->ema_deliver_mport)) {
1061                 rc = EINVAL;
1062                 goto fail1;
1063         }
1064
1065         if (arg == NULL) {
1066                 rc = EINVAL;
1067                 goto fail2;
1068         }
1069
1070         memcpy(&spec->ema_deliver_mport, arg, arg_size);
1071
1072         return (0);
1073
1074 fail2:
1075         EFSYS_PROBE(fail2);
1076 fail1:
1077         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1078         return (rc);
1079 }
1080
1081 typedef struct efx_mae_action_desc_s {
1082         /* Action specific handler */
1083         efx_rc_t        (*emad_add)(efx_mae_actions_t *,
1084                                     size_t, const uint8_t *);
1085 } efx_mae_action_desc_t;
1086
1087 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
1088         [EFX_MAE_ACTION_VLAN_POP] = {
1089                 .emad_add = efx_mae_action_set_add_vlan_pop
1090         },
1091         [EFX_MAE_ACTION_VLAN_PUSH] = {
1092                 .emad_add = efx_mae_action_set_add_vlan_push
1093         },
1094         [EFX_MAE_ACTION_FLAG] = {
1095                 .emad_add = efx_mae_action_set_add_flag
1096         },
1097         [EFX_MAE_ACTION_MARK] = {
1098                 .emad_add = efx_mae_action_set_add_mark
1099         },
1100         [EFX_MAE_ACTION_DELIVER] = {
1101                 .emad_add = efx_mae_action_set_add_deliver
1102         }
1103 };
1104
1105 static const uint32_t efx_mae_action_ordered_map =
1106         (1U << EFX_MAE_ACTION_VLAN_POP) |
1107         (1U << EFX_MAE_ACTION_VLAN_PUSH) |
1108         (1U << EFX_MAE_ACTION_FLAG) |
1109         (1U << EFX_MAE_ACTION_MARK) |
1110         (1U << EFX_MAE_ACTION_DELIVER);
1111
1112 /*
1113  * These actions must not be added after DELIVER, but
1114  * they can have any place among the rest of
1115  * strictly ordered actions.
1116  */
1117 static const uint32_t efx_mae_action_nonstrict_map =
1118         (1U << EFX_MAE_ACTION_FLAG) |
1119         (1U << EFX_MAE_ACTION_MARK);
1120
1121 static const uint32_t efx_mae_action_repeat_map =
1122         (1U << EFX_MAE_ACTION_VLAN_POP) |
1123         (1U << EFX_MAE_ACTION_VLAN_PUSH);
1124
1125 /*
1126  * Add an action to an action set.
1127  *
1128  * This has to be invoked in the desired action order.
1129  * An out-of-order action request will be turned down.
1130  */
1131 static  __checkReturn                   efx_rc_t
1132 efx_mae_action_set_spec_populate(
1133         __in                            efx_mae_actions_t *spec,
1134         __in                            efx_mae_action_t type,
1135         __in                            size_t arg_size,
1136         __in_bcount(arg_size)           const uint8_t *arg)
1137 {
1138         uint32_t action_mask;
1139         efx_rc_t rc;
1140
1141         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1142             (sizeof (efx_mae_action_ordered_map) * 8));
1143         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1144             (sizeof (efx_mae_action_repeat_map) * 8));
1145
1146         EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1147         EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1148         EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1149
1150         if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1151                 rc = EINVAL;
1152                 goto fail1;
1153         }
1154
1155         action_mask = (1U << type);
1156
1157         if ((spec->ema_actions & action_mask) != 0) {
1158                 /* The action set already contains this action. */
1159                 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1160                         /* Cannot add another non-repeatable action. */
1161                         rc = ENOTSUP;
1162                         goto fail2;
1163                 }
1164         }
1165
1166         if ((efx_mae_action_ordered_map & action_mask) != 0) {
1167                 uint32_t strict_ordered_map =
1168                     efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1169                 uint32_t later_actions_mask =
1170                     strict_ordered_map & ~(action_mask | (action_mask - 1));
1171
1172                 if ((spec->ema_actions & later_actions_mask) != 0) {
1173                         /* Cannot add an action after later ordered actions. */
1174                         rc = ENOTSUP;
1175                         goto fail3;
1176                 }
1177         }
1178
1179         if (efx_mae_actions[type].emad_add != NULL) {
1180                 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1181                 if (rc != 0)
1182                         goto fail4;
1183         }
1184
1185         spec->ema_actions |= action_mask;
1186
1187         return (0);
1188
1189 fail4:
1190         EFSYS_PROBE(fail4);
1191 fail3:
1192         EFSYS_PROBE(fail3);
1193 fail2:
1194         EFSYS_PROBE(fail2);
1195 fail1:
1196         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1197         return (rc);
1198 }
1199
1200         __checkReturn                   efx_rc_t
1201 efx_mae_action_set_populate_vlan_pop(
1202         __in                            efx_mae_actions_t *spec)
1203 {
1204         return (efx_mae_action_set_spec_populate(spec,
1205             EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1206 }
1207
1208         __checkReturn                   efx_rc_t
1209 efx_mae_action_set_populate_vlan_push(
1210         __in                            efx_mae_actions_t *spec,
1211         __in                            uint16_t tpid_be,
1212         __in                            uint16_t tci_be)
1213 {
1214         efx_mae_action_vlan_push_t action;
1215         const uint8_t *arg = (const uint8_t *)&action;
1216
1217         action.emavp_tpid_be = tpid_be;
1218         action.emavp_tci_be = tci_be;
1219
1220         return (efx_mae_action_set_spec_populate(spec,
1221             EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1222 }
1223
1224         __checkReturn                   efx_rc_t
1225 efx_mae_action_set_populate_flag(
1226         __in                            efx_mae_actions_t *spec)
1227 {
1228         return (efx_mae_action_set_spec_populate(spec,
1229             EFX_MAE_ACTION_FLAG, 0, NULL));
1230 }
1231
1232         __checkReturn                   efx_rc_t
1233 efx_mae_action_set_populate_mark(
1234         __in                            efx_mae_actions_t *spec,
1235         __in                            uint32_t mark_value)
1236 {
1237         const uint8_t *arg = (const uint8_t *)&mark_value;
1238
1239         return (efx_mae_action_set_spec_populate(spec,
1240             EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1241 }
1242
1243         __checkReturn                   efx_rc_t
1244 efx_mae_action_set_populate_deliver(
1245         __in                            efx_mae_actions_t *spec,
1246         __in                            const efx_mport_sel_t *mportp)
1247 {
1248         const uint8_t *arg;
1249         efx_rc_t rc;
1250
1251         if (mportp == NULL) {
1252                 rc = EINVAL;
1253                 goto fail1;
1254         }
1255
1256         arg = (const uint8_t *)&mportp->sel;
1257
1258         return (efx_mae_action_set_spec_populate(spec,
1259             EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1260
1261 fail1:
1262         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1263         return (rc);
1264 }
1265
1266         __checkReturn                   efx_rc_t
1267 efx_mae_action_set_populate_drop(
1268         __in                            efx_mae_actions_t *spec)
1269 {
1270         efx_mport_sel_t mport;
1271         const uint8_t *arg;
1272         efx_dword_t dword;
1273
1274         EFX_POPULATE_DWORD_1(dword,
1275             MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1276
1277         mport.sel = dword.ed_u32[0];
1278
1279         arg = (const uint8_t *)&mport.sel;
1280
1281         return (efx_mae_action_set_spec_populate(spec,
1282             EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1283 }
1284
1285         __checkReturn                   boolean_t
1286 efx_mae_action_set_specs_equal(
1287         __in                            const efx_mae_actions_t *left,
1288         __in                            const efx_mae_actions_t *right)
1289 {
1290         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1291 }
1292
1293         __checkReturn                   efx_rc_t
1294 efx_mae_match_specs_class_cmp(
1295         __in                            efx_nic_t *enp,
1296         __in                            const efx_mae_match_spec_t *left,
1297         __in                            const efx_mae_match_spec_t *right,
1298         __out                           boolean_t *have_same_classp)
1299 {
1300         efx_mae_t *maep = enp->en_maep;
1301         unsigned int field_ncaps = maep->em_max_nfields;
1302         const efx_mae_field_cap_t *field_caps;
1303         const efx_mae_mv_desc_t *desc_setp;
1304         unsigned int desc_set_nentries;
1305         boolean_t have_same_class = B_TRUE;
1306         efx_mae_field_id_t field_id;
1307         const uint8_t *mvpl;
1308         const uint8_t *mvpr;
1309         efx_rc_t rc;
1310
1311         switch (left->emms_type) {
1312         case EFX_MAE_RULE_OUTER:
1313                 field_caps = maep->em_outer_rule_field_caps;
1314                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
1315                 desc_set_nentries =
1316                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
1317                 mvpl = left->emms_mask_value_pairs.outer;
1318                 mvpr = right->emms_mask_value_pairs.outer;
1319                 break;
1320         case EFX_MAE_RULE_ACTION:
1321                 field_caps = maep->em_action_rule_field_caps;
1322                 desc_setp = __efx_mae_action_rule_mv_desc_set;
1323                 desc_set_nentries =
1324                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1325                 mvpl = left->emms_mask_value_pairs.action;
1326                 mvpr = right->emms_mask_value_pairs.action;
1327                 break;
1328         default:
1329                 rc = ENOTSUP;
1330                 goto fail1;
1331         }
1332
1333         if (field_caps == NULL) {
1334                 rc = EAGAIN;
1335                 goto fail2;
1336         }
1337
1338         if (left->emms_type != right->emms_type ||
1339             left->emms_prio != right->emms_prio) {
1340                 /*
1341                  * Rules of different types can never map to the same class.
1342                  *
1343                  * The FW can support some set of match criteria for one
1344                  * priority and not support the very same set for
1345                  * another priority. Thus, two rules which have
1346                  * different priorities can never map to
1347                  * the same class.
1348                  */
1349                 *have_same_classp = B_FALSE;
1350                 return (0);
1351         }
1352
1353         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
1354                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1355                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1356
1357                 if (descp->emmd_mask_size == 0)
1358                         continue; /* Skip array gap */
1359
1360                 if (field_cap_id >= field_ncaps)
1361                         break;
1362
1363                 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1364                         const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1365                         const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1366                         size_t mask_size = descp->emmd_mask_size;
1367
1368                         if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1369                                 have_same_class = B_FALSE;
1370                                 break;
1371                         }
1372                 }
1373
1374                 if (field_caps[field_cap_id].emfc_match_affects_class) {
1375                         const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1376                         const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1377                         size_t value_size = descp->emmd_value_size;
1378
1379                         if (memcmp(lvalp, rvalp, value_size) != 0) {
1380                                 have_same_class = B_FALSE;
1381                                 break;
1382                         }
1383                 }
1384         }
1385
1386         *have_same_classp = have_same_class;
1387
1388         return (0);
1389
1390 fail2:
1391         EFSYS_PROBE(fail2);
1392 fail1:
1393         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1394         return (rc);
1395 }
1396
1397         __checkReturn           efx_rc_t
1398 efx_mae_outer_rule_insert(
1399         __in                    efx_nic_t *enp,
1400         __in                    const efx_mae_match_spec_t *spec,
1401         __in                    efx_tunnel_protocol_t encap_type,
1402         __out                   efx_mae_rule_id_t *or_idp)
1403 {
1404         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1405         efx_mcdi_req_t req;
1406         EFX_MCDI_DECLARE_BUF(payload,
1407             MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,
1408             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);
1409         uint32_t encap_type_mcdi;
1410         efx_mae_rule_id_t or_id;
1411         size_t offset;
1412         efx_rc_t rc;
1413
1414         EFX_STATIC_ASSERT(sizeof (or_idp->id) ==
1415             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);
1416
1417         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1418             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);
1419
1420         if (encp->enc_mae_supported == B_FALSE) {
1421                 rc = ENOTSUP;
1422                 goto fail1;
1423         }
1424
1425         if (spec->emms_type != EFX_MAE_RULE_OUTER) {
1426                 rc = EINVAL;
1427                 goto fail2;
1428         }
1429
1430         switch (encap_type) {
1431         case EFX_TUNNEL_PROTOCOL_NONE:
1432                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
1433                 break;
1434         case EFX_TUNNEL_PROTOCOL_VXLAN:
1435                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
1436                 break;
1437         case EFX_TUNNEL_PROTOCOL_GENEVE:
1438                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
1439                 break;
1440         case EFX_TUNNEL_PROTOCOL_NVGRE:
1441                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
1442                 break;
1443         default:
1444                 rc = ENOTSUP;
1445                 goto fail3;
1446         }
1447
1448         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;
1449         req.emr_in_buf = payload;
1450         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;
1451         req.emr_out_buf = payload;
1452         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;
1453
1454         MCDI_IN_SET_DWORD(req,
1455             MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);
1456
1457         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);
1458
1459         /*
1460          * Mask-value pairs have been stored in the byte order needed for the
1461          * MCDI request and are thus safe to be copied directly to the buffer.
1462          * The library cares about byte order in efx_mae_match_spec_field_set().
1463          */
1464         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=
1465             MAE_ENC_FIELD_PAIRS_LEN);
1466         offset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;
1467         memcpy(payload + offset, spec->emms_mask_value_pairs.outer,
1468             MAE_ENC_FIELD_PAIRS_LEN);
1469
1470         efx_mcdi_execute(enp, &req);
1471
1472         if (req.emr_rc != 0) {
1473                 rc = req.emr_rc;
1474                 goto fail4;
1475         }
1476
1477         if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {
1478                 rc = EMSGSIZE;
1479                 goto fail5;
1480         }
1481
1482         or_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);
1483         if (or_id.id == EFX_MAE_RSRC_ID_INVALID) {
1484                 rc = ENOENT;
1485                 goto fail6;
1486         }
1487
1488         or_idp->id = or_id.id;
1489
1490         return (0);
1491
1492 fail6:
1493         EFSYS_PROBE(fail6);
1494 fail5:
1495         EFSYS_PROBE(fail5);
1496 fail4:
1497         EFSYS_PROBE(fail4);
1498 fail3:
1499         EFSYS_PROBE(fail3);
1500 fail2:
1501         EFSYS_PROBE(fail2);
1502 fail1:
1503         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1504         return (rc);
1505 }
1506
1507         __checkReturn           efx_rc_t
1508 efx_mae_outer_rule_remove(
1509         __in                    efx_nic_t *enp,
1510         __in                    const efx_mae_rule_id_t *or_idp)
1511 {
1512         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1513         efx_mcdi_req_t req;
1514         EFX_MCDI_DECLARE_BUF(payload,
1515             MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),
1516             MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));
1517         efx_rc_t rc;
1518
1519         if (encp->enc_mae_supported == B_FALSE) {
1520                 rc = ENOTSUP;
1521                 goto fail1;
1522         }
1523
1524         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;
1525         req.emr_in_buf = payload;
1526         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);
1527         req.emr_out_buf = payload;
1528         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);
1529
1530         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);
1531
1532         efx_mcdi_execute(enp, &req);
1533
1534         if (req.emr_rc != 0) {
1535                 rc = req.emr_rc;
1536                 goto fail2;
1537         }
1538
1539         if (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=
1540             or_idp->id) {
1541                 /* Firmware failed to remove the outer rule. */
1542                 rc = EAGAIN;
1543                 goto fail3;
1544         }
1545
1546         return (0);
1547
1548 fail3:
1549         EFSYS_PROBE(fail3);
1550 fail2:
1551         EFSYS_PROBE(fail2);
1552 fail1:
1553         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1554         return (rc);
1555 }
1556
1557         __checkReturn                   efx_rc_t
1558 efx_mae_match_spec_outer_rule_id_set(
1559         __in                            efx_mae_match_spec_t *spec,
1560         __in                            const efx_mae_rule_id_t *or_idp)
1561 {
1562         uint32_t full_mask = UINT32_MAX;
1563         efx_rc_t rc;
1564
1565         if (spec->emms_type != EFX_MAE_RULE_ACTION) {
1566                 rc = EINVAL;
1567                 goto fail1;
1568         }
1569
1570         if (or_idp == NULL) {
1571                 rc = EINVAL;
1572                 goto fail2;
1573         }
1574
1575         rc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,
1576             sizeof (or_idp->id), (const uint8_t *)&or_idp->id,
1577             sizeof (full_mask), (const uint8_t *)&full_mask);
1578         if (rc != 0)
1579                 goto fail3;
1580
1581         return (0);
1582
1583 fail3:
1584         EFSYS_PROBE(fail3);
1585 fail2:
1586         EFSYS_PROBE(fail2);
1587 fail1:
1588         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1589         return (rc);
1590 }
1591
1592         __checkReturn                   efx_rc_t
1593 efx_mae_action_set_alloc(
1594         __in                            efx_nic_t *enp,
1595         __in                            const efx_mae_actions_t *spec,
1596         __out                           efx_mae_aset_id_t *aset_idp)
1597 {
1598         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1599         efx_mcdi_req_t req;
1600         EFX_MCDI_DECLARE_BUF(payload,
1601             MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1602             MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1603         efx_mae_aset_id_t aset_id;
1604         efx_rc_t rc;
1605
1606         if (encp->enc_mae_supported == B_FALSE) {
1607                 rc = ENOTSUP;
1608                 goto fail1;
1609         }
1610
1611         req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1612         req.emr_in_buf = payload;
1613         req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1614         req.emr_out_buf = payload;
1615         req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1616
1617         /*
1618          * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1619          * corresponding resource types are supported by the implementation.
1620          * Use proper resource ID assignments instead.
1621          */
1622         MCDI_IN_SET_DWORD(req,
1623             MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1624         MCDI_IN_SET_DWORD(req,
1625             MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1626         MCDI_IN_SET_DWORD(req,
1627             MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1628
1629         MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1630             MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1631
1632         if (spec->ema_n_vlan_tags_to_push > 0) {
1633                 unsigned int outer_tag_idx;
1634
1635                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1636                     MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1637                     spec->ema_n_vlan_tags_to_push);
1638
1639                 if (spec->ema_n_vlan_tags_to_push ==
1640                     EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1641                         MCDI_IN_SET_WORD(req,
1642                             MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1643                             spec->ema_vlan_push_descs[0].emavp_tpid_be);
1644                         MCDI_IN_SET_WORD(req,
1645                             MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1646                             spec->ema_vlan_push_descs[0].emavp_tci_be);
1647                 }
1648
1649                 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1650
1651                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1652                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1653                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1654                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1655         }
1656
1657         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1658                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1659                     MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1660         }
1661
1662         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1663                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1664                     MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1665
1666                 MCDI_IN_SET_DWORD(req,
1667                     MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1668         }
1669
1670         MCDI_IN_SET_DWORD(req,
1671             MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1672
1673         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1674             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1675         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1676             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1677
1678         efx_mcdi_execute(enp, &req);
1679
1680         if (req.emr_rc != 0) {
1681                 rc = req.emr_rc;
1682                 goto fail2;
1683         }
1684
1685         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1686                 rc = EMSGSIZE;
1687                 goto fail3;
1688         }
1689
1690         aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1691         if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1692                 rc = ENOENT;
1693                 goto fail4;
1694         }
1695
1696         aset_idp->id = aset_id.id;
1697
1698         return (0);
1699
1700 fail4:
1701         EFSYS_PROBE(fail4);
1702 fail3:
1703         EFSYS_PROBE(fail3);
1704 fail2:
1705         EFSYS_PROBE(fail2);
1706 fail1:
1707         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1708         return (rc);
1709 }
1710
1711         __checkReturn                   efx_rc_t
1712 efx_mae_action_set_free(
1713         __in                            efx_nic_t *enp,
1714         __in                            const efx_mae_aset_id_t *aset_idp)
1715 {
1716         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1717         efx_mcdi_req_t req;
1718         EFX_MCDI_DECLARE_BUF(payload,
1719             MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1720             MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1721         efx_rc_t rc;
1722
1723         if (encp->enc_mae_supported == B_FALSE) {
1724                 rc = ENOTSUP;
1725                 goto fail1;
1726         }
1727
1728         req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1729         req.emr_in_buf = payload;
1730         req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1731         req.emr_out_buf = payload;
1732         req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1733
1734         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1735
1736         efx_mcdi_execute(enp, &req);
1737
1738         if (req.emr_rc != 0) {
1739                 rc = req.emr_rc;
1740                 goto fail2;
1741         }
1742
1743         if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1744             aset_idp->id) {
1745                 /* Firmware failed to free the action set. */
1746                 rc = EAGAIN;
1747                 goto fail3;
1748         }
1749
1750         return (0);
1751
1752 fail3:
1753         EFSYS_PROBE(fail3);
1754 fail2:
1755         EFSYS_PROBE(fail2);
1756 fail1:
1757         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1758         return (rc);
1759 }
1760
1761         __checkReturn                   efx_rc_t
1762 efx_mae_action_rule_insert(
1763         __in                            efx_nic_t *enp,
1764         __in                            const efx_mae_match_spec_t *spec,
1765         __in                            const efx_mae_aset_list_id_t *asl_idp,
1766         __in                            const efx_mae_aset_id_t *as_idp,
1767         __out                           efx_mae_rule_id_t *ar_idp)
1768 {
1769         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1770         efx_mcdi_req_t req;
1771         EFX_MCDI_DECLARE_BUF(payload,
1772             MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1773             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1774         efx_oword_t *rule_response;
1775         efx_mae_rule_id_t ar_id;
1776         size_t offset;
1777         efx_rc_t rc;
1778
1779         EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1780             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1781
1782         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1783             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1784
1785         if (encp->enc_mae_supported == B_FALSE) {
1786                 rc = ENOTSUP;
1787                 goto fail1;
1788         }
1789
1790         if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1791             (asl_idp != NULL && as_idp != NULL) ||
1792             (asl_idp == NULL && as_idp == NULL)) {
1793                 rc = EINVAL;
1794                 goto fail2;
1795         }
1796
1797         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1798         req.emr_in_buf = payload;
1799         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1800         req.emr_out_buf = payload;
1801         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1802
1803         EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1804             MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1805         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1806         rule_response = (efx_oword_t *)(payload + offset);
1807         EFX_POPULATE_OWORD_3(*rule_response,
1808             MAE_ACTION_RULE_RESPONSE_ASL_ID,
1809             (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1810             MAE_ACTION_RULE_RESPONSE_AS_ID,
1811             (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1812             MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1813
1814         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1815
1816         /*
1817          * Mask-value pairs have been stored in the byte order needed for the
1818          * MCDI request and are thus safe to be copied directly to the buffer.
1819          */
1820         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1821             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1822         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1823         memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1824             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1825
1826         efx_mcdi_execute(enp, &req);
1827
1828         if (req.emr_rc != 0) {
1829                 rc = req.emr_rc;
1830                 goto fail3;
1831         }
1832
1833         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1834                 rc = EMSGSIZE;
1835                 goto fail4;
1836         }
1837
1838         ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1839         if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1840                 rc = ENOENT;
1841                 goto fail5;
1842         }
1843
1844         ar_idp->id = ar_id.id;
1845
1846         return (0);
1847
1848 fail5:
1849         EFSYS_PROBE(fail5);
1850 fail4:
1851         EFSYS_PROBE(fail4);
1852 fail3:
1853         EFSYS_PROBE(fail3);
1854 fail2:
1855         EFSYS_PROBE(fail2);
1856 fail1:
1857         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1858         return (rc);
1859 }
1860
1861         __checkReturn                   efx_rc_t
1862 efx_mae_action_rule_remove(
1863         __in                            efx_nic_t *enp,
1864         __in                            const efx_mae_rule_id_t *ar_idp)
1865 {
1866         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1867         efx_mcdi_req_t req;
1868         EFX_MCDI_DECLARE_BUF(payload,
1869             MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1870             MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1871         efx_rc_t rc;
1872
1873         if (encp->enc_mae_supported == B_FALSE) {
1874                 rc = ENOTSUP;
1875                 goto fail1;
1876         }
1877
1878         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1879         req.emr_in_buf = payload;
1880         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1881         req.emr_out_buf = payload;
1882         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1883
1884         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1885
1886         efx_mcdi_execute(enp, &req);
1887
1888         if (req.emr_rc != 0) {
1889                 rc = req.emr_rc;
1890                 goto fail2;
1891         }
1892
1893         if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1894             ar_idp->id) {
1895                 /* Firmware failed to delete the action rule. */
1896                 rc = EAGAIN;
1897                 goto fail3;
1898         }
1899
1900         return (0);
1901
1902 fail3:
1903         EFSYS_PROBE(fail3);
1904 fail2:
1905         EFSYS_PROBE(fail2);
1906 fail1:
1907         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1908         return (rc);
1909 }
1910
1911 #endif /* EFSYS_OPT_MAE */