drivers/common/sfc_efx/base/efx_mae.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_MAE
  12
  13 static  __checkReturn                   efx_rc_t
  14 efx_mae_get_capabilities(
  15         __in                            efx_nic_t *enp)
  16 {
  17         efx_mcdi_req_t req;
  18         EFX_MCDI_DECLARE_BUF(payload,
  19             MC_CMD_MAE_GET_CAPS_IN_LEN,
  20             MC_CMD_MAE_GET_CAPS_OUT_LEN);
  21         struct efx_mae_s *maep = enp->en_maep;
  22         efx_rc_t rc;
  23
  24         req.emr_cmd = MC_CMD_MAE_GET_CAPS;
  25         req.emr_in_buf = payload;
  26         req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
  27         req.emr_out_buf = payload;
  28         req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
  29
  30         efx_mcdi_execute(enp, &req);
  31
  32         if (req.emr_rc != 0) {
  33                 rc = req.emr_rc;
  34                 goto fail1;
  35         }
  36
  37         if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
  38                 rc = EMSGSIZE;
  39                 goto fail2;
  40         }
  41
  42         maep->em_max_n_outer_prios =
  43             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
  44
  45         maep->em_max_n_action_prios =
  46             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
  47
  48         maep->em_encap_types_supported = 0;
  49
  50         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
  51                 maep->em_encap_types_supported |=
  52                     (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
  53         }
  54
  55         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
  56                 maep->em_encap_types_supported |=
  57                     (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
  58         }
  59
  60         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
  61                 maep->em_encap_types_supported |=
  62                     (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
  63         }
  64
  65         maep->em_max_nfields =
  66             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
  67
  68         return (0);
  69
  70 fail2:
  71         EFSYS_PROBE(fail2);
  72 fail1:
  73         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  74         return (rc);
  75 }
  76
  77 static  __checkReturn                   efx_rc_t
  78 efx_mae_get_outer_rule_caps(
  79         __in                            efx_nic_t *enp,
  80         __in                            unsigned int field_ncaps,
  81         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
  82 {
  83         efx_mcdi_req_t req;
  84         EFX_MCDI_DECLARE_BUF(payload,
  85             MC_CMD_MAE_GET_OR_CAPS_IN_LEN,
  86             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2);
  87         unsigned int mcdi_field_ncaps;
  88         unsigned int i;
  89         efx_rc_t rc;
  90
  91         if (MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps) >
  92             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2) {
  93                 rc = EINVAL;
  94                 goto fail1;
  95         }
  96
  97         req.emr_cmd = MC_CMD_MAE_GET_OR_CAPS;
  98         req.emr_in_buf = payload;
  99         req.emr_in_length = MC_CMD_MAE_GET_OR_CAPS_IN_LEN;
 100         req.emr_out_buf = payload;
 101         req.emr_out_length = MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps);
 102
 103         efx_mcdi_execute(enp, &req);
 104
 105         if (req.emr_rc != 0) {
 106                 rc = req.emr_rc;
 107                 goto fail2;
 108         }
 109
 110         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 111
 112         if (req.emr_out_length_used <
 113             MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 114                 rc = EMSGSIZE;
 115                 goto fail3;
 116         }
 117
 118         if (mcdi_field_ncaps > field_ncaps) {
 119                 rc = EMSGSIZE;
 120                 goto fail4;
 121         }
 122
 123         for (i = 0; i < mcdi_field_ncaps; ++i) {
 124                 uint32_t match_flag;
 125                 uint32_t mask_flag;
 126
 127                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 128                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 129                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 130
 131                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 132                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 133                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 134
 135                 field_caps[i].emfc_match_affects_class =
 136                     (match_flag != 0) ? B_TRUE : B_FALSE;
 137
 138                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 139                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 140                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 141
 142                 field_caps[i].emfc_mask_affects_class =
 143                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 144         }
 145
 146         return (0);
 147
 148 fail4:
 149         EFSYS_PROBE(fail4);
 150 fail3:
 151         EFSYS_PROBE(fail3);
 152 fail2:
 153         EFSYS_PROBE(fail2);
 154 fail1:
 155         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 156         return (rc);
 157 }
 158
 159 static  __checkReturn                   efx_rc_t
 160 efx_mae_get_action_rule_caps(
 161         __in                            efx_nic_t *enp,
 162         __in                            unsigned int field_ncaps,
 163         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
 164 {
 165         efx_mcdi_req_t req;
 166         EFX_MCDI_DECLARE_BUF(payload,
 167             MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
 168             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
 169         unsigned int mcdi_field_ncaps;
 170         unsigned int i;
 171         efx_rc_t rc;
 172
 173         if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
 174             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
 175                 rc = EINVAL;
 176                 goto fail1;
 177         }
 178
 179         req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
 180         req.emr_in_buf = payload;
 181         req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
 182         req.emr_out_buf = payload;
 183         req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
 184
 185         efx_mcdi_execute(enp, &req);
 186
 187         if (req.emr_rc != 0) {
 188                 rc = req.emr_rc;
 189                 goto fail2;
 190         }
 191
 192         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 193
 194         if (req.emr_out_length_used <
 195             MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 196                 rc = EMSGSIZE;
 197                 goto fail3;
 198         }
 199
 200         if (mcdi_field_ncaps > field_ncaps) {
 201                 rc = EMSGSIZE;
 202                 goto fail4;
 203         }
 204
 205         for (i = 0; i < mcdi_field_ncaps; ++i) {
 206                 uint32_t match_flag;
 207                 uint32_t mask_flag;
 208
 209                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 210                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 211                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 212
 213                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 214                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 215                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 216
 217                 field_caps[i].emfc_match_affects_class =
 218                     (match_flag != 0) ? B_TRUE : B_FALSE;
 219
 220                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 221                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 222                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 223
 224                 field_caps[i].emfc_mask_affects_class =
 225                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 226         }
 227
 228         return (0);
 229
 230 fail4:
 231         EFSYS_PROBE(fail4);
 232 fail3:
 233         EFSYS_PROBE(fail3);
 234 fail2:
 235         EFSYS_PROBE(fail2);
 236 fail1:
 237         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 238         return (rc);
 239 }
 240
 241         __checkReturn                   efx_rc_t
 242 efx_mae_init(
 243         __in                            efx_nic_t *enp)
 244 {
 245         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 246         efx_mae_field_cap_t *or_fcaps;
 247         size_t or_fcaps_size;
 248         efx_mae_field_cap_t *ar_fcaps;
 249         size_t ar_fcaps_size;
 250         efx_mae_t *maep;
 251         efx_rc_t rc;
 252
 253         if (encp->enc_mae_supported == B_FALSE) {
 254                 rc = ENOTSUP;
 255                 goto fail1;
 256         }
 257
 258         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
 259         if (maep == NULL) {
 260                 rc = ENOMEM;
 261                 goto fail2;
 262         }
 263
 264         enp->en_maep = maep;
 265
 266         rc = efx_mae_get_capabilities(enp);
 267         if (rc != 0)
 268                 goto fail3;
 269
 270         or_fcaps_size = maep->em_max_nfields * sizeof (*or_fcaps);
 271         EFSYS_KMEM_ALLOC(enp->en_esip, or_fcaps_size, or_fcaps);
 272         if (or_fcaps == NULL) {
 273                 rc = ENOMEM;
 274                 goto fail4;
 275         }
 276
 277         maep->em_outer_rule_field_caps_size = or_fcaps_size;
 278         maep->em_outer_rule_field_caps = or_fcaps;
 279
 280         rc = efx_mae_get_outer_rule_caps(enp, maep->em_max_nfields, or_fcaps);
 281         if (rc != 0)
 282                 goto fail5;
 283
 284         ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
 285         EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
 286         if (ar_fcaps == NULL) {
 287                 rc = ENOMEM;
 288                 goto fail6;
 289         }
 290
 291         maep->em_action_rule_field_caps_size = ar_fcaps_size;
 292         maep->em_action_rule_field_caps = ar_fcaps;
 293
 294         rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
 295         if (rc != 0)
 296                 goto fail7;
 297
 298         return (0);
 299
 300 fail7:
 301         EFSYS_PROBE(fail5);
 302         EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
 303 fail6:
 304         EFSYS_PROBE(fail4);
 305 fail5:
 306         EFSYS_PROBE(fail5);
 307         EFSYS_KMEM_FREE(enp->en_esip, or_fcaps_size, or_fcaps);
 308 fail4:
 309         EFSYS_PROBE(fail4);
 310 fail3:
 311         EFSYS_PROBE(fail3);
 312         EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
 313         enp->en_maep = NULL;
 314 fail2:
 315         EFSYS_PROBE(fail2);
 316 fail1:
 317         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 318         return (rc);
 319 }
 320
 321                                         void
 322 efx_mae_fini(
 323         __in                            efx_nic_t *enp)
 324 {
 325         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 326         efx_mae_t *maep = enp->en_maep;
 327
 328         if (encp->enc_mae_supported == B_FALSE)
 329                 return;
 330
 331         EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
 332             maep->em_action_rule_field_caps);
 333         EFSYS_KMEM_FREE(enp->en_esip, maep->em_outer_rule_field_caps_size,
 334             maep->em_outer_rule_field_caps);
 335         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
 336         enp->en_maep = NULL;
 337 }
 338
 339         __checkReturn                   efx_rc_t
 340 efx_mae_get_limits(
 341         __in                            efx_nic_t *enp,
 342         __out                           efx_mae_limits_t *emlp)
 343 {
 344         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 345         struct efx_mae_s *maep = enp->en_maep;
 346         efx_rc_t rc;
 347
 348         if (encp->enc_mae_supported == B_FALSE) {
 349                 rc = ENOTSUP;
 350                 goto fail1;
 351         }
 352
 353         emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
 354         emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
 355         emlp->eml_encap_types_supported = maep->em_encap_types_supported;
 356
 357         return (0);
 358
 359 fail1:
 360         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 361         return (rc);
 362 }
 363
 364         __checkReturn                   efx_rc_t
 365 efx_mae_match_spec_init(
 366         __in                            efx_nic_t *enp,
 367         __in                            efx_mae_rule_type_t type,
 368         __in                            uint32_t prio,
 369         __out                           efx_mae_match_spec_t **specp)
 370 {
 371         efx_mae_match_spec_t *spec;
 372         efx_rc_t rc;
 373
 374         switch (type) {
 375         case EFX_MAE_RULE_OUTER:
 376                 break;
 377         case EFX_MAE_RULE_ACTION:
 378                 break;
 379         default:
 380                 rc = ENOTSUP;
 381                 goto fail1;
 382         }
 383
 384         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 385         if (spec == NULL) {
 386                 rc = ENOMEM;
 387                 goto fail2;
 388         }
 389
 390         spec->emms_type = type;
 391         spec->emms_prio = prio;
 392
 393         *specp = spec;
 394
 395         return (0);
 396
 397 fail2:
 398         EFSYS_PROBE(fail2);
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401         return (rc);
 402 }
 403
 404                                         void
 405 efx_mae_match_spec_fini(
 406         __in                            efx_nic_t *enp,
 407         __in                            efx_mae_match_spec_t *spec)
 408 {
 409         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 410 }
 411
 412 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
 413 typedef enum efx_mae_field_cap_id_e {
 414         EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
 415         EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
 416         EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
 417         EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
 418         EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
 419         EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
 420         EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
 421         EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
 422         EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
 423         EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
 424         EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
 425         EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
 426         EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
 427         EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
 428         EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
 429         EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
 430         EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
 431         EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
 432         EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
 433         EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
 434         EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
 435         EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
 436         EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
 437         EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
 438         EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
 439         EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
 440         EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
 441         EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
 442         EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
 443         EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
 444         EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
 445         EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
 446         EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
 447         EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
 448         EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
 449         EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
 450
 451         EFX_MAE_FIELD_CAP_NIDS
 452 } efx_mae_field_cap_id_t;
 453
 454 typedef enum efx_mae_field_endianness_e {
 455         EFX_MAE_FIELD_LE = 0,
 456         EFX_MAE_FIELD_BE,
 457
 458         EFX_MAE_FIELD_ENDIANNESS_NTYPES
 459 } efx_mae_field_endianness_t;
 460
 461 /*
 462  * The following structure is a means to describe an MAE field.
 463  * The information in it is meant to be used internally by
 464  * APIs for addressing a given field in a mask-value pairs
 465  * structure and for validation purposes.
 466  *
 467  * A field may have an alternative one. This structure
 468  * has additional members to reference the alternative
 469  * field's mask. See efx_mae_match_spec_is_valid().
 470  */
 471 typedef struct efx_mae_mv_desc_s {
 472         efx_mae_field_cap_id_t          emmd_field_cap_id;
 473
 474         size_t                          emmd_value_size;
 475         size_t                          emmd_value_offset;
 476         size_t                          emmd_mask_size;
 477         size_t                          emmd_mask_offset;
 478
 479         /*
 480          * Having the alternative field's mask size set to 0
 481          * means that there's no alternative field specified.
 482          */
 483         size_t                          emmd_alt_mask_size;
 484         size_t                          emmd_alt_mask_offset;
 485
 486         /* Primary field and the alternative one are of the same endianness. */
 487         efx_mae_field_endianness_t      emmd_endianness;
 488 } efx_mae_mv_desc_t;
 489
 490 /* Indices to this array are provided by efx_mae_field_id_t */
 491 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
 492 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 493         [EFX_MAE_FIELD_##_name] =                                       \
 494         {                                                               \
 495                 EFX_MAE_FIELD_ID_##_name,                               \
 496                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN,               \
 497                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,              \
 498                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,          \
 499                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,         \
 500                 0, 0 /* no alternative field */,                        \
 501                 _endianness                                             \
 502         }
 503
 504         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 505         EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 506         EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 507         EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 508         EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 509         EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 510         EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 511         EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 512         EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
 513         EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
 514         EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
 515         EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
 516         EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
 517         EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
 518         EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
 519         EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
 520         EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
 521         EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
 522         EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
 523         EFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),
 524
 525 #undef EFX_MAE_MV_DESC
 526 };
 527
 528 /* Indices to this array are provided by efx_mae_field_id_t */
 529 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 530 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 531         [EFX_MAE_FIELD_##_name] =                                       \
 532         {                                                               \
 533                 EFX_MAE_FIELD_ID_##_name,                               \
 534                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 535                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 536                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 537                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 538                 0, 0 /* no alternative field */,                        \
 539                 _endianness                                             \
 540         }
 541
 542 /* Same as EFX_MAE_MV_DESC(), but also indicates an alternative field. */
 543 #define EFX_MAE_MV_DESC_ALT(_name, _alt_name, _endianness)              \
 544         [EFX_MAE_FIELD_##_name] =                                       \
 545         {                                                               \
 546                 EFX_MAE_FIELD_ID_##_name,                               \
 547                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 548                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 549                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 550                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 551                 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_LEN,             \
 552                 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_OFST,            \
 553                 _endianness                                             \
 554         }
 555
 556         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 557         EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 558         EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 559         EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 560         EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 561         EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 562         EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 563         EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 564         EFX_MAE_MV_DESC_ALT(ENC_SRC_IP4_BE, ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
 565         EFX_MAE_MV_DESC_ALT(ENC_DST_IP4_BE, ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
 566         EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
 567         EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
 568         EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
 569         EFX_MAE_MV_DESC_ALT(ENC_SRC_IP6_BE, ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
 570         EFX_MAE_MV_DESC_ALT(ENC_DST_IP6_BE, ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
 571         EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
 572         EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
 573
 574 #undef EFX_MAE_MV_DESC_ALT
 575 #undef EFX_MAE_MV_DESC
 576 };
 577
 578         __checkReturn                   efx_rc_t
 579 efx_mae_mport_by_phy_port(
 580         __in                            uint32_t phy_port,
 581         __out                           efx_mport_sel_t *mportp)
 582 {
 583         efx_dword_t dword;
 584         efx_rc_t rc;
 585
 586         if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
 587                 rc = EINVAL;
 588                 goto fail1;
 589         }
 590
 591         EFX_POPULATE_DWORD_2(dword,
 592             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
 593             MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
 594
 595         memset(mportp, 0, sizeof (*mportp));
 596         /*
 597          * The constructed DWORD is little-endian,
 598          * but the resulting value is meant to be
 599          * passed to MCDIs, where it will undergo
 600          * host-order to little endian conversion.
 601          */
 602         mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
 603
 604         return (0);
 605
 606 fail1:
 607         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 608         return (rc);
 609 }
 610
 611         __checkReturn                   efx_rc_t
 612 efx_mae_mport_by_pcie_function(
 613         __in                            uint32_t pf,
 614         __in                            uint32_t vf,
 615         __out                           efx_mport_sel_t *mportp)
 616 {
 617         efx_dword_t dword;
 618         efx_rc_t rc;
 619
 620         EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
 621             MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
 622
 623         if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
 624                 rc = EINVAL;
 625                 goto fail1;
 626         }
 627
 628         if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
 629                 rc = EINVAL;
 630                 goto fail2;
 631         }
 632
 633         EFX_POPULATE_DWORD_3(dword,
 634             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
 635             MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
 636             MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
 637
 638         memset(mportp, 0, sizeof (*mportp));
 639         /*
 640          * The constructed DWORD is little-endian,
 641          * but the resulting value is meant to be
 642          * passed to MCDIs, where it will undergo
 643          * host-order to little endian conversion.
 644          */
 645         mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
 646
 647         return (0);
 648
 649 fail2:
 650         EFSYS_PROBE(fail2);
 651 fail1:
 652         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 653         return (rc);
 654 }
 655
 656         __checkReturn                   efx_rc_t
 657 efx_mae_match_spec_field_set(
 658         __in                            efx_mae_match_spec_t *spec,
 659         __in                            efx_mae_field_id_t field_id,
 660         __in                            size_t value_size,
 661         __in_bcount(value_size)         const uint8_t *value,
 662         __in                            size_t mask_size,
 663         __in_bcount(mask_size)          const uint8_t *mask)
 664 {
 665         const efx_mae_mv_desc_t *descp;
 666         unsigned int desc_set_nentries;
 667         uint8_t *mvp;
 668         efx_rc_t rc;
 669
 670         switch (spec->emms_type) {
 671         case EFX_MAE_RULE_OUTER:
 672                 desc_set_nentries =
 673                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
 674                 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
 675                 mvp = spec->emms_mask_value_pairs.outer;
 676                 break;
 677         case EFX_MAE_RULE_ACTION:
 678                 desc_set_nentries =
 679                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 680                 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
 681                 mvp = spec->emms_mask_value_pairs.action;
 682                 break;
 683         default:
 684                 rc = ENOTSUP;
 685                 goto fail1;
 686         }
 687
 688         if ((unsigned int)field_id >= desc_set_nentries) {
 689                 rc = EINVAL;
 690                 goto fail2;
 691         }
 692
 693         if (value_size != descp->emmd_value_size) {
 694                 rc = EINVAL;
 695                 goto fail3;
 696         }
 697
 698         if (mask_size != descp->emmd_mask_size) {
 699                 rc = EINVAL;
 700                 goto fail4;
 701         }
 702
 703         if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
 704                 /*
 705                  * The mask/value are in network (big endian) order.
 706                  * The MCDI request field is also big endian.
 707                  */
 708                 memcpy(mvp + descp->emmd_value_offset, value, value_size);
 709                 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
 710         } else {
 711                 efx_dword_t dword;
 712
 713                 /*
 714                  * The mask/value are in host byte order.
 715                  * The MCDI request field is little endian.
 716                  */
 717                 switch (value_size) {
 718                 case 4:
 719                         EFX_POPULATE_DWORD_1(dword,
 720                             EFX_DWORD_0, *(const uint32_t *)value);
 721
 722                         memcpy(mvp + descp->emmd_value_offset,
 723                             &dword, sizeof (dword));
 724                         break;
 725                 default:
 726                         EFSYS_ASSERT(B_FALSE);
 727                 }
 728
 729                 switch (mask_size) {
 730                 case 4:
 731                         EFX_POPULATE_DWORD_1(dword,
 732                             EFX_DWORD_0, *(const uint32_t *)mask);
 733
 734                         memcpy(mvp + descp->emmd_mask_offset,
 735                             &dword, sizeof (dword));
 736                         break;
 737                 default:
 738                         EFSYS_ASSERT(B_FALSE);
 739                 }
 740         }
 741
 742         return (0);
 743
 744 fail4:
 745         EFSYS_PROBE(fail4);
 746 fail3:
 747         EFSYS_PROBE(fail3);
 748 fail2:
 749         EFSYS_PROBE(fail2);
 750 fail1:
 751         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 752         return (rc);
 753 }
 754
 755         __checkReturn                   efx_rc_t
 756 efx_mae_match_spec_mport_set(
 757         __in                            efx_mae_match_spec_t *spec,
 758         __in                            const efx_mport_sel_t *valuep,
 759         __in_opt                        const efx_mport_sel_t *maskp)
 760 {
 761         uint32_t full_mask = UINT32_MAX;
 762         const uint8_t *vp;
 763         const uint8_t *mp;
 764         efx_rc_t rc;
 765
 766         if (valuep == NULL) {
 767                 rc = EINVAL;
 768                 goto fail1;
 769         }
 770
 771         vp = (const uint8_t *)&valuep->sel;
 772         if (maskp != NULL)
 773                 mp = (const uint8_t *)&maskp->sel;
 774         else
 775                 mp = (const uint8_t *)&full_mask;
 776
 777         rc = efx_mae_match_spec_field_set(spec,
 778             EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
 779             sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
 780         if (rc != 0)
 781                 goto fail2;
 782
 783         return (0);
 784
 785 fail2:
 786         EFSYS_PROBE(fail2);
 787 fail1:
 788         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 789         return (rc);
 790 }
 791
 792         __checkReturn                   boolean_t
 793 efx_mae_match_specs_equal(
 794         __in                            const efx_mae_match_spec_t *left,
 795         __in                            const efx_mae_match_spec_t *right)
 796 {
 797         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
 798 }
 799
 800 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)              \
 801             ((_mask)[(_bit) / (_mask_page_nbits)] &                     \
 802                     (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
 803
 804 static                                  boolean_t
 805 efx_mask_is_prefix(
 806         __in                            size_t mask_nbytes,
 807         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 808 {
 809         boolean_t prev_bit_is_set = B_TRUE;
 810         unsigned int i;
 811
 812         for (i = 0; i < 8 * mask_nbytes; ++i) {
 813                 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
 814
 815                 if (!prev_bit_is_set && bit_is_set)
 816                         return B_FALSE;
 817
 818                 prev_bit_is_set = bit_is_set;
 819         }
 820
 821         return B_TRUE;
 822 }
 823
 824 static                                  boolean_t
 825 efx_mask_is_all_ones(
 826         __in                            size_t mask_nbytes,
 827         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 828 {
 829         unsigned int i;
 830         uint8_t t = ~0;
 831
 832         for (i = 0; i < mask_nbytes; ++i)
 833                 t &= maskp[i];
 834
 835         return (t == (uint8_t)(~0));
 836 }
 837
 838 static                                  boolean_t
 839 efx_mask_is_all_zeros(
 840         __in                            size_t mask_nbytes,
 841         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 842 {
 843         unsigned int i;
 844         uint8_t t = 0;
 845
 846         for (i = 0; i < mask_nbytes; ++i)
 847                 t |= maskp[i];
 848
 849         return (t == 0);
 850 }
 851
 852         __checkReturn                   boolean_t
 853 efx_mae_match_spec_is_valid(
 854         __in                            efx_nic_t *enp,
 855         __in                            const efx_mae_match_spec_t *spec)
 856 {
 857         efx_mae_t *maep = enp->en_maep;
 858         unsigned int field_ncaps = maep->em_max_nfields;
 859         const efx_mae_field_cap_t *field_caps;
 860         const efx_mae_mv_desc_t *desc_setp;
 861         unsigned int desc_set_nentries;
 862         boolean_t is_valid = B_TRUE;
 863         efx_mae_field_id_t field_id;
 864         const uint8_t *mvp;
 865
 866         switch (spec->emms_type) {
 867         case EFX_MAE_RULE_OUTER:
 868                 field_caps = maep->em_outer_rule_field_caps;
 869                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
 870                 desc_set_nentries =
 871                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
 872                 mvp = spec->emms_mask_value_pairs.outer;
 873                 break;
 874         case EFX_MAE_RULE_ACTION:
 875                 field_caps = maep->em_action_rule_field_caps;
 876                 desc_setp = __efx_mae_action_rule_mv_desc_set;
 877                 desc_set_nentries =
 878                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 879                 mvp = spec->emms_mask_value_pairs.action;
 880                 break;
 881         default:
 882                 return (B_FALSE);
 883         }
 884
 885         if (field_caps == NULL)
 886                 return (B_FALSE);
 887
 888         for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
 889              ++field_id) {
 890                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
 891                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
 892                 const uint8_t *alt_m_buf = mvp + descp->emmd_alt_mask_offset;
 893                 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
 894                 size_t alt_m_size = descp->emmd_alt_mask_size;
 895                 size_t m_size = descp->emmd_mask_size;
 896
 897                 if (m_size == 0)
 898                         continue; /* Skip array gap */
 899
 900                 if ((unsigned int)field_cap_id >= field_ncaps) {
 901                         /*
 902                          * The FW has not reported capability status for
 903                          * this field. Make sure that its mask is zeroed.
 904                          */
 905                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
 906                         if (is_valid != B_FALSE)
 907                                 continue;
 908                         else
 909                                 break;
 910                 }
 911
 912                 switch (field_caps[field_cap_id].emfc_support) {
 913                 case MAE_FIELD_SUPPORTED_MATCH_MASK:
 914                         is_valid = B_TRUE;
 915                         break;
 916                 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
 917                         is_valid = efx_mask_is_prefix(m_size, m_buf);
 918                         break;
 919                 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
 920                         is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
 921                             efx_mask_is_all_zeros(m_size, m_buf));
 922                         break;
 923                 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
 924                         is_valid = efx_mask_is_all_ones(m_size, m_buf);
 925
 926                         if ((is_valid == B_FALSE) && (alt_m_size != 0)) {
 927                                 /*
 928                                  * This field has an alternative one. The FW
 929                                  * reports ALWAYS for both implying that one
 930                                  * of them is required to have all-ones mask.
 931                                  *
 932                                  * The primary field's mask is incorrect; go
 933                                  * on to check that of the alternative field.
 934                                  */
 935                                 is_valid = efx_mask_is_all_ones(alt_m_size,
 936                                                                 alt_m_buf);
 937                         }
 938                         break;
 939                 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
 940                 case MAE_FIELD_UNSUPPORTED:
 941                 default:
 942                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
 943                         break;
 944                 }
 945
 946                 if (is_valid == B_FALSE)
 947                         break;
 948         }
 949
 950         return (is_valid);
 951 }
 952
 953         __checkReturn                   efx_rc_t
 954 efx_mae_action_set_spec_init(
 955         __in                            efx_nic_t *enp,
 956         __out                           efx_mae_actions_t **specp)
 957 {
 958         efx_mae_actions_t *spec;
 959         efx_rc_t rc;
 960
 961         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 962         if (spec == NULL) {
 963                 rc = ENOMEM;
 964                 goto fail1;
 965         }
 966
 967         *specp = spec;
 968
 969         return (0);
 970
 971 fail1:
 972         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 973         return (rc);
 974 }
 975
 976                                         void
 977 efx_mae_action_set_spec_fini(
 978         __in                            efx_nic_t *enp,
 979         __in                            efx_mae_actions_t *spec)
 980 {
 981         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 982 }
 983
 984 static  __checkReturn                   efx_rc_t
 985 efx_mae_action_set_add_vlan_pop(
 986         __in                            efx_mae_actions_t *spec,
 987         __in                            size_t arg_size,
 988         __in_bcount(arg_size)           const uint8_t *arg)
 989 {
 990         efx_rc_t rc;
 991
 992         if (arg_size != 0) {
 993                 rc = EINVAL;
 994                 goto fail1;
 995         }
 996
 997         if (arg != NULL) {
 998                 rc = EINVAL;
 999                 goto fail2;
1000         }
1001
1002         if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
1003                 rc = ENOTSUP;
1004                 goto fail3;
1005         }
1006
1007         ++spec->ema_n_vlan_tags_to_pop;
1008
1009         return (0);
1010
1011 fail3:
1012         EFSYS_PROBE(fail3);
1013 fail2:
1014         EFSYS_PROBE(fail2);
1015 fail1:
1016         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1017         return (rc);
1018 }
1019
1020 static  __checkReturn                   efx_rc_t
1021 efx_mae_action_set_add_vlan_push(
1022         __in                            efx_mae_actions_t *spec,
1023         __in                            size_t arg_size,
1024         __in_bcount(arg_size)           const uint8_t *arg)
1025 {
1026         unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
1027         efx_rc_t rc;
1028
1029         if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
1030                 rc = EINVAL;
1031                 goto fail1;
1032         }
1033
1034         if (arg == NULL) {
1035                 rc = EINVAL;
1036                 goto fail2;
1037         }
1038
1039         if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1040                 rc = ENOTSUP;
1041                 goto fail3;
1042         }
1043
1044         memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
1045         ++(spec->ema_n_vlan_tags_to_push);
1046
1047         return (0);
1048
1049 fail3:
1050         EFSYS_PROBE(fail3);
1051 fail2:
1052         EFSYS_PROBE(fail2);
1053 fail1:
1054         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1055         return (rc);
1056 }
1057
1058 static  __checkReturn                   efx_rc_t
1059 efx_mae_action_set_add_flag(
1060         __in                            efx_mae_actions_t *spec,
1061         __in                            size_t arg_size,
1062         __in_bcount(arg_size)           const uint8_t *arg)
1063 {
1064         efx_rc_t rc;
1065
1066         _NOTE(ARGUNUSED(spec))
1067
1068         if (arg_size != 0) {
1069                 rc = EINVAL;
1070                 goto fail1;
1071         }
1072
1073         if (arg != NULL) {
1074                 rc = EINVAL;
1075                 goto fail2;
1076         }
1077
1078         /* This action does not have any arguments, so do nothing here. */
1079
1080         return (0);
1081
1082 fail2:
1083         EFSYS_PROBE(fail2);
1084 fail1:
1085         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1086         return (rc);
1087 }
1088
1089 static  __checkReturn                   efx_rc_t
1090 efx_mae_action_set_add_mark(
1091         __in                            efx_mae_actions_t *spec,
1092         __in                            size_t arg_size,
1093         __in_bcount(arg_size)           const uint8_t *arg)
1094 {
1095         efx_rc_t rc;
1096
1097         if (arg_size != sizeof (spec->ema_mark_value)) {
1098                 rc = EINVAL;
1099                 goto fail1;
1100         }
1101
1102         if (arg == NULL) {
1103                 rc = EINVAL;
1104                 goto fail2;
1105         }
1106
1107         memcpy(&spec->ema_mark_value, arg, arg_size);
1108
1109         return (0);
1110
1111 fail2:
1112         EFSYS_PROBE(fail2);
1113 fail1:
1114         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1115         return (rc);
1116 }
1117
1118 static  __checkReturn                   efx_rc_t
1119 efx_mae_action_set_add_deliver(
1120         __in                            efx_mae_actions_t *spec,
1121         __in                            size_t arg_size,
1122         __in_bcount(arg_size)           const uint8_t *arg)
1123 {
1124         efx_rc_t rc;
1125
1126         if (arg_size != sizeof (spec->ema_deliver_mport)) {
1127                 rc = EINVAL;
1128                 goto fail1;
1129         }
1130
1131         if (arg == NULL) {
1132                 rc = EINVAL;
1133                 goto fail2;
1134         }
1135
1136         memcpy(&spec->ema_deliver_mport, arg, arg_size);
1137
1138         return (0);
1139
1140 fail2:
1141         EFSYS_PROBE(fail2);
1142 fail1:
1143         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1144         return (rc);
1145 }
1146
1147 typedef struct efx_mae_action_desc_s {
1148         /* Action specific handler */
1149         efx_rc_t        (*emad_add)(efx_mae_actions_t *,
1150                                     size_t, const uint8_t *);
1151 } efx_mae_action_desc_t;
1152
1153 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
1154         [EFX_MAE_ACTION_VLAN_POP] = {
1155                 .emad_add = efx_mae_action_set_add_vlan_pop
1156         },
1157         [EFX_MAE_ACTION_VLAN_PUSH] = {
1158                 .emad_add = efx_mae_action_set_add_vlan_push
1159         },
1160         [EFX_MAE_ACTION_FLAG] = {
1161                 .emad_add = efx_mae_action_set_add_flag
1162         },
1163         [EFX_MAE_ACTION_MARK] = {
1164                 .emad_add = efx_mae_action_set_add_mark
1165         },
1166         [EFX_MAE_ACTION_DELIVER] = {
1167                 .emad_add = efx_mae_action_set_add_deliver
1168         }
1169 };
1170
1171 static const uint32_t efx_mae_action_ordered_map =
1172         (1U << EFX_MAE_ACTION_VLAN_POP) |
1173         (1U << EFX_MAE_ACTION_VLAN_PUSH) |
1174         (1U << EFX_MAE_ACTION_FLAG) |
1175         (1U << EFX_MAE_ACTION_MARK) |
1176         (1U << EFX_MAE_ACTION_DELIVER);
1177
1178 /*
1179  * These actions must not be added after DELIVER, but
1180  * they can have any place among the rest of
1181  * strictly ordered actions.
1182  */
1183 static const uint32_t efx_mae_action_nonstrict_map =
1184         (1U << EFX_MAE_ACTION_FLAG) |
1185         (1U << EFX_MAE_ACTION_MARK);
1186
1187 static const uint32_t efx_mae_action_repeat_map =
1188         (1U << EFX_MAE_ACTION_VLAN_POP) |
1189         (1U << EFX_MAE_ACTION_VLAN_PUSH);
1190
1191 /*
1192  * Add an action to an action set.
1193  *
1194  * This has to be invoked in the desired action order.
1195  * An out-of-order action request will be turned down.
1196  */
1197 static  __checkReturn                   efx_rc_t
1198 efx_mae_action_set_spec_populate(
1199         __in                            efx_mae_actions_t *spec,
1200         __in                            efx_mae_action_t type,
1201         __in                            size_t arg_size,
1202         __in_bcount(arg_size)           const uint8_t *arg)
1203 {
1204         uint32_t action_mask;
1205         efx_rc_t rc;
1206
1207         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1208             (sizeof (efx_mae_action_ordered_map) * 8));
1209         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1210             (sizeof (efx_mae_action_repeat_map) * 8));
1211
1212         EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1213         EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1214         EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1215
1216         if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1217                 rc = EINVAL;
1218                 goto fail1;
1219         }
1220
1221         action_mask = (1U << type);
1222
1223         if ((spec->ema_actions & action_mask) != 0) {
1224                 /* The action set already contains this action. */
1225                 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1226                         /* Cannot add another non-repeatable action. */
1227                         rc = ENOTSUP;
1228                         goto fail2;
1229                 }
1230         }
1231
1232         if ((efx_mae_action_ordered_map & action_mask) != 0) {
1233                 uint32_t strict_ordered_map =
1234                     efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1235                 uint32_t later_actions_mask =
1236                     strict_ordered_map & ~(action_mask | (action_mask - 1));
1237
1238                 if ((spec->ema_actions & later_actions_mask) != 0) {
1239                         /* Cannot add an action after later ordered actions. */
1240                         rc = ENOTSUP;
1241                         goto fail3;
1242                 }
1243         }
1244
1245         if (efx_mae_actions[type].emad_add != NULL) {
1246                 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1247                 if (rc != 0)
1248                         goto fail4;
1249         }
1250
1251         spec->ema_actions |= action_mask;
1252
1253         return (0);
1254
1255 fail4:
1256         EFSYS_PROBE(fail4);
1257 fail3:
1258         EFSYS_PROBE(fail3);
1259 fail2:
1260         EFSYS_PROBE(fail2);
1261 fail1:
1262         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1263         return (rc);
1264 }
1265
1266         __checkReturn                   efx_rc_t
1267 efx_mae_action_set_populate_vlan_pop(
1268         __in                            efx_mae_actions_t *spec)
1269 {
1270         return (efx_mae_action_set_spec_populate(spec,
1271             EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1272 }
1273
1274         __checkReturn                   efx_rc_t
1275 efx_mae_action_set_populate_vlan_push(
1276         __in                            efx_mae_actions_t *spec,
1277         __in                            uint16_t tpid_be,
1278         __in                            uint16_t tci_be)
1279 {
1280         efx_mae_action_vlan_push_t action;
1281         const uint8_t *arg = (const uint8_t *)&action;
1282
1283         action.emavp_tpid_be = tpid_be;
1284         action.emavp_tci_be = tci_be;
1285
1286         return (efx_mae_action_set_spec_populate(spec,
1287             EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1288 }
1289
1290         __checkReturn                   efx_rc_t
1291 efx_mae_action_set_populate_flag(
1292         __in                            efx_mae_actions_t *spec)
1293 {
1294         return (efx_mae_action_set_spec_populate(spec,
1295             EFX_MAE_ACTION_FLAG, 0, NULL));
1296 }
1297
1298         __checkReturn                   efx_rc_t
1299 efx_mae_action_set_populate_mark(
1300         __in                            efx_mae_actions_t *spec,
1301         __in                            uint32_t mark_value)
1302 {
1303         const uint8_t *arg = (const uint8_t *)&mark_value;
1304
1305         return (efx_mae_action_set_spec_populate(spec,
1306             EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1307 }
1308
1309         __checkReturn                   efx_rc_t
1310 efx_mae_action_set_populate_deliver(
1311         __in                            efx_mae_actions_t *spec,
1312         __in                            const efx_mport_sel_t *mportp)
1313 {
1314         const uint8_t *arg;
1315         efx_rc_t rc;
1316
1317         if (mportp == NULL) {
1318                 rc = EINVAL;
1319                 goto fail1;
1320         }
1321
1322         arg = (const uint8_t *)&mportp->sel;
1323
1324         return (efx_mae_action_set_spec_populate(spec,
1325             EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1326
1327 fail1:
1328         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1329         return (rc);
1330 }
1331
1332         __checkReturn                   efx_rc_t
1333 efx_mae_action_set_populate_drop(
1334         __in                            efx_mae_actions_t *spec)
1335 {
1336         efx_mport_sel_t mport;
1337         const uint8_t *arg;
1338         efx_dword_t dword;
1339
1340         EFX_POPULATE_DWORD_1(dword,
1341             MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1342
1343         /*
1344          * The constructed DWORD is little-endian,
1345          * but the resulting value is meant to be
1346          * passed to MCDIs, where it will undergo
1347          * host-order to little endian conversion.
1348          */
1349         mport.sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
1350
1351         arg = (const uint8_t *)&mport.sel;
1352
1353         return (efx_mae_action_set_spec_populate(spec,
1354             EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1355 }
1356
1357         __checkReturn                   boolean_t
1358 efx_mae_action_set_specs_equal(
1359         __in                            const efx_mae_actions_t *left,
1360         __in                            const efx_mae_actions_t *right)
1361 {
1362         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1363 }
1364
1365         __checkReturn                   efx_rc_t
1366 efx_mae_match_specs_class_cmp(
1367         __in                            efx_nic_t *enp,
1368         __in                            const efx_mae_match_spec_t *left,
1369         __in                            const efx_mae_match_spec_t *right,
1370         __out                           boolean_t *have_same_classp)
1371 {
1372         efx_mae_t *maep = enp->en_maep;
1373         unsigned int field_ncaps = maep->em_max_nfields;
1374         const efx_mae_field_cap_t *field_caps;
1375         const efx_mae_mv_desc_t *desc_setp;
1376         unsigned int desc_set_nentries;
1377         boolean_t have_same_class = B_TRUE;
1378         efx_mae_field_id_t field_id;
1379         const uint8_t *mvpl;
1380         const uint8_t *mvpr;
1381         efx_rc_t rc;
1382
1383         switch (left->emms_type) {
1384         case EFX_MAE_RULE_OUTER:
1385                 field_caps = maep->em_outer_rule_field_caps;
1386                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
1387                 desc_set_nentries =
1388                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
1389                 mvpl = left->emms_mask_value_pairs.outer;
1390                 mvpr = right->emms_mask_value_pairs.outer;
1391                 break;
1392         case EFX_MAE_RULE_ACTION:
1393                 field_caps = maep->em_action_rule_field_caps;
1394                 desc_setp = __efx_mae_action_rule_mv_desc_set;
1395                 desc_set_nentries =
1396                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1397                 mvpl = left->emms_mask_value_pairs.action;
1398                 mvpr = right->emms_mask_value_pairs.action;
1399                 break;
1400         default:
1401                 rc = ENOTSUP;
1402                 goto fail1;
1403         }
1404
1405         if (field_caps == NULL) {
1406                 rc = EAGAIN;
1407                 goto fail2;
1408         }
1409
1410         if (left->emms_type != right->emms_type ||
1411             left->emms_prio != right->emms_prio) {
1412                 /*
1413                  * Rules of different types can never map to the same class.
1414                  *
1415                  * The FW can support some set of match criteria for one
1416                  * priority and not support the very same set for
1417                  * another priority. Thus, two rules which have
1418                  * different priorities can never map to
1419                  * the same class.
1420                  */
1421                 *have_same_classp = B_FALSE;
1422                 return (0);
1423         }
1424
1425         for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
1426              ++field_id) {
1427                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1428                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1429                 const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1430                 const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1431                 size_t mask_size = descp->emmd_mask_size;
1432                 const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1433                 const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1434                 size_t value_size = descp->emmd_value_size;
1435
1436                 if (mask_size == 0)
1437                         continue; /* Skip array gap */
1438
1439                 if ((unsigned int)field_cap_id >= field_ncaps) {
1440                         /*
1441                          * The FW has not reported capability status for this
1442                          * field. It's unknown whether any difference between
1443                          * the two masks / values affects the class. The only
1444                          * case when the class must be the same is when these
1445                          * mask-value pairs match. Otherwise, report mismatch.
1446                          */
1447                         if ((memcmp(lmaskp, rmaskp, mask_size) == 0) &&
1448                             (memcmp(lvalp, rvalp, value_size) == 0))
1449                                 continue;
1450                         else
1451                                 break;
1452                 }
1453
1454                 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1455                         if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1456                                 have_same_class = B_FALSE;
1457                                 break;
1458                         }
1459                 }
1460
1461                 if (field_caps[field_cap_id].emfc_match_affects_class) {
1462                         if (memcmp(lvalp, rvalp, value_size) != 0) {
1463                                 have_same_class = B_FALSE;
1464                                 break;
1465                         }
1466                 }
1467         }
1468
1469         *have_same_classp = have_same_class;
1470
1471         return (0);
1472
1473 fail2:
1474         EFSYS_PROBE(fail2);
1475 fail1:
1476         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1477         return (rc);
1478 }
1479
1480         __checkReturn           efx_rc_t
1481 efx_mae_outer_rule_insert(
1482         __in                    efx_nic_t *enp,
1483         __in                    const efx_mae_match_spec_t *spec,
1484         __in                    efx_tunnel_protocol_t encap_type,
1485         __out                   efx_mae_rule_id_t *or_idp)
1486 {
1487         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1488         efx_mcdi_req_t req;
1489         EFX_MCDI_DECLARE_BUF(payload,
1490             MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,
1491             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);
1492         uint32_t encap_type_mcdi;
1493         efx_mae_rule_id_t or_id;
1494         size_t offset;
1495         efx_rc_t rc;
1496
1497         EFX_STATIC_ASSERT(sizeof (or_idp->id) ==
1498             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);
1499
1500         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1501             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);
1502
1503         if (encp->enc_mae_supported == B_FALSE) {
1504                 rc = ENOTSUP;
1505                 goto fail1;
1506         }
1507
1508         if (spec->emms_type != EFX_MAE_RULE_OUTER) {
1509                 rc = EINVAL;
1510                 goto fail2;
1511         }
1512
1513         switch (encap_type) {
1514         case EFX_TUNNEL_PROTOCOL_NONE:
1515                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
1516                 break;
1517         case EFX_TUNNEL_PROTOCOL_VXLAN:
1518                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
1519                 break;
1520         case EFX_TUNNEL_PROTOCOL_GENEVE:
1521                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
1522                 break;
1523         case EFX_TUNNEL_PROTOCOL_NVGRE:
1524                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
1525                 break;
1526         default:
1527                 rc = ENOTSUP;
1528                 goto fail3;
1529         }
1530
1531         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;
1532         req.emr_in_buf = payload;
1533         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;
1534         req.emr_out_buf = payload;
1535         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;
1536
1537         MCDI_IN_SET_DWORD(req,
1538             MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);
1539
1540         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);
1541
1542         /*
1543          * Mask-value pairs have been stored in the byte order needed for the
1544          * MCDI request and are thus safe to be copied directly to the buffer.
1545          * The library cares about byte order in efx_mae_match_spec_field_set().
1546          */
1547         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=
1548             MAE_ENC_FIELD_PAIRS_LEN);
1549         offset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;
1550         memcpy(payload + offset, spec->emms_mask_value_pairs.outer,
1551             MAE_ENC_FIELD_PAIRS_LEN);
1552
1553         efx_mcdi_execute(enp, &req);
1554
1555         if (req.emr_rc != 0) {
1556                 rc = req.emr_rc;
1557                 goto fail4;
1558         }
1559
1560         if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {
1561                 rc = EMSGSIZE;
1562                 goto fail5;
1563         }
1564
1565         or_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);
1566         if (or_id.id == EFX_MAE_RSRC_ID_INVALID) {
1567                 rc = ENOENT;
1568                 goto fail6;
1569         }
1570
1571         or_idp->id = or_id.id;
1572
1573         return (0);
1574
1575 fail6:
1576         EFSYS_PROBE(fail6);
1577 fail5:
1578         EFSYS_PROBE(fail5);
1579 fail4:
1580         EFSYS_PROBE(fail4);
1581 fail3:
1582         EFSYS_PROBE(fail3);
1583 fail2:
1584         EFSYS_PROBE(fail2);
1585 fail1:
1586         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1587         return (rc);
1588 }
1589
1590         __checkReturn           efx_rc_t
1591 efx_mae_outer_rule_remove(
1592         __in                    efx_nic_t *enp,
1593         __in                    const efx_mae_rule_id_t *or_idp)
1594 {
1595         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1596         efx_mcdi_req_t req;
1597         EFX_MCDI_DECLARE_BUF(payload,
1598             MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),
1599             MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));
1600         efx_rc_t rc;
1601
1602         if (encp->enc_mae_supported == B_FALSE) {
1603                 rc = ENOTSUP;
1604                 goto fail1;
1605         }
1606
1607         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;
1608         req.emr_in_buf = payload;
1609         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);
1610         req.emr_out_buf = payload;
1611         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);
1612
1613         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);
1614
1615         efx_mcdi_execute(enp, &req);
1616
1617         if (req.emr_rc != 0) {
1618                 rc = req.emr_rc;
1619                 goto fail2;
1620         }
1621
1622         if (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=
1623             or_idp->id) {
1624                 /* Firmware failed to remove the outer rule. */
1625                 rc = EAGAIN;
1626                 goto fail3;
1627         }
1628
1629         return (0);
1630
1631 fail3:
1632         EFSYS_PROBE(fail3);
1633 fail2:
1634         EFSYS_PROBE(fail2);
1635 fail1:
1636         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1637         return (rc);
1638 }
1639
1640         __checkReturn                   efx_rc_t
1641 efx_mae_match_spec_outer_rule_id_set(
1642         __in                            efx_mae_match_spec_t *spec,
1643         __in                            const efx_mae_rule_id_t *or_idp)
1644 {
1645         uint32_t full_mask = UINT32_MAX;
1646         efx_rc_t rc;
1647
1648         if (spec->emms_type != EFX_MAE_RULE_ACTION) {
1649                 rc = EINVAL;
1650                 goto fail1;
1651         }
1652
1653         if (or_idp == NULL) {
1654                 rc = EINVAL;
1655                 goto fail2;
1656         }
1657
1658         rc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,
1659             sizeof (or_idp->id), (const uint8_t *)&or_idp->id,
1660             sizeof (full_mask), (const uint8_t *)&full_mask);
1661         if (rc != 0)
1662                 goto fail3;
1663
1664         return (0);
1665
1666 fail3:
1667         EFSYS_PROBE(fail3);
1668 fail2:
1669         EFSYS_PROBE(fail2);
1670 fail1:
1671         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1672         return (rc);
1673 }
1674
1675         __checkReturn                   efx_rc_t
1676 efx_mae_action_set_alloc(
1677         __in                            efx_nic_t *enp,
1678         __in                            const efx_mae_actions_t *spec,
1679         __out                           efx_mae_aset_id_t *aset_idp)
1680 {
1681         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1682         efx_mcdi_req_t req;
1683         EFX_MCDI_DECLARE_BUF(payload,
1684             MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1685             MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1686         efx_mae_aset_id_t aset_id;
1687         efx_rc_t rc;
1688
1689         if (encp->enc_mae_supported == B_FALSE) {
1690                 rc = ENOTSUP;
1691                 goto fail1;
1692         }
1693
1694         req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1695         req.emr_in_buf = payload;
1696         req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1697         req.emr_out_buf = payload;
1698         req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1699
1700         /*
1701          * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1702          * corresponding resource types are supported by the implementation.
1703          * Use proper resource ID assignments instead.
1704          */
1705         MCDI_IN_SET_DWORD(req,
1706             MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1707         MCDI_IN_SET_DWORD(req,
1708             MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1709         MCDI_IN_SET_DWORD(req,
1710             MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1711
1712         MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1713             MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1714
1715         if (spec->ema_n_vlan_tags_to_push > 0) {
1716                 unsigned int outer_tag_idx;
1717
1718                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1719                     MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1720                     spec->ema_n_vlan_tags_to_push);
1721
1722                 if (spec->ema_n_vlan_tags_to_push ==
1723                     EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1724                         MCDI_IN_SET_WORD(req,
1725                             MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1726                             spec->ema_vlan_push_descs[0].emavp_tpid_be);
1727                         MCDI_IN_SET_WORD(req,
1728                             MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1729                             spec->ema_vlan_push_descs[0].emavp_tci_be);
1730                 }
1731
1732                 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1733
1734                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1735                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1736                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1737                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1738         }
1739
1740         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1741                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1742                     MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1743         }
1744
1745         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1746                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1747                     MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1748
1749                 MCDI_IN_SET_DWORD(req,
1750                     MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1751         }
1752
1753         MCDI_IN_SET_DWORD(req,
1754             MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1755
1756         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1757             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1758         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1759             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1760
1761         efx_mcdi_execute(enp, &req);
1762
1763         if (req.emr_rc != 0) {
1764                 rc = req.emr_rc;
1765                 goto fail2;
1766         }
1767
1768         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1769                 rc = EMSGSIZE;
1770                 goto fail3;
1771         }
1772
1773         aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1774         if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1775                 rc = ENOENT;
1776                 goto fail4;
1777         }
1778
1779         aset_idp->id = aset_id.id;
1780
1781         return (0);
1782
1783 fail4:
1784         EFSYS_PROBE(fail4);
1785 fail3:
1786         EFSYS_PROBE(fail3);
1787 fail2:
1788         EFSYS_PROBE(fail2);
1789 fail1:
1790         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1791         return (rc);
1792 }
1793
1794         __checkReturn                   efx_rc_t
1795 efx_mae_action_set_free(
1796         __in                            efx_nic_t *enp,
1797         __in                            const efx_mae_aset_id_t *aset_idp)
1798 {
1799         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1800         efx_mcdi_req_t req;
1801         EFX_MCDI_DECLARE_BUF(payload,
1802             MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1803             MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1804         efx_rc_t rc;
1805
1806         if (encp->enc_mae_supported == B_FALSE) {
1807                 rc = ENOTSUP;
1808                 goto fail1;
1809         }
1810
1811         req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1812         req.emr_in_buf = payload;
1813         req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1814         req.emr_out_buf = payload;
1815         req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1816
1817         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1818
1819         efx_mcdi_execute(enp, &req);
1820
1821         if (req.emr_rc != 0) {
1822                 rc = req.emr_rc;
1823                 goto fail2;
1824         }
1825
1826         if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1827             aset_idp->id) {
1828                 /* Firmware failed to free the action set. */
1829                 rc = EAGAIN;
1830                 goto fail3;
1831         }
1832
1833         return (0);
1834
1835 fail3:
1836         EFSYS_PROBE(fail3);
1837 fail2:
1838         EFSYS_PROBE(fail2);
1839 fail1:
1840         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1841         return (rc);
1842 }
1843
1844         __checkReturn                   efx_rc_t
1845 efx_mae_action_rule_insert(
1846         __in                            efx_nic_t *enp,
1847         __in                            const efx_mae_match_spec_t *spec,
1848         __in                            const efx_mae_aset_list_id_t *asl_idp,
1849         __in                            const efx_mae_aset_id_t *as_idp,
1850         __out                           efx_mae_rule_id_t *ar_idp)
1851 {
1852         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1853         efx_mcdi_req_t req;
1854         EFX_MCDI_DECLARE_BUF(payload,
1855             MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1856             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1857         efx_oword_t *rule_response;
1858         efx_mae_rule_id_t ar_id;
1859         size_t offset;
1860         efx_rc_t rc;
1861
1862         EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1863             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1864
1865         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1866             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1867
1868         if (encp->enc_mae_supported == B_FALSE) {
1869                 rc = ENOTSUP;
1870                 goto fail1;
1871         }
1872
1873         if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1874             (asl_idp != NULL && as_idp != NULL) ||
1875             (asl_idp == NULL && as_idp == NULL)) {
1876                 rc = EINVAL;
1877                 goto fail2;
1878         }
1879
1880         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1881         req.emr_in_buf = payload;
1882         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1883         req.emr_out_buf = payload;
1884         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1885
1886         EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1887             MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1888         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1889         rule_response = (efx_oword_t *)(payload + offset);
1890         EFX_POPULATE_OWORD_3(*rule_response,
1891             MAE_ACTION_RULE_RESPONSE_ASL_ID,
1892             (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1893             MAE_ACTION_RULE_RESPONSE_AS_ID,
1894             (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1895             MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1896
1897         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1898
1899         /*
1900          * Mask-value pairs have been stored in the byte order needed for the
1901          * MCDI request and are thus safe to be copied directly to the buffer.
1902          */
1903         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1904             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1905         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1906         memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1907             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1908
1909         efx_mcdi_execute(enp, &req);
1910
1911         if (req.emr_rc != 0) {
1912                 rc = req.emr_rc;
1913                 goto fail3;
1914         }
1915
1916         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1917                 rc = EMSGSIZE;
1918                 goto fail4;
1919         }
1920
1921         ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1922         if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1923                 rc = ENOENT;
1924                 goto fail5;
1925         }
1926
1927         ar_idp->id = ar_id.id;
1928
1929         return (0);
1930
1931 fail5:
1932         EFSYS_PROBE(fail5);
1933 fail4:
1934         EFSYS_PROBE(fail4);
1935 fail3:
1936         EFSYS_PROBE(fail3);
1937 fail2:
1938         EFSYS_PROBE(fail2);
1939 fail1:
1940         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1941         return (rc);
1942 }
1943
1944         __checkReturn                   efx_rc_t
1945 efx_mae_action_rule_remove(
1946         __in                            efx_nic_t *enp,
1947         __in                            const efx_mae_rule_id_t *ar_idp)
1948 {
1949         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1950         efx_mcdi_req_t req;
1951         EFX_MCDI_DECLARE_BUF(payload,
1952             MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1953             MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1954         efx_rc_t rc;
1955
1956         if (encp->enc_mae_supported == B_FALSE) {
1957                 rc = ENOTSUP;
1958                 goto fail1;
1959         }
1960
1961         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1962         req.emr_in_buf = payload;
1963         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1964         req.emr_out_buf = payload;
1965         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1966
1967         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1968
1969         efx_mcdi_execute(enp, &req);
1970
1971         if (req.emr_rc != 0) {
1972                 rc = req.emr_rc;
1973                 goto fail2;
1974         }
1975
1976         if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1977             ar_idp->id) {
1978                 /* Firmware failed to delete the action rule. */
1979                 rc = EAGAIN;
1980                 goto fail3;
1981         }
1982
1983         return (0);
1984
1985 fail3:
1986         EFSYS_PROBE(fail3);
1987 fail2:
1988         EFSYS_PROBE(fail2);
1989 fail1:
1990         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1991         return (rc);
1992 }
1993
1994 #endif /* EFSYS_OPT_MAE */