1 /* SPDX-License-Identifier: BSD-3-Clause
3 * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
13 static __checkReturn efx_rc_t
14 efx_mae_get_capabilities(
18 EFX_MCDI_DECLARE_BUF(payload,
19 MC_CMD_MAE_GET_CAPS_IN_LEN,
20 MC_CMD_MAE_GET_CAPS_OUT_LEN);
21 struct efx_mae_s *maep = enp->en_maep;
24 req.emr_cmd = MC_CMD_MAE_GET_CAPS;
25 req.emr_in_buf = payload;
26 req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
27 req.emr_out_buf = payload;
28 req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
30 efx_mcdi_execute(enp, &req);
32 if (req.emr_rc != 0) {
37 if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
42 maep->em_max_n_outer_prios =
43 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
45 maep->em_max_n_action_prios =
46 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
48 maep->em_encap_types_supported = 0;
50 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
51 maep->em_encap_types_supported |=
52 (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
55 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
56 maep->em_encap_types_supported |=
57 (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
60 if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
61 maep->em_encap_types_supported |=
62 (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
65 maep->em_max_nfields =
66 MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
73 EFSYS_PROBE1(fail1, efx_rc_t, rc);
77 static __checkReturn efx_rc_t
78 efx_mae_get_outer_rule_caps(
80 __in unsigned int field_ncaps,
81 __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
84 EFX_MCDI_DECLARE_BUF(payload,
85 MC_CMD_MAE_GET_OR_CAPS_IN_LEN,
86 MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2);
87 unsigned int mcdi_field_ncaps;
91 if (MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps) >
92 MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2) {
97 req.emr_cmd = MC_CMD_MAE_GET_OR_CAPS;
98 req.emr_in_buf = payload;
99 req.emr_in_length = MC_CMD_MAE_GET_OR_CAPS_IN_LEN;
100 req.emr_out_buf = payload;
101 req.emr_out_length = MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps);
103 efx_mcdi_execute(enp, &req);
105 if (req.emr_rc != 0) {
110 mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
112 if (req.emr_out_length_used <
113 MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
118 if (mcdi_field_ncaps > field_ncaps) {
123 for (i = 0; i < mcdi_field_ncaps; ++i) {
127 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
128 MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
129 MAE_FIELD_FLAGS_SUPPORT_STATUS);
131 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
132 MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
133 MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
135 field_caps[i].emfc_match_affects_class =
136 (match_flag != 0) ? B_TRUE : B_FALSE;
138 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
139 MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
140 MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
142 field_caps[i].emfc_mask_affects_class =
143 (mask_flag != 0) ? B_TRUE : B_FALSE;
155 EFSYS_PROBE1(fail1, efx_rc_t, rc);
159 static __checkReturn efx_rc_t
160 efx_mae_get_action_rule_caps(
162 __in unsigned int field_ncaps,
163 __out_ecount(field_ncaps) efx_mae_field_cap_t *field_caps)
166 EFX_MCDI_DECLARE_BUF(payload,
167 MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
168 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
169 unsigned int mcdi_field_ncaps;
173 if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
174 MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
179 req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
180 req.emr_in_buf = payload;
181 req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
182 req.emr_out_buf = payload;
183 req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
185 efx_mcdi_execute(enp, &req);
187 if (req.emr_rc != 0) {
192 mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
194 if (req.emr_out_length_used <
195 MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
200 if (mcdi_field_ncaps > field_ncaps) {
205 for (i = 0; i < mcdi_field_ncaps; ++i) {
209 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
210 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
211 MAE_FIELD_FLAGS_SUPPORT_STATUS);
213 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
214 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
215 MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
217 field_caps[i].emfc_match_affects_class =
218 (match_flag != 0) ? B_TRUE : B_FALSE;
220 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
221 MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
222 MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
224 field_caps[i].emfc_mask_affects_class =
225 (mask_flag != 0) ? B_TRUE : B_FALSE;
237 EFSYS_PROBE1(fail1, efx_rc_t, rc);
241 __checkReturn efx_rc_t
245 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
246 efx_mae_field_cap_t *or_fcaps;
247 size_t or_fcaps_size;
248 efx_mae_field_cap_t *ar_fcaps;
249 size_t ar_fcaps_size;
253 if (encp->enc_mae_supported == B_FALSE) {
258 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
266 rc = efx_mae_get_capabilities(enp);
270 or_fcaps_size = maep->em_max_nfields * sizeof (*or_fcaps);
271 EFSYS_KMEM_ALLOC(enp->en_esip, or_fcaps_size, or_fcaps);
272 if (or_fcaps == NULL) {
277 maep->em_outer_rule_field_caps_size = or_fcaps_size;
278 maep->em_outer_rule_field_caps = or_fcaps;
280 rc = efx_mae_get_outer_rule_caps(enp, maep->em_max_nfields, or_fcaps);
284 ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
285 EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
286 if (ar_fcaps == NULL) {
291 maep->em_action_rule_field_caps_size = ar_fcaps_size;
292 maep->em_action_rule_field_caps = ar_fcaps;
294 rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
302 EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
307 EFSYS_KMEM_FREE(enp->en_esip, or_fcaps_size, or_fcaps);
312 EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
317 EFSYS_PROBE1(fail1, efx_rc_t, rc);
325 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
326 efx_mae_t *maep = enp->en_maep;
328 if (encp->enc_mae_supported == B_FALSE)
331 EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
332 maep->em_action_rule_field_caps);
333 EFSYS_KMEM_FREE(enp->en_esip, maep->em_outer_rule_field_caps_size,
334 maep->em_outer_rule_field_caps);
335 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
339 __checkReturn efx_rc_t
342 __out efx_mae_limits_t *emlp)
344 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
345 struct efx_mae_s *maep = enp->en_maep;
348 if (encp->enc_mae_supported == B_FALSE) {
353 emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
354 emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
355 emlp->eml_encap_types_supported = maep->em_encap_types_supported;
360 EFSYS_PROBE1(fail1, efx_rc_t, rc);
364 __checkReturn efx_rc_t
365 efx_mae_match_spec_init(
367 __in efx_mae_rule_type_t type,
369 __out efx_mae_match_spec_t **specp)
371 efx_mae_match_spec_t *spec;
375 case EFX_MAE_RULE_OUTER:
377 case EFX_MAE_RULE_ACTION:
384 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
390 spec->emms_type = type;
391 spec->emms_prio = prio;
400 EFSYS_PROBE1(fail1, efx_rc_t, rc);
405 efx_mae_match_spec_fini(
407 __in efx_mae_match_spec_t *spec)
409 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
412 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
413 typedef enum efx_mae_field_cap_id_e {
414 EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
415 EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
416 EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
417 EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
418 EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
419 EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
420 EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
421 EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
422 EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
423 EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
424 EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
425 EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
426 EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
427 EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
428 EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
429 EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
430 EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
431 EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
432 EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
433 EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
434 EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
435 EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
436 EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
437 EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
438 EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
439 EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
440 EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
441 EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
442 EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
443 EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
444 EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
445 EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
446 EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
447 EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
448 EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
449 EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
451 EFX_MAE_FIELD_CAP_NIDS
452 } efx_mae_field_cap_id_t;
454 typedef enum efx_mae_field_endianness_e {
455 EFX_MAE_FIELD_LE = 0,
458 EFX_MAE_FIELD_ENDIANNESS_NTYPES
459 } efx_mae_field_endianness_t;
462 * The following structure is a means to describe an MAE field.
463 * The information in it is meant to be used internally by
464 * APIs for addressing a given field in a mask-value pairs
465 * structure and for validation purposes.
467 * A field may have an alternative one. This structure
468 * has additional members to reference the alternative
469 * field's mask. See efx_mae_match_spec_is_valid().
471 typedef struct efx_mae_mv_desc_s {
472 efx_mae_field_cap_id_t emmd_field_cap_id;
474 size_t emmd_value_size;
475 size_t emmd_value_offset;
476 size_t emmd_mask_size;
477 size_t emmd_mask_offset;
480 * Having the alternative field's mask size set to 0
481 * means that there's no alternative field specified.
483 size_t emmd_alt_mask_size;
484 size_t emmd_alt_mask_offset;
486 /* Primary field and the alternative one are of the same endianness. */
487 efx_mae_field_endianness_t emmd_endianness;
490 /* Indices to this array are provided by efx_mae_field_id_t */
491 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
492 #define EFX_MAE_MV_DESC(_name, _endianness) \
493 [EFX_MAE_FIELD_##_name] = \
495 EFX_MAE_FIELD_ID_##_name, \
496 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN, \
497 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST, \
498 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN, \
499 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST, \
500 0, 0 /* no alternative field */, \
504 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
505 EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
506 EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
507 EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
508 EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
509 EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
510 EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
511 EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
512 EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
513 EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
514 EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
515 EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
516 EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
517 EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
518 EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
519 EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
520 EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
521 EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
522 EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
523 EFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),
525 #undef EFX_MAE_MV_DESC
528 /* Indices to this array are provided by efx_mae_field_id_t */
529 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
530 #define EFX_MAE_MV_DESC(_name, _endianness) \
531 [EFX_MAE_FIELD_##_name] = \
533 EFX_MAE_FIELD_ID_##_name, \
534 MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
535 MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
536 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
537 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
538 0, 0 /* no alternative field */, \
542 /* Same as EFX_MAE_MV_DESC(), but also indicates an alternative field. */
543 #define EFX_MAE_MV_DESC_ALT(_name, _alt_name, _endianness) \
544 [EFX_MAE_FIELD_##_name] = \
546 EFX_MAE_FIELD_ID_##_name, \
547 MAE_ENC_FIELD_PAIRS_##_name##_LEN, \
548 MAE_ENC_FIELD_PAIRS_##_name##_OFST, \
549 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN, \
550 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST, \
551 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_LEN, \
552 MAE_ENC_FIELD_PAIRS_##_alt_name##_MASK_OFST, \
556 EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
557 EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
558 EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
559 EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
560 EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
561 EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
562 EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
563 EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
564 EFX_MAE_MV_DESC_ALT(ENC_SRC_IP4_BE, ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
565 EFX_MAE_MV_DESC_ALT(ENC_DST_IP4_BE, ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
566 EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
567 EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
568 EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
569 EFX_MAE_MV_DESC_ALT(ENC_SRC_IP6_BE, ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
570 EFX_MAE_MV_DESC_ALT(ENC_DST_IP6_BE, ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
571 EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
572 EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
574 #undef EFX_MAE_MV_DESC_ALT
575 #undef EFX_MAE_MV_DESC
578 __checkReturn efx_rc_t
579 efx_mae_mport_by_phy_port(
580 __in uint32_t phy_port,
581 __out efx_mport_sel_t *mportp)
586 if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
591 EFX_POPULATE_DWORD_2(dword,
592 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
593 MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
595 memset(mportp, 0, sizeof (*mportp));
597 * The constructed DWORD is little-endian,
598 * but the resulting value is meant to be
599 * passed to MCDIs, where it will undergo
600 * host-order to little endian conversion.
602 mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
607 EFSYS_PROBE1(fail1, efx_rc_t, rc);
611 __checkReturn efx_rc_t
612 efx_mae_mport_by_pcie_function(
615 __out efx_mport_sel_t *mportp)
620 EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
621 MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
623 if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
628 if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
633 EFX_POPULATE_DWORD_3(dword,
634 MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
635 MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
636 MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
638 memset(mportp, 0, sizeof (*mportp));
640 * The constructed DWORD is little-endian,
641 * but the resulting value is meant to be
642 * passed to MCDIs, where it will undergo
643 * host-order to little endian conversion.
645 mportp->sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
652 EFSYS_PROBE1(fail1, efx_rc_t, rc);
656 __checkReturn efx_rc_t
657 efx_mae_match_spec_field_set(
658 __in efx_mae_match_spec_t *spec,
659 __in efx_mae_field_id_t field_id,
660 __in size_t value_size,
661 __in_bcount(value_size) const uint8_t *value,
662 __in size_t mask_size,
663 __in_bcount(mask_size) const uint8_t *mask)
665 const efx_mae_mv_desc_t *descp;
666 unsigned int desc_set_nentries;
670 switch (spec->emms_type) {
671 case EFX_MAE_RULE_OUTER:
673 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
674 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
675 mvp = spec->emms_mask_value_pairs.outer;
677 case EFX_MAE_RULE_ACTION:
679 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
680 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
681 mvp = spec->emms_mask_value_pairs.action;
688 if ((unsigned int)field_id >= desc_set_nentries) {
693 if (value_size != descp->emmd_value_size) {
698 if (mask_size != descp->emmd_mask_size) {
703 if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
705 * The mask/value are in network (big endian) order.
706 * The MCDI request field is also big endian.
708 memcpy(mvp + descp->emmd_value_offset, value, value_size);
709 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
714 * The mask/value are in host byte order.
715 * The MCDI request field is little endian.
717 switch (value_size) {
719 EFX_POPULATE_DWORD_1(dword,
720 EFX_DWORD_0, *(const uint32_t *)value);
722 memcpy(mvp + descp->emmd_value_offset,
723 &dword, sizeof (dword));
726 EFSYS_ASSERT(B_FALSE);
731 EFX_POPULATE_DWORD_1(dword,
732 EFX_DWORD_0, *(const uint32_t *)mask);
734 memcpy(mvp + descp->emmd_mask_offset,
735 &dword, sizeof (dword));
738 EFSYS_ASSERT(B_FALSE);
751 EFSYS_PROBE1(fail1, efx_rc_t, rc);
755 __checkReturn efx_rc_t
756 efx_mae_match_spec_mport_set(
757 __in efx_mae_match_spec_t *spec,
758 __in const efx_mport_sel_t *valuep,
759 __in_opt const efx_mport_sel_t *maskp)
761 uint32_t full_mask = UINT32_MAX;
766 if (valuep == NULL) {
771 vp = (const uint8_t *)&valuep->sel;
773 mp = (const uint8_t *)&maskp->sel;
775 mp = (const uint8_t *)&full_mask;
777 rc = efx_mae_match_spec_field_set(spec,
778 EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
779 sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
788 EFSYS_PROBE1(fail1, efx_rc_t, rc);
792 __checkReturn boolean_t
793 efx_mae_match_specs_equal(
794 __in const efx_mae_match_spec_t *left,
795 __in const efx_mae_match_spec_t *right)
797 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
800 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit) \
801 ((_mask)[(_bit) / (_mask_page_nbits)] & \
802 (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
806 __in size_t mask_nbytes,
807 __in_bcount(mask_nbytes) const uint8_t *maskp)
809 boolean_t prev_bit_is_set = B_TRUE;
812 for (i = 0; i < 8 * mask_nbytes; ++i) {
813 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
815 if (!prev_bit_is_set && bit_is_set)
818 prev_bit_is_set = bit_is_set;
825 efx_mask_is_all_ones(
826 __in size_t mask_nbytes,
827 __in_bcount(mask_nbytes) const uint8_t *maskp)
832 for (i = 0; i < mask_nbytes; ++i)
835 return (t == (uint8_t)(~0));
839 efx_mask_is_all_zeros(
840 __in size_t mask_nbytes,
841 __in_bcount(mask_nbytes) const uint8_t *maskp)
846 for (i = 0; i < mask_nbytes; ++i)
852 __checkReturn boolean_t
853 efx_mae_match_spec_is_valid(
855 __in const efx_mae_match_spec_t *spec)
857 efx_mae_t *maep = enp->en_maep;
858 unsigned int field_ncaps = maep->em_max_nfields;
859 const efx_mae_field_cap_t *field_caps;
860 const efx_mae_mv_desc_t *desc_setp;
861 unsigned int desc_set_nentries;
862 boolean_t is_valid = B_TRUE;
863 efx_mae_field_id_t field_id;
866 switch (spec->emms_type) {
867 case EFX_MAE_RULE_OUTER:
868 field_caps = maep->em_outer_rule_field_caps;
869 desc_setp = __efx_mae_outer_rule_mv_desc_set;
871 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
872 mvp = spec->emms_mask_value_pairs.outer;
874 case EFX_MAE_RULE_ACTION:
875 field_caps = maep->em_action_rule_field_caps;
876 desc_setp = __efx_mae_action_rule_mv_desc_set;
878 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
879 mvp = spec->emms_mask_value_pairs.action;
885 if (field_caps == NULL)
888 for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
890 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
891 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
892 const uint8_t *alt_m_buf = mvp + descp->emmd_alt_mask_offset;
893 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
894 size_t alt_m_size = descp->emmd_alt_mask_size;
895 size_t m_size = descp->emmd_mask_size;
898 continue; /* Skip array gap */
900 if ((unsigned int)field_cap_id >= field_ncaps) {
902 * The FW has not reported capability status for
903 * this field. Make sure that its mask is zeroed.
905 is_valid = efx_mask_is_all_zeros(m_size, m_buf);
906 if (is_valid != B_FALSE)
912 switch (field_caps[field_cap_id].emfc_support) {
913 case MAE_FIELD_SUPPORTED_MATCH_MASK:
916 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
917 is_valid = efx_mask_is_prefix(m_size, m_buf);
919 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
920 is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
921 efx_mask_is_all_zeros(m_size, m_buf));
923 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
924 is_valid = efx_mask_is_all_ones(m_size, m_buf);
926 if ((is_valid == B_FALSE) && (alt_m_size != 0)) {
928 * This field has an alternative one. The FW
929 * reports ALWAYS for both implying that one
930 * of them is required to have all-ones mask.
932 * The primary field's mask is incorrect; go
933 * on to check that of the alternative field.
935 is_valid = efx_mask_is_all_ones(alt_m_size,
939 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
940 case MAE_FIELD_UNSUPPORTED:
942 is_valid = efx_mask_is_all_zeros(m_size, m_buf);
946 if (is_valid == B_FALSE)
953 __checkReturn efx_rc_t
954 efx_mae_action_set_spec_init(
956 __out efx_mae_actions_t **specp)
958 efx_mae_actions_t *spec;
961 EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
972 EFSYS_PROBE1(fail1, efx_rc_t, rc);
977 efx_mae_action_set_spec_fini(
979 __in efx_mae_actions_t *spec)
981 EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
984 static __checkReturn efx_rc_t
985 efx_mae_action_set_add_vlan_pop(
986 __in efx_mae_actions_t *spec,
987 __in size_t arg_size,
988 __in_bcount(arg_size) const uint8_t *arg)
1002 if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
1007 ++spec->ema_n_vlan_tags_to_pop;
1016 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1020 static __checkReturn efx_rc_t
1021 efx_mae_action_set_add_vlan_push(
1022 __in efx_mae_actions_t *spec,
1023 __in size_t arg_size,
1024 __in_bcount(arg_size) const uint8_t *arg)
1026 unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
1029 if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
1039 if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1044 memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
1045 ++(spec->ema_n_vlan_tags_to_push);
1054 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1058 static __checkReturn efx_rc_t
1059 efx_mae_action_set_add_flag(
1060 __in efx_mae_actions_t *spec,
1061 __in size_t arg_size,
1062 __in_bcount(arg_size) const uint8_t *arg)
1066 _NOTE(ARGUNUSED(spec))
1068 if (arg_size != 0) {
1078 /* This action does not have any arguments, so do nothing here. */
1085 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1089 static __checkReturn efx_rc_t
1090 efx_mae_action_set_add_mark(
1091 __in efx_mae_actions_t *spec,
1092 __in size_t arg_size,
1093 __in_bcount(arg_size) const uint8_t *arg)
1097 if (arg_size != sizeof (spec->ema_mark_value)) {
1107 memcpy(&spec->ema_mark_value, arg, arg_size);
1114 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1118 static __checkReturn efx_rc_t
1119 efx_mae_action_set_add_deliver(
1120 __in efx_mae_actions_t *spec,
1121 __in size_t arg_size,
1122 __in_bcount(arg_size) const uint8_t *arg)
1126 if (arg_size != sizeof (spec->ema_deliver_mport)) {
1136 memcpy(&spec->ema_deliver_mport, arg, arg_size);
1143 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1147 typedef struct efx_mae_action_desc_s {
1148 /* Action specific handler */
1149 efx_rc_t (*emad_add)(efx_mae_actions_t *,
1150 size_t, const uint8_t *);
1151 } efx_mae_action_desc_t;
1153 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
1154 [EFX_MAE_ACTION_VLAN_POP] = {
1155 .emad_add = efx_mae_action_set_add_vlan_pop
1157 [EFX_MAE_ACTION_VLAN_PUSH] = {
1158 .emad_add = efx_mae_action_set_add_vlan_push
1160 [EFX_MAE_ACTION_FLAG] = {
1161 .emad_add = efx_mae_action_set_add_flag
1163 [EFX_MAE_ACTION_MARK] = {
1164 .emad_add = efx_mae_action_set_add_mark
1166 [EFX_MAE_ACTION_DELIVER] = {
1167 .emad_add = efx_mae_action_set_add_deliver
1171 static const uint32_t efx_mae_action_ordered_map =
1172 (1U << EFX_MAE_ACTION_VLAN_POP) |
1173 (1U << EFX_MAE_ACTION_VLAN_PUSH) |
1174 (1U << EFX_MAE_ACTION_FLAG) |
1175 (1U << EFX_MAE_ACTION_MARK) |
1176 (1U << EFX_MAE_ACTION_DELIVER);
1179 * These actions must not be added after DELIVER, but
1180 * they can have any place among the rest of
1181 * strictly ordered actions.
1183 static const uint32_t efx_mae_action_nonstrict_map =
1184 (1U << EFX_MAE_ACTION_FLAG) |
1185 (1U << EFX_MAE_ACTION_MARK);
1187 static const uint32_t efx_mae_action_repeat_map =
1188 (1U << EFX_MAE_ACTION_VLAN_POP) |
1189 (1U << EFX_MAE_ACTION_VLAN_PUSH);
1192 * Add an action to an action set.
1194 * This has to be invoked in the desired action order.
1195 * An out-of-order action request will be turned down.
1197 static __checkReturn efx_rc_t
1198 efx_mae_action_set_spec_populate(
1199 __in efx_mae_actions_t *spec,
1200 __in efx_mae_action_t type,
1201 __in size_t arg_size,
1202 __in_bcount(arg_size) const uint8_t *arg)
1204 uint32_t action_mask;
1207 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1208 (sizeof (efx_mae_action_ordered_map) * 8));
1209 EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1210 (sizeof (efx_mae_action_repeat_map) * 8));
1212 EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1213 EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1214 EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1216 if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1221 action_mask = (1U << type);
1223 if ((spec->ema_actions & action_mask) != 0) {
1224 /* The action set already contains this action. */
1225 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1226 /* Cannot add another non-repeatable action. */
1232 if ((efx_mae_action_ordered_map & action_mask) != 0) {
1233 uint32_t strict_ordered_map =
1234 efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1235 uint32_t later_actions_mask =
1236 strict_ordered_map & ~(action_mask | (action_mask - 1));
1238 if ((spec->ema_actions & later_actions_mask) != 0) {
1239 /* Cannot add an action after later ordered actions. */
1245 if (efx_mae_actions[type].emad_add != NULL) {
1246 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1251 spec->ema_actions |= action_mask;
1262 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1266 __checkReturn efx_rc_t
1267 efx_mae_action_set_populate_vlan_pop(
1268 __in efx_mae_actions_t *spec)
1270 return (efx_mae_action_set_spec_populate(spec,
1271 EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1274 __checkReturn efx_rc_t
1275 efx_mae_action_set_populate_vlan_push(
1276 __in efx_mae_actions_t *spec,
1277 __in uint16_t tpid_be,
1278 __in uint16_t tci_be)
1280 efx_mae_action_vlan_push_t action;
1281 const uint8_t *arg = (const uint8_t *)&action;
1283 action.emavp_tpid_be = tpid_be;
1284 action.emavp_tci_be = tci_be;
1286 return (efx_mae_action_set_spec_populate(spec,
1287 EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1290 __checkReturn efx_rc_t
1291 efx_mae_action_set_populate_flag(
1292 __in efx_mae_actions_t *spec)
1294 return (efx_mae_action_set_spec_populate(spec,
1295 EFX_MAE_ACTION_FLAG, 0, NULL));
1298 __checkReturn efx_rc_t
1299 efx_mae_action_set_populate_mark(
1300 __in efx_mae_actions_t *spec,
1301 __in uint32_t mark_value)
1303 const uint8_t *arg = (const uint8_t *)&mark_value;
1305 return (efx_mae_action_set_spec_populate(spec,
1306 EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1309 __checkReturn efx_rc_t
1310 efx_mae_action_set_populate_deliver(
1311 __in efx_mae_actions_t *spec,
1312 __in const efx_mport_sel_t *mportp)
1317 if (mportp == NULL) {
1322 arg = (const uint8_t *)&mportp->sel;
1324 return (efx_mae_action_set_spec_populate(spec,
1325 EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1328 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1332 __checkReturn efx_rc_t
1333 efx_mae_action_set_populate_drop(
1334 __in efx_mae_actions_t *spec)
1336 efx_mport_sel_t mport;
1340 EFX_POPULATE_DWORD_1(dword,
1341 MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1344 * The constructed DWORD is little-endian,
1345 * but the resulting value is meant to be
1346 * passed to MCDIs, where it will undergo
1347 * host-order to little endian conversion.
1349 mport.sel = EFX_DWORD_FIELD(dword, EFX_DWORD_0);
1351 arg = (const uint8_t *)&mport.sel;
1353 return (efx_mae_action_set_spec_populate(spec,
1354 EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1357 __checkReturn boolean_t
1358 efx_mae_action_set_specs_equal(
1359 __in const efx_mae_actions_t *left,
1360 __in const efx_mae_actions_t *right)
1362 return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1365 __checkReturn efx_rc_t
1366 efx_mae_match_specs_class_cmp(
1367 __in efx_nic_t *enp,
1368 __in const efx_mae_match_spec_t *left,
1369 __in const efx_mae_match_spec_t *right,
1370 __out boolean_t *have_same_classp)
1372 efx_mae_t *maep = enp->en_maep;
1373 unsigned int field_ncaps = maep->em_max_nfields;
1374 const efx_mae_field_cap_t *field_caps;
1375 const efx_mae_mv_desc_t *desc_setp;
1376 unsigned int desc_set_nentries;
1377 boolean_t have_same_class = B_TRUE;
1378 efx_mae_field_id_t field_id;
1379 const uint8_t *mvpl;
1380 const uint8_t *mvpr;
1383 switch (left->emms_type) {
1384 case EFX_MAE_RULE_OUTER:
1385 field_caps = maep->em_outer_rule_field_caps;
1386 desc_setp = __efx_mae_outer_rule_mv_desc_set;
1388 EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
1389 mvpl = left->emms_mask_value_pairs.outer;
1390 mvpr = right->emms_mask_value_pairs.outer;
1392 case EFX_MAE_RULE_ACTION:
1393 field_caps = maep->em_action_rule_field_caps;
1394 desc_setp = __efx_mae_action_rule_mv_desc_set;
1396 EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1397 mvpl = left->emms_mask_value_pairs.action;
1398 mvpr = right->emms_mask_value_pairs.action;
1405 if (field_caps == NULL) {
1410 if (left->emms_type != right->emms_type ||
1411 left->emms_prio != right->emms_prio) {
1413 * Rules of different types can never map to the same class.
1415 * The FW can support some set of match criteria for one
1416 * priority and not support the very same set for
1417 * another priority. Thus, two rules which have
1418 * different priorities can never map to
1421 *have_same_classp = B_FALSE;
1425 for (field_id = 0; (unsigned int)field_id < desc_set_nentries;
1427 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1428 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1429 const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1430 const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1431 size_t mask_size = descp->emmd_mask_size;
1432 const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1433 const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1434 size_t value_size = descp->emmd_value_size;
1437 continue; /* Skip array gap */
1439 if ((unsigned int)field_cap_id >= field_ncaps) {
1441 * The FW has not reported capability status for this
1442 * field. It's unknown whether any difference between
1443 * the two masks / values affects the class. The only
1444 * case when the class must be the same is when these
1445 * mask-value pairs match. Otherwise, report mismatch.
1447 if ((memcmp(lmaskp, rmaskp, mask_size) == 0) &&
1448 (memcmp(lvalp, rvalp, value_size) == 0))
1454 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1455 if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1456 have_same_class = B_FALSE;
1461 if (field_caps[field_cap_id].emfc_match_affects_class) {
1462 if (memcmp(lvalp, rvalp, value_size) != 0) {
1463 have_same_class = B_FALSE;
1469 *have_same_classp = have_same_class;
1476 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1480 __checkReturn efx_rc_t
1481 efx_mae_outer_rule_insert(
1482 __in efx_nic_t *enp,
1483 __in const efx_mae_match_spec_t *spec,
1484 __in efx_tunnel_protocol_t encap_type,
1485 __out efx_mae_rule_id_t *or_idp)
1487 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1489 EFX_MCDI_DECLARE_BUF(payload,
1490 MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,
1491 MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);
1492 uint32_t encap_type_mcdi;
1493 efx_mae_rule_id_t or_id;
1497 EFX_STATIC_ASSERT(sizeof (or_idp->id) ==
1498 MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);
1500 EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1501 MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);
1503 if (encp->enc_mae_supported == B_FALSE) {
1508 if (spec->emms_type != EFX_MAE_RULE_OUTER) {
1513 switch (encap_type) {
1514 case EFX_TUNNEL_PROTOCOL_NONE:
1515 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
1517 case EFX_TUNNEL_PROTOCOL_VXLAN:
1518 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
1520 case EFX_TUNNEL_PROTOCOL_GENEVE:
1521 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
1523 case EFX_TUNNEL_PROTOCOL_NVGRE:
1524 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
1531 req.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;
1532 req.emr_in_buf = payload;
1533 req.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;
1534 req.emr_out_buf = payload;
1535 req.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;
1537 MCDI_IN_SET_DWORD(req,
1538 MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);
1540 MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);
1543 * Mask-value pairs have been stored in the byte order needed for the
1544 * MCDI request and are thus safe to be copied directly to the buffer.
1545 * The library cares about byte order in efx_mae_match_spec_field_set().
1547 EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=
1548 MAE_ENC_FIELD_PAIRS_LEN);
1549 offset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;
1550 memcpy(payload + offset, spec->emms_mask_value_pairs.outer,
1551 MAE_ENC_FIELD_PAIRS_LEN);
1553 efx_mcdi_execute(enp, &req);
1555 if (req.emr_rc != 0) {
1560 if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {
1565 or_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);
1566 if (or_id.id == EFX_MAE_RSRC_ID_INVALID) {
1571 or_idp->id = or_id.id;
1586 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1590 __checkReturn efx_rc_t
1591 efx_mae_outer_rule_remove(
1592 __in efx_nic_t *enp,
1593 __in const efx_mae_rule_id_t *or_idp)
1595 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1597 EFX_MCDI_DECLARE_BUF(payload,
1598 MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),
1599 MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));
1602 if (encp->enc_mae_supported == B_FALSE) {
1607 req.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;
1608 req.emr_in_buf = payload;
1609 req.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);
1610 req.emr_out_buf = payload;
1611 req.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);
1613 MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);
1615 efx_mcdi_execute(enp, &req);
1617 if (req.emr_rc != 0) {
1622 if (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=
1624 /* Firmware failed to remove the outer rule. */
1636 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1640 __checkReturn efx_rc_t
1641 efx_mae_match_spec_outer_rule_id_set(
1642 __in efx_mae_match_spec_t *spec,
1643 __in const efx_mae_rule_id_t *or_idp)
1645 uint32_t full_mask = UINT32_MAX;
1648 if (spec->emms_type != EFX_MAE_RULE_ACTION) {
1653 if (or_idp == NULL) {
1658 rc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,
1659 sizeof (or_idp->id), (const uint8_t *)&or_idp->id,
1660 sizeof (full_mask), (const uint8_t *)&full_mask);
1671 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1675 __checkReturn efx_rc_t
1676 efx_mae_action_set_alloc(
1677 __in efx_nic_t *enp,
1678 __in const efx_mae_actions_t *spec,
1679 __out efx_mae_aset_id_t *aset_idp)
1681 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1683 EFX_MCDI_DECLARE_BUF(payload,
1684 MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1685 MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1686 efx_mae_aset_id_t aset_id;
1689 if (encp->enc_mae_supported == B_FALSE) {
1694 req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1695 req.emr_in_buf = payload;
1696 req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1697 req.emr_out_buf = payload;
1698 req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1701 * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1702 * corresponding resource types are supported by the implementation.
1703 * Use proper resource ID assignments instead.
1705 MCDI_IN_SET_DWORD(req,
1706 MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1707 MCDI_IN_SET_DWORD(req,
1708 MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1709 MCDI_IN_SET_DWORD(req,
1710 MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1712 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1713 MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1715 if (spec->ema_n_vlan_tags_to_push > 0) {
1716 unsigned int outer_tag_idx;
1718 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1719 MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1720 spec->ema_n_vlan_tags_to_push);
1722 if (spec->ema_n_vlan_tags_to_push ==
1723 EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1724 MCDI_IN_SET_WORD(req,
1725 MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1726 spec->ema_vlan_push_descs[0].emavp_tpid_be);
1727 MCDI_IN_SET_WORD(req,
1728 MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1729 spec->ema_vlan_push_descs[0].emavp_tci_be);
1732 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1734 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1735 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1736 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1737 spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1740 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1741 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1742 MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1745 if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1746 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1747 MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1749 MCDI_IN_SET_DWORD(req,
1750 MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1753 MCDI_IN_SET_DWORD(req,
1754 MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1756 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1757 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1758 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1759 MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1761 efx_mcdi_execute(enp, &req);
1763 if (req.emr_rc != 0) {
1768 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1773 aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1774 if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1779 aset_idp->id = aset_id.id;
1790 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1794 __checkReturn efx_rc_t
1795 efx_mae_action_set_free(
1796 __in efx_nic_t *enp,
1797 __in const efx_mae_aset_id_t *aset_idp)
1799 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1801 EFX_MCDI_DECLARE_BUF(payload,
1802 MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1803 MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1806 if (encp->enc_mae_supported == B_FALSE) {
1811 req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1812 req.emr_in_buf = payload;
1813 req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1814 req.emr_out_buf = payload;
1815 req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1817 MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1819 efx_mcdi_execute(enp, &req);
1821 if (req.emr_rc != 0) {
1826 if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1828 /* Firmware failed to free the action set. */
1840 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1844 __checkReturn efx_rc_t
1845 efx_mae_action_rule_insert(
1846 __in efx_nic_t *enp,
1847 __in const efx_mae_match_spec_t *spec,
1848 __in const efx_mae_aset_list_id_t *asl_idp,
1849 __in const efx_mae_aset_id_t *as_idp,
1850 __out efx_mae_rule_id_t *ar_idp)
1852 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1854 EFX_MCDI_DECLARE_BUF(payload,
1855 MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1856 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1857 efx_oword_t *rule_response;
1858 efx_mae_rule_id_t ar_id;
1862 EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1863 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1865 EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1866 MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1868 if (encp->enc_mae_supported == B_FALSE) {
1873 if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1874 (asl_idp != NULL && as_idp != NULL) ||
1875 (asl_idp == NULL && as_idp == NULL)) {
1880 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1881 req.emr_in_buf = payload;
1882 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1883 req.emr_out_buf = payload;
1884 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1886 EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1887 MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1888 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1889 rule_response = (efx_oword_t *)(payload + offset);
1890 EFX_POPULATE_OWORD_3(*rule_response,
1891 MAE_ACTION_RULE_RESPONSE_ASL_ID,
1892 (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1893 MAE_ACTION_RULE_RESPONSE_AS_ID,
1894 (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1895 MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1897 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1900 * Mask-value pairs have been stored in the byte order needed for the
1901 * MCDI request and are thus safe to be copied directly to the buffer.
1903 EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1904 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1905 offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1906 memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1907 MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1909 efx_mcdi_execute(enp, &req);
1911 if (req.emr_rc != 0) {
1916 if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1921 ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1922 if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1927 ar_idp->id = ar_id.id;
1940 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1944 __checkReturn efx_rc_t
1945 efx_mae_action_rule_remove(
1946 __in efx_nic_t *enp,
1947 __in const efx_mae_rule_id_t *ar_idp)
1949 const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1951 EFX_MCDI_DECLARE_BUF(payload,
1952 MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1953 MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1956 if (encp->enc_mae_supported == B_FALSE) {
1961 req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1962 req.emr_in_buf = payload;
1963 req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1964 req.emr_out_buf = payload;
1965 req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1967 MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1969 efx_mcdi_execute(enp, &req);
1971 if (req.emr_rc != 0) {
1976 if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1978 /* Firmware failed to delete the action rule. */
1990 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1994 #endif /* EFSYS_OPT_MAE */