drivers/common/sfc_efx/base/efx_mae.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019 Xilinx, Inc. All rights reserved.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11 #if EFSYS_OPT_MAE
  12
  13 static  __checkReturn                   efx_rc_t
  14 efx_mae_get_capabilities(
  15         __in                            efx_nic_t *enp)
  16 {
  17         efx_mcdi_req_t req;
  18         EFX_MCDI_DECLARE_BUF(payload,
  19             MC_CMD_MAE_GET_CAPS_IN_LEN,
  20             MC_CMD_MAE_GET_CAPS_OUT_LEN);
  21         struct efx_mae_s *maep = enp->en_maep;
  22         efx_rc_t rc;
  23
  24         req.emr_cmd = MC_CMD_MAE_GET_CAPS;
  25         req.emr_in_buf = payload;
  26         req.emr_in_length = MC_CMD_MAE_GET_CAPS_IN_LEN;
  27         req.emr_out_buf = payload;
  28         req.emr_out_length = MC_CMD_MAE_GET_CAPS_OUT_LEN;
  29
  30         efx_mcdi_execute(enp, &req);
  31
  32         if (req.emr_rc != 0) {
  33                 rc = req.emr_rc;
  34                 goto fail1;
  35         }
  36
  37         if (req.emr_out_length_used < MC_CMD_MAE_GET_CAPS_OUT_LEN) {
  38                 rc = EMSGSIZE;
  39                 goto fail2;
  40         }
  41
  42         maep->em_max_n_outer_prios =
  43             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_OUTER_PRIOS);
  44
  45         maep->em_max_n_action_prios =
  46             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ACTION_PRIOS);
  47
  48         maep->em_encap_types_supported = 0;
  49
  50         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN) == 1) {
  51                 maep->em_encap_types_supported |=
  52                     (1U << EFX_TUNNEL_PROTOCOL_VXLAN);
  53         }
  54
  55         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE) == 1) {
  56                 maep->em_encap_types_supported |=
  57                     (1U << EFX_TUNNEL_PROTOCOL_GENEVE);
  58         }
  59
  60         if (MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE) == 1) {
  61                 maep->em_encap_types_supported |=
  62                     (1U << EFX_TUNNEL_PROTOCOL_NVGRE);
  63         }
  64
  65         maep->em_max_nfields =
  66             MCDI_OUT_DWORD(req, MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT);
  67
  68         return (0);
  69
  70 fail2:
  71         EFSYS_PROBE(fail2);
  72 fail1:
  73         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  74         return (rc);
  75 }
  76
  77 static  __checkReturn                   efx_rc_t
  78 efx_mae_get_outer_rule_caps(
  79         __in                            efx_nic_t *enp,
  80         __in                            unsigned int field_ncaps,
  81         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
  82 {
  83         efx_mcdi_req_t req;
  84         EFX_MCDI_DECLARE_BUF(payload,
  85             MC_CMD_MAE_GET_OR_CAPS_IN_LEN,
  86             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2);
  87         unsigned int mcdi_field_ncaps;
  88         unsigned int i;
  89         efx_rc_t rc;
  90
  91         if (MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps) >
  92             MC_CMD_MAE_GET_OR_CAPS_OUT_LENMAX_MCDI2) {
  93                 rc = EINVAL;
  94                 goto fail1;
  95         }
  96
  97         req.emr_cmd = MC_CMD_MAE_GET_OR_CAPS;
  98         req.emr_in_buf = payload;
  99         req.emr_in_length = MC_CMD_MAE_GET_OR_CAPS_IN_LEN;
 100         req.emr_out_buf = payload;
 101         req.emr_out_length = MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(field_ncaps);
 102
 103         efx_mcdi_execute(enp, &req);
 104
 105         if (req.emr_rc != 0) {
 106                 rc = req.emr_rc;
 107                 goto fail2;
 108         }
 109
 110         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 111
 112         if (req.emr_out_length_used <
 113             MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 114                 rc = EMSGSIZE;
 115                 goto fail3;
 116         }
 117
 118         if (mcdi_field_ncaps > field_ncaps) {
 119                 rc = EMSGSIZE;
 120                 goto fail4;
 121         }
 122
 123         for (i = 0; i < mcdi_field_ncaps; ++i) {
 124                 uint32_t match_flag;
 125                 uint32_t mask_flag;
 126
 127                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 128                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 129                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 130
 131                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 132                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 133                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 134
 135                 field_caps[i].emfc_match_affects_class =
 136                     (match_flag != 0) ? B_TRUE : B_FALSE;
 137
 138                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 139                     MAE_GET_OR_CAPS_OUT_FIELD_FLAGS, i,
 140                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 141
 142                 field_caps[i].emfc_mask_affects_class =
 143                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 144         }
 145
 146         return (0);
 147
 148 fail4:
 149         EFSYS_PROBE(fail4);
 150 fail3:
 151         EFSYS_PROBE(fail3);
 152 fail2:
 153         EFSYS_PROBE(fail2);
 154 fail1:
 155         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 156         return (rc);
 157 }
 158
 159 static  __checkReturn                   efx_rc_t
 160 efx_mae_get_action_rule_caps(
 161         __in                            efx_nic_t *enp,
 162         __in                            unsigned int field_ncaps,
 163         __out_ecount(field_ncaps)       efx_mae_field_cap_t *field_caps)
 164 {
 165         efx_mcdi_req_t req;
 166         EFX_MCDI_DECLARE_BUF(payload,
 167             MC_CMD_MAE_GET_AR_CAPS_IN_LEN,
 168             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2);
 169         unsigned int mcdi_field_ncaps;
 170         unsigned int i;
 171         efx_rc_t rc;
 172
 173         if (MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps) >
 174             MC_CMD_MAE_GET_AR_CAPS_OUT_LENMAX_MCDI2) {
 175                 rc = EINVAL;
 176                 goto fail1;
 177         }
 178
 179         req.emr_cmd = MC_CMD_MAE_GET_AR_CAPS;
 180         req.emr_in_buf = payload;
 181         req.emr_in_length = MC_CMD_MAE_GET_AR_CAPS_IN_LEN;
 182         req.emr_out_buf = payload;
 183         req.emr_out_length = MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(field_ncaps);
 184
 185         efx_mcdi_execute(enp, &req);
 186
 187         if (req.emr_rc != 0) {
 188                 rc = req.emr_rc;
 189                 goto fail2;
 190         }
 191
 192         mcdi_field_ncaps = MCDI_OUT_DWORD(req, MAE_GET_OR_CAPS_OUT_COUNT);
 193
 194         if (req.emr_out_length_used <
 195             MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(mcdi_field_ncaps)) {
 196                 rc = EMSGSIZE;
 197                 goto fail3;
 198         }
 199
 200         if (mcdi_field_ncaps > field_ncaps) {
 201                 rc = EMSGSIZE;
 202                 goto fail4;
 203         }
 204
 205         for (i = 0; i < mcdi_field_ncaps; ++i) {
 206                 uint32_t match_flag;
 207                 uint32_t mask_flag;
 208
 209                 field_caps[i].emfc_support = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 210                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 211                     MAE_FIELD_FLAGS_SUPPORT_STATUS);
 212
 213                 match_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 214                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 215                     MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS);
 216
 217                 field_caps[i].emfc_match_affects_class =
 218                     (match_flag != 0) ? B_TRUE : B_FALSE;
 219
 220                 mask_flag = MCDI_OUT_INDEXED_DWORD_FIELD(req,
 221                     MAE_GET_AR_CAPS_OUT_FIELD_FLAGS, i,
 222                     MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS);
 223
 224                 field_caps[i].emfc_mask_affects_class =
 225                     (mask_flag != 0) ? B_TRUE : B_FALSE;
 226         }
 227
 228         return (0);
 229
 230 fail4:
 231         EFSYS_PROBE(fail4);
 232 fail3:
 233         EFSYS_PROBE(fail3);
 234 fail2:
 235         EFSYS_PROBE(fail2);
 236 fail1:
 237         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 238         return (rc);
 239 }
 240
 241         __checkReturn                   efx_rc_t
 242 efx_mae_init(
 243         __in                            efx_nic_t *enp)
 244 {
 245         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 246         efx_mae_field_cap_t *or_fcaps;
 247         size_t or_fcaps_size;
 248         efx_mae_field_cap_t *ar_fcaps;
 249         size_t ar_fcaps_size;
 250         efx_mae_t *maep;
 251         efx_rc_t rc;
 252
 253         if (encp->enc_mae_supported == B_FALSE) {
 254                 rc = ENOTSUP;
 255                 goto fail1;
 256         }
 257
 258         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*maep), maep);
 259         if (maep == NULL) {
 260                 rc = ENOMEM;
 261                 goto fail2;
 262         }
 263
 264         enp->en_maep = maep;
 265
 266         rc = efx_mae_get_capabilities(enp);
 267         if (rc != 0)
 268                 goto fail3;
 269
 270         or_fcaps_size = maep->em_max_nfields * sizeof (*or_fcaps);
 271         EFSYS_KMEM_ALLOC(enp->en_esip, or_fcaps_size, or_fcaps);
 272         if (or_fcaps == NULL) {
 273                 rc = ENOMEM;
 274                 goto fail4;
 275         }
 276
 277         maep->em_outer_rule_field_caps_size = or_fcaps_size;
 278         maep->em_outer_rule_field_caps = or_fcaps;
 279
 280         rc = efx_mae_get_outer_rule_caps(enp, maep->em_max_nfields, or_fcaps);
 281         if (rc != 0)
 282                 goto fail5;
 283
 284         ar_fcaps_size = maep->em_max_nfields * sizeof (*ar_fcaps);
 285         EFSYS_KMEM_ALLOC(enp->en_esip, ar_fcaps_size, ar_fcaps);
 286         if (ar_fcaps == NULL) {
 287                 rc = ENOMEM;
 288                 goto fail6;
 289         }
 290
 291         maep->em_action_rule_field_caps_size = ar_fcaps_size;
 292         maep->em_action_rule_field_caps = ar_fcaps;
 293
 294         rc = efx_mae_get_action_rule_caps(enp, maep->em_max_nfields, ar_fcaps);
 295         if (rc != 0)
 296                 goto fail7;
 297
 298         return (0);
 299
 300 fail7:
 301         EFSYS_PROBE(fail5);
 302         EFSYS_KMEM_FREE(enp->en_esip, ar_fcaps_size, ar_fcaps);
 303 fail6:
 304         EFSYS_PROBE(fail4);
 305 fail5:
 306         EFSYS_PROBE(fail5);
 307         EFSYS_KMEM_FREE(enp->en_esip, or_fcaps_size, or_fcaps);
 308 fail4:
 309         EFSYS_PROBE(fail4);
 310 fail3:
 311         EFSYS_PROBE(fail3);
 312         EFSYS_KMEM_FREE(enp->en_esip, sizeof (struct efx_mae_s), enp->en_maep);
 313         enp->en_maep = NULL;
 314 fail2:
 315         EFSYS_PROBE(fail2);
 316 fail1:
 317         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 318         return (rc);
 319 }
 320
 321                                         void
 322 efx_mae_fini(
 323         __in                            efx_nic_t *enp)
 324 {
 325         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 326         efx_mae_t *maep = enp->en_maep;
 327
 328         if (encp->enc_mae_supported == B_FALSE)
 329                 return;
 330
 331         EFSYS_KMEM_FREE(enp->en_esip, maep->em_action_rule_field_caps_size,
 332             maep->em_action_rule_field_caps);
 333         EFSYS_KMEM_FREE(enp->en_esip, maep->em_outer_rule_field_caps_size,
 334             maep->em_outer_rule_field_caps);
 335         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*maep), maep);
 336         enp->en_maep = NULL;
 337 }
 338
 339         __checkReturn                   efx_rc_t
 340 efx_mae_get_limits(
 341         __in                            efx_nic_t *enp,
 342         __out                           efx_mae_limits_t *emlp)
 343 {
 344         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
 345         struct efx_mae_s *maep = enp->en_maep;
 346         efx_rc_t rc;
 347
 348         if (encp->enc_mae_supported == B_FALSE) {
 349                 rc = ENOTSUP;
 350                 goto fail1;
 351         }
 352
 353         emlp->eml_max_n_outer_prios = maep->em_max_n_outer_prios;
 354         emlp->eml_max_n_action_prios = maep->em_max_n_action_prios;
 355         emlp->eml_encap_types_supported = maep->em_encap_types_supported;
 356
 357         return (0);
 358
 359 fail1:
 360         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 361         return (rc);
 362 }
 363
 364         __checkReturn                   efx_rc_t
 365 efx_mae_match_spec_init(
 366         __in                            efx_nic_t *enp,
 367         __in                            efx_mae_rule_type_t type,
 368         __in                            uint32_t prio,
 369         __out                           efx_mae_match_spec_t **specp)
 370 {
 371         efx_mae_match_spec_t *spec;
 372         efx_rc_t rc;
 373
 374         switch (type) {
 375         case EFX_MAE_RULE_OUTER:
 376                 break;
 377         case EFX_MAE_RULE_ACTION:
 378                 break;
 379         default:
 380                 rc = ENOTSUP;
 381                 goto fail1;
 382         }
 383
 384         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 385         if (spec == NULL) {
 386                 rc = ENOMEM;
 387                 goto fail2;
 388         }
 389
 390         spec->emms_type = type;
 391         spec->emms_prio = prio;
 392
 393         *specp = spec;
 394
 395         return (0);
 396
 397 fail2:
 398         EFSYS_PROBE(fail2);
 399 fail1:
 400         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 401         return (rc);
 402 }
 403
 404                                         void
 405 efx_mae_match_spec_fini(
 406         __in                            efx_nic_t *enp,
 407         __in                            efx_mae_match_spec_t *spec)
 408 {
 409         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 410 }
 411
 412 /* Named identifiers which are valid indices to efx_mae_field_cap_t */
 413 typedef enum efx_mae_field_cap_id_e {
 414         EFX_MAE_FIELD_ID_INGRESS_MPORT_SELECTOR = MAE_FIELD_INGRESS_PORT,
 415         EFX_MAE_FIELD_ID_ETHER_TYPE_BE = MAE_FIELD_ETHER_TYPE,
 416         EFX_MAE_FIELD_ID_ETH_SADDR_BE = MAE_FIELD_ETH_SADDR,
 417         EFX_MAE_FIELD_ID_ETH_DADDR_BE = MAE_FIELD_ETH_DADDR,
 418         EFX_MAE_FIELD_ID_VLAN0_TCI_BE = MAE_FIELD_VLAN0_TCI,
 419         EFX_MAE_FIELD_ID_VLAN0_PROTO_BE = MAE_FIELD_VLAN0_PROTO,
 420         EFX_MAE_FIELD_ID_VLAN1_TCI_BE = MAE_FIELD_VLAN1_TCI,
 421         EFX_MAE_FIELD_ID_VLAN1_PROTO_BE = MAE_FIELD_VLAN1_PROTO,
 422         EFX_MAE_FIELD_ID_SRC_IP4_BE = MAE_FIELD_SRC_IP4,
 423         EFX_MAE_FIELD_ID_DST_IP4_BE = MAE_FIELD_DST_IP4,
 424         EFX_MAE_FIELD_ID_IP_PROTO = MAE_FIELD_IP_PROTO,
 425         EFX_MAE_FIELD_ID_IP_TOS = MAE_FIELD_IP_TOS,
 426         EFX_MAE_FIELD_ID_IP_TTL = MAE_FIELD_IP_TTL,
 427         EFX_MAE_FIELD_ID_SRC_IP6_BE = MAE_FIELD_SRC_IP6,
 428         EFX_MAE_FIELD_ID_DST_IP6_BE = MAE_FIELD_DST_IP6,
 429         EFX_MAE_FIELD_ID_L4_SPORT_BE = MAE_FIELD_L4_SPORT,
 430         EFX_MAE_FIELD_ID_L4_DPORT_BE = MAE_FIELD_L4_DPORT,
 431         EFX_MAE_FIELD_ID_TCP_FLAGS_BE = MAE_FIELD_TCP_FLAGS,
 432         EFX_MAE_FIELD_ID_ENC_ETHER_TYPE_BE = MAE_FIELD_ENC_ETHER_TYPE,
 433         EFX_MAE_FIELD_ID_ENC_ETH_SADDR_BE = MAE_FIELD_ENC_ETH_SADDR,
 434         EFX_MAE_FIELD_ID_ENC_ETH_DADDR_BE = MAE_FIELD_ENC_ETH_DADDR,
 435         EFX_MAE_FIELD_ID_ENC_VLAN0_TCI_BE = MAE_FIELD_ENC_VLAN0_TCI,
 436         EFX_MAE_FIELD_ID_ENC_VLAN0_PROTO_BE = MAE_FIELD_ENC_VLAN0_PROTO,
 437         EFX_MAE_FIELD_ID_ENC_VLAN1_TCI_BE = MAE_FIELD_ENC_VLAN1_TCI,
 438         EFX_MAE_FIELD_ID_ENC_VLAN1_PROTO_BE = MAE_FIELD_ENC_VLAN1_PROTO,
 439         EFX_MAE_FIELD_ID_ENC_SRC_IP4_BE = MAE_FIELD_ENC_SRC_IP4,
 440         EFX_MAE_FIELD_ID_ENC_DST_IP4_BE = MAE_FIELD_ENC_DST_IP4,
 441         EFX_MAE_FIELD_ID_ENC_IP_PROTO = MAE_FIELD_ENC_IP_PROTO,
 442         EFX_MAE_FIELD_ID_ENC_IP_TOS = MAE_FIELD_ENC_IP_TOS,
 443         EFX_MAE_FIELD_ID_ENC_IP_TTL = MAE_FIELD_ENC_IP_TTL,
 444         EFX_MAE_FIELD_ID_ENC_SRC_IP6_BE = MAE_FIELD_ENC_SRC_IP6,
 445         EFX_MAE_FIELD_ID_ENC_DST_IP6_BE = MAE_FIELD_ENC_DST_IP6,
 446         EFX_MAE_FIELD_ID_ENC_L4_SPORT_BE = MAE_FIELD_ENC_L4_SPORT,
 447         EFX_MAE_FIELD_ID_ENC_L4_DPORT_BE = MAE_FIELD_ENC_L4_DPORT,
 448         EFX_MAE_FIELD_ID_ENC_VNET_ID_BE = MAE_FIELD_ENC_VNET_ID,
 449         EFX_MAE_FIELD_ID_OUTER_RULE_ID = MAE_FIELD_OUTER_RULE_ID,
 450
 451         EFX_MAE_FIELD_CAP_NIDS
 452 } efx_mae_field_cap_id_t;
 453
 454 typedef enum efx_mae_field_endianness_e {
 455         EFX_MAE_FIELD_LE = 0,
 456         EFX_MAE_FIELD_BE,
 457
 458         EFX_MAE_FIELD_ENDIANNESS_NTYPES
 459 } efx_mae_field_endianness_t;
 460
 461 /*
 462  * The following structure is a means to describe an MAE field.
 463  * The information in it is meant to be used internally by
 464  * APIs for addressing a given field in a mask-value pairs
 465  * structure and for validation purposes.
 466  */
 467 typedef struct efx_mae_mv_desc_s {
 468         efx_mae_field_cap_id_t          emmd_field_cap_id;
 469
 470         size_t                          emmd_value_size;
 471         size_t                          emmd_value_offset;
 472         size_t                          emmd_mask_size;
 473         size_t                          emmd_mask_offset;
 474
 475         efx_mae_field_endianness_t      emmd_endianness;
 476 } efx_mae_mv_desc_t;
 477
 478 /* Indices to this array are provided by efx_mae_field_id_t */
 479 static const efx_mae_mv_desc_t __efx_mae_action_rule_mv_desc_set[] = {
 480 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 481         [EFX_MAE_FIELD_##_name] =                                       \
 482         {                                                               \
 483                 EFX_MAE_FIELD_ID_##_name,                               \
 484                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_LEN,               \
 485                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_OFST,              \
 486                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_LEN,          \
 487                 MAE_FIELD_MASK_VALUE_PAIRS_##_name##_MASK_OFST,         \
 488                 _endianness                                             \
 489         }
 490
 491         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 492         EFX_MAE_MV_DESC(ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 493         EFX_MAE_MV_DESC(ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 494         EFX_MAE_MV_DESC(ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 495         EFX_MAE_MV_DESC(VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 496         EFX_MAE_MV_DESC(VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 497         EFX_MAE_MV_DESC(VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 498         EFX_MAE_MV_DESC(VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 499         EFX_MAE_MV_DESC(SRC_IP4_BE, EFX_MAE_FIELD_BE),
 500         EFX_MAE_MV_DESC(DST_IP4_BE, EFX_MAE_FIELD_BE),
 501         EFX_MAE_MV_DESC(IP_PROTO, EFX_MAE_FIELD_BE),
 502         EFX_MAE_MV_DESC(IP_TOS, EFX_MAE_FIELD_BE),
 503         EFX_MAE_MV_DESC(IP_TTL, EFX_MAE_FIELD_BE),
 504         EFX_MAE_MV_DESC(SRC_IP6_BE, EFX_MAE_FIELD_BE),
 505         EFX_MAE_MV_DESC(DST_IP6_BE, EFX_MAE_FIELD_BE),
 506         EFX_MAE_MV_DESC(L4_SPORT_BE, EFX_MAE_FIELD_BE),
 507         EFX_MAE_MV_DESC(L4_DPORT_BE, EFX_MAE_FIELD_BE),
 508         EFX_MAE_MV_DESC(TCP_FLAGS_BE, EFX_MAE_FIELD_BE),
 509         EFX_MAE_MV_DESC(ENC_VNET_ID_BE, EFX_MAE_FIELD_BE),
 510         EFX_MAE_MV_DESC(OUTER_RULE_ID, EFX_MAE_FIELD_LE),
 511
 512 #undef EFX_MAE_MV_DESC
 513 };
 514
 515 /* Indices to this array are provided by efx_mae_field_id_t */
 516 static const efx_mae_mv_desc_t __efx_mae_outer_rule_mv_desc_set[] = {
 517 #define EFX_MAE_MV_DESC(_name, _endianness)                             \
 518         [EFX_MAE_FIELD_##_name] =                                       \
 519         {                                                               \
 520                 EFX_MAE_FIELD_ID_##_name,                               \
 521                 MAE_ENC_FIELD_PAIRS_##_name##_LEN,                      \
 522                 MAE_ENC_FIELD_PAIRS_##_name##_OFST,                     \
 523                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_LEN,                 \
 524                 MAE_ENC_FIELD_PAIRS_##_name##_MASK_OFST,                \
 525                 _endianness                                             \
 526         }
 527
 528         EFX_MAE_MV_DESC(INGRESS_MPORT_SELECTOR, EFX_MAE_FIELD_LE),
 529         EFX_MAE_MV_DESC(ENC_ETHER_TYPE_BE, EFX_MAE_FIELD_BE),
 530         EFX_MAE_MV_DESC(ENC_ETH_SADDR_BE, EFX_MAE_FIELD_BE),
 531         EFX_MAE_MV_DESC(ENC_ETH_DADDR_BE, EFX_MAE_FIELD_BE),
 532         EFX_MAE_MV_DESC(ENC_VLAN0_TCI_BE, EFX_MAE_FIELD_BE),
 533         EFX_MAE_MV_DESC(ENC_VLAN0_PROTO_BE, EFX_MAE_FIELD_BE),
 534         EFX_MAE_MV_DESC(ENC_VLAN1_TCI_BE, EFX_MAE_FIELD_BE),
 535         EFX_MAE_MV_DESC(ENC_VLAN1_PROTO_BE, EFX_MAE_FIELD_BE),
 536         EFX_MAE_MV_DESC(ENC_SRC_IP4_BE, EFX_MAE_FIELD_BE),
 537         EFX_MAE_MV_DESC(ENC_DST_IP4_BE, EFX_MAE_FIELD_BE),
 538         EFX_MAE_MV_DESC(ENC_IP_PROTO, EFX_MAE_FIELD_BE),
 539         EFX_MAE_MV_DESC(ENC_IP_TOS, EFX_MAE_FIELD_BE),
 540         EFX_MAE_MV_DESC(ENC_IP_TTL, EFX_MAE_FIELD_BE),
 541         EFX_MAE_MV_DESC(ENC_SRC_IP6_BE, EFX_MAE_FIELD_BE),
 542         EFX_MAE_MV_DESC(ENC_DST_IP6_BE, EFX_MAE_FIELD_BE),
 543         EFX_MAE_MV_DESC(ENC_L4_SPORT_BE, EFX_MAE_FIELD_BE),
 544         EFX_MAE_MV_DESC(ENC_L4_DPORT_BE, EFX_MAE_FIELD_BE),
 545
 546 #undef EFX_MAE_MV_DESC
 547 };
 548
 549         __checkReturn                   efx_rc_t
 550 efx_mae_mport_by_phy_port(
 551         __in                            uint32_t phy_port,
 552         __out                           efx_mport_sel_t *mportp)
 553 {
 554         efx_dword_t dword;
 555         efx_rc_t rc;
 556
 557         if (phy_port > EFX_MASK32(MAE_MPORT_SELECTOR_PPORT_ID)) {
 558                 rc = EINVAL;
 559                 goto fail1;
 560         }
 561
 562         EFX_POPULATE_DWORD_2(dword,
 563             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_PPORT,
 564             MAE_MPORT_SELECTOR_PPORT_ID, phy_port);
 565
 566         memset(mportp, 0, sizeof (*mportp));
 567         mportp->sel = dword.ed_u32[0];
 568
 569         return (0);
 570
 571 fail1:
 572         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 573         return (rc);
 574 }
 575
 576         __checkReturn                   efx_rc_t
 577 efx_mae_mport_by_pcie_function(
 578         __in                            uint32_t pf,
 579         __in                            uint32_t vf,
 580         __out                           efx_mport_sel_t *mportp)
 581 {
 582         efx_dword_t dword;
 583         efx_rc_t rc;
 584
 585         EFX_STATIC_ASSERT(EFX_PCI_VF_INVALID ==
 586             MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL);
 587
 588         if (pf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_PF_ID)) {
 589                 rc = EINVAL;
 590                 goto fail1;
 591         }
 592
 593         if (vf > EFX_MASK32(MAE_MPORT_SELECTOR_FUNC_VF_ID)) {
 594                 rc = EINVAL;
 595                 goto fail2;
 596         }
 597
 598         EFX_POPULATE_DWORD_3(dword,
 599             MAE_MPORT_SELECTOR_TYPE, MAE_MPORT_SELECTOR_TYPE_FUNC,
 600             MAE_MPORT_SELECTOR_FUNC_PF_ID, pf,
 601             MAE_MPORT_SELECTOR_FUNC_VF_ID, vf);
 602
 603         memset(mportp, 0, sizeof (*mportp));
 604         mportp->sel = dword.ed_u32[0];
 605
 606         return (0);
 607
 608 fail2:
 609         EFSYS_PROBE(fail2);
 610 fail1:
 611         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 612         return (rc);
 613 }
 614
 615         __checkReturn                   efx_rc_t
 616 efx_mae_match_spec_field_set(
 617         __in                            efx_mae_match_spec_t *spec,
 618         __in                            efx_mae_field_id_t field_id,
 619         __in                            size_t value_size,
 620         __in_bcount(value_size)         const uint8_t *value,
 621         __in                            size_t mask_size,
 622         __in_bcount(mask_size)          const uint8_t *mask)
 623 {
 624         const efx_mae_mv_desc_t *descp;
 625         uint8_t *mvp;
 626         efx_rc_t rc;
 627
 628         if (field_id >= EFX_MAE_FIELD_NIDS) {
 629                 rc = EINVAL;
 630                 goto fail1;
 631         }
 632
 633         switch (spec->emms_type) {
 634         case EFX_MAE_RULE_OUTER:
 635                 descp = &__efx_mae_outer_rule_mv_desc_set[field_id];
 636                 mvp = spec->emms_mask_value_pairs.outer;
 637                 break;
 638         case EFX_MAE_RULE_ACTION:
 639                 descp = &__efx_mae_action_rule_mv_desc_set[field_id];
 640                 mvp = spec->emms_mask_value_pairs.action;
 641                 break;
 642         default:
 643                 rc = ENOTSUP;
 644                 goto fail2;
 645         }
 646
 647         if (value_size != descp->emmd_value_size) {
 648                 rc = EINVAL;
 649                 goto fail3;
 650         }
 651
 652         if (mask_size != descp->emmd_mask_size) {
 653                 rc = EINVAL;
 654                 goto fail4;
 655         }
 656
 657         if (descp->emmd_endianness == EFX_MAE_FIELD_BE) {
 658                 /*
 659                  * The mask/value are in network (big endian) order.
 660                  * The MCDI request field is also big endian.
 661                  */
 662                 memcpy(mvp + descp->emmd_value_offset, value, value_size);
 663                 memcpy(mvp + descp->emmd_mask_offset, mask, mask_size);
 664         } else {
 665                 efx_dword_t dword;
 666
 667                 /*
 668                  * The mask/value are in host byte order.
 669                  * The MCDI request field is little endian.
 670                  */
 671                 switch (value_size) {
 672                 case 4:
 673                         EFX_POPULATE_DWORD_1(dword,
 674                             EFX_DWORD_0, *(const uint32_t *)value);
 675
 676                         memcpy(mvp + descp->emmd_value_offset,
 677                             &dword, sizeof (dword));
 678                         break;
 679                 default:
 680                         EFSYS_ASSERT(B_FALSE);
 681                 }
 682
 683                 switch (mask_size) {
 684                 case 4:
 685                         EFX_POPULATE_DWORD_1(dword,
 686                             EFX_DWORD_0, *(const uint32_t *)mask);
 687
 688                         memcpy(mvp + descp->emmd_mask_offset,
 689                             &dword, sizeof (dword));
 690                         break;
 691                 default:
 692                         EFSYS_ASSERT(B_FALSE);
 693                 }
 694         }
 695
 696         return (0);
 697
 698 fail4:
 699         EFSYS_PROBE(fail4);
 700 fail3:
 701         EFSYS_PROBE(fail3);
 702 fail2:
 703         EFSYS_PROBE(fail2);
 704 fail1:
 705         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 706         return (rc);
 707 }
 708
 709         __checkReturn                   efx_rc_t
 710 efx_mae_match_spec_mport_set(
 711         __in                            efx_mae_match_spec_t *spec,
 712         __in                            const efx_mport_sel_t *valuep,
 713         __in_opt                        const efx_mport_sel_t *maskp)
 714 {
 715         uint32_t full_mask = UINT32_MAX;
 716         const uint8_t *vp;
 717         const uint8_t *mp;
 718         efx_rc_t rc;
 719
 720         if (valuep == NULL) {
 721                 rc = EINVAL;
 722                 goto fail1;
 723         }
 724
 725         vp = (const uint8_t *)&valuep->sel;
 726         if (maskp != NULL)
 727                 mp = (const uint8_t *)&maskp->sel;
 728         else
 729                 mp = (const uint8_t *)&full_mask;
 730
 731         rc = efx_mae_match_spec_field_set(spec,
 732             EFX_MAE_FIELD_INGRESS_MPORT_SELECTOR,
 733             sizeof (valuep->sel), vp, sizeof (maskp->sel), mp);
 734         if (rc != 0)
 735                 goto fail2;
 736
 737         return (0);
 738
 739 fail2:
 740         EFSYS_PROBE(fail2);
 741 fail1:
 742         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 743         return (rc);
 744 }
 745
 746         __checkReturn                   boolean_t
 747 efx_mae_match_specs_equal(
 748         __in                            const efx_mae_match_spec_t *left,
 749         __in                            const efx_mae_match_spec_t *right)
 750 {
 751         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
 752 }
 753
 754 #define EFX_MASK_BIT_IS_SET(_mask, _mask_page_nbits, _bit)              \
 755             ((_mask)[(_bit) / (_mask_page_nbits)] &                     \
 756                     (1ULL << ((_bit) & ((_mask_page_nbits) - 1))))
 757
 758 static inline                           boolean_t
 759 efx_mask_is_prefix(
 760         __in                            size_t mask_nbytes,
 761         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 762 {
 763         boolean_t prev_bit_is_set = B_TRUE;
 764         unsigned int i;
 765
 766         for (i = 0; i < 8 * mask_nbytes; ++i) {
 767                 boolean_t bit_is_set = EFX_MASK_BIT_IS_SET(maskp, 8, i);
 768
 769                 if (!prev_bit_is_set && bit_is_set)
 770                         return B_FALSE;
 771
 772                 prev_bit_is_set = bit_is_set;
 773         }
 774
 775         return B_TRUE;
 776 }
 777
 778 static inline                           boolean_t
 779 efx_mask_is_all_ones(
 780         __in                            size_t mask_nbytes,
 781         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 782 {
 783         unsigned int i;
 784         uint8_t t = ~0;
 785
 786         for (i = 0; i < mask_nbytes; ++i)
 787                 t &= maskp[i];
 788
 789         return (t == (uint8_t)(~0));
 790 }
 791
 792 static inline                           boolean_t
 793 efx_mask_is_all_zeros(
 794         __in                            size_t mask_nbytes,
 795         __in_bcount(mask_nbytes)        const uint8_t *maskp)
 796 {
 797         unsigned int i;
 798         uint8_t t = 0;
 799
 800         for (i = 0; i < mask_nbytes; ++i)
 801                 t |= maskp[i];
 802
 803         return (t == 0);
 804 }
 805
 806         __checkReturn                   boolean_t
 807 efx_mae_match_spec_is_valid(
 808         __in                            efx_nic_t *enp,
 809         __in                            const efx_mae_match_spec_t *spec)
 810 {
 811         efx_mae_t *maep = enp->en_maep;
 812         unsigned int field_ncaps = maep->em_max_nfields;
 813         const efx_mae_field_cap_t *field_caps;
 814         const efx_mae_mv_desc_t *desc_setp;
 815         unsigned int desc_set_nentries;
 816         boolean_t is_valid = B_TRUE;
 817         efx_mae_field_id_t field_id;
 818         const uint8_t *mvp;
 819
 820         switch (spec->emms_type) {
 821         case EFX_MAE_RULE_OUTER:
 822                 field_caps = maep->em_outer_rule_field_caps;
 823                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
 824                 desc_set_nentries =
 825                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
 826                 mvp = spec->emms_mask_value_pairs.outer;
 827                 break;
 828         case EFX_MAE_RULE_ACTION:
 829                 field_caps = maep->em_action_rule_field_caps;
 830                 desc_setp = __efx_mae_action_rule_mv_desc_set;
 831                 desc_set_nentries =
 832                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
 833                 mvp = spec->emms_mask_value_pairs.action;
 834                 break;
 835         default:
 836                 return (B_FALSE);
 837         }
 838
 839         if (field_caps == NULL)
 840                 return (B_FALSE);
 841
 842         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
 843                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
 844                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
 845                 const uint8_t *m_buf = mvp + descp->emmd_mask_offset;
 846                 size_t m_size = descp->emmd_mask_size;
 847
 848                 if (m_size == 0)
 849                         continue; /* Skip array gap */
 850
 851                 if (field_cap_id >= field_ncaps)
 852                         break;
 853
 854                 switch (field_caps[field_cap_id].emfc_support) {
 855                 case MAE_FIELD_SUPPORTED_MATCH_MASK:
 856                         is_valid = B_TRUE;
 857                         break;
 858                 case MAE_FIELD_SUPPORTED_MATCH_PREFIX:
 859                         is_valid = efx_mask_is_prefix(m_size, m_buf);
 860                         break;
 861                 case MAE_FIELD_SUPPORTED_MATCH_OPTIONAL:
 862                         is_valid = (efx_mask_is_all_ones(m_size, m_buf) ||
 863                             efx_mask_is_all_zeros(m_size, m_buf));
 864                         break;
 865                 case MAE_FIELD_SUPPORTED_MATCH_ALWAYS:
 866                         is_valid = efx_mask_is_all_ones(m_size, m_buf);
 867                         break;
 868                 case MAE_FIELD_SUPPORTED_MATCH_NEVER:
 869                 case MAE_FIELD_UNSUPPORTED:
 870                 default:
 871                         is_valid = efx_mask_is_all_zeros(m_size, m_buf);
 872                         break;
 873                 }
 874
 875                 if (is_valid == B_FALSE)
 876                         break;
 877         }
 878
 879         return (is_valid);
 880 }
 881
 882         __checkReturn                   efx_rc_t
 883 efx_mae_action_set_spec_init(
 884         __in                            efx_nic_t *enp,
 885         __out                           efx_mae_actions_t **specp)
 886 {
 887         efx_mae_actions_t *spec;
 888         efx_rc_t rc;
 889
 890         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (*spec), spec);
 891         if (spec == NULL) {
 892                 rc = ENOMEM;
 893                 goto fail1;
 894         }
 895
 896         *specp = spec;
 897
 898         return (0);
 899
 900 fail1:
 901         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 902         return (rc);
 903 }
 904
 905                                         void
 906 efx_mae_action_set_spec_fini(
 907         __in                            efx_nic_t *enp,
 908         __in                            efx_mae_actions_t *spec)
 909 {
 910         EFSYS_KMEM_FREE(enp->en_esip, sizeof (*spec), spec);
 911 }
 912
 913 static  __checkReturn                   efx_rc_t
 914 efx_mae_action_set_add_vlan_pop(
 915         __in                            efx_mae_actions_t *spec,
 916         __in                            size_t arg_size,
 917         __in_bcount(arg_size)           const uint8_t *arg)
 918 {
 919         efx_rc_t rc;
 920
 921         if (arg_size != 0) {
 922                 rc = EINVAL;
 923                 goto fail1;
 924         }
 925
 926         if (arg != NULL) {
 927                 rc = EINVAL;
 928                 goto fail2;
 929         }
 930
 931         if (spec->ema_n_vlan_tags_to_pop == EFX_MAE_VLAN_POP_MAX_NTAGS) {
 932                 rc = ENOTSUP;
 933                 goto fail3;
 934         }
 935
 936         ++spec->ema_n_vlan_tags_to_pop;
 937
 938         return (0);
 939
 940 fail3:
 941         EFSYS_PROBE(fail3);
 942 fail2:
 943         EFSYS_PROBE(fail2);
 944 fail1:
 945         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 946         return (rc);
 947 }
 948
 949 static  __checkReturn                   efx_rc_t
 950 efx_mae_action_set_add_vlan_push(
 951         __in                            efx_mae_actions_t *spec,
 952         __in                            size_t arg_size,
 953         __in_bcount(arg_size)           const uint8_t *arg)
 954 {
 955         unsigned int n_tags = spec->ema_n_vlan_tags_to_push;
 956         efx_rc_t rc;
 957
 958         if (arg_size != sizeof (*spec->ema_vlan_push_descs)) {
 959                 rc = EINVAL;
 960                 goto fail1;
 961         }
 962
 963         if (arg == NULL) {
 964                 rc = EINVAL;
 965                 goto fail2;
 966         }
 967
 968         if (n_tags == EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
 969                 rc = ENOTSUP;
 970                 goto fail3;
 971         }
 972
 973         memcpy(&spec->ema_vlan_push_descs[n_tags], arg, arg_size);
 974         ++(spec->ema_n_vlan_tags_to_push);
 975
 976         return (0);
 977
 978 fail3:
 979         EFSYS_PROBE(fail3);
 980 fail2:
 981         EFSYS_PROBE(fail2);
 982 fail1:
 983         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 984         return (rc);
 985 }
 986
 987 static  __checkReturn                   efx_rc_t
 988 efx_mae_action_set_add_flag(
 989         __in                            efx_mae_actions_t *spec,
 990         __in                            size_t arg_size,
 991         __in_bcount(arg_size)           const uint8_t *arg)
 992 {
 993         efx_rc_t rc;
 994
 995         _NOTE(ARGUNUSED(spec))
 996
 997         if (arg_size != 0) {
 998                 rc = EINVAL;
 999                 goto fail1;
1000         }
1001
1002         if (arg != NULL) {
1003                 rc = EINVAL;
1004                 goto fail2;
1005         }
1006
1007         /* This action does not have any arguments, so do nothing here. */
1008
1009         return (0);
1010
1011 fail2:
1012         EFSYS_PROBE(fail2);
1013 fail1:
1014         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1015         return (rc);
1016 }
1017
1018 static  __checkReturn                   efx_rc_t
1019 efx_mae_action_set_add_mark(
1020         __in                            efx_mae_actions_t *spec,
1021         __in                            size_t arg_size,
1022         __in_bcount(arg_size)           const uint8_t *arg)
1023 {
1024         efx_rc_t rc;
1025
1026         if (arg_size != sizeof (spec->ema_mark_value)) {
1027                 rc = EINVAL;
1028                 goto fail1;
1029         }
1030
1031         if (arg == NULL) {
1032                 rc = EINVAL;
1033                 goto fail2;
1034         }
1035
1036         memcpy(&spec->ema_mark_value, arg, arg_size);
1037
1038         return (0);
1039
1040 fail2:
1041         EFSYS_PROBE(fail2);
1042 fail1:
1043         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1044         return (rc);
1045 }
1046
1047 static  __checkReturn                   efx_rc_t
1048 efx_mae_action_set_add_deliver(
1049         __in                            efx_mae_actions_t *spec,
1050         __in                            size_t arg_size,
1051         __in_bcount(arg_size)           const uint8_t *arg)
1052 {
1053         efx_rc_t rc;
1054
1055         if (arg_size != sizeof (spec->ema_deliver_mport)) {
1056                 rc = EINVAL;
1057                 goto fail1;
1058         }
1059
1060         if (arg == NULL) {
1061                 rc = EINVAL;
1062                 goto fail2;
1063         }
1064
1065         memcpy(&spec->ema_deliver_mport, arg, arg_size);
1066
1067         return (0);
1068
1069 fail2:
1070         EFSYS_PROBE(fail2);
1071 fail1:
1072         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1073         return (rc);
1074 }
1075
1076 typedef struct efx_mae_action_desc_s {
1077         /* Action specific handler */
1078         efx_rc_t        (*emad_add)(efx_mae_actions_t *,
1079                                     size_t, const uint8_t *);
1080 } efx_mae_action_desc_t;
1081
1082 static const efx_mae_action_desc_t efx_mae_actions[EFX_MAE_NACTIONS] = {
1083         [EFX_MAE_ACTION_VLAN_POP] = {
1084                 .emad_add = efx_mae_action_set_add_vlan_pop
1085         },
1086         [EFX_MAE_ACTION_VLAN_PUSH] = {
1087                 .emad_add = efx_mae_action_set_add_vlan_push
1088         },
1089         [EFX_MAE_ACTION_FLAG] = {
1090                 .emad_add = efx_mae_action_set_add_flag
1091         },
1092         [EFX_MAE_ACTION_MARK] = {
1093                 .emad_add = efx_mae_action_set_add_mark
1094         },
1095         [EFX_MAE_ACTION_DELIVER] = {
1096                 .emad_add = efx_mae_action_set_add_deliver
1097         }
1098 };
1099
1100 static const uint32_t efx_mae_action_ordered_map =
1101         (1U << EFX_MAE_ACTION_VLAN_POP) |
1102         (1U << EFX_MAE_ACTION_VLAN_PUSH) |
1103         (1U << EFX_MAE_ACTION_FLAG) |
1104         (1U << EFX_MAE_ACTION_MARK) |
1105         (1U << EFX_MAE_ACTION_DELIVER);
1106
1107 /*
1108  * These actions must not be added after DELIVER, but
1109  * they can have any place among the rest of
1110  * strictly ordered actions.
1111  */
1112 static const uint32_t efx_mae_action_nonstrict_map =
1113         (1U << EFX_MAE_ACTION_FLAG) |
1114         (1U << EFX_MAE_ACTION_MARK);
1115
1116 static const uint32_t efx_mae_action_repeat_map =
1117         (1U << EFX_MAE_ACTION_VLAN_POP) |
1118         (1U << EFX_MAE_ACTION_VLAN_PUSH);
1119
1120 /*
1121  * Add an action to an action set.
1122  *
1123  * This has to be invoked in the desired action order.
1124  * An out-of-order action request will be turned down.
1125  */
1126 static  __checkReturn                   efx_rc_t
1127 efx_mae_action_set_spec_populate(
1128         __in                            efx_mae_actions_t *spec,
1129         __in                            efx_mae_action_t type,
1130         __in                            size_t arg_size,
1131         __in_bcount(arg_size)           const uint8_t *arg)
1132 {
1133         uint32_t action_mask;
1134         efx_rc_t rc;
1135
1136         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1137             (sizeof (efx_mae_action_ordered_map) * 8));
1138         EFX_STATIC_ASSERT(EFX_MAE_NACTIONS <=
1139             (sizeof (efx_mae_action_repeat_map) * 8));
1140
1141         EFX_STATIC_ASSERT(EFX_MAE_ACTION_DELIVER + 1 == EFX_MAE_NACTIONS);
1142         EFX_STATIC_ASSERT(EFX_MAE_ACTION_FLAG + 1 == EFX_MAE_ACTION_MARK);
1143         EFX_STATIC_ASSERT(EFX_MAE_ACTION_MARK + 1 == EFX_MAE_ACTION_DELIVER);
1144
1145         if (type >= EFX_ARRAY_SIZE(efx_mae_actions)) {
1146                 rc = EINVAL;
1147                 goto fail1;
1148         }
1149
1150         action_mask = (1U << type);
1151
1152         if ((spec->ema_actions & action_mask) != 0) {
1153                 /* The action set already contains this action. */
1154                 if ((efx_mae_action_repeat_map & action_mask) == 0) {
1155                         /* Cannot add another non-repeatable action. */
1156                         rc = ENOTSUP;
1157                         goto fail2;
1158                 }
1159         }
1160
1161         if ((efx_mae_action_ordered_map & action_mask) != 0) {
1162                 uint32_t strict_ordered_map =
1163                     efx_mae_action_ordered_map & ~efx_mae_action_nonstrict_map;
1164                 uint32_t later_actions_mask =
1165                     strict_ordered_map & ~(action_mask | (action_mask - 1));
1166
1167                 if ((spec->ema_actions & later_actions_mask) != 0) {
1168                         /* Cannot add an action after later ordered actions. */
1169                         rc = ENOTSUP;
1170                         goto fail3;
1171                 }
1172         }
1173
1174         if (efx_mae_actions[type].emad_add != NULL) {
1175                 rc = efx_mae_actions[type].emad_add(spec, arg_size, arg);
1176                 if (rc != 0)
1177                         goto fail4;
1178         }
1179
1180         spec->ema_actions |= action_mask;
1181
1182         return (0);
1183
1184 fail4:
1185         EFSYS_PROBE(fail4);
1186 fail3:
1187         EFSYS_PROBE(fail3);
1188 fail2:
1189         EFSYS_PROBE(fail2);
1190 fail1:
1191         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1192         return (rc);
1193 }
1194
1195         __checkReturn                   efx_rc_t
1196 efx_mae_action_set_populate_vlan_pop(
1197         __in                            efx_mae_actions_t *spec)
1198 {
1199         return (efx_mae_action_set_spec_populate(spec,
1200             EFX_MAE_ACTION_VLAN_POP, 0, NULL));
1201 }
1202
1203         __checkReturn                   efx_rc_t
1204 efx_mae_action_set_populate_vlan_push(
1205         __in                            efx_mae_actions_t *spec,
1206         __in                            uint16_t tpid_be,
1207         __in                            uint16_t tci_be)
1208 {
1209         efx_mae_action_vlan_push_t action;
1210         const uint8_t *arg = (const uint8_t *)&action;
1211
1212         action.emavp_tpid_be = tpid_be;
1213         action.emavp_tci_be = tci_be;
1214
1215         return (efx_mae_action_set_spec_populate(spec,
1216             EFX_MAE_ACTION_VLAN_PUSH, sizeof (action), arg));
1217 }
1218
1219         __checkReturn                   efx_rc_t
1220 efx_mae_action_set_populate_flag(
1221         __in                            efx_mae_actions_t *spec)
1222 {
1223         return (efx_mae_action_set_spec_populate(spec,
1224             EFX_MAE_ACTION_FLAG, 0, NULL));
1225 }
1226
1227         __checkReturn                   efx_rc_t
1228 efx_mae_action_set_populate_mark(
1229         __in                            efx_mae_actions_t *spec,
1230         __in                            uint32_t mark_value)
1231 {
1232         const uint8_t *arg = (const uint8_t *)&mark_value;
1233
1234         return (efx_mae_action_set_spec_populate(spec,
1235             EFX_MAE_ACTION_MARK, sizeof (mark_value), arg));
1236 }
1237
1238         __checkReturn                   efx_rc_t
1239 efx_mae_action_set_populate_deliver(
1240         __in                            efx_mae_actions_t *spec,
1241         __in                            const efx_mport_sel_t *mportp)
1242 {
1243         const uint8_t *arg;
1244         efx_rc_t rc;
1245
1246         if (mportp == NULL) {
1247                 rc = EINVAL;
1248                 goto fail1;
1249         }
1250
1251         arg = (const uint8_t *)&mportp->sel;
1252
1253         return (efx_mae_action_set_spec_populate(spec,
1254             EFX_MAE_ACTION_DELIVER, sizeof (mportp->sel), arg));
1255
1256 fail1:
1257         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1258         return (rc);
1259 }
1260
1261         __checkReturn                   efx_rc_t
1262 efx_mae_action_set_populate_drop(
1263         __in                            efx_mae_actions_t *spec)
1264 {
1265         efx_mport_sel_t mport;
1266         const uint8_t *arg;
1267         efx_dword_t dword;
1268
1269         EFX_POPULATE_DWORD_1(dword,
1270             MAE_MPORT_SELECTOR_FLAT, MAE_MPORT_SELECTOR_NULL);
1271
1272         mport.sel = dword.ed_u32[0];
1273
1274         arg = (const uint8_t *)&mport.sel;
1275
1276         return (efx_mae_action_set_spec_populate(spec,
1277             EFX_MAE_ACTION_DELIVER, sizeof (mport.sel), arg));
1278 }
1279
1280         __checkReturn                   boolean_t
1281 efx_mae_action_set_specs_equal(
1282         __in                            const efx_mae_actions_t *left,
1283         __in                            const efx_mae_actions_t *right)
1284 {
1285         return ((memcmp(left, right, sizeof (*left)) == 0) ? B_TRUE : B_FALSE);
1286 }
1287
1288         __checkReturn                   efx_rc_t
1289 efx_mae_match_specs_class_cmp(
1290         __in                            efx_nic_t *enp,
1291         __in                            const efx_mae_match_spec_t *left,
1292         __in                            const efx_mae_match_spec_t *right,
1293         __out                           boolean_t *have_same_classp)
1294 {
1295         efx_mae_t *maep = enp->en_maep;
1296         unsigned int field_ncaps = maep->em_max_nfields;
1297         const efx_mae_field_cap_t *field_caps;
1298         const efx_mae_mv_desc_t *desc_setp;
1299         unsigned int desc_set_nentries;
1300         boolean_t have_same_class = B_TRUE;
1301         efx_mae_field_id_t field_id;
1302         const uint8_t *mvpl;
1303         const uint8_t *mvpr;
1304         efx_rc_t rc;
1305
1306         switch (left->emms_type) {
1307         case EFX_MAE_RULE_OUTER:
1308                 field_caps = maep->em_outer_rule_field_caps;
1309                 desc_setp = __efx_mae_outer_rule_mv_desc_set;
1310                 desc_set_nentries =
1311                     EFX_ARRAY_SIZE(__efx_mae_outer_rule_mv_desc_set);
1312                 mvpl = left->emms_mask_value_pairs.outer;
1313                 mvpr = right->emms_mask_value_pairs.outer;
1314                 break;
1315         case EFX_MAE_RULE_ACTION:
1316                 field_caps = maep->em_action_rule_field_caps;
1317                 desc_setp = __efx_mae_action_rule_mv_desc_set;
1318                 desc_set_nentries =
1319                     EFX_ARRAY_SIZE(__efx_mae_action_rule_mv_desc_set);
1320                 mvpl = left->emms_mask_value_pairs.action;
1321                 mvpr = right->emms_mask_value_pairs.action;
1322                 break;
1323         default:
1324                 rc = ENOTSUP;
1325                 goto fail1;
1326         }
1327
1328         if (field_caps == NULL) {
1329                 rc = EAGAIN;
1330                 goto fail2;
1331         }
1332
1333         if (left->emms_type != right->emms_type ||
1334             left->emms_prio != right->emms_prio) {
1335                 /*
1336                  * Rules of different types can never map to the same class.
1337                  *
1338                  * The FW can support some set of match criteria for one
1339                  * priority and not support the very same set for
1340                  * another priority. Thus, two rules which have
1341                  * different priorities can never map to
1342                  * the same class.
1343                  */
1344                 *have_same_classp = B_FALSE;
1345                 return (0);
1346         }
1347
1348         for (field_id = 0; field_id < desc_set_nentries; ++field_id) {
1349                 const efx_mae_mv_desc_t *descp = &desc_setp[field_id];
1350                 efx_mae_field_cap_id_t field_cap_id = descp->emmd_field_cap_id;
1351
1352                 if (descp->emmd_mask_size == 0)
1353                         continue; /* Skip array gap */
1354
1355                 if (field_cap_id >= field_ncaps)
1356                         break;
1357
1358                 if (field_caps[field_cap_id].emfc_mask_affects_class) {
1359                         const uint8_t *lmaskp = mvpl + descp->emmd_mask_offset;
1360                         const uint8_t *rmaskp = mvpr + descp->emmd_mask_offset;
1361                         size_t mask_size = descp->emmd_mask_size;
1362
1363                         if (memcmp(lmaskp, rmaskp, mask_size) != 0) {
1364                                 have_same_class = B_FALSE;
1365                                 break;
1366                         }
1367                 }
1368
1369                 if (field_caps[field_cap_id].emfc_match_affects_class) {
1370                         const uint8_t *lvalp = mvpl + descp->emmd_value_offset;
1371                         const uint8_t *rvalp = mvpr + descp->emmd_value_offset;
1372                         size_t value_size = descp->emmd_value_size;
1373
1374                         if (memcmp(lvalp, rvalp, value_size) != 0) {
1375                                 have_same_class = B_FALSE;
1376                                 break;
1377                         }
1378                 }
1379         }
1380
1381         *have_same_classp = have_same_class;
1382
1383         return (0);
1384
1385 fail2:
1386         EFSYS_PROBE(fail2);
1387 fail1:
1388         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1389         return (rc);
1390 }
1391
1392         __checkReturn           efx_rc_t
1393 efx_mae_outer_rule_insert(
1394         __in                    efx_nic_t *enp,
1395         __in                    const efx_mae_match_spec_t *spec,
1396         __in                    efx_tunnel_protocol_t encap_type,
1397         __out                   efx_mae_rule_id_t *or_idp)
1398 {
1399         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1400         efx_mcdi_req_t req;
1401         EFX_MCDI_DECLARE_BUF(payload,
1402             MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2,
1403             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN);
1404         uint32_t encap_type_mcdi;
1405         efx_mae_rule_id_t or_id;
1406         size_t offset;
1407         efx_rc_t rc;
1408
1409         EFX_STATIC_ASSERT(sizeof (or_idp->id) ==
1410             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN);
1411
1412         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1413             MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL);
1414
1415         if (encp->enc_mae_supported == B_FALSE) {
1416                 rc = ENOTSUP;
1417                 goto fail1;
1418         }
1419
1420         if (spec->emms_type != EFX_MAE_RULE_OUTER) {
1421                 rc = EINVAL;
1422                 goto fail2;
1423         }
1424
1425         switch (encap_type) {
1426         case EFX_TUNNEL_PROTOCOL_NONE:
1427                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NONE;
1428                 break;
1429         case EFX_TUNNEL_PROTOCOL_VXLAN:
1430                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_VXLAN;
1431                 break;
1432         case EFX_TUNNEL_PROTOCOL_GENEVE:
1433                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_GENEVE;
1434                 break;
1435         case EFX_TUNNEL_PROTOCOL_NVGRE:
1436                 encap_type_mcdi = MAE_MCDI_ENCAP_TYPE_NVGRE;
1437                 break;
1438         default:
1439                 rc = ENOTSUP;
1440                 goto fail3;
1441         }
1442
1443         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_INSERT;
1444         req.emr_in_buf = payload;
1445         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_INSERT_IN_LENMAX_MCDI2;
1446         req.emr_out_buf = payload;
1447         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN;
1448
1449         MCDI_IN_SET_DWORD(req,
1450             MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE, encap_type_mcdi);
1451
1452         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_INSERT_IN_PRIO, spec->emms_prio);
1453
1454         /*
1455          * Mask-value pairs have been stored in the byte order needed for the
1456          * MCDI request and are thus safe to be copied directly to the buffer.
1457          * The library cares about byte order in efx_mae_match_spec_field_set().
1458          */
1459         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.outer) >=
1460             MAE_ENC_FIELD_PAIRS_LEN);
1461         offset = MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_OFST;
1462         memcpy(payload + offset, spec->emms_mask_value_pairs.outer,
1463             MAE_ENC_FIELD_PAIRS_LEN);
1464
1465         efx_mcdi_execute(enp, &req);
1466
1467         if (req.emr_rc != 0) {
1468                 rc = req.emr_rc;
1469                 goto fail4;
1470         }
1471
1472         if (req.emr_out_length_used < MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN) {
1473                 rc = EMSGSIZE;
1474                 goto fail5;
1475         }
1476
1477         or_id.id = MCDI_OUT_DWORD(req, MAE_OUTER_RULE_INSERT_OUT_OR_ID);
1478         if (or_id.id == EFX_MAE_RSRC_ID_INVALID) {
1479                 rc = ENOENT;
1480                 goto fail6;
1481         }
1482
1483         or_idp->id = or_id.id;
1484
1485         return (0);
1486
1487 fail6:
1488         EFSYS_PROBE(fail6);
1489 fail5:
1490         EFSYS_PROBE(fail5);
1491 fail4:
1492         EFSYS_PROBE(fail4);
1493 fail3:
1494         EFSYS_PROBE(fail3);
1495 fail2:
1496         EFSYS_PROBE(fail2);
1497 fail1:
1498         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1499         return (rc);
1500 }
1501
1502         __checkReturn           efx_rc_t
1503 efx_mae_outer_rule_remove(
1504         __in                    efx_nic_t *enp,
1505         __in                    const efx_mae_rule_id_t *or_idp)
1506 {
1507         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1508         efx_mcdi_req_t req;
1509         EFX_MCDI_DECLARE_BUF(payload,
1510             MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1),
1511             MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1));
1512         efx_rc_t rc;
1513
1514         if (encp->enc_mae_supported == B_FALSE) {
1515                 rc = ENOTSUP;
1516                 goto fail1;
1517         }
1518
1519         req.emr_cmd = MC_CMD_MAE_OUTER_RULE_REMOVE;
1520         req.emr_in_buf = payload;
1521         req.emr_in_length = MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(1);
1522         req.emr_out_buf = payload;
1523         req.emr_out_length = MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(1);
1524
1525         MCDI_IN_SET_DWORD(req, MAE_OUTER_RULE_REMOVE_IN_OR_ID, or_idp->id);
1526
1527         efx_mcdi_execute(enp, &req);
1528
1529         if (req.emr_rc != 0) {
1530                 rc = req.emr_rc;
1531                 goto fail2;
1532         }
1533
1534         if (MCDI_OUT_DWORD(req, MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID) !=
1535             or_idp->id) {
1536                 /* Firmware failed to remove the outer rule. */
1537                 rc = EAGAIN;
1538                 goto fail3;
1539         }
1540
1541         return (0);
1542
1543 fail3:
1544         EFSYS_PROBE(fail3);
1545 fail2:
1546         EFSYS_PROBE(fail2);
1547 fail1:
1548         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1549         return (rc);
1550 }
1551
1552         __checkReturn                   efx_rc_t
1553 efx_mae_match_spec_outer_rule_id_set(
1554         __in                            efx_mae_match_spec_t *spec,
1555         __in                            const efx_mae_rule_id_t *or_idp)
1556 {
1557         uint32_t full_mask = UINT32_MAX;
1558         efx_rc_t rc;
1559
1560         if (spec->emms_type != EFX_MAE_RULE_ACTION) {
1561                 rc = EINVAL;
1562                 goto fail1;
1563         }
1564
1565         if (or_idp == NULL) {
1566                 rc = EINVAL;
1567                 goto fail2;
1568         }
1569
1570         rc = efx_mae_match_spec_field_set(spec, EFX_MAE_FIELD_OUTER_RULE_ID,
1571             sizeof (or_idp->id), (const uint8_t *)&or_idp->id,
1572             sizeof (full_mask), (const uint8_t *)&full_mask);
1573         if (rc != 0)
1574                 goto fail3;
1575
1576         return (0);
1577
1578 fail3:
1579         EFSYS_PROBE(fail3);
1580 fail2:
1581         EFSYS_PROBE(fail2);
1582 fail1:
1583         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1584         return (rc);
1585 }
1586
1587         __checkReturn                   efx_rc_t
1588 efx_mae_action_set_alloc(
1589         __in                            efx_nic_t *enp,
1590         __in                            const efx_mae_actions_t *spec,
1591         __out                           efx_mae_aset_id_t *aset_idp)
1592 {
1593         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1594         efx_mcdi_req_t req;
1595         EFX_MCDI_DECLARE_BUF(payload,
1596             MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN,
1597             MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN);
1598         efx_mae_aset_id_t aset_id;
1599         efx_rc_t rc;
1600
1601         if (encp->enc_mae_supported == B_FALSE) {
1602                 rc = ENOTSUP;
1603                 goto fail1;
1604         }
1605
1606         req.emr_cmd = MC_CMD_MAE_ACTION_SET_ALLOC;
1607         req.emr_in_buf = payload;
1608         req.emr_in_length = MC_CMD_MAE_ACTION_SET_ALLOC_IN_LEN;
1609         req.emr_out_buf = payload;
1610         req.emr_out_length = MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN;
1611
1612         /*
1613          * TODO: Remove these EFX_MAE_RSRC_ID_INVALID assignments once the
1614          * corresponding resource types are supported by the implementation.
1615          * Use proper resource ID assignments instead.
1616          */
1617         MCDI_IN_SET_DWORD(req,
1618             MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID, EFX_MAE_RSRC_ID_INVALID);
1619         MCDI_IN_SET_DWORD(req,
1620             MAE_ACTION_SET_ALLOC_IN_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1621         MCDI_IN_SET_DWORD(req,
1622             MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID, EFX_MAE_RSRC_ID_INVALID);
1623
1624         MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1625             MAE_ACTION_SET_ALLOC_IN_VLAN_POP, spec->ema_n_vlan_tags_to_pop);
1626
1627         if (spec->ema_n_vlan_tags_to_push > 0) {
1628                 unsigned int outer_tag_idx;
1629
1630                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1631                     MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH,
1632                     spec->ema_n_vlan_tags_to_push);
1633
1634                 if (spec->ema_n_vlan_tags_to_push ==
1635                     EFX_MAE_VLAN_PUSH_MAX_NTAGS) {
1636                         MCDI_IN_SET_WORD(req,
1637                             MAE_ACTION_SET_ALLOC_IN_VLAN1_PROTO_BE,
1638                             spec->ema_vlan_push_descs[0].emavp_tpid_be);
1639                         MCDI_IN_SET_WORD(req,
1640                             MAE_ACTION_SET_ALLOC_IN_VLAN1_TCI_BE,
1641                             spec->ema_vlan_push_descs[0].emavp_tci_be);
1642                 }
1643
1644                 outer_tag_idx = spec->ema_n_vlan_tags_to_push - 1;
1645
1646                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_PROTO_BE,
1647                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tpid_be);
1648                 MCDI_IN_SET_WORD(req, MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE,
1649                     spec->ema_vlan_push_descs[outer_tag_idx].emavp_tci_be);
1650         }
1651
1652         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_FLAG)) != 0) {
1653                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1654                     MAE_ACTION_SET_ALLOC_IN_FLAG, 1);
1655         }
1656
1657         if ((spec->ema_actions & (1U << EFX_MAE_ACTION_MARK)) != 0) {
1658                 MCDI_IN_SET_DWORD_FIELD(req, MAE_ACTION_SET_ALLOC_IN_FLAGS,
1659                     MAE_ACTION_SET_ALLOC_IN_MARK, 1);
1660
1661                 MCDI_IN_SET_DWORD(req,
1662                     MAE_ACTION_SET_ALLOC_IN_MARK_VALUE, spec->ema_mark_value);
1663         }
1664
1665         MCDI_IN_SET_DWORD(req,
1666             MAE_ACTION_SET_ALLOC_IN_DELIVER, spec->ema_deliver_mport.sel);
1667
1668         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID,
1669             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1670         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID,
1671             MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL);
1672
1673         efx_mcdi_execute(enp, &req);
1674
1675         if (req.emr_rc != 0) {
1676                 rc = req.emr_rc;
1677                 goto fail2;
1678         }
1679
1680         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN) {
1681                 rc = EMSGSIZE;
1682                 goto fail3;
1683         }
1684
1685         aset_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_SET_ALLOC_OUT_AS_ID);
1686         if (aset_id.id == EFX_MAE_RSRC_ID_INVALID) {
1687                 rc = ENOENT;
1688                 goto fail4;
1689         }
1690
1691         aset_idp->id = aset_id.id;
1692
1693         return (0);
1694
1695 fail4:
1696         EFSYS_PROBE(fail4);
1697 fail3:
1698         EFSYS_PROBE(fail3);
1699 fail2:
1700         EFSYS_PROBE(fail2);
1701 fail1:
1702         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1703         return (rc);
1704 }
1705
1706         __checkReturn                   efx_rc_t
1707 efx_mae_action_set_free(
1708         __in                            efx_nic_t *enp,
1709         __in                            const efx_mae_aset_id_t *aset_idp)
1710 {
1711         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1712         efx_mcdi_req_t req;
1713         EFX_MCDI_DECLARE_BUF(payload,
1714             MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1),
1715             MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1));
1716         efx_rc_t rc;
1717
1718         if (encp->enc_mae_supported == B_FALSE) {
1719                 rc = ENOTSUP;
1720                 goto fail1;
1721         }
1722
1723         req.emr_cmd = MC_CMD_MAE_ACTION_SET_FREE;
1724         req.emr_in_buf = payload;
1725         req.emr_in_length = MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(1);
1726         req.emr_out_buf = payload;
1727         req.emr_out_length = MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(1);
1728
1729         MCDI_IN_SET_DWORD(req, MAE_ACTION_SET_FREE_IN_AS_ID, aset_idp->id);
1730
1731         efx_mcdi_execute(enp, &req);
1732
1733         if (req.emr_rc != 0) {
1734                 rc = req.emr_rc;
1735                 goto fail2;
1736         }
1737
1738         if (MCDI_OUT_DWORD(req, MAE_ACTION_SET_FREE_OUT_FREED_AS_ID) !=
1739             aset_idp->id) {
1740                 /* Firmware failed to free the action set. */
1741                 rc = EAGAIN;
1742                 goto fail3;
1743         }
1744
1745         return (0);
1746
1747 fail3:
1748         EFSYS_PROBE(fail3);
1749 fail2:
1750         EFSYS_PROBE(fail2);
1751 fail1:
1752         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1753         return (rc);
1754 }
1755
1756         __checkReturn                   efx_rc_t
1757 efx_mae_action_rule_insert(
1758         __in                            efx_nic_t *enp,
1759         __in                            const efx_mae_match_spec_t *spec,
1760         __in                            const efx_mae_aset_list_id_t *asl_idp,
1761         __in                            const efx_mae_aset_id_t *as_idp,
1762         __out                           efx_mae_rule_id_t *ar_idp)
1763 {
1764         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1765         efx_mcdi_req_t req;
1766         EFX_MCDI_DECLARE_BUF(payload,
1767             MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2,
1768             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN);
1769         efx_oword_t *rule_response;
1770         efx_mae_rule_id_t ar_id;
1771         size_t offset;
1772         efx_rc_t rc;
1773
1774         EFX_STATIC_ASSERT(sizeof (ar_idp->id) ==
1775             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN);
1776
1777         EFX_STATIC_ASSERT(EFX_MAE_RSRC_ID_INVALID ==
1778             MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL);
1779
1780         if (encp->enc_mae_supported == B_FALSE) {
1781                 rc = ENOTSUP;
1782                 goto fail1;
1783         }
1784
1785         if (spec->emms_type != EFX_MAE_RULE_ACTION ||
1786             (asl_idp != NULL && as_idp != NULL) ||
1787             (asl_idp == NULL && as_idp == NULL)) {
1788                 rc = EINVAL;
1789                 goto fail2;
1790         }
1791
1792         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_INSERT;
1793         req.emr_in_buf = payload;
1794         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_INSERT_IN_LENMAX_MCDI2;
1795         req.emr_out_buf = payload;
1796         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN;
1797
1798         EFX_STATIC_ASSERT(sizeof (*rule_response) <=
1799             MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_LEN);
1800         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST;
1801         rule_response = (efx_oword_t *)(payload + offset);
1802         EFX_POPULATE_OWORD_3(*rule_response,
1803             MAE_ACTION_RULE_RESPONSE_ASL_ID,
1804             (asl_idp != NULL) ? asl_idp->id : EFX_MAE_RSRC_ID_INVALID,
1805             MAE_ACTION_RULE_RESPONSE_AS_ID,
1806             (as_idp != NULL) ? as_idp->id : EFX_MAE_RSRC_ID_INVALID,
1807             MAE_ACTION_RULE_RESPONSE_COUNTER_ID, EFX_MAE_RSRC_ID_INVALID);
1808
1809         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_INSERT_IN_PRIO, spec->emms_prio);
1810
1811         /*
1812          * Mask-value pairs have been stored in the byte order needed for the
1813          * MCDI request and are thus safe to be copied directly to the buffer.
1814          */
1815         EFX_STATIC_ASSERT(sizeof (spec->emms_mask_value_pairs.action) >=
1816             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1817         offset = MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_OFST;
1818         memcpy(payload + offset, spec->emms_mask_value_pairs.action,
1819             MAE_FIELD_MASK_VALUE_PAIRS_LEN);
1820
1821         efx_mcdi_execute(enp, &req);
1822
1823         if (req.emr_rc != 0) {
1824                 rc = req.emr_rc;
1825                 goto fail3;
1826         }
1827
1828         if (req.emr_out_length_used < MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN) {
1829                 rc = EMSGSIZE;
1830                 goto fail4;
1831         }
1832
1833         ar_id.id = MCDI_OUT_DWORD(req, MAE_ACTION_RULE_INSERT_OUT_AR_ID);
1834         if (ar_id.id == EFX_MAE_RSRC_ID_INVALID) {
1835                 rc = ENOENT;
1836                 goto fail5;
1837         }
1838
1839         ar_idp->id = ar_id.id;
1840
1841         return (0);
1842
1843 fail5:
1844         EFSYS_PROBE(fail5);
1845 fail4:
1846         EFSYS_PROBE(fail4);
1847 fail3:
1848         EFSYS_PROBE(fail3);
1849 fail2:
1850         EFSYS_PROBE(fail2);
1851 fail1:
1852         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1853         return (rc);
1854 }
1855
1856         __checkReturn                   efx_rc_t
1857 efx_mae_action_rule_remove(
1858         __in                            efx_nic_t *enp,
1859         __in                            const efx_mae_rule_id_t *ar_idp)
1860 {
1861         const efx_nic_cfg_t *encp = efx_nic_cfg_get(enp);
1862         efx_mcdi_req_t req;
1863         EFX_MCDI_DECLARE_BUF(payload,
1864             MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1),
1865             MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1));
1866         efx_rc_t rc;
1867
1868         if (encp->enc_mae_supported == B_FALSE) {
1869                 rc = ENOTSUP;
1870                 goto fail1;
1871         }
1872
1873         req.emr_cmd = MC_CMD_MAE_ACTION_RULE_DELETE;
1874         req.emr_in_buf = payload;
1875         req.emr_in_length = MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(1);
1876         req.emr_out_buf = payload;
1877         req.emr_out_length = MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(1);
1878
1879         MCDI_IN_SET_DWORD(req, MAE_ACTION_RULE_DELETE_IN_AR_ID, ar_idp->id);
1880
1881         efx_mcdi_execute(enp, &req);
1882
1883         if (req.emr_rc != 0) {
1884                 rc = req.emr_rc;
1885                 goto fail2;
1886         }
1887
1888         if (MCDI_OUT_DWORD(req, MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID) !=
1889             ar_idp->id) {
1890                 /* Firmware failed to delete the action rule. */
1891                 rc = EAGAIN;
1892                 goto fail3;
1893         }
1894
1895         return (0);
1896
1897 fail3:
1898         EFSYS_PROBE(fail3);
1899 fail2:
1900         EFSYS_PROBE(fail2);
1901 fail1:
1902         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1903         return (rc);
1904 }
1905
1906 #endif /* EFSYS_OPT_MAE */