drivers/common/sfc_efx/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         if (venid == EFX_PCI_VENID_XILINX) {
  89                 switch (devid) {
  90 #if EFSYS_OPT_RIVERHEAD
  91                 case EFX_PCI_DEVID_RIVERHEAD:
  92                 case EFX_PCI_DEVID_RIVERHEAD_VF:
  93                         *efp = EFX_FAMILY_RIVERHEAD;
  94                         *membarp = EFX_MEM_BAR_RIVERHEAD;
  95                         return (0);
  96 #endif /* EFSYS_OPT_RIVERHEAD */
  97                 default:
  98                         break;
  99                 }
 100         }
 101
 102         *efp = EFX_FAMILY_INVALID;
 103         return (ENOTSUP);
 104 }
 105
 106
 107 #if EFSYS_OPT_SIENA
 108
 109 static const efx_nic_ops_t      __efx_nic_siena_ops = {
 110         siena_nic_probe,                /* eno_probe */
 111         NULL,                           /* eno_board_cfg */
 112         NULL,                           /* eno_set_drv_limits */
 113         siena_nic_reset,                /* eno_reset */
 114         siena_nic_init,                 /* eno_init */
 115         NULL,                           /* eno_get_vi_pool */
 116         NULL,                           /* eno_get_bar_region */
 117         NULL,                           /* eno_hw_unavailable */
 118         NULL,                           /* eno_set_hw_unavailable */
 119 #if EFSYS_OPT_DIAG
 120         siena_nic_register_test,        /* eno_register_test */
 121 #endif  /* EFSYS_OPT_DIAG */
 122         siena_nic_fini,                 /* eno_fini */
 123         siena_nic_unprobe,              /* eno_unprobe */
 124 };
 125
 126 #endif  /* EFSYS_OPT_SIENA */
 127
 128 #if EFSYS_OPT_HUNTINGTON
 129
 130 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 131         ef10_nic_probe,                 /* eno_probe */
 132         hunt_board_cfg,                 /* eno_board_cfg */
 133         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 134         ef10_nic_reset,                 /* eno_reset */
 135         ef10_nic_init,                  /* eno_init */
 136         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 137         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 138         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 139         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 140 #if EFSYS_OPT_DIAG
 141         ef10_nic_register_test,         /* eno_register_test */
 142 #endif  /* EFSYS_OPT_DIAG */
 143         ef10_nic_fini,                  /* eno_fini */
 144         ef10_nic_unprobe,               /* eno_unprobe */
 145 };
 146
 147 #endif  /* EFSYS_OPT_HUNTINGTON */
 148
 149 #if EFSYS_OPT_MEDFORD
 150
 151 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 152         ef10_nic_probe,                 /* eno_probe */
 153         medford_board_cfg,              /* eno_board_cfg */
 154         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 155         ef10_nic_reset,                 /* eno_reset */
 156         ef10_nic_init,                  /* eno_init */
 157         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 158         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 159         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 160         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 161 #if EFSYS_OPT_DIAG
 162         ef10_nic_register_test,         /* eno_register_test */
 163 #endif  /* EFSYS_OPT_DIAG */
 164         ef10_nic_fini,                  /* eno_fini */
 165         ef10_nic_unprobe,               /* eno_unprobe */
 166 };
 167
 168 #endif  /* EFSYS_OPT_MEDFORD */
 169
 170 #if EFSYS_OPT_MEDFORD2
 171
 172 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 173         ef10_nic_probe,                 /* eno_probe */
 174         medford2_board_cfg,             /* eno_board_cfg */
 175         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 176         ef10_nic_reset,                 /* eno_reset */
 177         ef10_nic_init,                  /* eno_init */
 178         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 179         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 180         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 181         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 182 #if EFSYS_OPT_DIAG
 183         ef10_nic_register_test,         /* eno_register_test */
 184 #endif  /* EFSYS_OPT_DIAG */
 185         ef10_nic_fini,                  /* eno_fini */
 186         ef10_nic_unprobe,               /* eno_unprobe */
 187 };
 188
 189 #endif  /* EFSYS_OPT_MEDFORD2 */
 190
 191 #if EFSYS_OPT_RIVERHEAD
 192
 193 static const efx_nic_ops_t      __efx_nic_riverhead_ops = {
 194         rhead_nic_probe,                /* eno_probe */
 195         rhead_board_cfg,                /* eno_board_cfg */
 196         rhead_nic_set_drv_limits,       /* eno_set_drv_limits */
 197         rhead_nic_reset,                /* eno_reset */
 198         rhead_nic_init,                 /* eno_init */
 199         rhead_nic_get_vi_pool,          /* eno_get_vi_pool */
 200         rhead_nic_get_bar_region,       /* eno_get_bar_region */
 201         rhead_nic_hw_unavailable,       /* eno_hw_unavailable */
 202         rhead_nic_set_hw_unavailable,   /* eno_set_hw_unavailable */
 203 #if EFSYS_OPT_DIAG
 204         rhead_nic_register_test,        /* eno_register_test */
 205 #endif  /* EFSYS_OPT_DIAG */
 206         rhead_nic_fini,                 /* eno_fini */
 207         rhead_nic_unprobe,              /* eno_unprobe */
 208 };
 209
 210 #endif  /* EFSYS_OPT_RIVERHEAD */
 211
 212
 213         __checkReturn   efx_rc_t
 214 efx_nic_create(
 215         __in            efx_family_t family,
 216         __in            efsys_identifier_t *esip,
 217         __in            efsys_bar_t *esbp,
 218         __in            uint32_t fcw_offset,
 219         __in            efsys_lock_t *eslp,
 220         __deref_out     efx_nic_t **enpp)
 221 {
 222         efx_nic_t *enp;
 223         efx_rc_t rc;
 224
 225         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 226         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 227
 228         /* Allocate a NIC object */
 229         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 230
 231         if (enp == NULL) {
 232                 rc = ENOMEM;
 233                 goto fail1;
 234         }
 235
 236         enp->en_magic = EFX_NIC_MAGIC;
 237
 238         switch (family) {
 239 #if EFSYS_OPT_SIENA
 240         case EFX_FAMILY_SIENA:
 241                 enp->en_enop = &__efx_nic_siena_ops;
 242                 enp->en_features =
 243                     EFX_FEATURE_IPV6 |
 244                     EFX_FEATURE_LFSR_HASH_INSERT |
 245                     EFX_FEATURE_LINK_EVENTS |
 246                     EFX_FEATURE_PERIODIC_MAC_STATS |
 247                     EFX_FEATURE_MCDI |
 248                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 249                     EFX_FEATURE_MAC_HEADER_FILTERS |
 250                     EFX_FEATURE_TX_SRC_FILTERS;
 251                 break;
 252 #endif  /* EFSYS_OPT_SIENA */
 253
 254 #if EFSYS_OPT_HUNTINGTON
 255         case EFX_FAMILY_HUNTINGTON:
 256                 enp->en_enop = &__efx_nic_hunt_ops;
 257                 enp->en_features =
 258                     EFX_FEATURE_IPV6 |
 259                     EFX_FEATURE_LINK_EVENTS |
 260                     EFX_FEATURE_PERIODIC_MAC_STATS |
 261                     EFX_FEATURE_MCDI |
 262                     EFX_FEATURE_MAC_HEADER_FILTERS |
 263                     EFX_FEATURE_MCDI_DMA |
 264                     EFX_FEATURE_PIO_BUFFERS |
 265                     EFX_FEATURE_FW_ASSISTED_TSO |
 266                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 267                     EFX_FEATURE_PACKED_STREAM |
 268                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 269                 break;
 270 #endif  /* EFSYS_OPT_HUNTINGTON */
 271
 272 #if EFSYS_OPT_MEDFORD
 273         case EFX_FAMILY_MEDFORD:
 274                 enp->en_enop = &__efx_nic_medford_ops;
 275                 /*
 276                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 277                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 278                  */
 279                 enp->en_features =
 280                     EFX_FEATURE_IPV6 |
 281                     EFX_FEATURE_LINK_EVENTS |
 282                     EFX_FEATURE_PERIODIC_MAC_STATS |
 283                     EFX_FEATURE_MCDI |
 284                     EFX_FEATURE_MAC_HEADER_FILTERS |
 285                     EFX_FEATURE_MCDI_DMA |
 286                     EFX_FEATURE_PIO_BUFFERS |
 287                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 288                     EFX_FEATURE_PACKED_STREAM |
 289                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 290                 break;
 291 #endif  /* EFSYS_OPT_MEDFORD */
 292
 293 #if EFSYS_OPT_MEDFORD2
 294         case EFX_FAMILY_MEDFORD2:
 295                 enp->en_enop = &__efx_nic_medford2_ops;
 296                 enp->en_features =
 297                     EFX_FEATURE_IPV6 |
 298                     EFX_FEATURE_LINK_EVENTS |
 299                     EFX_FEATURE_PERIODIC_MAC_STATS |
 300                     EFX_FEATURE_MCDI |
 301                     EFX_FEATURE_MAC_HEADER_FILTERS |
 302                     EFX_FEATURE_MCDI_DMA |
 303                     EFX_FEATURE_PIO_BUFFERS |
 304                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 305                     EFX_FEATURE_PACKED_STREAM |
 306                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 307                 break;
 308 #endif  /* EFSYS_OPT_MEDFORD2 */
 309
 310 #if EFSYS_OPT_RIVERHEAD
 311         case EFX_FAMILY_RIVERHEAD:
 312                 enp->en_enop = &__efx_nic_riverhead_ops;
 313                 enp->en_features =
 314                     EFX_FEATURE_IPV6 |
 315                     EFX_FEATURE_LINK_EVENTS |
 316                     EFX_FEATURE_PERIODIC_MAC_STATS |
 317                     EFX_FEATURE_MCDI |
 318                     EFX_FEATURE_MAC_HEADER_FILTERS |
 319                     EFX_FEATURE_MCDI_DMA;
 320                 enp->en_arch.ef10.ena_fcw_base = fcw_offset;
 321                 break;
 322 #endif  /* EFSYS_OPT_RIVERHEAD */
 323
 324         default:
 325                 rc = ENOTSUP;
 326                 goto fail2;
 327         }
 328
 329         if ((family != EFX_FAMILY_RIVERHEAD) && (fcw_offset != 0)) {
 330                 rc = EINVAL;
 331                 goto fail3;
 332         }
 333
 334         enp->en_family = family;
 335         enp->en_esip = esip;
 336         enp->en_esbp = esbp;
 337         enp->en_eslp = eslp;
 338
 339         *enpp = enp;
 340
 341         return (0);
 342
 343 fail3:
 344         EFSYS_PROBE(fail3);
 345 fail2:
 346         EFSYS_PROBE(fail2);
 347
 348         enp->en_magic = 0;
 349
 350         /* Free the NIC object */
 351         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 352
 353 fail1:
 354         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 355
 356         return (rc);
 357 }
 358
 359         __checkReturn   efx_rc_t
 360 efx_nic_probe(
 361         __in            efx_nic_t *enp,
 362         __in            efx_fw_variant_t efv)
 363 {
 364         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 365         const efx_nic_ops_t *enop;
 366         efx_rc_t rc;
 367
 368         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 369 #if EFSYS_OPT_MCDI
 370         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 371 #endif  /* EFSYS_OPT_MCDI */
 372         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 373
 374         /* Ensure FW variant codes match with MC_CMD_FW codes */
 375         EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
 376             MC_CMD_FW_FULL_FEATURED);
 377         EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
 378             MC_CMD_FW_LOW_LATENCY);
 379         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
 380             MC_CMD_FW_PACKED_STREAM);
 381         EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
 382             MC_CMD_FW_HIGH_TX_RATE);
 383         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
 384             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
 385         EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
 386             MC_CMD_FW_RULES_ENGINE);
 387         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
 388             MC_CMD_FW_DPDK);
 389         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
 390             (int)MC_CMD_FW_DONT_CARE);
 391
 392         enop = enp->en_enop;
 393         enp->efv = efv;
 394
 395         if ((rc = enop->eno_probe(enp)) != 0)
 396                 goto fail1;
 397
 398         encp->enc_features = enp->en_features;
 399
 400         if ((rc = efx_phy_probe(enp)) != 0)
 401                 goto fail2;
 402
 403         enp->en_mod_flags |= EFX_MOD_PROBE;
 404
 405         return (0);
 406
 407 fail2:
 408         EFSYS_PROBE(fail2);
 409
 410         enop->eno_unprobe(enp);
 411
 412 fail1:
 413         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 414
 415         return (rc);
 416 }
 417
 418         __checkReturn   efx_rc_t
 419 efx_nic_set_drv_limits(
 420         __inout         efx_nic_t *enp,
 421         __in            efx_drv_limits_t *edlp)
 422 {
 423         const efx_nic_ops_t *enop = enp->en_enop;
 424         efx_rc_t rc;
 425
 426         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 427         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 428
 429         if (enop->eno_set_drv_limits != NULL) {
 430                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 431                         goto fail1;
 432         }
 433
 434         return (0);
 435
 436 fail1:
 437         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 438
 439         return (rc);
 440 }
 441
 442         __checkReturn   efx_rc_t
 443 efx_nic_set_drv_version(
 444         __inout                 efx_nic_t *enp,
 445         __in_ecount(length)     char const *verp,
 446         __in                    size_t length)
 447 {
 448         efx_rc_t rc;
 449
 450         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 451         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 452
 453         /*
 454          * length is the string content length in bytes.
 455          * Accept any content which fits into the version
 456          * buffer, excluding the last byte. This is reserved
 457          * for an appended NUL terminator.
 458          */
 459         if (length >= sizeof (enp->en_drv_version)) {
 460                 rc = E2BIG;
 461                 goto fail1;
 462         }
 463
 464         (void) memset(enp->en_drv_version, 0,
 465             sizeof (enp->en_drv_version));
 466         memcpy(enp->en_drv_version, verp, length);
 467
 468         return (0);
 469
 470 fail1:
 471         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 472
 473         return (rc);
 474 }
 475
 476
 477         __checkReturn   efx_rc_t
 478 efx_nic_get_bar_region(
 479         __in            efx_nic_t *enp,
 480         __in            efx_nic_region_t region,
 481         __out           uint32_t *offsetp,
 482         __out           size_t *sizep)
 483 {
 484         const efx_nic_ops_t *enop = enp->en_enop;
 485         efx_rc_t rc;
 486
 487         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 488         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 489         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 490
 491         if (enop->eno_get_bar_region == NULL) {
 492                 rc = ENOTSUP;
 493                 goto fail1;
 494         }
 495         if ((rc = (enop->eno_get_bar_region)(enp,
 496                     region, offsetp, sizep)) != 0) {
 497                 goto fail2;
 498         }
 499
 500         return (0);
 501
 502 fail2:
 503         EFSYS_PROBE(fail2);
 504
 505 fail1:
 506         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 507
 508         return (rc);
 509 }
 510
 511
 512         __checkReturn   efx_rc_t
 513 efx_nic_get_vi_pool(
 514         __in            efx_nic_t *enp,
 515         __out           uint32_t *evq_countp,
 516         __out           uint32_t *rxq_countp,
 517         __out           uint32_t *txq_countp)
 518 {
 519         const efx_nic_ops_t *enop = enp->en_enop;
 520         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 521         efx_rc_t rc;
 522
 523         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 524         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 525         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 526
 527         if (enop->eno_get_vi_pool != NULL) {
 528                 uint32_t vi_count = 0;
 529
 530                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 531                         goto fail1;
 532
 533                 *evq_countp = vi_count;
 534                 *rxq_countp = vi_count;
 535                 *txq_countp = vi_count;
 536         } else {
 537                 /* Use NIC limits as default value */
 538                 *evq_countp = encp->enc_evq_limit;
 539                 *rxq_countp = encp->enc_rxq_limit;
 540                 *txq_countp = encp->enc_txq_limit;
 541         }
 542
 543         return (0);
 544
 545 fail1:
 546         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 547
 548         return (rc);
 549 }
 550
 551
 552         __checkReturn   efx_rc_t
 553 efx_nic_init(
 554         __in            efx_nic_t *enp)
 555 {
 556         const efx_nic_ops_t *enop = enp->en_enop;
 557         efx_rc_t rc;
 558
 559         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 560         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 561
 562         if (enp->en_mod_flags & EFX_MOD_NIC) {
 563                 rc = EINVAL;
 564                 goto fail1;
 565         }
 566
 567         if ((rc = enop->eno_init(enp)) != 0)
 568                 goto fail2;
 569
 570         enp->en_mod_flags |= EFX_MOD_NIC;
 571
 572         return (0);
 573
 574 fail2:
 575         EFSYS_PROBE(fail2);
 576 fail1:
 577         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 578
 579         return (rc);
 580 }
 581
 582                         void
 583 efx_nic_fini(
 584         __in            efx_nic_t *enp)
 585 {
 586         const efx_nic_ops_t *enop = enp->en_enop;
 587
 588         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 589         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 590         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 591         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 592         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 593         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 594         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 595
 596         enop->eno_fini(enp);
 597
 598         enp->en_mod_flags &= ~EFX_MOD_NIC;
 599 }
 600
 601                         void
 602 efx_nic_unprobe(
 603         __in            efx_nic_t *enp)
 604 {
 605         const efx_nic_ops_t *enop = enp->en_enop;
 606
 607         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 608 #if EFSYS_OPT_MCDI
 609         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 610 #endif  /* EFSYS_OPT_MCDI */
 611         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 612         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 613         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 614         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 615         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 616         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 617
 618         efx_phy_unprobe(enp);
 619
 620         enop->eno_unprobe(enp);
 621
 622         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 623 }
 624
 625                         void
 626 efx_nic_destroy(
 627         __in    efx_nic_t *enp)
 628 {
 629         efsys_identifier_t *esip = enp->en_esip;
 630
 631         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 632         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 633
 634         enp->en_family = EFX_FAMILY_INVALID;
 635         enp->en_esip = NULL;
 636         enp->en_esbp = NULL;
 637         enp->en_eslp = NULL;
 638
 639         enp->en_enop = NULL;
 640
 641         enp->en_magic = 0;
 642
 643         /* Free the NIC object */
 644         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 645 }
 646
 647         __checkReturn   efx_rc_t
 648 efx_nic_reset(
 649         __in            efx_nic_t *enp)
 650 {
 651         const efx_nic_ops_t *enop = enp->en_enop;
 652         unsigned int mod_flags;
 653         efx_rc_t rc;
 654
 655         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 656         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 657         /*
 658          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 659          * (which we do not reset here) must have been shut down or never
 660          * initialized.
 661          *
 662          * A rule of thumb here is: If the controller or MC reboots, is *any*
 663          * state lost. If it's lost and needs reapplying, then the module
 664          * *must* not be initialised during the reset.
 665          */
 666         mod_flags = enp->en_mod_flags;
 667         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 668             EFX_MOD_VPD | EFX_MOD_MON);
 669 #if EFSYS_OPT_TUNNEL
 670         mod_flags &= ~EFX_MOD_TUNNEL;
 671 #endif /* EFSYS_OPT_TUNNEL */
 672         EFSYS_ASSERT3U(mod_flags, ==, 0);
 673         if (mod_flags != 0) {
 674                 rc = EINVAL;
 675                 goto fail1;
 676         }
 677
 678         if ((rc = enop->eno_reset(enp)) != 0)
 679                 goto fail2;
 680
 681         return (0);
 682
 683 fail2:
 684         EFSYS_PROBE(fail2);
 685 fail1:
 686         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 687
 688         return (rc);
 689 }
 690
 691                         const efx_nic_cfg_t *
 692 efx_nic_cfg_get(
 693         __in            const efx_nic_t *enp)
 694 {
 695         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 696         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 697
 698         return (&(enp->en_nic_cfg));
 699 }
 700
 701         __checkReturn           efx_rc_t
 702 efx_nic_get_fw_version(
 703         __in                    efx_nic_t *enp,
 704         __out                   efx_nic_fw_info_t *enfip)
 705 {
 706         uint16_t mc_fw_version[4];
 707         efx_rc_t rc;
 708
 709         if (enfip == NULL) {
 710                 rc = EINVAL;
 711                 goto fail1;
 712         }
 713
 714         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 715         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 716
 717         /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
 718         EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
 719             MC_CMD_GET_CAPABILITIES_OUT_RXDP);
 720         EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
 721             MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
 722         EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
 723             MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
 724         EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
 725             MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
 726         EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
 727             MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
 728
 729         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 730         if (rc != 0)
 731                 goto fail2;
 732
 733         rc = efx_mcdi_get_capabilities(enp, NULL,
 734             &enfip->enfi_rx_dpcpu_fw_id,
 735             &enfip->enfi_tx_dpcpu_fw_id,
 736             NULL, NULL);
 737         if (rc == 0) {
 738                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 739         } else if (rc == ENOTSUP) {
 740                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 741                 enfip->enfi_rx_dpcpu_fw_id = 0;
 742                 enfip->enfi_tx_dpcpu_fw_id = 0;
 743         } else {
 744                 goto fail3;
 745         }
 746
 747         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 748             sizeof (mc_fw_version));
 749
 750         return (0);
 751
 752 fail3:
 753         EFSYS_PROBE(fail3);
 754 fail2:
 755         EFSYS_PROBE(fail2);
 756 fail1:
 757         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 758
 759         return (rc);
 760 }
 761
 762         __checkReturn   boolean_t
 763 efx_nic_hw_unavailable(
 764         __in            efx_nic_t *enp)
 765 {
 766         const efx_nic_ops_t *enop = enp->en_enop;
 767
 768         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 769         /* NOTE: can be used by MCDI before NIC probe */
 770
 771         if (enop->eno_hw_unavailable != NULL) {
 772                 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
 773                         goto unavail;
 774         }
 775
 776         return (B_FALSE);
 777
 778 unavail:
 779         return (B_TRUE);
 780 }
 781
 782                         void
 783 efx_nic_set_hw_unavailable(
 784         __in            efx_nic_t *enp)
 785 {
 786         const efx_nic_ops_t *enop = enp->en_enop;
 787
 788         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 789
 790         if (enop->eno_set_hw_unavailable != NULL)
 791                 enop->eno_set_hw_unavailable(enp);
 792 }
 793
 794
 795 #if EFSYS_OPT_DIAG
 796
 797         __checkReturn   efx_rc_t
 798 efx_nic_register_test(
 799         __in            efx_nic_t *enp)
 800 {
 801         const efx_nic_ops_t *enop = enp->en_enop;
 802         efx_rc_t rc;
 803
 804         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 805         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 806         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 807
 808         if ((rc = enop->eno_register_test(enp)) != 0)
 809                 goto fail1;
 810
 811         return (0);
 812
 813 fail1:
 814         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 815
 816         return (rc);
 817 }
 818
 819 #endif  /* EFSYS_OPT_DIAG */
 820
 821 #if EFSYS_OPT_LOOPBACK
 822
 823 extern                  void
 824 efx_loopback_mask(
 825         __in    efx_loopback_kind_t loopback_kind,
 826         __out   efx_qword_t *maskp)
 827 {
 828         efx_qword_t mask;
 829
 830         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 831         EFSYS_ASSERT(maskp != NULL);
 832
 833         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
 834 #define LOOPBACK_CHECK(_mcdi, _efx) \
 835         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
 836
 837         LOOPBACK_CHECK(NONE, OFF);
 838         LOOPBACK_CHECK(DATA, DATA);
 839         LOOPBACK_CHECK(GMAC, GMAC);
 840         LOOPBACK_CHECK(XGMII, XGMII);
 841         LOOPBACK_CHECK(XGXS, XGXS);
 842         LOOPBACK_CHECK(XAUI, XAUI);
 843         LOOPBACK_CHECK(GMII, GMII);
 844         LOOPBACK_CHECK(SGMII, SGMII);
 845         LOOPBACK_CHECK(XGBR, XGBR);
 846         LOOPBACK_CHECK(XFI, XFI);
 847         LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
 848         LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
 849         LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
 850         LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
 851         LOOPBACK_CHECK(GPHY, GPHY);
 852         LOOPBACK_CHECK(PHYXS, PHY_XS);
 853         LOOPBACK_CHECK(PCS, PCS);
 854         LOOPBACK_CHECK(PMAPMD, PMA_PMD);
 855         LOOPBACK_CHECK(XPORT, XPORT);
 856         LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
 857         LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
 858         LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
 859         LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
 860         LOOPBACK_CHECK(GMII_WS, GMII_WS);
 861         LOOPBACK_CHECK(XFI_WS, XFI_WS);
 862         LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
 863         LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
 864         LOOPBACK_CHECK(PMA_INT, PMA_INT);
 865         LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
 866         LOOPBACK_CHECK(SD_FAR, SD_FAR);
 867         LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
 868         LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
 869         LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
 870         LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
 871         LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
 872         LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
 873         LOOPBACK_CHECK(DATA_WS, DATA_WS);
 874         LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
 875 #undef LOOPBACK_CHECK
 876
 877         /* Build bitmask of possible loopback types */
 878         EFX_ZERO_QWORD(mask);
 879
 880         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 881             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 882                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 883         }
 884
 885         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 886             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 887                 /*
 888                  * The "MAC" grouping has historically been used by drivers to
 889                  * mean loopbacks supported by on-chip hardware. Keep that
 890                  * meaning here, and include on-chip PHY layer loopbacks.
 891                  */
 892                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 893                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 894                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 895                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 896                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 897                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 898                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 899                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 900                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 901                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 902                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 903                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 904                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 905                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 906                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 907                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 908         }
 909
 910         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 911             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 912                 /*
 913                  * The "PHY" grouping has historically been used by drivers to
 914                  * mean loopbacks supported by off-chip hardware. Keep that
 915                  * meaning here.
 916                  */
 917                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 918                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 919                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 920                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 921         }
 922
 923         *maskp = mask;
 924 }
 925
 926         __checkReturn   efx_rc_t
 927 efx_mcdi_get_loopback_modes(
 928         __in            efx_nic_t *enp)
 929 {
 930         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 931         efx_mcdi_req_t req;
 932         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 933                 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
 934         efx_qword_t mask;
 935         efx_qword_t modes;
 936         efx_rc_t rc;
 937
 938         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 939         req.emr_in_buf = payload;
 940         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 941         req.emr_out_buf = payload;
 942         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
 943
 944         efx_mcdi_execute(enp, &req);
 945
 946         if (req.emr_rc != 0) {
 947                 rc = req.emr_rc;
 948                 goto fail1;
 949         }
 950
 951         if (req.emr_out_length_used <
 952             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 953             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 954                 rc = EMSGSIZE;
 955                 goto fail2;
 956         }
 957
 958         /*
 959          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 960          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 961          */
 962         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 963
 964         EFX_AND_QWORD(mask,
 965             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 966
 967         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 968         EFX_AND_QWORD(modes, mask);
 969         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 970
 971         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 972         EFX_AND_QWORD(modes, mask);
 973         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 974
 975         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 976         EFX_AND_QWORD(modes, mask);
 977         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 978
 979         if (req.emr_out_length_used >=
 980             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 981             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 982                 /* Response includes 40G loopback modes */
 983                 modes = *MCDI_OUT2(req, efx_qword_t,
 984                     GET_LOOPBACK_MODES_OUT_40G);
 985                 EFX_AND_QWORD(modes, mask);
 986                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 987         }
 988
 989         if (req.emr_out_length_used >=
 990             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
 991             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
 992                 /* Response includes 25G loopback modes */
 993                 modes = *MCDI_OUT2(req, efx_qword_t,
 994                     GET_LOOPBACK_MODES_OUT_V2_25G);
 995                 EFX_AND_QWORD(modes, mask);
 996                 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
 997         }
 998
 999         if (req.emr_out_length_used >=
1000             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
1001             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
1002                 /* Response includes 50G loopback modes */
1003                 modes = *MCDI_OUT2(req, efx_qword_t,
1004                     GET_LOOPBACK_MODES_OUT_V2_50G);
1005                 EFX_AND_QWORD(modes, mask);
1006                 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
1007         }
1008
1009         if (req.emr_out_length_used >=
1010             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
1011             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
1012                 /* Response includes 100G loopback modes */
1013                 modes = *MCDI_OUT2(req, efx_qword_t,
1014                     GET_LOOPBACK_MODES_OUT_V2_100G);
1015                 EFX_AND_QWORD(modes, mask);
1016                 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
1017         }
1018
1019         EFX_ZERO_QWORD(modes);
1020         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
1021         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
1022         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
1023         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
1024         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
1025         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
1026         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
1027         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
1028         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
1029
1030         return (0);
1031
1032 fail2:
1033         EFSYS_PROBE(fail2);
1034 fail1:
1035         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1036
1037         return (rc);
1038 }
1039
1040 #endif /* EFSYS_OPT_LOOPBACK */
1041
1042         __checkReturn   efx_rc_t
1043 efx_nic_calculate_pcie_link_bandwidth(
1044         __in            uint32_t pcie_link_width,
1045         __in            uint32_t pcie_link_gen,
1046         __out           uint32_t *bandwidth_mbpsp)
1047 {
1048         uint32_t lane_bandwidth;
1049         uint32_t total_bandwidth;
1050         efx_rc_t rc;
1051
1052         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
1053             !ISP2(pcie_link_width)) {
1054                 rc = EINVAL;
1055                 goto fail1;
1056         }
1057
1058         switch (pcie_link_gen) {
1059         case EFX_PCIE_LINK_SPEED_GEN1:
1060                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
1061                 lane_bandwidth = 2000;
1062                 break;
1063         case EFX_PCIE_LINK_SPEED_GEN2:
1064                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
1065                 lane_bandwidth = 4000;
1066                 break;
1067         case EFX_PCIE_LINK_SPEED_GEN3:
1068                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
1069                 lane_bandwidth = 7877;
1070                 break;
1071         default:
1072                 rc = EINVAL;
1073                 goto fail2;
1074         }
1075
1076         total_bandwidth = lane_bandwidth * pcie_link_width;
1077         *bandwidth_mbpsp = total_bandwidth;
1078
1079         return (0);
1080
1081 fail2:
1082         EFSYS_PROBE(fail2);
1083 fail1:
1084         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1085
1086         return (rc);
1087 }
1088
1089 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1090
1091         __checkReturn   efx_rc_t
1092 efx_nic_get_fw_subvariant(
1093         __in            efx_nic_t *enp,
1094         __out           efx_nic_fw_subvariant_t *subvariantp)
1095 {
1096         efx_rc_t rc;
1097         uint32_t value;
1098
1099         rc = efx_mcdi_get_nic_global(enp,
1100             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1101         if (rc != 0)
1102                 goto fail1;
1103
1104         /* Mapping is not required since values match MCDI */
1105         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1106             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1107         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1108             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1109
1110         switch (value) {
1111         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1112         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1113                 *subvariantp = value;
1114                 break;
1115         default:
1116                 rc = EINVAL;
1117                 goto fail2;
1118         }
1119
1120         return (0);
1121
1122 fail2:
1123         EFSYS_PROBE(fail2);
1124
1125 fail1:
1126         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1127
1128         return (rc);
1129 }
1130
1131         __checkReturn   efx_rc_t
1132 efx_nic_set_fw_subvariant(
1133         __in            efx_nic_t *enp,
1134         __in            efx_nic_fw_subvariant_t subvariant)
1135 {
1136         efx_rc_t rc;
1137
1138         switch (subvariant) {
1139         case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1140         case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1141                 /* Mapping is not required since values match MCDI */
1142                 break;
1143         default:
1144                 rc = EINVAL;
1145                 goto fail1;
1146         }
1147
1148         rc = efx_mcdi_set_nic_global(enp,
1149             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1150         if (rc != 0)
1151                 goto fail2;
1152
1153         return (0);
1154
1155 fail2:
1156         EFSYS_PROBE(fail2);
1157
1158 fail1:
1159         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1160
1161         return (rc);
1162 }
1163
1164 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1165
1166         __checkReturn   efx_rc_t
1167 efx_nic_check_pcie_link_speed(
1168         __in            efx_nic_t *enp,
1169         __in            uint32_t pcie_link_width,
1170         __in            uint32_t pcie_link_gen,
1171         __out           efx_pcie_link_performance_t *resultp)
1172 {
1173         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1174         uint32_t bandwidth;
1175         efx_pcie_link_performance_t result;
1176         efx_rc_t rc;
1177
1178         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1179             (pcie_link_width == 0) || (pcie_link_width == 32) ||
1180             (pcie_link_gen == 0)) {
1181                 /*
1182                  * No usable info on what is required and/or in use. In virtual
1183                  * machines, sometimes the PCIe link width is reported as 0 or
1184                  * 32, or the speed as 0.
1185                  */
1186                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1187                 goto out;
1188         }
1189
1190         /* Calculate the available bandwidth in megabits per second */
1191         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1192                                             pcie_link_gen, &bandwidth);
1193         if (rc != 0)
1194                 goto fail1;
1195
1196         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1197                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1198         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1199                 /* The link provides enough bandwidth but not optimal latency */
1200                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1201         } else {
1202                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1203         }
1204
1205 out:
1206         *resultp = result;
1207
1208         return (0);
1209
1210 fail1:
1211         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1212
1213         return (rc);
1214 }