drivers/common/sfc_efx/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         if (venid == EFX_PCI_VENID_XILINX) {
  89                 switch (devid) {
  90 #if EFSYS_OPT_RIVERHEAD
  91                 case EFX_PCI_DEVID_RIVERHEAD:
  92                 case EFX_PCI_DEVID_RIVERHEAD_VF:
  93                         *efp = EFX_FAMILY_RIVERHEAD;
  94                         *membarp = EFX_MEM_BAR_RIVERHEAD;
  95                         return (0);
  96 #endif /* EFSYS_OPT_RIVERHEAD */
  97                 default:
  98                         break;
  99                 }
 100         }
 101
 102         *efp = EFX_FAMILY_INVALID;
 103         return (ENOTSUP);
 104 }
 105
 106
 107 #if EFSYS_OPT_SIENA
 108
 109 static const efx_nic_ops_t      __efx_nic_siena_ops = {
 110         siena_nic_probe,                /* eno_probe */
 111         NULL,                           /* eno_board_cfg */
 112         NULL,                           /* eno_set_drv_limits */
 113         siena_nic_reset,                /* eno_reset */
 114         siena_nic_init,                 /* eno_init */
 115         NULL,                           /* eno_get_vi_pool */
 116         NULL,                           /* eno_get_bar_region */
 117         NULL,                           /* eno_hw_unavailable */
 118         NULL,                           /* eno_set_hw_unavailable */
 119 #if EFSYS_OPT_DIAG
 120         siena_nic_register_test,        /* eno_register_test */
 121 #endif  /* EFSYS_OPT_DIAG */
 122         siena_nic_fini,                 /* eno_fini */
 123         siena_nic_unprobe,              /* eno_unprobe */
 124 };
 125
 126 #endif  /* EFSYS_OPT_SIENA */
 127
 128 #if EFSYS_OPT_HUNTINGTON
 129
 130 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 131         ef10_nic_probe,                 /* eno_probe */
 132         hunt_board_cfg,                 /* eno_board_cfg */
 133         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 134         ef10_nic_reset,                 /* eno_reset */
 135         ef10_nic_init,                  /* eno_init */
 136         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 137         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 138         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 139         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 140 #if EFSYS_OPT_DIAG
 141         ef10_nic_register_test,         /* eno_register_test */
 142 #endif  /* EFSYS_OPT_DIAG */
 143         ef10_nic_fini,                  /* eno_fini */
 144         ef10_nic_unprobe,               /* eno_unprobe */
 145 };
 146
 147 #endif  /* EFSYS_OPT_HUNTINGTON */
 148
 149 #if EFSYS_OPT_MEDFORD
 150
 151 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 152         ef10_nic_probe,                 /* eno_probe */
 153         medford_board_cfg,              /* eno_board_cfg */
 154         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 155         ef10_nic_reset,                 /* eno_reset */
 156         ef10_nic_init,                  /* eno_init */
 157         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 158         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 159         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 160         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 161 #if EFSYS_OPT_DIAG
 162         ef10_nic_register_test,         /* eno_register_test */
 163 #endif  /* EFSYS_OPT_DIAG */
 164         ef10_nic_fini,                  /* eno_fini */
 165         ef10_nic_unprobe,               /* eno_unprobe */
 166 };
 167
 168 #endif  /* EFSYS_OPT_MEDFORD */
 169
 170 #if EFSYS_OPT_MEDFORD2
 171
 172 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 173         ef10_nic_probe,                 /* eno_probe */
 174         medford2_board_cfg,             /* eno_board_cfg */
 175         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 176         ef10_nic_reset,                 /* eno_reset */
 177         ef10_nic_init,                  /* eno_init */
 178         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 179         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 180         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 181         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 182 #if EFSYS_OPT_DIAG
 183         ef10_nic_register_test,         /* eno_register_test */
 184 #endif  /* EFSYS_OPT_DIAG */
 185         ef10_nic_fini,                  /* eno_fini */
 186         ef10_nic_unprobe,               /* eno_unprobe */
 187 };
 188
 189 #endif  /* EFSYS_OPT_MEDFORD2 */
 190
 191 #if EFSYS_OPT_RIVERHEAD
 192
 193 static const efx_nic_ops_t      __efx_nic_riverhead_ops = {
 194         rhead_nic_probe,                /* eno_probe */
 195         rhead_board_cfg,                /* eno_board_cfg */
 196         rhead_nic_set_drv_limits,       /* eno_set_drv_limits */
 197         rhead_nic_reset,                /* eno_reset */
 198         rhead_nic_init,                 /* eno_init */
 199         rhead_nic_get_vi_pool,          /* eno_get_vi_pool */
 200         rhead_nic_get_bar_region,       /* eno_get_bar_region */
 201         rhead_nic_hw_unavailable,       /* eno_hw_unavailable */
 202         rhead_nic_set_hw_unavailable,   /* eno_set_hw_unavailable */
 203 #if EFSYS_OPT_DIAG
 204         rhead_nic_register_test,        /* eno_register_test */
 205 #endif  /* EFSYS_OPT_DIAG */
 206         rhead_nic_fini,                 /* eno_fini */
 207         rhead_nic_unprobe,              /* eno_unprobe */
 208 };
 209
 210 #endif  /* EFSYS_OPT_RIVERHEAD */
 211
 212
 213         __checkReturn   efx_rc_t
 214 efx_nic_create(
 215         __in            efx_family_t family,
 216         __in            efsys_identifier_t *esip,
 217         __in            efsys_bar_t *esbp,
 218         __in            efsys_lock_t *eslp,
 219         __deref_out     efx_nic_t **enpp)
 220 {
 221         efx_nic_t *enp;
 222         efx_rc_t rc;
 223
 224         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 225         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 226
 227         /* Allocate a NIC object */
 228         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 229
 230         if (enp == NULL) {
 231                 rc = ENOMEM;
 232                 goto fail1;
 233         }
 234
 235         enp->en_magic = EFX_NIC_MAGIC;
 236
 237         switch (family) {
 238 #if EFSYS_OPT_SIENA
 239         case EFX_FAMILY_SIENA:
 240                 enp->en_enop = &__efx_nic_siena_ops;
 241                 enp->en_features =
 242                     EFX_FEATURE_IPV6 |
 243                     EFX_FEATURE_LFSR_HASH_INSERT |
 244                     EFX_FEATURE_LINK_EVENTS |
 245                     EFX_FEATURE_PERIODIC_MAC_STATS |
 246                     EFX_FEATURE_MCDI |
 247                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 248                     EFX_FEATURE_MAC_HEADER_FILTERS |
 249                     EFX_FEATURE_TX_SRC_FILTERS;
 250                 break;
 251 #endif  /* EFSYS_OPT_SIENA */
 252
 253 #if EFSYS_OPT_HUNTINGTON
 254         case EFX_FAMILY_HUNTINGTON:
 255                 enp->en_enop = &__efx_nic_hunt_ops;
 256                 enp->en_features =
 257                     EFX_FEATURE_IPV6 |
 258                     EFX_FEATURE_LINK_EVENTS |
 259                     EFX_FEATURE_PERIODIC_MAC_STATS |
 260                     EFX_FEATURE_MCDI |
 261                     EFX_FEATURE_MAC_HEADER_FILTERS |
 262                     EFX_FEATURE_MCDI_DMA |
 263                     EFX_FEATURE_PIO_BUFFERS |
 264                     EFX_FEATURE_FW_ASSISTED_TSO |
 265                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 266                     EFX_FEATURE_PACKED_STREAM |
 267                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 268                 break;
 269 #endif  /* EFSYS_OPT_HUNTINGTON */
 270
 271 #if EFSYS_OPT_MEDFORD
 272         case EFX_FAMILY_MEDFORD:
 273                 enp->en_enop = &__efx_nic_medford_ops;
 274                 /*
 275                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 276                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 277                  */
 278                 enp->en_features =
 279                     EFX_FEATURE_IPV6 |
 280                     EFX_FEATURE_LINK_EVENTS |
 281                     EFX_FEATURE_PERIODIC_MAC_STATS |
 282                     EFX_FEATURE_MCDI |
 283                     EFX_FEATURE_MAC_HEADER_FILTERS |
 284                     EFX_FEATURE_MCDI_DMA |
 285                     EFX_FEATURE_PIO_BUFFERS |
 286                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 287                     EFX_FEATURE_PACKED_STREAM |
 288                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 289                 break;
 290 #endif  /* EFSYS_OPT_MEDFORD */
 291
 292 #if EFSYS_OPT_MEDFORD2
 293         case EFX_FAMILY_MEDFORD2:
 294                 enp->en_enop = &__efx_nic_medford2_ops;
 295                 enp->en_features =
 296                     EFX_FEATURE_IPV6 |
 297                     EFX_FEATURE_LINK_EVENTS |
 298                     EFX_FEATURE_PERIODIC_MAC_STATS |
 299                     EFX_FEATURE_MCDI |
 300                     EFX_FEATURE_MAC_HEADER_FILTERS |
 301                     EFX_FEATURE_MCDI_DMA |
 302                     EFX_FEATURE_PIO_BUFFERS |
 303                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 304                     EFX_FEATURE_PACKED_STREAM |
 305                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 306                 break;
 307 #endif  /* EFSYS_OPT_MEDFORD2 */
 308
 309 #if EFSYS_OPT_RIVERHEAD
 310         case EFX_FAMILY_RIVERHEAD:
 311                 enp->en_enop = &__efx_nic_riverhead_ops;
 312                 enp->en_features =
 313                     EFX_FEATURE_IPV6 |
 314                     EFX_FEATURE_LINK_EVENTS |
 315                     EFX_FEATURE_PERIODIC_MAC_STATS |
 316                     EFX_FEATURE_MCDI |
 317                     EFX_FEATURE_MAC_HEADER_FILTERS |
 318                     EFX_FEATURE_MCDI_DMA;
 319                 break;
 320 #endif  /* EFSYS_OPT_RIVERHEAD */
 321
 322         default:
 323                 rc = ENOTSUP;
 324                 goto fail2;
 325         }
 326
 327         enp->en_family = family;
 328         enp->en_esip = esip;
 329         enp->en_esbp = esbp;
 330         enp->en_eslp = eslp;
 331
 332         *enpp = enp;
 333
 334         return (0);
 335
 336 fail2:
 337         EFSYS_PROBE(fail2);
 338
 339         enp->en_magic = 0;
 340
 341         /* Free the NIC object */
 342         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 343
 344 fail1:
 345         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 346
 347         return (rc);
 348 }
 349
 350         __checkReturn   efx_rc_t
 351 efx_nic_probe(
 352         __in            efx_nic_t *enp,
 353         __in            efx_fw_variant_t efv)
 354 {
 355         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 356         const efx_nic_ops_t *enop;
 357         efx_rc_t rc;
 358
 359         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 360 #if EFSYS_OPT_MCDI
 361         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 362 #endif  /* EFSYS_OPT_MCDI */
 363         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 364
 365         /* Ensure FW variant codes match with MC_CMD_FW codes */
 366         EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
 367             MC_CMD_FW_FULL_FEATURED);
 368         EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
 369             MC_CMD_FW_LOW_LATENCY);
 370         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
 371             MC_CMD_FW_PACKED_STREAM);
 372         EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
 373             MC_CMD_FW_HIGH_TX_RATE);
 374         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
 375             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
 376         EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
 377             MC_CMD_FW_RULES_ENGINE);
 378         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
 379             MC_CMD_FW_DPDK);
 380         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
 381             (int)MC_CMD_FW_DONT_CARE);
 382
 383         enop = enp->en_enop;
 384         enp->efv = efv;
 385
 386         if ((rc = enop->eno_probe(enp)) != 0)
 387                 goto fail1;
 388
 389         encp->enc_features = enp->en_features;
 390
 391         if ((rc = efx_phy_probe(enp)) != 0)
 392                 goto fail2;
 393
 394         enp->en_mod_flags |= EFX_MOD_PROBE;
 395
 396         return (0);
 397
 398 fail2:
 399         EFSYS_PROBE(fail2);
 400
 401         enop->eno_unprobe(enp);
 402
 403 fail1:
 404         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 405
 406         return (rc);
 407 }
 408
 409         __checkReturn   efx_rc_t
 410 efx_nic_set_drv_limits(
 411         __inout         efx_nic_t *enp,
 412         __in            efx_drv_limits_t *edlp)
 413 {
 414         const efx_nic_ops_t *enop = enp->en_enop;
 415         efx_rc_t rc;
 416
 417         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 418         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 419
 420         if (enop->eno_set_drv_limits != NULL) {
 421                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 422                         goto fail1;
 423         }
 424
 425         return (0);
 426
 427 fail1:
 428         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 429
 430         return (rc);
 431 }
 432
 433         __checkReturn   efx_rc_t
 434 efx_nic_set_drv_version(
 435         __inout                 efx_nic_t *enp,
 436         __in_ecount(length)     char const *verp,
 437         __in                    size_t length)
 438 {
 439         efx_rc_t rc;
 440
 441         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 442         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 443
 444         /*
 445          * length is the string content length in bytes.
 446          * Accept any content which fits into the version
 447          * buffer, excluding the last byte. This is reserved
 448          * for an appended NUL terminator.
 449          */
 450         if (length >= sizeof (enp->en_drv_version)) {
 451                 rc = E2BIG;
 452                 goto fail1;
 453         }
 454
 455         (void) memset(enp->en_drv_version, 0,
 456             sizeof (enp->en_drv_version));
 457         memcpy(enp->en_drv_version, verp, length);
 458
 459         return (0);
 460
 461 fail1:
 462         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 463
 464         return (rc);
 465 }
 466
 467
 468         __checkReturn   efx_rc_t
 469 efx_nic_get_bar_region(
 470         __in            efx_nic_t *enp,
 471         __in            efx_nic_region_t region,
 472         __out           uint32_t *offsetp,
 473         __out           size_t *sizep)
 474 {
 475         const efx_nic_ops_t *enop = enp->en_enop;
 476         efx_rc_t rc;
 477
 478         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 479         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 480         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 481
 482         if (enop->eno_get_bar_region == NULL) {
 483                 rc = ENOTSUP;
 484                 goto fail1;
 485         }
 486         if ((rc = (enop->eno_get_bar_region)(enp,
 487                     region, offsetp, sizep)) != 0) {
 488                 goto fail2;
 489         }
 490
 491         return (0);
 492
 493 fail2:
 494         EFSYS_PROBE(fail2);
 495
 496 fail1:
 497         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 498
 499         return (rc);
 500 }
 501
 502
 503         __checkReturn   efx_rc_t
 504 efx_nic_get_vi_pool(
 505         __in            efx_nic_t *enp,
 506         __out           uint32_t *evq_countp,
 507         __out           uint32_t *rxq_countp,
 508         __out           uint32_t *txq_countp)
 509 {
 510         const efx_nic_ops_t *enop = enp->en_enop;
 511         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 512         efx_rc_t rc;
 513
 514         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 515         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 516         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 517
 518         if (enop->eno_get_vi_pool != NULL) {
 519                 uint32_t vi_count = 0;
 520
 521                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 522                         goto fail1;
 523
 524                 *evq_countp = vi_count;
 525                 *rxq_countp = vi_count;
 526                 *txq_countp = vi_count;
 527         } else {
 528                 /* Use NIC limits as default value */
 529                 *evq_countp = encp->enc_evq_limit;
 530                 *rxq_countp = encp->enc_rxq_limit;
 531                 *txq_countp = encp->enc_txq_limit;
 532         }
 533
 534         return (0);
 535
 536 fail1:
 537         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 538
 539         return (rc);
 540 }
 541
 542
 543         __checkReturn   efx_rc_t
 544 efx_nic_init(
 545         __in            efx_nic_t *enp)
 546 {
 547         const efx_nic_ops_t *enop = enp->en_enop;
 548         efx_rc_t rc;
 549
 550         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 551         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 552
 553         if (enp->en_mod_flags & EFX_MOD_NIC) {
 554                 rc = EINVAL;
 555                 goto fail1;
 556         }
 557
 558         if ((rc = enop->eno_init(enp)) != 0)
 559                 goto fail2;
 560
 561         enp->en_mod_flags |= EFX_MOD_NIC;
 562
 563         return (0);
 564
 565 fail2:
 566         EFSYS_PROBE(fail2);
 567 fail1:
 568         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 569
 570         return (rc);
 571 }
 572
 573                         void
 574 efx_nic_fini(
 575         __in            efx_nic_t *enp)
 576 {
 577         const efx_nic_ops_t *enop = enp->en_enop;
 578
 579         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 580         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 581         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 582         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 583         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 584         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 585         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 586
 587         enop->eno_fini(enp);
 588
 589         enp->en_mod_flags &= ~EFX_MOD_NIC;
 590 }
 591
 592                         void
 593 efx_nic_unprobe(
 594         __in            efx_nic_t *enp)
 595 {
 596         const efx_nic_ops_t *enop = enp->en_enop;
 597
 598         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 599 #if EFSYS_OPT_MCDI
 600         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 601 #endif  /* EFSYS_OPT_MCDI */
 602         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 603         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 604         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 605         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 606         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 607         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 608
 609         efx_phy_unprobe(enp);
 610
 611         enop->eno_unprobe(enp);
 612
 613         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 614 }
 615
 616                         void
 617 efx_nic_destroy(
 618         __in    efx_nic_t *enp)
 619 {
 620         efsys_identifier_t *esip = enp->en_esip;
 621
 622         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 623         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 624
 625         enp->en_family = EFX_FAMILY_INVALID;
 626         enp->en_esip = NULL;
 627         enp->en_esbp = NULL;
 628         enp->en_eslp = NULL;
 629
 630         enp->en_enop = NULL;
 631
 632         enp->en_magic = 0;
 633
 634         /* Free the NIC object */
 635         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 636 }
 637
 638         __checkReturn   efx_rc_t
 639 efx_nic_reset(
 640         __in            efx_nic_t *enp)
 641 {
 642         const efx_nic_ops_t *enop = enp->en_enop;
 643         unsigned int mod_flags;
 644         efx_rc_t rc;
 645
 646         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 647         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 648         /*
 649          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 650          * (which we do not reset here) must have been shut down or never
 651          * initialized.
 652          *
 653          * A rule of thumb here is: If the controller or MC reboots, is *any*
 654          * state lost. If it's lost and needs reapplying, then the module
 655          * *must* not be initialised during the reset.
 656          */
 657         mod_flags = enp->en_mod_flags;
 658         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 659             EFX_MOD_VPD | EFX_MOD_MON);
 660 #if EFSYS_OPT_TUNNEL
 661         mod_flags &= ~EFX_MOD_TUNNEL;
 662 #endif /* EFSYS_OPT_TUNNEL */
 663         EFSYS_ASSERT3U(mod_flags, ==, 0);
 664         if (mod_flags != 0) {
 665                 rc = EINVAL;
 666                 goto fail1;
 667         }
 668
 669         if ((rc = enop->eno_reset(enp)) != 0)
 670                 goto fail2;
 671
 672         return (0);
 673
 674 fail2:
 675         EFSYS_PROBE(fail2);
 676 fail1:
 677         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 678
 679         return (rc);
 680 }
 681
 682                         const efx_nic_cfg_t *
 683 efx_nic_cfg_get(
 684         __in            const efx_nic_t *enp)
 685 {
 686         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 687         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 688
 689         return (&(enp->en_nic_cfg));
 690 }
 691
 692         __checkReturn           efx_rc_t
 693 efx_nic_get_fw_version(
 694         __in                    efx_nic_t *enp,
 695         __out                   efx_nic_fw_info_t *enfip)
 696 {
 697         uint16_t mc_fw_version[4];
 698         efx_rc_t rc;
 699
 700         if (enfip == NULL) {
 701                 rc = EINVAL;
 702                 goto fail1;
 703         }
 704
 705         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 706         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 707
 708         /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
 709         EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
 710             MC_CMD_GET_CAPABILITIES_OUT_RXDP);
 711         EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
 712             MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
 713         EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
 714             MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
 715         EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
 716             MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
 717         EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
 718             MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
 719
 720         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 721         if (rc != 0)
 722                 goto fail2;
 723
 724         rc = efx_mcdi_get_capabilities(enp, NULL,
 725             &enfip->enfi_rx_dpcpu_fw_id,
 726             &enfip->enfi_tx_dpcpu_fw_id,
 727             NULL, NULL);
 728         if (rc == 0) {
 729                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 730         } else if (rc == ENOTSUP) {
 731                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 732                 enfip->enfi_rx_dpcpu_fw_id = 0;
 733                 enfip->enfi_tx_dpcpu_fw_id = 0;
 734         } else {
 735                 goto fail3;
 736         }
 737
 738         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 739             sizeof (mc_fw_version));
 740
 741         return (0);
 742
 743 fail3:
 744         EFSYS_PROBE(fail3);
 745 fail2:
 746         EFSYS_PROBE(fail2);
 747 fail1:
 748         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 749
 750         return (rc);
 751 }
 752
 753         __checkReturn   boolean_t
 754 efx_nic_hw_unavailable(
 755         __in            efx_nic_t *enp)
 756 {
 757         const efx_nic_ops_t *enop = enp->en_enop;
 758
 759         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 760         /* NOTE: can be used by MCDI before NIC probe */
 761
 762         if (enop->eno_hw_unavailable != NULL) {
 763                 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
 764                         goto unavail;
 765         }
 766
 767         return (B_FALSE);
 768
 769 unavail:
 770         return (B_TRUE);
 771 }
 772
 773                         void
 774 efx_nic_set_hw_unavailable(
 775         __in            efx_nic_t *enp)
 776 {
 777         const efx_nic_ops_t *enop = enp->en_enop;
 778
 779         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 780
 781         if (enop->eno_set_hw_unavailable != NULL)
 782                 enop->eno_set_hw_unavailable(enp);
 783 }
 784
 785
 786 #if EFSYS_OPT_DIAG
 787
 788         __checkReturn   efx_rc_t
 789 efx_nic_register_test(
 790         __in            efx_nic_t *enp)
 791 {
 792         const efx_nic_ops_t *enop = enp->en_enop;
 793         efx_rc_t rc;
 794
 795         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 796         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 797         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 798
 799         if ((rc = enop->eno_register_test(enp)) != 0)
 800                 goto fail1;
 801
 802         return (0);
 803
 804 fail1:
 805         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 806
 807         return (rc);
 808 }
 809
 810 #endif  /* EFSYS_OPT_DIAG */
 811
 812 #if EFSYS_OPT_LOOPBACK
 813
 814 extern                  void
 815 efx_loopback_mask(
 816         __in    efx_loopback_kind_t loopback_kind,
 817         __out   efx_qword_t *maskp)
 818 {
 819         efx_qword_t mask;
 820
 821         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 822         EFSYS_ASSERT(maskp != NULL);
 823
 824         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
 825 #define LOOPBACK_CHECK(_mcdi, _efx) \
 826         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
 827
 828         LOOPBACK_CHECK(NONE, OFF);
 829         LOOPBACK_CHECK(DATA, DATA);
 830         LOOPBACK_CHECK(GMAC, GMAC);
 831         LOOPBACK_CHECK(XGMII, XGMII);
 832         LOOPBACK_CHECK(XGXS, XGXS);
 833         LOOPBACK_CHECK(XAUI, XAUI);
 834         LOOPBACK_CHECK(GMII, GMII);
 835         LOOPBACK_CHECK(SGMII, SGMII);
 836         LOOPBACK_CHECK(XGBR, XGBR);
 837         LOOPBACK_CHECK(XFI, XFI);
 838         LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
 839         LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
 840         LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
 841         LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
 842         LOOPBACK_CHECK(GPHY, GPHY);
 843         LOOPBACK_CHECK(PHYXS, PHY_XS);
 844         LOOPBACK_CHECK(PCS, PCS);
 845         LOOPBACK_CHECK(PMAPMD, PMA_PMD);
 846         LOOPBACK_CHECK(XPORT, XPORT);
 847         LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
 848         LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
 849         LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
 850         LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
 851         LOOPBACK_CHECK(GMII_WS, GMII_WS);
 852         LOOPBACK_CHECK(XFI_WS, XFI_WS);
 853         LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
 854         LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
 855         LOOPBACK_CHECK(PMA_INT, PMA_INT);
 856         LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
 857         LOOPBACK_CHECK(SD_FAR, SD_FAR);
 858         LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
 859         LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
 860         LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
 861         LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
 862         LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
 863         LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
 864         LOOPBACK_CHECK(DATA_WS, DATA_WS);
 865         LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
 866 #undef LOOPBACK_CHECK
 867
 868         /* Build bitmask of possible loopback types */
 869         EFX_ZERO_QWORD(mask);
 870
 871         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 872             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 873                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 874         }
 875
 876         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 877             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 878                 /*
 879                  * The "MAC" grouping has historically been used by drivers to
 880                  * mean loopbacks supported by on-chip hardware. Keep that
 881                  * meaning here, and include on-chip PHY layer loopbacks.
 882                  */
 883                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 884                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 885                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 886                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 887                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 888                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 889                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 890                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 891                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 892                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 893                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 894                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 895                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 896                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 897                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 898                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 899         }
 900
 901         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 902             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 903                 /*
 904                  * The "PHY" grouping has historically been used by drivers to
 905                  * mean loopbacks supported by off-chip hardware. Keep that
 906                  * meaning here.
 907                  */
 908                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 909                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 910                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 911                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 912         }
 913
 914         *maskp = mask;
 915 }
 916
 917         __checkReturn   efx_rc_t
 918 efx_mcdi_get_loopback_modes(
 919         __in            efx_nic_t *enp)
 920 {
 921         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 922         efx_mcdi_req_t req;
 923         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 924                 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
 925         efx_qword_t mask;
 926         efx_qword_t modes;
 927         efx_rc_t rc;
 928
 929         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 930         req.emr_in_buf = payload;
 931         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 932         req.emr_out_buf = payload;
 933         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
 934
 935         efx_mcdi_execute(enp, &req);
 936
 937         if (req.emr_rc != 0) {
 938                 rc = req.emr_rc;
 939                 goto fail1;
 940         }
 941
 942         if (req.emr_out_length_used <
 943             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 944             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 945                 rc = EMSGSIZE;
 946                 goto fail2;
 947         }
 948
 949         /*
 950          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
 951          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
 952          */
 953         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
 954
 955         EFX_AND_QWORD(mask,
 956             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
 957
 958         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
 959         EFX_AND_QWORD(modes, mask);
 960         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
 961
 962         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
 963         EFX_AND_QWORD(modes, mask);
 964         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
 965
 966         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
 967         EFX_AND_QWORD(modes, mask);
 968         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
 969
 970         if (req.emr_out_length_used >=
 971             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
 972             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
 973                 /* Response includes 40G loopback modes */
 974                 modes = *MCDI_OUT2(req, efx_qword_t,
 975                     GET_LOOPBACK_MODES_OUT_40G);
 976                 EFX_AND_QWORD(modes, mask);
 977                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
 978         }
 979
 980         if (req.emr_out_length_used >=
 981             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
 982             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
 983                 /* Response includes 25G loopback modes */
 984                 modes = *MCDI_OUT2(req, efx_qword_t,
 985                     GET_LOOPBACK_MODES_OUT_V2_25G);
 986                 EFX_AND_QWORD(modes, mask);
 987                 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
 988         }
 989
 990         if (req.emr_out_length_used >=
 991             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
 992             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
 993                 /* Response includes 50G loopback modes */
 994                 modes = *MCDI_OUT2(req, efx_qword_t,
 995                     GET_LOOPBACK_MODES_OUT_V2_50G);
 996                 EFX_AND_QWORD(modes, mask);
 997                 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
 998         }
 999
1000         if (req.emr_out_length_used >=
1001             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
1002             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
1003                 /* Response includes 100G loopback modes */
1004                 modes = *MCDI_OUT2(req, efx_qword_t,
1005                     GET_LOOPBACK_MODES_OUT_V2_100G);
1006                 EFX_AND_QWORD(modes, mask);
1007                 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
1008         }
1009
1010         EFX_ZERO_QWORD(modes);
1011         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
1012         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
1013         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
1014         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
1015         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
1016         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
1017         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
1018         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
1019         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
1020
1021         return (0);
1022
1023 fail2:
1024         EFSYS_PROBE(fail2);
1025 fail1:
1026         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1027
1028         return (rc);
1029 }
1030
1031 #endif /* EFSYS_OPT_LOOPBACK */
1032
1033         __checkReturn   efx_rc_t
1034 efx_nic_calculate_pcie_link_bandwidth(
1035         __in            uint32_t pcie_link_width,
1036         __in            uint32_t pcie_link_gen,
1037         __out           uint32_t *bandwidth_mbpsp)
1038 {
1039         uint32_t lane_bandwidth;
1040         uint32_t total_bandwidth;
1041         efx_rc_t rc;
1042
1043         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
1044             !ISP2(pcie_link_width)) {
1045                 rc = EINVAL;
1046                 goto fail1;
1047         }
1048
1049         switch (pcie_link_gen) {
1050         case EFX_PCIE_LINK_SPEED_GEN1:
1051                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
1052                 lane_bandwidth = 2000;
1053                 break;
1054         case EFX_PCIE_LINK_SPEED_GEN2:
1055                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
1056                 lane_bandwidth = 4000;
1057                 break;
1058         case EFX_PCIE_LINK_SPEED_GEN3:
1059                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
1060                 lane_bandwidth = 7877;
1061                 break;
1062         default:
1063                 rc = EINVAL;
1064                 goto fail2;
1065         }
1066
1067         total_bandwidth = lane_bandwidth * pcie_link_width;
1068         *bandwidth_mbpsp = total_bandwidth;
1069
1070         return (0);
1071
1072 fail2:
1073         EFSYS_PROBE(fail2);
1074 fail1:
1075         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1076
1077         return (rc);
1078 }
1079
1080 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1081
1082         __checkReturn   efx_rc_t
1083 efx_nic_get_fw_subvariant(
1084         __in            efx_nic_t *enp,
1085         __out           efx_nic_fw_subvariant_t *subvariantp)
1086 {
1087         efx_rc_t rc;
1088         uint32_t value;
1089
1090         rc = efx_mcdi_get_nic_global(enp,
1091             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1092         if (rc != 0)
1093                 goto fail1;
1094
1095         /* Mapping is not required since values match MCDI */
1096         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1097             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1098         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1099             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1100
1101         switch (value) {
1102         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1103         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1104                 *subvariantp = value;
1105                 break;
1106         default:
1107                 rc = EINVAL;
1108                 goto fail2;
1109         }
1110
1111         return (0);
1112
1113 fail2:
1114         EFSYS_PROBE(fail2);
1115
1116 fail1:
1117         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1118
1119         return (rc);
1120 }
1121
1122         __checkReturn   efx_rc_t
1123 efx_nic_set_fw_subvariant(
1124         __in            efx_nic_t *enp,
1125         __in            efx_nic_fw_subvariant_t subvariant)
1126 {
1127         efx_rc_t rc;
1128
1129         switch (subvariant) {
1130         case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1131         case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1132                 /* Mapping is not required since values match MCDI */
1133                 break;
1134         default:
1135                 rc = EINVAL;
1136                 goto fail1;
1137         }
1138
1139         rc = efx_mcdi_set_nic_global(enp,
1140             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1141         if (rc != 0)
1142                 goto fail2;
1143
1144         return (0);
1145
1146 fail2:
1147         EFSYS_PROBE(fail2);
1148
1149 fail1:
1150         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1151
1152         return (rc);
1153 }
1154
1155 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1156
1157         __checkReturn   efx_rc_t
1158 efx_nic_check_pcie_link_speed(
1159         __in            efx_nic_t *enp,
1160         __in            uint32_t pcie_link_width,
1161         __in            uint32_t pcie_link_gen,
1162         __out           efx_pcie_link_performance_t *resultp)
1163 {
1164         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1165         uint32_t bandwidth;
1166         efx_pcie_link_performance_t result;
1167         efx_rc_t rc;
1168
1169         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1170             (pcie_link_width == 0) || (pcie_link_width == 32) ||
1171             (pcie_link_gen == 0)) {
1172                 /*
1173                  * No usable info on what is required and/or in use. In virtual
1174                  * machines, sometimes the PCIe link width is reported as 0 or
1175                  * 32, or the speed as 0.
1176                  */
1177                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1178                 goto out;
1179         }
1180
1181         /* Calculate the available bandwidth in megabits per second */
1182         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1183                                             pcie_link_gen, &bandwidth);
1184         if (rc != 0)
1185                 goto fail1;
1186
1187         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1188                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1189         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1190                 /* The link provides enough bandwidth but not optimal latency */
1191                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1192         } else {
1193                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1194         }
1195
1196 out:
1197         *resultp = result;
1198
1199         return (0);
1200
1201 fail1:
1202         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1203
1204         return (rc);
1205 }