drivers/common/sfc_efx/base/efx_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9
  10
  11         __checkReturn   efx_rc_t
  12 efx_family(
  13         __in            uint16_t venid,
  14         __in            uint16_t devid,
  15         __out           efx_family_t *efp,
  16         __out           unsigned int *membarp)
  17 {
  18         if (venid == EFX_PCI_VENID_SFC) {
  19                 switch (devid) {
  20 #if EFSYS_OPT_SIENA
  21                 case EFX_PCI_DEVID_SIENA_F1_UNINIT:
  22                         /*
  23                          * Hardware default for PF0 of uninitialised Siena.
  24                          * manftest must be able to cope with this device id.
  25                          */
  26                 case EFX_PCI_DEVID_BETHPAGE:
  27                 case EFX_PCI_DEVID_SIENA:
  28                         *efp = EFX_FAMILY_SIENA;
  29                         *membarp = EFX_MEM_BAR_SIENA;
  30                         return (0);
  31 #endif /* EFSYS_OPT_SIENA */
  32
  33 #if EFSYS_OPT_HUNTINGTON
  34                 case EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT:
  35                         /*
  36                          * Hardware default for PF0 of uninitialised Huntington.
  37                          * manftest must be able to cope with this device id.
  38                          */
  39                 case EFX_PCI_DEVID_FARMINGDALE:
  40                 case EFX_PCI_DEVID_GREENPORT:
  41                         *efp = EFX_FAMILY_HUNTINGTON;
  42                         *membarp = EFX_MEM_BAR_HUNTINGTON_PF;
  43                         return (0);
  44
  45                 case EFX_PCI_DEVID_FARMINGDALE_VF:
  46                 case EFX_PCI_DEVID_GREENPORT_VF:
  47                         *efp = EFX_FAMILY_HUNTINGTON;
  48                         *membarp = EFX_MEM_BAR_HUNTINGTON_VF;
  49                         return (0);
  50 #endif /* EFSYS_OPT_HUNTINGTON */
  51
  52 #if EFSYS_OPT_MEDFORD
  53                 case EFX_PCI_DEVID_MEDFORD_PF_UNINIT:
  54                         /*
  55                          * Hardware default for PF0 of uninitialised Medford.
  56                          * manftest must be able to cope with this device id.
  57                          */
  58                 case EFX_PCI_DEVID_MEDFORD:
  59                         *efp = EFX_FAMILY_MEDFORD;
  60                         *membarp = EFX_MEM_BAR_MEDFORD_PF;
  61                         return (0);
  62
  63                 case EFX_PCI_DEVID_MEDFORD_VF:
  64                         *efp = EFX_FAMILY_MEDFORD;
  65                         *membarp = EFX_MEM_BAR_MEDFORD_VF;
  66                         return (0);
  67 #endif /* EFSYS_OPT_MEDFORD */
  68
  69 #if EFSYS_OPT_MEDFORD2
  70                 case EFX_PCI_DEVID_MEDFORD2_PF_UNINIT:
  71                         /*
  72                          * Hardware default for PF0 of uninitialised Medford2.
  73                          * manftest must be able to cope with this device id.
  74                          */
  75                 case EFX_PCI_DEVID_MEDFORD2:
  76                 case EFX_PCI_DEVID_MEDFORD2_VF:
  77                         *efp = EFX_FAMILY_MEDFORD2;
  78                         *membarp = EFX_MEM_BAR_MEDFORD2;
  79                         return (0);
  80 #endif /* EFSYS_OPT_MEDFORD2 */
  81
  82                 case EFX_PCI_DEVID_FALCON:      /* Obsolete, not supported */
  83                 default:
  84                         break;
  85                 }
  86         }
  87
  88         if (venid == EFX_PCI_VENID_XILINX) {
  89                 switch (devid) {
  90 #if EFSYS_OPT_RIVERHEAD
  91                 case EFX_PCI_DEVID_RIVERHEAD:
  92                 case EFX_PCI_DEVID_RIVERHEAD_VF:
  93                         *efp = EFX_FAMILY_RIVERHEAD;
  94                         *membarp = EFX_MEM_BAR_RIVERHEAD;
  95                         return (0);
  96 #endif /* EFSYS_OPT_RIVERHEAD */
  97                 default:
  98                         break;
  99                 }
 100         }
 101
 102         *efp = EFX_FAMILY_INVALID;
 103         return (ENOTSUP);
 104 }
 105
 106 #if EFSYS_OPT_PCI
 107
 108         __checkReturn   efx_rc_t
 109 efx_family_probe_bar(
 110         __in            uint16_t venid,
 111         __in            uint16_t devid,
 112         __in            efsys_pci_config_t *espcp,
 113         __out           efx_family_t *efp,
 114         __out           efx_bar_region_t *ebrp)
 115 {
 116         efx_rc_t rc;
 117         unsigned int membar;
 118
 119         if (venid == EFX_PCI_VENID_XILINX) {
 120                 switch (devid) {
 121 #if EFSYS_OPT_RIVERHEAD
 122                 case EFX_PCI_DEVID_RIVERHEAD:
 123                 case EFX_PCI_DEVID_RIVERHEAD_VF:
 124                         rc = rhead_pci_nic_membar_lookup(espcp, ebrp);
 125                         if (rc == 0)
 126                                 *efp = EFX_FAMILY_RIVERHEAD;
 127
 128                         return (rc);
 129 #endif /* EFSYS_OPT_RIVERHEAD */
 130                 default:
 131                         break;
 132                 }
 133         }
 134
 135         rc = efx_family(venid, devid, efp, &membar);
 136         if (rc == 0) {
 137                 ebrp->ebr_type = EFX_BAR_TYPE_MEM;
 138                 ebrp->ebr_index = membar;
 139                 ebrp->ebr_offset = 0;
 140                 ebrp->ebr_length = 0;
 141         }
 142
 143         return (rc);
 144 }
 145
 146 #endif /* EFSYS_OPT_PCI */
 147
 148 #if EFSYS_OPT_SIENA
 149
 150 static const efx_nic_ops_t      __efx_nic_siena_ops = {
 151         siena_nic_probe,                /* eno_probe */
 152         NULL,                           /* eno_board_cfg */
 153         NULL,                           /* eno_set_drv_limits */
 154         siena_nic_reset,                /* eno_reset */
 155         siena_nic_init,                 /* eno_init */
 156         NULL,                           /* eno_get_vi_pool */
 157         NULL,                           /* eno_get_bar_region */
 158         NULL,                           /* eno_hw_unavailable */
 159         NULL,                           /* eno_set_hw_unavailable */
 160 #if EFSYS_OPT_DIAG
 161         siena_nic_register_test,        /* eno_register_test */
 162 #endif  /* EFSYS_OPT_DIAG */
 163         siena_nic_fini,                 /* eno_fini */
 164         siena_nic_unprobe,              /* eno_unprobe */
 165 };
 166
 167 #endif  /* EFSYS_OPT_SIENA */
 168
 169 #if EFSYS_OPT_HUNTINGTON
 170
 171 static const efx_nic_ops_t      __efx_nic_hunt_ops = {
 172         ef10_nic_probe,                 /* eno_probe */
 173         hunt_board_cfg,                 /* eno_board_cfg */
 174         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 175         ef10_nic_reset,                 /* eno_reset */
 176         ef10_nic_init,                  /* eno_init */
 177         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 178         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 179         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 180         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 181 #if EFSYS_OPT_DIAG
 182         ef10_nic_register_test,         /* eno_register_test */
 183 #endif  /* EFSYS_OPT_DIAG */
 184         ef10_nic_fini,                  /* eno_fini */
 185         ef10_nic_unprobe,               /* eno_unprobe */
 186 };
 187
 188 #endif  /* EFSYS_OPT_HUNTINGTON */
 189
 190 #if EFSYS_OPT_MEDFORD
 191
 192 static const efx_nic_ops_t      __efx_nic_medford_ops = {
 193         ef10_nic_probe,                 /* eno_probe */
 194         medford_board_cfg,              /* eno_board_cfg */
 195         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 196         ef10_nic_reset,                 /* eno_reset */
 197         ef10_nic_init,                  /* eno_init */
 198         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 199         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 200         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 201         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 202 #if EFSYS_OPT_DIAG
 203         ef10_nic_register_test,         /* eno_register_test */
 204 #endif  /* EFSYS_OPT_DIAG */
 205         ef10_nic_fini,                  /* eno_fini */
 206         ef10_nic_unprobe,               /* eno_unprobe */
 207 };
 208
 209 #endif  /* EFSYS_OPT_MEDFORD */
 210
 211 #if EFSYS_OPT_MEDFORD2
 212
 213 static const efx_nic_ops_t      __efx_nic_medford2_ops = {
 214         ef10_nic_probe,                 /* eno_probe */
 215         medford2_board_cfg,             /* eno_board_cfg */
 216         ef10_nic_set_drv_limits,        /* eno_set_drv_limits */
 217         ef10_nic_reset,                 /* eno_reset */
 218         ef10_nic_init,                  /* eno_init */
 219         ef10_nic_get_vi_pool,           /* eno_get_vi_pool */
 220         ef10_nic_get_bar_region,        /* eno_get_bar_region */
 221         ef10_nic_hw_unavailable,        /* eno_hw_unavailable */
 222         ef10_nic_set_hw_unavailable,    /* eno_set_hw_unavailable */
 223 #if EFSYS_OPT_DIAG
 224         ef10_nic_register_test,         /* eno_register_test */
 225 #endif  /* EFSYS_OPT_DIAG */
 226         ef10_nic_fini,                  /* eno_fini */
 227         ef10_nic_unprobe,               /* eno_unprobe */
 228 };
 229
 230 #endif  /* EFSYS_OPT_MEDFORD2 */
 231
 232 #if EFSYS_OPT_RIVERHEAD
 233
 234 static const efx_nic_ops_t      __efx_nic_riverhead_ops = {
 235         rhead_nic_probe,                /* eno_probe */
 236         rhead_board_cfg,                /* eno_board_cfg */
 237         rhead_nic_set_drv_limits,       /* eno_set_drv_limits */
 238         rhead_nic_reset,                /* eno_reset */
 239         rhead_nic_init,                 /* eno_init */
 240         rhead_nic_get_vi_pool,          /* eno_get_vi_pool */
 241         rhead_nic_get_bar_region,       /* eno_get_bar_region */
 242         rhead_nic_hw_unavailable,       /* eno_hw_unavailable */
 243         rhead_nic_set_hw_unavailable,   /* eno_set_hw_unavailable */
 244 #if EFSYS_OPT_DIAG
 245         rhead_nic_register_test,        /* eno_register_test */
 246 #endif  /* EFSYS_OPT_DIAG */
 247         rhead_nic_fini,                 /* eno_fini */
 248         rhead_nic_unprobe,              /* eno_unprobe */
 249 };
 250
 251 #endif  /* EFSYS_OPT_RIVERHEAD */
 252
 253
 254         __checkReturn   efx_rc_t
 255 efx_nic_create(
 256         __in            efx_family_t family,
 257         __in            efsys_identifier_t *esip,
 258         __in            efsys_bar_t *esbp,
 259         __in            uint32_t fcw_offset,
 260         __in            efsys_lock_t *eslp,
 261         __deref_out     efx_nic_t **enpp)
 262 {
 263         efx_nic_t *enp;
 264         efx_rc_t rc;
 265
 266         EFSYS_ASSERT3U(family, >, EFX_FAMILY_INVALID);
 267         EFSYS_ASSERT3U(family, <, EFX_FAMILY_NTYPES);
 268
 269         /* Allocate a NIC object */
 270         EFSYS_KMEM_ALLOC(esip, sizeof (efx_nic_t), enp);
 271
 272         if (enp == NULL) {
 273                 rc = ENOMEM;
 274                 goto fail1;
 275         }
 276
 277         enp->en_magic = EFX_NIC_MAGIC;
 278
 279         switch (family) {
 280 #if EFSYS_OPT_SIENA
 281         case EFX_FAMILY_SIENA:
 282                 enp->en_enop = &__efx_nic_siena_ops;
 283                 enp->en_features =
 284                     EFX_FEATURE_IPV6 |
 285                     EFX_FEATURE_LFSR_HASH_INSERT |
 286                     EFX_FEATURE_LINK_EVENTS |
 287                     EFX_FEATURE_PERIODIC_MAC_STATS |
 288                     EFX_FEATURE_MCDI |
 289                     EFX_FEATURE_LOOKAHEAD_SPLIT |
 290                     EFX_FEATURE_MAC_HEADER_FILTERS |
 291                     EFX_FEATURE_TX_SRC_FILTERS;
 292                 break;
 293 #endif  /* EFSYS_OPT_SIENA */
 294
 295 #if EFSYS_OPT_HUNTINGTON
 296         case EFX_FAMILY_HUNTINGTON:
 297                 enp->en_enop = &__efx_nic_hunt_ops;
 298                 enp->en_features =
 299                     EFX_FEATURE_IPV6 |
 300                     EFX_FEATURE_LINK_EVENTS |
 301                     EFX_FEATURE_PERIODIC_MAC_STATS |
 302                     EFX_FEATURE_MCDI |
 303                     EFX_FEATURE_MAC_HEADER_FILTERS |
 304                     EFX_FEATURE_MCDI_DMA |
 305                     EFX_FEATURE_PIO_BUFFERS |
 306                     EFX_FEATURE_FW_ASSISTED_TSO |
 307                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 308                     EFX_FEATURE_PACKED_STREAM |
 309                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 310                 break;
 311 #endif  /* EFSYS_OPT_HUNTINGTON */
 312
 313 #if EFSYS_OPT_MEDFORD
 314         case EFX_FAMILY_MEDFORD:
 315                 enp->en_enop = &__efx_nic_medford_ops;
 316                 /*
 317                  * FW_ASSISTED_TSO omitted as Medford only supports firmware
 318                  * assisted TSO version 2, not the v1 scheme used on Huntington.
 319                  */
 320                 enp->en_features =
 321                     EFX_FEATURE_IPV6 |
 322                     EFX_FEATURE_LINK_EVENTS |
 323                     EFX_FEATURE_PERIODIC_MAC_STATS |
 324                     EFX_FEATURE_MCDI |
 325                     EFX_FEATURE_MAC_HEADER_FILTERS |
 326                     EFX_FEATURE_MCDI_DMA |
 327                     EFX_FEATURE_PIO_BUFFERS |
 328                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 329                     EFX_FEATURE_PACKED_STREAM |
 330                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 331                 break;
 332 #endif  /* EFSYS_OPT_MEDFORD */
 333
 334 #if EFSYS_OPT_MEDFORD2
 335         case EFX_FAMILY_MEDFORD2:
 336                 enp->en_enop = &__efx_nic_medford2_ops;
 337                 enp->en_features =
 338                     EFX_FEATURE_IPV6 |
 339                     EFX_FEATURE_LINK_EVENTS |
 340                     EFX_FEATURE_PERIODIC_MAC_STATS |
 341                     EFX_FEATURE_MCDI |
 342                     EFX_FEATURE_MAC_HEADER_FILTERS |
 343                     EFX_FEATURE_MCDI_DMA |
 344                     EFX_FEATURE_PIO_BUFFERS |
 345                     EFX_FEATURE_FW_ASSISTED_TSO_V2 |
 346                     EFX_FEATURE_PACKED_STREAM |
 347                     EFX_FEATURE_TXQ_CKSUM_OP_DESC;
 348                 break;
 349 #endif  /* EFSYS_OPT_MEDFORD2 */
 350
 351 #if EFSYS_OPT_RIVERHEAD
 352         case EFX_FAMILY_RIVERHEAD:
 353                 enp->en_enop = &__efx_nic_riverhead_ops;
 354                 enp->en_features =
 355                     EFX_FEATURE_IPV6 |
 356                     EFX_FEATURE_LINK_EVENTS |
 357                     EFX_FEATURE_PERIODIC_MAC_STATS |
 358                     EFX_FEATURE_MCDI |
 359                     EFX_FEATURE_MAC_HEADER_FILTERS |
 360                     EFX_FEATURE_MCDI_DMA;
 361                 enp->en_arch.ef10.ena_fcw_base = fcw_offset;
 362                 break;
 363 #endif  /* EFSYS_OPT_RIVERHEAD */
 364
 365         default:
 366                 rc = ENOTSUP;
 367                 goto fail2;
 368         }
 369
 370         if ((family != EFX_FAMILY_RIVERHEAD) && (fcw_offset != 0)) {
 371                 rc = EINVAL;
 372                 goto fail3;
 373         }
 374
 375         enp->en_family = family;
 376         enp->en_esip = esip;
 377         enp->en_esbp = esbp;
 378         enp->en_eslp = eslp;
 379
 380         *enpp = enp;
 381
 382         return (0);
 383
 384 fail3:
 385         EFSYS_PROBE(fail3);
 386 fail2:
 387         EFSYS_PROBE(fail2);
 388
 389         enp->en_magic = 0;
 390
 391         /* Free the NIC object */
 392         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 393
 394 fail1:
 395         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 396
 397         return (rc);
 398 }
 399
 400         __checkReturn   efx_rc_t
 401 efx_nic_probe(
 402         __in            efx_nic_t *enp,
 403         __in            efx_fw_variant_t efv)
 404 {
 405         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 406         const efx_nic_ops_t *enop;
 407         efx_rc_t rc;
 408
 409         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 410 #if EFSYS_OPT_MCDI
 411         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 412 #endif  /* EFSYS_OPT_MCDI */
 413         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 414
 415         /* Ensure FW variant codes match with MC_CMD_FW codes */
 416         EFX_STATIC_ASSERT(EFX_FW_VARIANT_FULL_FEATURED ==
 417             MC_CMD_FW_FULL_FEATURED);
 418         EFX_STATIC_ASSERT(EFX_FW_VARIANT_LOW_LATENCY ==
 419             MC_CMD_FW_LOW_LATENCY);
 420         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM ==
 421             MC_CMD_FW_PACKED_STREAM);
 422         EFX_STATIC_ASSERT(EFX_FW_VARIANT_HIGH_TX_RATE ==
 423             MC_CMD_FW_HIGH_TX_RATE);
 424         EFX_STATIC_ASSERT(EFX_FW_VARIANT_PACKED_STREAM_HASH_MODE_1 ==
 425             MC_CMD_FW_PACKED_STREAM_HASH_MODE_1);
 426         EFX_STATIC_ASSERT(EFX_FW_VARIANT_RULES_ENGINE ==
 427             MC_CMD_FW_RULES_ENGINE);
 428         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DPDK ==
 429             MC_CMD_FW_DPDK);
 430         EFX_STATIC_ASSERT(EFX_FW_VARIANT_DONT_CARE ==
 431             (int)MC_CMD_FW_DONT_CARE);
 432
 433         enop = enp->en_enop;
 434         enp->efv = efv;
 435
 436         if ((rc = enop->eno_probe(enp)) != 0)
 437                 goto fail1;
 438
 439         encp->enc_features = enp->en_features;
 440
 441         if ((rc = efx_phy_probe(enp)) != 0)
 442                 goto fail2;
 443
 444         enp->en_mod_flags |= EFX_MOD_PROBE;
 445
 446         return (0);
 447
 448 fail2:
 449         EFSYS_PROBE(fail2);
 450
 451         enop->eno_unprobe(enp);
 452
 453 fail1:
 454         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 455
 456         return (rc);
 457 }
 458
 459         __checkReturn   efx_rc_t
 460 efx_nic_set_drv_limits(
 461         __inout         efx_nic_t *enp,
 462         __in            efx_drv_limits_t *edlp)
 463 {
 464         const efx_nic_ops_t *enop = enp->en_enop;
 465         efx_rc_t rc;
 466
 467         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 468         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 469
 470         if (enop->eno_set_drv_limits != NULL) {
 471                 if ((rc = enop->eno_set_drv_limits(enp, edlp)) != 0)
 472                         goto fail1;
 473         }
 474
 475         return (0);
 476
 477 fail1:
 478         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 479
 480         return (rc);
 481 }
 482
 483         __checkReturn   efx_rc_t
 484 efx_nic_set_drv_version(
 485         __inout                 efx_nic_t *enp,
 486         __in_ecount(length)     char const *verp,
 487         __in                    size_t length)
 488 {
 489         efx_rc_t rc;
 490
 491         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 492         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_PROBE));
 493
 494         /*
 495          * length is the string content length in bytes.
 496          * Accept any content which fits into the version
 497          * buffer, excluding the last byte. This is reserved
 498          * for an appended NUL terminator.
 499          */
 500         if (length >= sizeof (enp->en_drv_version)) {
 501                 rc = E2BIG;
 502                 goto fail1;
 503         }
 504
 505         (void) memset(enp->en_drv_version, 0,
 506             sizeof (enp->en_drv_version));
 507         memcpy(enp->en_drv_version, verp, length);
 508
 509         return (0);
 510
 511 fail1:
 512         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 513
 514         return (rc);
 515 }
 516
 517
 518         __checkReturn   efx_rc_t
 519 efx_nic_get_bar_region(
 520         __in            efx_nic_t *enp,
 521         __in            efx_nic_region_t region,
 522         __out           uint32_t *offsetp,
 523         __out           size_t *sizep)
 524 {
 525         const efx_nic_ops_t *enop = enp->en_enop;
 526         efx_rc_t rc;
 527
 528         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 529         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 530         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 531
 532         if (enop->eno_get_bar_region == NULL) {
 533                 rc = ENOTSUP;
 534                 goto fail1;
 535         }
 536         if ((rc = (enop->eno_get_bar_region)(enp,
 537                     region, offsetp, sizep)) != 0) {
 538                 goto fail2;
 539         }
 540
 541         return (0);
 542
 543 fail2:
 544         EFSYS_PROBE(fail2);
 545
 546 fail1:
 547         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 548
 549         return (rc);
 550 }
 551
 552
 553         __checkReturn   efx_rc_t
 554 efx_nic_get_vi_pool(
 555         __in            efx_nic_t *enp,
 556         __out           uint32_t *evq_countp,
 557         __out           uint32_t *rxq_countp,
 558         __out           uint32_t *txq_countp)
 559 {
 560         const efx_nic_ops_t *enop = enp->en_enop;
 561         efx_nic_cfg_t *encp = &enp->en_nic_cfg;
 562         efx_rc_t rc;
 563
 564         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 565         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 566         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_NIC);
 567
 568         if (enop->eno_get_vi_pool != NULL) {
 569                 uint32_t vi_count = 0;
 570
 571                 if ((rc = (enop->eno_get_vi_pool)(enp, &vi_count)) != 0)
 572                         goto fail1;
 573
 574                 *evq_countp = vi_count;
 575                 *rxq_countp = vi_count;
 576                 *txq_countp = vi_count;
 577         } else {
 578                 /* Use NIC limits as default value */
 579                 *evq_countp = encp->enc_evq_limit;
 580                 *rxq_countp = encp->enc_rxq_limit;
 581                 *txq_countp = encp->enc_txq_limit;
 582         }
 583
 584         return (0);
 585
 586 fail1:
 587         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 588
 589         return (rc);
 590 }
 591
 592
 593         __checkReturn   efx_rc_t
 594 efx_nic_init(
 595         __in            efx_nic_t *enp)
 596 {
 597         const efx_nic_ops_t *enop = enp->en_enop;
 598         efx_rc_t rc;
 599
 600         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 601         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 602
 603         if (enp->en_mod_flags & EFX_MOD_NIC) {
 604                 rc = EINVAL;
 605                 goto fail1;
 606         }
 607
 608         if ((rc = enop->eno_init(enp)) != 0)
 609                 goto fail2;
 610
 611         enp->en_mod_flags |= EFX_MOD_NIC;
 612
 613         return (0);
 614
 615 fail2:
 616         EFSYS_PROBE(fail2);
 617 fail1:
 618         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 619
 620         return (rc);
 621 }
 622
 623                         void
 624 efx_nic_fini(
 625         __in            efx_nic_t *enp)
 626 {
 627         const efx_nic_ops_t *enop = enp->en_enop;
 628
 629         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 630         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 631         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_NIC);
 632         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 633         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 634         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 635         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 636
 637         enop->eno_fini(enp);
 638
 639         enp->en_mod_flags &= ~EFX_MOD_NIC;
 640 }
 641
 642                         void
 643 efx_nic_unprobe(
 644         __in            efx_nic_t *enp)
 645 {
 646         const efx_nic_ops_t *enop = enp->en_enop;
 647
 648         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 649 #if EFSYS_OPT_MCDI
 650         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 651 #endif  /* EFSYS_OPT_MCDI */
 652         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 653         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 654         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_INTR));
 655         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_EV));
 656         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 657         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 658
 659         efx_phy_unprobe(enp);
 660
 661         enop->eno_unprobe(enp);
 662
 663         enp->en_mod_flags &= ~EFX_MOD_PROBE;
 664 }
 665
 666                         void
 667 efx_nic_destroy(
 668         __in    efx_nic_t *enp)
 669 {
 670         efsys_identifier_t *esip = enp->en_esip;
 671
 672         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 673         EFSYS_ASSERT3U(enp->en_mod_flags, ==, 0);
 674
 675         enp->en_family = EFX_FAMILY_INVALID;
 676         enp->en_esip = NULL;
 677         enp->en_esbp = NULL;
 678         enp->en_eslp = NULL;
 679
 680         enp->en_enop = NULL;
 681
 682         enp->en_magic = 0;
 683
 684         /* Free the NIC object */
 685         EFSYS_KMEM_FREE(esip, sizeof (efx_nic_t), enp);
 686 }
 687
 688         __checkReturn   efx_rc_t
 689 efx_nic_reset(
 690         __in            efx_nic_t *enp)
 691 {
 692         const efx_nic_ops_t *enop = enp->en_enop;
 693         unsigned int mod_flags;
 694         efx_rc_t rc;
 695
 696         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 697         EFSYS_ASSERT(enp->en_mod_flags & EFX_MOD_PROBE);
 698         /*
 699          * All modules except the MCDI, PROBE, NVRAM, VPD, MON, TUNNEL
 700          * (which we do not reset here) must have been shut down or never
 701          * initialized.
 702          *
 703          * A rule of thumb here is: If the controller or MC reboots, is *any*
 704          * state lost. If it's lost and needs reapplying, then the module
 705          * *must* not be initialised during the reset.
 706          */
 707         mod_flags = enp->en_mod_flags;
 708         mod_flags &= ~(EFX_MOD_MCDI | EFX_MOD_PROBE | EFX_MOD_NVRAM |
 709             EFX_MOD_VPD | EFX_MOD_MON);
 710 #if EFSYS_OPT_TUNNEL
 711         mod_flags &= ~EFX_MOD_TUNNEL;
 712 #endif /* EFSYS_OPT_TUNNEL */
 713         EFSYS_ASSERT3U(mod_flags, ==, 0);
 714         if (mod_flags != 0) {
 715                 rc = EINVAL;
 716                 goto fail1;
 717         }
 718
 719         if ((rc = enop->eno_reset(enp)) != 0)
 720                 goto fail2;
 721
 722         return (0);
 723
 724 fail2:
 725         EFSYS_PROBE(fail2);
 726 fail1:
 727         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 728
 729         return (rc);
 730 }
 731
 732                         const efx_nic_cfg_t *
 733 efx_nic_cfg_get(
 734         __in            const efx_nic_t *enp)
 735 {
 736         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 737         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 738
 739         return (&(enp->en_nic_cfg));
 740 }
 741
 742         __checkReturn           efx_rc_t
 743 efx_nic_get_fw_version(
 744         __in                    efx_nic_t *enp,
 745         __out                   efx_nic_fw_info_t *enfip)
 746 {
 747         uint16_t mc_fw_version[4];
 748         efx_rc_t rc;
 749
 750         if (enfip == NULL) {
 751                 rc = EINVAL;
 752                 goto fail1;
 753         }
 754
 755         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_MCDI);
 756         EFSYS_ASSERT3U(enp->en_features, &, EFX_FEATURE_MCDI);
 757
 758         /* Ensure RXDP_FW_ID codes match with MC_CMD_GET_CAPABILITIES codes */
 759         EFX_STATIC_ASSERT(EFX_RXDP_FULL_FEATURED_FW_ID ==
 760             MC_CMD_GET_CAPABILITIES_OUT_RXDP);
 761         EFX_STATIC_ASSERT(EFX_RXDP_LOW_LATENCY_FW_ID ==
 762             MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY);
 763         EFX_STATIC_ASSERT(EFX_RXDP_PACKED_STREAM_FW_ID ==
 764             MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM);
 765         EFX_STATIC_ASSERT(EFX_RXDP_RULES_ENGINE_FW_ID ==
 766             MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE);
 767         EFX_STATIC_ASSERT(EFX_RXDP_DPDK_FW_ID ==
 768             MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK);
 769
 770         rc = efx_mcdi_version(enp, mc_fw_version, NULL, NULL);
 771         if (rc != 0)
 772                 goto fail2;
 773
 774         rc = efx_mcdi_get_capabilities(enp, NULL,
 775             &enfip->enfi_rx_dpcpu_fw_id,
 776             &enfip->enfi_tx_dpcpu_fw_id,
 777             NULL, NULL);
 778         if (rc == 0) {
 779                 enfip->enfi_dpcpu_fw_ids_valid = B_TRUE;
 780         } else if (rc == ENOTSUP) {
 781                 enfip->enfi_dpcpu_fw_ids_valid = B_FALSE;
 782                 enfip->enfi_rx_dpcpu_fw_id = 0;
 783                 enfip->enfi_tx_dpcpu_fw_id = 0;
 784         } else {
 785                 goto fail3;
 786         }
 787
 788         memcpy(enfip->enfi_mc_fw_version, mc_fw_version,
 789             sizeof (mc_fw_version));
 790
 791         return (0);
 792
 793 fail3:
 794         EFSYS_PROBE(fail3);
 795 fail2:
 796         EFSYS_PROBE(fail2);
 797 fail1:
 798         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 799
 800         return (rc);
 801 }
 802
 803         __checkReturn   boolean_t
 804 efx_nic_hw_unavailable(
 805         __in            efx_nic_t *enp)
 806 {
 807         const efx_nic_ops_t *enop = enp->en_enop;
 808
 809         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 810         /* NOTE: can be used by MCDI before NIC probe */
 811
 812         if (enop->eno_hw_unavailable != NULL) {
 813                 if ((enop->eno_hw_unavailable)(enp) != B_FALSE)
 814                         goto unavail;
 815         }
 816
 817         return (B_FALSE);
 818
 819 unavail:
 820         return (B_TRUE);
 821 }
 822
 823                         void
 824 efx_nic_set_hw_unavailable(
 825         __in            efx_nic_t *enp)
 826 {
 827         const efx_nic_ops_t *enop = enp->en_enop;
 828
 829         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 830
 831         if (enop->eno_set_hw_unavailable != NULL)
 832                 enop->eno_set_hw_unavailable(enp);
 833 }
 834
 835
 836 #if EFSYS_OPT_DIAG
 837
 838         __checkReturn   efx_rc_t
 839 efx_nic_register_test(
 840         __in            efx_nic_t *enp)
 841 {
 842         const efx_nic_ops_t *enop = enp->en_enop;
 843         efx_rc_t rc;
 844
 845         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 846         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_PROBE);
 847         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_NIC));
 848
 849         if ((rc = enop->eno_register_test(enp)) != 0)
 850                 goto fail1;
 851
 852         return (0);
 853
 854 fail1:
 855         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 856
 857         return (rc);
 858 }
 859
 860 #endif  /* EFSYS_OPT_DIAG */
 861
 862 #if EFSYS_OPT_LOOPBACK
 863
 864 extern                  void
 865 efx_loopback_mask(
 866         __in    efx_loopback_kind_t loopback_kind,
 867         __out   efx_qword_t *maskp)
 868 {
 869         efx_qword_t mask;
 870
 871         EFSYS_ASSERT3U(loopback_kind, <, EFX_LOOPBACK_NKINDS);
 872         EFSYS_ASSERT(maskp != NULL);
 873
 874         /* Assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree */
 875 #define LOOPBACK_CHECK(_mcdi, _efx) \
 876         EFX_STATIC_ASSERT(MC_CMD_LOOPBACK_##_mcdi == EFX_LOOPBACK_##_efx)
 877
 878         LOOPBACK_CHECK(NONE, OFF);
 879         LOOPBACK_CHECK(DATA, DATA);
 880         LOOPBACK_CHECK(GMAC, GMAC);
 881         LOOPBACK_CHECK(XGMII, XGMII);
 882         LOOPBACK_CHECK(XGXS, XGXS);
 883         LOOPBACK_CHECK(XAUI, XAUI);
 884         LOOPBACK_CHECK(GMII, GMII);
 885         LOOPBACK_CHECK(SGMII, SGMII);
 886         LOOPBACK_CHECK(XGBR, XGBR);
 887         LOOPBACK_CHECK(XFI, XFI);
 888         LOOPBACK_CHECK(XAUI_FAR, XAUI_FAR);
 889         LOOPBACK_CHECK(GMII_FAR, GMII_FAR);
 890         LOOPBACK_CHECK(SGMII_FAR, SGMII_FAR);
 891         LOOPBACK_CHECK(XFI_FAR, XFI_FAR);
 892         LOOPBACK_CHECK(GPHY, GPHY);
 893         LOOPBACK_CHECK(PHYXS, PHY_XS);
 894         LOOPBACK_CHECK(PCS, PCS);
 895         LOOPBACK_CHECK(PMAPMD, PMA_PMD);
 896         LOOPBACK_CHECK(XPORT, XPORT);
 897         LOOPBACK_CHECK(XGMII_WS, XGMII_WS);
 898         LOOPBACK_CHECK(XAUI_WS, XAUI_WS);
 899         LOOPBACK_CHECK(XAUI_WS_FAR, XAUI_WS_FAR);
 900         LOOPBACK_CHECK(XAUI_WS_NEAR, XAUI_WS_NEAR);
 901         LOOPBACK_CHECK(GMII_WS, GMII_WS);
 902         LOOPBACK_CHECK(XFI_WS, XFI_WS);
 903         LOOPBACK_CHECK(XFI_WS_FAR, XFI_WS_FAR);
 904         LOOPBACK_CHECK(PHYXS_WS, PHYXS_WS);
 905         LOOPBACK_CHECK(PMA_INT, PMA_INT);
 906         LOOPBACK_CHECK(SD_NEAR, SD_NEAR);
 907         LOOPBACK_CHECK(SD_FAR, SD_FAR);
 908         LOOPBACK_CHECK(PMA_INT_WS, PMA_INT_WS);
 909         LOOPBACK_CHECK(SD_FEP2_WS, SD_FEP2_WS);
 910         LOOPBACK_CHECK(SD_FEP1_5_WS, SD_FEP1_5_WS);
 911         LOOPBACK_CHECK(SD_FEP_WS, SD_FEP_WS);
 912         LOOPBACK_CHECK(SD_FES_WS, SD_FES_WS);
 913         LOOPBACK_CHECK(AOE_INT_NEAR, AOE_INT_NEAR);
 914         LOOPBACK_CHECK(DATA_WS, DATA_WS);
 915         LOOPBACK_CHECK(FORCE_EXT_LINK, FORCE_EXT_LINK);
 916 #undef LOOPBACK_CHECK
 917
 918         /* Build bitmask of possible loopback types */
 919         EFX_ZERO_QWORD(mask);
 920
 921         if ((loopback_kind == EFX_LOOPBACK_KIND_OFF) ||
 922             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 923                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_OFF);
 924         }
 925
 926         if ((loopback_kind == EFX_LOOPBACK_KIND_MAC) ||
 927             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 928                 /*
 929                  * The "MAC" grouping has historically been used by drivers to
 930                  * mean loopbacks supported by on-chip hardware. Keep that
 931                  * meaning here, and include on-chip PHY layer loopbacks.
 932                  */
 933                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_DATA);
 934                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMAC);
 935                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGMII);
 936                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGXS);
 937                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI);
 938                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII);
 939                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII);
 940                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XGBR);
 941                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI);
 942                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XAUI_FAR);
 943                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GMII_FAR);
 944                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SGMII_FAR);
 945                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_XFI_FAR);
 946                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_INT);
 947                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_NEAR);
 948                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_SD_FAR);
 949         }
 950
 951         if ((loopback_kind == EFX_LOOPBACK_KIND_PHY) ||
 952             (loopback_kind == EFX_LOOPBACK_KIND_ALL)) {
 953                 /*
 954                  * The "PHY" grouping has historically been used by drivers to
 955                  * mean loopbacks supported by off-chip hardware. Keep that
 956                  * meaning here.
 957                  */
 958                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_GPHY);
 959                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PHY_XS);
 960                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PCS);
 961                 EFX_SET_QWORD_BIT(mask, EFX_LOOPBACK_PMA_PMD);
 962         }
 963
 964         *maskp = mask;
 965 }
 966
 967         __checkReturn   efx_rc_t
 968 efx_mcdi_get_loopback_modes(
 969         __in            efx_nic_t *enp)
 970 {
 971         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 972         efx_mcdi_req_t req;
 973         EFX_MCDI_DECLARE_BUF(payload, MC_CMD_GET_LOOPBACK_MODES_IN_LEN,
 974                 MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN);
 975         efx_qword_t mask;
 976         efx_qword_t modes;
 977         efx_rc_t rc;
 978
 979         req.emr_cmd = MC_CMD_GET_LOOPBACK_MODES;
 980         req.emr_in_buf = payload;
 981         req.emr_in_length = MC_CMD_GET_LOOPBACK_MODES_IN_LEN;
 982         req.emr_out_buf = payload;
 983         req.emr_out_length = MC_CMD_GET_LOOPBACK_MODES_OUT_V2_LEN;
 984
 985         efx_mcdi_execute(enp, &req);
 986
 987         if (req.emr_rc != 0) {
 988                 rc = req.emr_rc;
 989                 goto fail1;
 990         }
 991
 992         if (req.emr_out_length_used <
 993             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST +
 994             MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN) {
 995                 rc = EMSGSIZE;
 996                 goto fail2;
 997         }
 998
 999         /*
1000          * We assert the MC_CMD_LOOPBACK and EFX_LOOPBACK namespaces agree
1001          * in efx_loopback_mask() and in siena_phy.c:siena_phy_get_link().
1002          */
1003         efx_loopback_mask(EFX_LOOPBACK_KIND_ALL, &mask);
1004
1005         EFX_AND_QWORD(mask,
1006             *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_SUGGESTED));
1007
1008         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_100M);
1009         EFX_AND_QWORD(modes, mask);
1010         encp->enc_loopback_types[EFX_LINK_100FDX] = modes;
1011
1012         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_1G);
1013         EFX_AND_QWORD(modes, mask);
1014         encp->enc_loopback_types[EFX_LINK_1000FDX] = modes;
1015
1016         modes = *MCDI_OUT2(req, efx_qword_t, GET_LOOPBACK_MODES_OUT_10G);
1017         EFX_AND_QWORD(modes, mask);
1018         encp->enc_loopback_types[EFX_LINK_10000FDX] = modes;
1019
1020         if (req.emr_out_length_used >=
1021             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST +
1022             MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN) {
1023                 /* Response includes 40G loopback modes */
1024                 modes = *MCDI_OUT2(req, efx_qword_t,
1025                     GET_LOOPBACK_MODES_OUT_40G);
1026                 EFX_AND_QWORD(modes, mask);
1027                 encp->enc_loopback_types[EFX_LINK_40000FDX] = modes;
1028         }
1029
1030         if (req.emr_out_length_used >=
1031             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_OFST +
1032             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LEN) {
1033                 /* Response includes 25G loopback modes */
1034                 modes = *MCDI_OUT2(req, efx_qword_t,
1035                     GET_LOOPBACK_MODES_OUT_V2_25G);
1036                 EFX_AND_QWORD(modes, mask);
1037                 encp->enc_loopback_types[EFX_LINK_25000FDX] = modes;
1038         }
1039
1040         if (req.emr_out_length_used >=
1041             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_OFST +
1042             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LEN) {
1043                 /* Response includes 50G loopback modes */
1044                 modes = *MCDI_OUT2(req, efx_qword_t,
1045                     GET_LOOPBACK_MODES_OUT_V2_50G);
1046                 EFX_AND_QWORD(modes, mask);
1047                 encp->enc_loopback_types[EFX_LINK_50000FDX] = modes;
1048         }
1049
1050         if (req.emr_out_length_used >=
1051             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_OFST +
1052             MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LEN) {
1053                 /* Response includes 100G loopback modes */
1054                 modes = *MCDI_OUT2(req, efx_qword_t,
1055                     GET_LOOPBACK_MODES_OUT_V2_100G);
1056                 EFX_AND_QWORD(modes, mask);
1057                 encp->enc_loopback_types[EFX_LINK_100000FDX] = modes;
1058         }
1059
1060         EFX_ZERO_QWORD(modes);
1061         EFX_SET_QWORD_BIT(modes, EFX_LOOPBACK_OFF);
1062         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100FDX]);
1063         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_1000FDX]);
1064         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_10000FDX]);
1065         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_40000FDX]);
1066         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_25000FDX]);
1067         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_50000FDX]);
1068         EFX_OR_QWORD(modes, encp->enc_loopback_types[EFX_LINK_100000FDX]);
1069         encp->enc_loopback_types[EFX_LINK_UNKNOWN] = modes;
1070
1071         return (0);
1072
1073 fail2:
1074         EFSYS_PROBE(fail2);
1075 fail1:
1076         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1077
1078         return (rc);
1079 }
1080
1081 #endif /* EFSYS_OPT_LOOPBACK */
1082
1083         __checkReturn   efx_rc_t
1084 efx_nic_calculate_pcie_link_bandwidth(
1085         __in            uint32_t pcie_link_width,
1086         __in            uint32_t pcie_link_gen,
1087         __out           uint32_t *bandwidth_mbpsp)
1088 {
1089         uint32_t lane_bandwidth;
1090         uint32_t total_bandwidth;
1091         efx_rc_t rc;
1092
1093         if ((pcie_link_width == 0) || (pcie_link_width > 16) ||
1094             !ISP2(pcie_link_width)) {
1095                 rc = EINVAL;
1096                 goto fail1;
1097         }
1098
1099         switch (pcie_link_gen) {
1100         case EFX_PCIE_LINK_SPEED_GEN1:
1101                 /* 2.5 Gb/s raw bandwidth with 8b/10b encoding */
1102                 lane_bandwidth = 2000;
1103                 break;
1104         case EFX_PCIE_LINK_SPEED_GEN2:
1105                 /* 5.0 Gb/s raw bandwidth with 8b/10b encoding */
1106                 lane_bandwidth = 4000;
1107                 break;
1108         case EFX_PCIE_LINK_SPEED_GEN3:
1109                 /* 8.0 Gb/s raw bandwidth with 128b/130b encoding */
1110                 lane_bandwidth = 7877;
1111                 break;
1112         default:
1113                 rc = EINVAL;
1114                 goto fail2;
1115         }
1116
1117         total_bandwidth = lane_bandwidth * pcie_link_width;
1118         *bandwidth_mbpsp = total_bandwidth;
1119
1120         return (0);
1121
1122 fail2:
1123         EFSYS_PROBE(fail2);
1124 fail1:
1125         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1126
1127         return (rc);
1128 }
1129
1130 #if EFSYS_OPT_FW_SUBVARIANT_AWARE
1131
1132         __checkReturn   efx_rc_t
1133 efx_nic_get_fw_subvariant(
1134         __in            efx_nic_t *enp,
1135         __out           efx_nic_fw_subvariant_t *subvariantp)
1136 {
1137         efx_rc_t rc;
1138         uint32_t value;
1139
1140         rc = efx_mcdi_get_nic_global(enp,
1141             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, &value);
1142         if (rc != 0)
1143                 goto fail1;
1144
1145         /* Mapping is not required since values match MCDI */
1146         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_DEFAULT ==
1147             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT);
1148         EFX_STATIC_ASSERT(EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM ==
1149             MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM);
1150
1151         switch (value) {
1152         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_DEFAULT:
1153         case MC_CMD_SET_NIC_GLOBAL_IN_FW_SUBVARIANT_NO_TX_CSUM:
1154                 *subvariantp = value;
1155                 break;
1156         default:
1157                 rc = EINVAL;
1158                 goto fail2;
1159         }
1160
1161         return (0);
1162
1163 fail2:
1164         EFSYS_PROBE(fail2);
1165
1166 fail1:
1167         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1168
1169         return (rc);
1170 }
1171
1172         __checkReturn   efx_rc_t
1173 efx_nic_set_fw_subvariant(
1174         __in            efx_nic_t *enp,
1175         __in            efx_nic_fw_subvariant_t subvariant)
1176 {
1177         efx_rc_t rc;
1178
1179         switch (subvariant) {
1180         case EFX_NIC_FW_SUBVARIANT_DEFAULT:
1181         case EFX_NIC_FW_SUBVARIANT_NO_TX_CSUM:
1182                 /* Mapping is not required since values match MCDI */
1183                 break;
1184         default:
1185                 rc = EINVAL;
1186                 goto fail1;
1187         }
1188
1189         rc = efx_mcdi_set_nic_global(enp,
1190             MC_CMD_SET_NIC_GLOBAL_IN_FIRMWARE_SUBVARIANT, subvariant);
1191         if (rc != 0)
1192                 goto fail2;
1193
1194         return (0);
1195
1196 fail2:
1197         EFSYS_PROBE(fail2);
1198
1199 fail1:
1200         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1201
1202         return (rc);
1203 }
1204
1205 #endif  /* EFSYS_OPT_FW_SUBVARIANT_AWARE */
1206
1207         __checkReturn   efx_rc_t
1208 efx_nic_check_pcie_link_speed(
1209         __in            efx_nic_t *enp,
1210         __in            uint32_t pcie_link_width,
1211         __in            uint32_t pcie_link_gen,
1212         __out           efx_pcie_link_performance_t *resultp)
1213 {
1214         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1215         uint32_t bandwidth;
1216         efx_pcie_link_performance_t result;
1217         efx_rc_t rc;
1218
1219         if ((encp->enc_required_pcie_bandwidth_mbps == 0) ||
1220             (pcie_link_width == 0) || (pcie_link_width == 32) ||
1221             (pcie_link_gen == 0)) {
1222                 /*
1223                  * No usable info on what is required and/or in use. In virtual
1224                  * machines, sometimes the PCIe link width is reported as 0 or
1225                  * 32, or the speed as 0.
1226                  */
1227                 result = EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH;
1228                 goto out;
1229         }
1230
1231         /* Calculate the available bandwidth in megabits per second */
1232         rc = efx_nic_calculate_pcie_link_bandwidth(pcie_link_width,
1233                                             pcie_link_gen, &bandwidth);
1234         if (rc != 0)
1235                 goto fail1;
1236
1237         if (bandwidth < encp->enc_required_pcie_bandwidth_mbps) {
1238                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH;
1239         } else if (pcie_link_gen < encp->enc_max_pcie_link_gen) {
1240                 /* The link provides enough bandwidth but not optimal latency */
1241                 result = EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY;
1242         } else {
1243                 result = EFX_PCIE_LINK_PERFORMANCE_OPTIMAL;
1244         }
1245
1246 out:
1247         *resultp = result;
1248
1249         return (0);
1250
1251 fail1:
1252         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1253
1254         return (rc);
1255 }