common/sfc_efx/base: add MAE init/fini APIs
[dpdk.git] / drivers / common / sfc_efx / version.map
1 INTERNAL {
2         global:
3
4         efx_crc32_calculate;
5
6         efx_ev_fini;
7         efx_ev_init;
8         efx_ev_qcreate;
9         efx_ev_qcreate_check_init_done;
10         efx_ev_qdestroy;
11         efx_ev_qmoderate;
12         efx_ev_qpending;
13         efx_ev_qpoll;
14         efx_ev_qpost;
15         efx_ev_qprime;
16         efx_ev_usecs_to_ticks;
17
18         efx_evb_fini;
19         efx_evb_init;
20         efx_evb_vport_mac_set;
21         efx_evb_vport_reset;
22         efx_evb_vport_stats;
23         efx_evb_vport_vlan_set;
24         efx_evb_vswitch_create;
25         efx_evb_vswitch_destroy;
26
27         efx_evq_nbufs;
28         efx_evq_size;
29
30         efx_family;
31         efx_family_probe_bar;
32
33         efx_filter_fini;
34         efx_filter_init;
35         efx_filter_insert;
36         efx_filter_remove;
37         efx_filter_restore;
38         efx_filter_spec_init_rx;
39         efx_filter_spec_init_tx;
40         efx_filter_spec_set_encap_type;
41         efx_filter_spec_set_eth_local;
42         efx_filter_spec_set_ether_type;
43         efx_filter_spec_set_geneve;
44         efx_filter_spec_set_ipv4_full;
45         efx_filter_spec_set_ipv4_local;
46         efx_filter_spec_set_mc_def;
47         efx_filter_spec_set_nvgre;
48         efx_filter_spec_set_rss_context;
49         efx_filter_spec_set_uc_def;
50         efx_filter_spec_set_vxlan;
51         efx_filter_supported_filters;
52
53         efx_hash_bytes;
54         efx_hash_dwords;
55
56         efx_intr_disable;
57         efx_intr_disable_unlocked;
58         efx_intr_enable;
59         efx_intr_fatal;
60         efx_intr_fini;
61         efx_intr_init;
62         efx_intr_status_line;
63         efx_intr_status_message;
64         efx_intr_trigger;
65
66         efx_loopback_mask;
67         efx_loopback_type_name;
68
69         efx_mac_addr_set;
70         efx_mac_drain;
71         efx_mac_fcntl_get;
72         efx_mac_fcntl_set;
73         efx_mac_filter_default_rxq_clear;
74         efx_mac_filter_default_rxq_set;
75         efx_mac_filter_get_all_ucast_mcast;
76         efx_mac_filter_set;
77         efx_mac_multicast_list_set;
78         efx_mac_pdu_get;
79         efx_mac_pdu_set;
80         efx_mac_stat_name;
81         efx_mac_stats_clear;
82         efx_mac_stats_get_mask;
83         efx_mac_stats_periodic;
84         efx_mac_stats_update;
85         efx_mac_stats_upload;
86         efx_mac_up;
87
88         efx_mae_fini;
89         efx_mae_init;
90
91         efx_mcdi_fini;
92         efx_mcdi_get_proxy_handle;
93         efx_mcdi_get_timeout;
94         efx_mcdi_init;
95         efx_mcdi_new_epoch;
96         efx_mcdi_reboot;
97         efx_mcdi_request_abort;
98         efx_mcdi_request_poll;
99         efx_mcdi_request_start;
100
101         efx_mon_fini;
102         efx_mon_init;
103         efx_mon_name;
104
105         efx_nic_calculate_pcie_link_bandwidth;
106         efx_nic_cfg_get;
107         efx_nic_check_pcie_link_speed;
108         efx_nic_create;
109         efx_nic_destroy;
110         efx_nic_fini;
111         efx_nic_get_bar_region;
112         efx_nic_get_fw_subvariant;
113         efx_nic_get_fw_version;
114         efx_nic_get_vi_pool;
115         efx_nic_hw_unavailable;
116         efx_nic_init;
117         efx_nic_probe;
118         efx_nic_reset;
119         efx_nic_set_drv_limits;
120         efx_nic_set_drv_version;
121         efx_nic_set_fw_subvariant;
122         efx_nic_set_hw_unavailable;
123         efx_nic_unprobe;
124
125         efx_phy_adv_cap_get;
126         efx_phy_adv_cap_set;
127         efx_phy_fec_type_get;
128         efx_phy_link_state_get;
129         efx_phy_lp_cap_get;
130         efx_phy_media_type_get;
131         efx_phy_module_get_info;
132         efx_phy_oui_get;
133         efx_phy_verify;
134
135         efx_port_fini;
136         efx_port_init;
137         efx_port_loopback_set;
138         efx_port_poll;
139
140         efx_pseudo_hdr_hash_get;
141         efx_pseudo_hdr_pkt_length_get;
142
143         efx_rx_fini;
144         efx_rx_hash_default_support_get;
145         efx_rx_init;
146         efx_rx_prefix_get_layout;
147         efx_rx_prefix_layout_check;
148         efx_rx_qcreate;
149         efx_rx_qcreate_es_super_buffer;
150         efx_rx_qdestroy;
151         efx_rx_qenable;
152         efx_rx_qflush;
153         efx_rx_qpost;
154         efx_rx_qpush;
155         efx_rx_scale_context_alloc;
156         efx_rx_scale_context_free;
157         efx_rx_scale_default_support_get;
158         efx_rx_scale_hash_flags_get;
159         efx_rx_scale_key_set;
160         efx_rx_scale_mode_set;
161         efx_rx_scale_tbl_set;
162         efx_rxq_nbufs;
163         efx_rxq_size;
164
165         efx_sram_buf_tbl_clear;
166         efx_sram_buf_tbl_set;
167
168         efx_tunnel_config_clear;
169         efx_tunnel_config_udp_add;
170         efx_tunnel_config_udp_remove;
171         efx_tunnel_fini;
172         efx_tunnel_init;
173         efx_tunnel_reconfigure;
174
175         efx_tx_fini;
176         efx_tx_init;
177         efx_tx_qcreate;
178         efx_tx_qdesc_checksum_create;
179         efx_tx_qdesc_dma_create;
180         efx_tx_qdesc_post;
181         efx_tx_qdesc_tso_create;
182         efx_tx_qdesc_tso2_create;
183         efx_tx_qdesc_vlantci_create;
184         efx_tx_qdestroy;
185         efx_tx_qenable;
186         efx_tx_qflush;
187         efx_tx_qpace;
188         efx_tx_qpio_disable;
189         efx_tx_qpio_enable;
190         efx_tx_qpio_post;
191         efx_tx_qpio_write;
192         efx_tx_qpost;
193         efx_tx_qpush;
194         efx_txq_nbufs;
195         efx_txq_size;
196
197         sfc_efx_mcdi_init;
198         sfc_efx_mcdi_fini;
199
200         local: *;
201 };