drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_bus_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_devx_cmds.h>
  17 #include <mlx5_common_os.h>
  18 #include <mlx5_common_devx.h>
  19 #include <mlx5_common_mr.h>
  20 #include <mlx5_prm.h>
  21
  22 #include "mlx5_compress_utils.h"
  23
  24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  25 #define MLX5_COMPRESS_MAX_QPS 1024
  26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  27
  28 struct mlx5_compress_xform {
  29         LIST_ENTRY(mlx5_compress_xform) next;
  30         enum rte_comp_xform_type type;
  31         enum rte_comp_checksum_type csum_type;
  32         uint32_t opcode;
  33         uint32_t gga_ctrl1; /* BE. */
  34 };
  35
  36 struct mlx5_compress_priv {
  37         TAILQ_ENTRY(mlx5_compress_priv) next;
  38         struct ibv_context *ctx; /* Device context. */
  39         struct rte_compressdev *cdev;
  40         void *uar;
  41         uint32_t pdn; /* Protection Domain number. */
  42         uint8_t min_block_size;
  43         uint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */
  44         /* Minimum huffman block size supported by the device. */
  45         struct ibv_pd *pd;
  46         struct rte_compressdev_config dev_config;
  47         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  48         rte_spinlock_t xform_sl;
  49         struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
  50         volatile uint64_t *uar_addr;
  51 #ifndef RTE_ARCH_64
  52         rte_spinlock_t uar32_sl;
  53 #endif /* RTE_ARCH_64 */
  54 };
  55
  56 struct mlx5_compress_qp {
  57         uint16_t qp_id;
  58         uint16_t entries_n;
  59         uint16_t pi;
  60         uint16_t ci;
  61         struct mlx5_mr_ctrl mr_ctrl;
  62         int socket_id;
  63         struct mlx5_devx_cq cq;
  64         struct mlx5_devx_sq sq;
  65         struct mlx5_pmd_mr opaque_mr;
  66         struct rte_comp_op **ops;
  67         struct mlx5_compress_priv *priv;
  68         struct rte_compressdev_stats stats;
  69 };
  70
  71 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  72                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  73 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  74
  75 int mlx5_compress_logtype;
  76
  77 static const struct rte_compressdev_capabilities mlx5_caps[] = {
  78         {
  79                 .algo = RTE_COMP_ALGO_NULL,
  80                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  81                                       RTE_COMP_FF_CRC32_CHECKSUM |
  82                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  83                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
  84         },
  85         {
  86                 .algo = RTE_COMP_ALGO_DEFLATE,
  87                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  88                                       RTE_COMP_FF_CRC32_CHECKSUM |
  89                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  90                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
  91                                       RTE_COMP_FF_HUFFMAN_FIXED |
  92                                       RTE_COMP_FF_HUFFMAN_DYNAMIC,
  93                 .window_size = {.min = 10, .max = 15, .increment = 1},
  94         },
  95         {
  96                 .algo = RTE_COMP_ALGO_LIST_END,
  97         }
  98 };
  99
 100 static void
 101 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
 102                            struct rte_compressdev_info *info)
 103 {
 104         RTE_SET_USED(dev);
 105         if (info != NULL) {
 106                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
 107                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 108                 info->capabilities = mlx5_caps;
 109         }
 110 }
 111
 112 static int
 113 mlx5_compress_dev_configure(struct rte_compressdev *dev,
 114                             struct rte_compressdev_config *config)
 115 {
 116         struct mlx5_compress_priv *priv;
 117
 118         if (dev == NULL || config == NULL)
 119                 return -EINVAL;
 120         priv = dev->data->dev_private;
 121         priv->dev_config = *config;
 122         return 0;
 123 }
 124
 125 static int
 126 mlx5_compress_dev_close(struct rte_compressdev *dev)
 127 {
 128         RTE_SET_USED(dev);
 129         return 0;
 130 }
 131
 132 static int
 133 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 134 {
 135         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 136
 137         if (qp->sq.sq != NULL)
 138                 mlx5_devx_sq_destroy(&qp->sq);
 139         if (qp->cq.cq != NULL)
 140                 mlx5_devx_cq_destroy(&qp->cq);
 141         if (qp->opaque_mr.obj != NULL) {
 142                 void *opaq = qp->opaque_mr.addr;
 143
 144                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 145                 if (opaq != NULL)
 146                         rte_free(opaq);
 147         }
 148         mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 149         rte_free(qp);
 150         dev->data->queue_pairs[qp_id] = NULL;
 151         return 0;
 152 }
 153
 154 static void
 155 mlx5_compress_init_sq(struct mlx5_compress_qp *qp)
 156 {
 157         volatile struct mlx5_gga_wqe *restrict wqe =
 158                                     (volatile struct mlx5_gga_wqe *)qp->sq.wqes;
 159         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 160         const uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);
 161         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 162                                         MLX5_COMP_MODE_OFFSET);
 163         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 164         int i;
 165
 166         /* All the next fields state should stay constant. */
 167         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 168                 wqe->sq_ds = sq_ds;
 169                 wqe->flags = flags;
 170                 wqe->opaque_lkey = opaq_lkey;
 171                 wqe->opaque_vaddr = rte_cpu_to_be_64
 172                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 173         }
 174 }
 175
 176 static int
 177 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 178                        uint32_t max_inflight_ops, int socket_id)
 179 {
 180         struct mlx5_compress_priv *priv = dev->data->dev_private;
 181         struct mlx5_compress_qp *qp;
 182         struct mlx5_devx_cq_attr cq_attr = {
 183                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
 184         };
 185         struct mlx5_devx_create_sq_attr sq_attr = {
 186                 .user_index = qp_id,
 187                 .wq_attr = (struct mlx5_devx_wq_attr){
 188                         .pd = priv->pdn,
 189                         .uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),
 190                 },
 191         };
 192         struct mlx5_devx_modify_sq_attr modify_attr = {
 193                 .state = MLX5_SQC_STATE_RDY,
 194         };
 195         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 196         uint32_t alloc_size = sizeof(*qp);
 197         void *opaq_buf;
 198         int ret;
 199
 200         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 201         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 202         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 203                                 socket_id);
 204         if (qp == NULL) {
 205                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 206                 rte_errno = ENOMEM;
 207                 return -rte_errno;
 208         }
 209         dev->data->queue_pairs[qp_id] = qp;
 210         opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,
 211                               sizeof(struct mlx5_gga_compress_opaque),
 212                               sizeof(struct mlx5_gga_compress_opaque));
 213         if (opaq_buf == NULL) {
 214                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 215                 rte_errno = ENOMEM;
 216                 goto err;
 217         }
 218         if (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,
 219                                priv->dev_config.socket_id)) {
 220                 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
 221                         (uint32_t)qp_id);
 222                 rte_errno = ENOMEM;
 223                 goto err;
 224         }
 225         qp->entries_n = 1 << log_ops_n;
 226         qp->socket_id = socket_id;
 227         qp->qp_id = qp_id;
 228         qp->priv = priv;
 229         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 230                                                    RTE_CACHE_LINE_SIZE);
 231         if (mlx5_common_verbs_reg_mr(priv->pd, opaq_buf, qp->entries_n *
 232                                         sizeof(struct mlx5_gga_compress_opaque),
 233                                                          &qp->opaque_mr) != 0) {
 234                 rte_free(opaq_buf);
 235                 DRV_LOG(ERR, "Failed to register opaque MR.");
 236                 rte_errno = ENOMEM;
 237                 goto err;
 238         }
 239         ret = mlx5_devx_cq_create(priv->ctx, &qp->cq, log_ops_n, &cq_attr,
 240                                   socket_id);
 241         if (ret != 0) {
 242                 DRV_LOG(ERR, "Failed to create CQ.");
 243                 goto err;
 244         }
 245         sq_attr.cqn = qp->cq.cq->id;
 246         sq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format);
 247         ret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,
 248                                   socket_id);
 249         if (ret != 0) {
 250                 DRV_LOG(ERR, "Failed to create SQ.");
 251                 goto err;
 252         }
 253         mlx5_compress_init_sq(qp);
 254         ret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);
 255         if (ret != 0) {
 256                 DRV_LOG(ERR, "Can't change SQ state to ready.");
 257                 goto err;
 258         }
 259         /* Save pointer of global generation number to check memory event. */
 260         qp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;
 261         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
 262                 (uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);
 263         return 0;
 264 err:
 265         mlx5_compress_qp_release(dev, qp_id);
 266         return -1;
 267 }
 268
 269 static int
 270 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 271 {
 272         struct mlx5_compress_priv *priv = dev->data->dev_private;
 273
 274         rte_spinlock_lock(&priv->xform_sl);
 275         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 276         rte_spinlock_unlock(&priv->xform_sl);
 277         rte_free(xform);
 278         return 0;
 279 }
 280
 281 static int
 282 mlx5_compress_xform_create(struct rte_compressdev *dev,
 283                            const struct rte_comp_xform *xform,
 284                            void **private_xform)
 285 {
 286         struct mlx5_compress_priv *priv = dev->data->dev_private;
 287         struct mlx5_compress_xform *xfrm;
 288         uint32_t size;
 289
 290         if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
 291                                                           RTE_COMP_LEVEL_NONE) {
 292                 DRV_LOG(ERR, "Non-compressed block is not supported.");
 293                 return -ENOTSUP;
 294         }
 295         if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
 296              RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
 297                       xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
 298                 DRV_LOG(ERR, "SHA is not supported.");
 299                 return -ENOTSUP;
 300         }
 301         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 302                                                     priv->dev_config.socket_id);
 303         if (xfrm == NULL)
 304                 return -ENOMEM;
 305         xfrm->opcode = MLX5_OPCODE_MMO;
 306         xfrm->type = xform->type;
 307         switch (xform->type) {
 308         case RTE_COMP_COMPRESS:
 309                 switch (xform->compress.algo) {
 310                 case RTE_COMP_ALGO_NULL:
 311                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 312                                                         WQE_CSEG_OPC_MOD_OFFSET;
 313                         break;
 314                 case RTE_COMP_ALGO_DEFLATE:
 315                         size = 1 << xform->compress.window_size;
 316                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 317                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 318                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 319                                            WQE_GGA_COMP_WIN_SIZE_OFFSET;
 320                         if (xform->compress.level == RTE_COMP_LEVEL_PMD_DEFAULT)
 321                                 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 322                         else
 323                                 size = priv->min_block_size - 1 +
 324                                                           xform->compress.level;
 325                         xfrm->gga_ctrl1 += RTE_MIN(size,
 326                                             MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
 327                                                  WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 328                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 329                                                         WQE_CSEG_OPC_MOD_OFFSET;
 330                         size = xform->compress.deflate.huffman ==
 331                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 332                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 333                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 334                         xfrm->gga_ctrl1 += size <<
 335                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 336                         break;
 337                 default:
 338                         goto err;
 339                 }
 340                 xfrm->csum_type = xform->compress.chksum;
 341                 break;
 342         case RTE_COMP_DECOMPRESS:
 343                 switch (xform->decompress.algo) {
 344                 case RTE_COMP_ALGO_NULL:
 345                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 346                                                         WQE_CSEG_OPC_MOD_OFFSET;
 347                         break;
 348                 case RTE_COMP_ALGO_DEFLATE:
 349                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 350                                                         WQE_CSEG_OPC_MOD_OFFSET;
 351                         break;
 352                 default:
 353                         goto err;
 354                 }
 355                 xfrm->csum_type = xform->decompress.chksum;
 356                 break;
 357         default:
 358                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 359                 goto err;
 360         }
 361         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 362                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 363         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 364         rte_spinlock_lock(&priv->xform_sl);
 365         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 366         rte_spinlock_unlock(&priv->xform_sl);
 367         *private_xform = xfrm;
 368         return 0;
 369 err:
 370         rte_free(xfrm);
 371         return -ENOTSUP;
 372 }
 373
 374 static void
 375 mlx5_compress_dev_stop(struct rte_compressdev *dev)
 376 {
 377         RTE_SET_USED(dev);
 378 }
 379
 380 static int
 381 mlx5_compress_dev_start(struct rte_compressdev *dev)
 382 {
 383         RTE_SET_USED(dev);
 384         return 0;
 385 }
 386
 387 static void
 388 mlx5_compress_stats_get(struct rte_compressdev *dev,
 389                 struct rte_compressdev_stats *stats)
 390 {
 391         int qp_id;
 392
 393         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 394                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 395
 396                 stats->enqueued_count += qp->stats.enqueued_count;
 397                 stats->dequeued_count += qp->stats.dequeued_count;
 398                 stats->enqueue_err_count += qp->stats.enqueue_err_count;
 399                 stats->dequeue_err_count += qp->stats.dequeue_err_count;
 400         }
 401 }
 402
 403 static void
 404 mlx5_compress_stats_reset(struct rte_compressdev *dev)
 405 {
 406         int qp_id;
 407
 408         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 409                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 410
 411                 memset(&qp->stats, 0, sizeof(qp->stats));
 412         }
 413 }
 414
 415 static struct rte_compressdev_ops mlx5_compress_ops = {
 416         .dev_configure          = mlx5_compress_dev_configure,
 417         .dev_start              = mlx5_compress_dev_start,
 418         .dev_stop               = mlx5_compress_dev_stop,
 419         .dev_close              = mlx5_compress_dev_close,
 420         .dev_infos_get          = mlx5_compress_dev_info_get,
 421         .stats_get              = mlx5_compress_stats_get,
 422         .stats_reset            = mlx5_compress_stats_reset,
 423         .queue_pair_setup       = mlx5_compress_qp_setup,
 424         .queue_pair_release     = mlx5_compress_qp_release,
 425         .private_xform_create   = mlx5_compress_xform_create,
 426         .private_xform_free     = mlx5_compress_xform_free,
 427         .stream_create          = NULL,
 428         .stream_free            = NULL,
 429 };
 430
 431 /**
 432  * Query LKey from a packet buffer for QP. If not found, add the mempool.
 433  *
 434  * @param priv
 435  *   Pointer to the priv object.
 436  * @param addr
 437  *   Search key.
 438  * @param mr_ctrl
 439  *   Pointer to per-queue MR control structure.
 440  * @param ol_flags
 441  *   Mbuf offload features.
 442  *
 443  * @return
 444  *   Searched LKey on success, UINT32_MAX on no match.
 445  */
 446 static __rte_always_inline uint32_t
 447 mlx5_compress_addr2mr(struct mlx5_compress_priv *priv, uintptr_t addr,
 448                       struct mlx5_mr_ctrl *mr_ctrl, uint64_t ol_flags)
 449 {
 450         uint32_t lkey;
 451
 452         /* Check generation bit to see if there's any change on existing MRs. */
 453         if (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))
 454                 mlx5_mr_flush_local_cache(mr_ctrl);
 455         /* Linear search on MR cache array. */
 456         lkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,
 457                                    MLX5_MR_CACHE_N, addr);
 458         if (likely(lkey != UINT32_MAX))
 459                 return lkey;
 460         /* Take slower bottom-half on miss. */
 461         return mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr,
 462                                   !!(ol_flags & EXT_ATTACHED_MBUF));
 463 }
 464
 465 static __rte_always_inline uint32_t
 466 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
 467                        volatile struct mlx5_wqe_dseg *restrict dseg,
 468                        struct rte_mbuf *restrict mbuf,
 469                        uint32_t offset, uint32_t len)
 470 {
 471         uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
 472
 473         dseg->bcount = rte_cpu_to_be_32(len);
 474         dseg->lkey = mlx5_compress_addr2mr(qp->priv, addr, &qp->mr_ctrl,
 475                                            mbuf->ol_flags);
 476         dseg->pbuf = rte_cpu_to_be_64(addr);
 477         return dseg->lkey;
 478 }
 479
 480 /*
 481  * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
 482  * 64bit architectures.
 483  */
 484 static __rte_always_inline void
 485 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv)
 486 {
 487 #ifdef RTE_ARCH_64
 488         *priv->uar_addr = val;
 489 #else /* !RTE_ARCH_64 */
 490         rte_spinlock_lock(&priv->uar32_sl);
 491         *(volatile uint32_t *)priv->uar_addr = val;
 492         rte_io_wmb();
 493         *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;
 494         rte_spinlock_unlock(&priv->uar32_sl);
 495 #endif
 496 }
 497
 498 static uint16_t
 499 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
 500                             uint16_t nb_ops)
 501 {
 502         struct mlx5_compress_qp *qp = queue_pair;
 503         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 504                                                               qp->sq.wqes, *wqe;
 505         struct mlx5_compress_xform *xform;
 506         struct rte_comp_op *op;
 507         uint16_t mask = qp->entries_n - 1;
 508         uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
 509         uint16_t idx;
 510         bool invalid;
 511
 512         if (remain < nb_ops)
 513                 nb_ops = remain;
 514         else
 515                 remain = nb_ops;
 516         if (unlikely(remain == 0))
 517                 return 0;
 518         do {
 519                 idx = qp->pi & mask;
 520                 wqe = &wqes[idx];
 521                 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
 522                 op = *ops++;
 523                 xform = op->private_xform;
 524                 /*
 525                  * Check operation arguments and error cases:
 526                  *   - Operation type must be state-less.
 527                  *   - Compress operation flush flag must be FULL or FINAL.
 528                  *   - Source and destination buffers must be mapped internally.
 529                  */
 530                 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
 531                                             (xform->type == RTE_COMP_COMPRESS &&
 532                                           op->flush_flag < RTE_COMP_FLUSH_FULL);
 533                 if (unlikely(invalid ||
 534                              (mlx5_compress_dseg_set(qp, &wqe->gather,
 535                                                      op->m_src,
 536                                                      op->src.offset,
 537                                                      op->src.length) ==
 538                                                                   UINT32_MAX) ||
 539                              (mlx5_compress_dseg_set(qp, &wqe->scatter,
 540                                                 op->m_dst,
 541                                                 op->dst.offset,
 542                                                 rte_pktmbuf_pkt_len(op->m_dst) -
 543                                                               op->dst.offset) ==
 544                                                                  UINT32_MAX))) {
 545                         op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
 546                                                        RTE_COMP_OP_STATUS_ERROR;
 547                         nb_ops -= remain;
 548                         if (unlikely(nb_ops == 0))
 549                                 return 0;
 550                         break;
 551                 }
 552                 wqe->gga_ctrl1 = xform->gga_ctrl1;
 553                 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
 554                 qp->ops[idx] = op;
 555                 qp->pi++;
 556         } while (--remain);
 557         qp->stats.enqueued_count += nb_ops;
 558         rte_io_wmb();
 559         qp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
 560         rte_wmb();
 561         mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);
 562         rte_wmb();
 563         return nb_ops;
 564 }
 565
 566 static void
 567 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
 568                              volatile uint32_t *opaq)
 569 {
 570         size_t i;
 571
 572         DRV_LOG(ERR, "Error cqe:");
 573         for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
 574                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 575                         cqe[i + 2], cqe[i + 3]);
 576         DRV_LOG(ERR, "\nError wqe:");
 577         for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
 578                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 579                         wqe[i + 2], wqe[i + 3]);
 580         DRV_LOG(ERR, "\nError opaq:");
 581         for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
 582                 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
 583                         opaq[i + 2], opaq[i + 3]);
 584 }
 585
 586 static void
 587 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
 588                              struct rte_comp_op *op)
 589 {
 590         const uint32_t idx = qp->ci & (qp->entries_n - 1);
 591         volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
 592                                                               &qp->cq.cqes[idx];
 593         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 594                                                                     qp->sq.wqes;
 595         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 596
 597         op->status = RTE_COMP_OP_STATUS_ERROR;
 598         op->consumed = 0;
 599         op->produced = 0;
 600         op->output_chksum = 0;
 601         op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
 602                               ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
 603         mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
 604                                  (volatile uint32_t *)&wqes[idx],
 605                                  (volatile uint32_t *)&opaq[idx]);
 606         qp->stats.dequeue_err_count++;
 607 }
 608
 609 static uint16_t
 610 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 611                             uint16_t nb_ops)
 612 {
 613         struct mlx5_compress_qp *qp = queue_pair;
 614         volatile struct mlx5_compress_xform *restrict xform;
 615         volatile struct mlx5_cqe *restrict cqe;
 616         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 617         struct rte_comp_op *restrict op;
 618         const unsigned int cq_size = qp->entries_n;
 619         const unsigned int mask = cq_size - 1;
 620         uint32_t idx;
 621         uint32_t next_idx = qp->ci & mask;
 622         const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
 623         uint16_t i = 0;
 624         int ret;
 625
 626         if (unlikely(max == 0))
 627                 return 0;
 628         do {
 629                 idx = next_idx;
 630                 next_idx = (qp->ci + 1) & mask;
 631                 rte_prefetch0(&qp->cq.cqes[next_idx]);
 632                 rte_prefetch0(qp->ops[next_idx]);
 633                 op = qp->ops[idx];
 634                 cqe = &qp->cq.cqes[idx];
 635                 ret = check_cqe(cqe, cq_size, qp->ci);
 636                 /*
 637                  * Be sure owner read is done before any other cookie field or
 638                  * opaque field.
 639                  */
 640                 rte_io_rmb();
 641                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 642                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 643                                 break;
 644                         mlx5_compress_cqe_err_handle(qp, op);
 645                 } else {
 646                         xform = op->private_xform;
 647                         op->status = RTE_COMP_OP_STATUS_SUCCESS;
 648                         op->consumed = op->src.length;
 649                         op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
 650                         MLX5_ASSERT(cqe->byte_cnt ==
 651                                     opaq[idx].scattered_length);
 652                         switch (xform->csum_type) {
 653                         case RTE_COMP_CHECKSUM_CRC32:
 654                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 655                                                     (opaq[idx].crc32);
 656                                 break;
 657                         case RTE_COMP_CHECKSUM_ADLER32:
 658                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 659                                             (opaq[idx].adler32) << 32;
 660                                 break;
 661                         case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 662                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 663                                                              (opaq[idx].crc32) |
 664                                                      ((uint64_t)rte_be_to_cpu_32
 665                                                      (opaq[idx].adler32) << 32);
 666                                 break;
 667                         default:
 668                                 break;
 669                         }
 670                 }
 671                 ops[i++] = op;
 672                 qp->ci++;
 673         } while (i < max);
 674         if (likely(i != 0)) {
 675                 rte_io_wmb();
 676                 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
 677                 qp->stats.dequeued_count += i;
 678         }
 679         return i;
 680 }
 681
 682 static void
 683 mlx5_compress_hw_global_release(struct mlx5_compress_priv *priv)
 684 {
 685         if (priv->pd != NULL) {
 686                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 687                 priv->pd = NULL;
 688         }
 689         if (priv->uar != NULL) {
 690                 mlx5_glue->devx_free_uar(priv->uar);
 691                 priv->uar = NULL;
 692         }
 693 }
 694
 695 static int
 696 mlx5_compress_pd_create(struct mlx5_compress_priv *priv)
 697 {
 698 #ifdef HAVE_IBV_FLOW_DV_SUPPORT
 699         struct mlx5dv_obj obj;
 700         struct mlx5dv_pd pd_info;
 701         int ret;
 702
 703         priv->pd = mlx5_glue->alloc_pd(priv->ctx);
 704         if (priv->pd == NULL) {
 705                 DRV_LOG(ERR, "Failed to allocate PD.");
 706                 return errno ? -errno : -ENOMEM;
 707         }
 708         obj.pd.in = priv->pd;
 709         obj.pd.out = &pd_info;
 710         ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);
 711         if (ret != 0) {
 712                 DRV_LOG(ERR, "Fail to get PD object info.");
 713                 mlx5_glue->dealloc_pd(priv->pd);
 714                 priv->pd = NULL;
 715                 return -errno;
 716         }
 717         priv->pdn = pd_info.pdn;
 718         return 0;
 719 #else
 720         (void)priv;
 721         DRV_LOG(ERR, "Cannot get pdn - no DV support.");
 722         return -ENOTSUP;
 723 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */
 724 }
 725
 726 static int
 727 mlx5_compress_hw_global_prepare(struct mlx5_compress_priv *priv)
 728 {
 729         if (mlx5_compress_pd_create(priv) != 0)
 730                 return -1;
 731         priv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);
 732         if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
 733             NULL) {
 734                 rte_errno = errno;
 735                 claim_zero(mlx5_glue->dealloc_pd(priv->pd));
 736                 DRV_LOG(ERR, "Failed to allocate UAR.");
 737                 return -1;
 738         }
 739         priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
 740         MLX5_ASSERT(priv->uar_addr);
 741 #ifndef RTE_ARCH_64
 742         rte_spinlock_init(&priv->uar32_sl);
 743 #endif /* RTE_ARCH_64 */
 744         return 0;
 745 }
 746
 747 /**
 748  * Callback for memory event.
 749  *
 750  * @param event_type
 751  *   Memory event type.
 752  * @param addr
 753  *   Address of memory.
 754  * @param len
 755  *   Size of memory.
 756  */
 757 static void
 758 mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,
 759                               size_t len, void *arg __rte_unused)
 760 {
 761         struct mlx5_compress_priv *priv;
 762
 763         /* Must be called from the primary process. */
 764         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 765         switch (event_type) {
 766         case RTE_MEM_EVENT_FREE:
 767                 pthread_mutex_lock(&priv_list_lock);
 768                 /* Iterate all the existing mlx5 devices. */
 769                 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 770                         mlx5_free_mr_by_addr(&priv->mr_scache,
 771                                              priv->ctx->device->name,
 772                                              addr, len);
 773                 pthread_mutex_unlock(&priv_list_lock);
 774                 break;
 775         case RTE_MEM_EVENT_ALLOC:
 776         default:
 777                 break;
 778         }
 779 }
 780
 781 static int
 782 mlx5_compress_dev_probe(struct rte_device *dev)
 783 {
 784         struct ibv_device *ibv;
 785         struct rte_compressdev *cdev;
 786         struct ibv_context *ctx;
 787         struct mlx5_compress_priv *priv;
 788         struct mlx5_hca_attr att = { 0 };
 789         struct rte_compressdev_pmd_init_params init_params = {
 790                 .name = "",
 791                 .socket_id = dev->numa_node,
 792         };
 793
 794         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 795                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 796                 rte_errno = ENOTSUP;
 797                 return -rte_errno;
 798         }
 799         ibv = mlx5_os_get_ibv_dev(dev);
 800         if (ibv == NULL)
 801                 return -rte_errno;
 802         ctx = mlx5_glue->dv_open_device(ibv);
 803         if (ctx == NULL) {
 804                 DRV_LOG(ERR, "Failed to open IB device \"%s\".", ibv->name);
 805                 rte_errno = ENODEV;
 806                 return -rte_errno;
 807         }
 808         if (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||
 809             att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||
 810             att.mmo_dma_en == 0) {
 811                 DRV_LOG(ERR, "Not enough capabilities to support compress "
 812                         "operations, maybe old FW/OFED version?");
 813                 claim_zero(mlx5_glue->close_device(ctx));
 814                 rte_errno = ENOTSUP;
 815                 return -ENOTSUP;
 816         }
 817         cdev = rte_compressdev_pmd_create(ibv->name, dev,
 818                                           sizeof(*priv), &init_params);
 819         if (cdev == NULL) {
 820                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibv->name);
 821                 claim_zero(mlx5_glue->close_device(ctx));
 822                 return -ENODEV;
 823         }
 824         DRV_LOG(INFO,
 825                 "Compress device %s was created successfully.", ibv->name);
 826         cdev->dev_ops = &mlx5_compress_ops;
 827         cdev->dequeue_burst = mlx5_compress_dequeue_burst;
 828         cdev->enqueue_burst = mlx5_compress_enqueue_burst;
 829         cdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 830         priv = cdev->data->dev_private;
 831         priv->ctx = ctx;
 832         priv->cdev = cdev;
 833         priv->min_block_size = att.compress_min_block_size;
 834         priv->sq_ts_format = att.sq_ts_format;
 835         if (mlx5_compress_hw_global_prepare(priv) != 0) {
 836                 rte_compressdev_pmd_destroy(priv->cdev);
 837                 claim_zero(mlx5_glue->close_device(priv->ctx));
 838                 return -1;
 839         }
 840         if (mlx5_mr_btree_init(&priv->mr_scache.cache,
 841                              MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {
 842                 DRV_LOG(ERR, "Failed to allocate shared cache MR memory.");
 843                 mlx5_compress_hw_global_release(priv);
 844                 rte_compressdev_pmd_destroy(priv->cdev);
 845                 claim_zero(mlx5_glue->close_device(priv->ctx));
 846                 rte_errno = ENOMEM;
 847                 return -rte_errno;
 848         }
 849         priv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;
 850         priv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;
 851         /* Register callback function for global shared MR cache management. */
 852         if (TAILQ_EMPTY(&mlx5_compress_priv_list))
 853                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
 854                                                 mlx5_compress_mr_mem_event_cb,
 855                                                 NULL);
 856         pthread_mutex_lock(&priv_list_lock);
 857         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 858         pthread_mutex_unlock(&priv_list_lock);
 859         return 0;
 860 }
 861
 862 static int
 863 mlx5_compress_dev_remove(struct rte_device *dev)
 864 {
 865         struct mlx5_compress_priv *priv = NULL;
 866
 867         pthread_mutex_lock(&priv_list_lock);
 868         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 869                 if (priv->cdev->device == dev)
 870                         break;
 871         if (priv)
 872                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 873         pthread_mutex_unlock(&priv_list_lock);
 874         if (priv) {
 875                 if (TAILQ_EMPTY(&mlx5_compress_priv_list))
 876                         rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB",
 877                                                           NULL);
 878                 mlx5_mr_release_cache(&priv->mr_scache);
 879                 mlx5_compress_hw_global_release(priv);
 880                 rte_compressdev_pmd_destroy(priv->cdev);
 881                 claim_zero(mlx5_glue->close_device(priv->ctx));
 882         }
 883         return 0;
 884 }
 885
 886 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 887         {
 888                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 889                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 890         },
 891         {
 892                 .vendor_id = 0
 893         }
 894 };
 895
 896 static struct mlx5_class_driver mlx5_compress_driver = {
 897         .drv_class = MLX5_CLASS_COMPRESS,
 898         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 899         .id_table = mlx5_compress_pci_id_map,
 900         .probe = mlx5_compress_dev_probe,
 901         .remove = mlx5_compress_dev_remove,
 902 };
 903
 904 RTE_INIT(rte_mlx5_compress_init)
 905 {
 906         mlx5_common_init();
 907         if (mlx5_glue != NULL)
 908                 mlx5_class_driver_register(&mlx5_compress_driver);
 909 }
 910
 911 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE)
 912 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 913 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 914 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");