drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_bus_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_devx_cmds.h>
  17 #include <mlx5_common_os.h>
  18 #include <mlx5_common_devx.h>
  19 #include <mlx5_common_mr.h>
  20 #include <mlx5_prm.h>
  21
  22 #include "mlx5_compress_utils.h"
  23
  24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  25 #define MLX5_COMPRESS_MAX_QPS 1024
  26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  27
  28 struct mlx5_compress_xform {
  29         LIST_ENTRY(mlx5_compress_xform) next;
  30         enum rte_comp_xform_type type;
  31         enum rte_comp_checksum_type csum_type;
  32         uint32_t opcode;
  33         uint32_t gga_ctrl1; /* BE. */
  34 };
  35
  36 struct mlx5_compress_priv {
  37         TAILQ_ENTRY(mlx5_compress_priv) next;
  38         struct rte_compressdev *compressdev;
  39         struct mlx5_common_device *cdev; /* Backend mlx5 device. */
  40         void *uar;
  41         uint8_t min_block_size;
  42         /* Minimum huffman block size supported by the device. */
  43         struct rte_compressdev_config dev_config;
  44         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  45         rte_spinlock_t xform_sl;
  46         volatile uint64_t *uar_addr;
  47         /* HCA caps*/
  48         uint32_t mmo_decomp_sq:1;
  49         uint32_t mmo_decomp_qp:1;
  50         uint32_t mmo_comp_sq:1;
  51         uint32_t mmo_comp_qp:1;
  52         uint32_t mmo_dma_sq:1;
  53         uint32_t mmo_dma_qp:1;
  54 #ifndef RTE_ARCH_64
  55         rte_spinlock_t uar32_sl;
  56 #endif /* RTE_ARCH_64 */
  57 };
  58
  59 struct mlx5_compress_qp {
  60         uint16_t qp_id;
  61         uint16_t entries_n;
  62         uint16_t pi;
  63         uint16_t ci;
  64         struct mlx5_mr_ctrl mr_ctrl;
  65         int socket_id;
  66         struct mlx5_devx_cq cq;
  67         struct mlx5_devx_qp qp;
  68         struct mlx5_pmd_mr opaque_mr;
  69         struct rte_comp_op **ops;
  70         struct mlx5_compress_priv *priv;
  71         struct rte_compressdev_stats stats;
  72 };
  73
  74 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  75                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  76 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  77
  78 int mlx5_compress_logtype;
  79
  80 static const struct rte_compressdev_capabilities mlx5_caps[] = {
  81         {
  82                 .algo = RTE_COMP_ALGO_NULL,
  83                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  84                                       RTE_COMP_FF_CRC32_CHECKSUM |
  85                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  86                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
  87         },
  88         {
  89                 .algo = RTE_COMP_ALGO_DEFLATE,
  90                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  91                                       RTE_COMP_FF_CRC32_CHECKSUM |
  92                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  93                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
  94                                       RTE_COMP_FF_HUFFMAN_FIXED |
  95                                       RTE_COMP_FF_HUFFMAN_DYNAMIC,
  96                 .window_size = {.min = 10, .max = 15, .increment = 1},
  97         },
  98         {
  99                 .algo = RTE_COMP_ALGO_LIST_END,
 100         }
 101 };
 102
 103 static void
 104 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
 105                            struct rte_compressdev_info *info)
 106 {
 107         RTE_SET_USED(dev);
 108         if (info != NULL) {
 109                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
 110                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 111                 info->capabilities = mlx5_caps;
 112         }
 113 }
 114
 115 static int
 116 mlx5_compress_dev_configure(struct rte_compressdev *dev,
 117                             struct rte_compressdev_config *config)
 118 {
 119         struct mlx5_compress_priv *priv;
 120
 121         if (dev == NULL || config == NULL)
 122                 return -EINVAL;
 123         priv = dev->data->dev_private;
 124         priv->dev_config = *config;
 125         return 0;
 126 }
 127
 128 static int
 129 mlx5_compress_dev_close(struct rte_compressdev *dev)
 130 {
 131         RTE_SET_USED(dev);
 132         return 0;
 133 }
 134
 135 static int
 136 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 137 {
 138         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 139
 140         if (qp->qp.qp != NULL)
 141                 mlx5_devx_qp_destroy(&qp->qp);
 142         if (qp->cq.cq != NULL)
 143                 mlx5_devx_cq_destroy(&qp->cq);
 144         if (qp->opaque_mr.obj != NULL) {
 145                 void *opaq = qp->opaque_mr.addr;
 146
 147                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 148                 if (opaq != NULL)
 149                         rte_free(opaq);
 150         }
 151         mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 152         rte_free(qp);
 153         dev->data->queue_pairs[qp_id] = NULL;
 154         return 0;
 155 }
 156
 157 static void
 158 mlx5_compress_init_qp(struct mlx5_compress_qp *qp)
 159 {
 160         volatile struct mlx5_gga_wqe *restrict wqe =
 161                                     (volatile struct mlx5_gga_wqe *)qp->qp.wqes;
 162         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 163         const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);
 164         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 165                                         MLX5_COMP_MODE_OFFSET);
 166         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 167         int i;
 168
 169         /* All the next fields state should stay constant. */
 170         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 171                 wqe->sq_ds = sq_ds;
 172                 wqe->flags = flags;
 173                 wqe->opaque_lkey = opaq_lkey;
 174                 wqe->opaque_vaddr = rte_cpu_to_be_64
 175                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 176         }
 177 }
 178
 179 static int
 180 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 181                        uint32_t max_inflight_ops, int socket_id)
 182 {
 183         struct mlx5_compress_priv *priv = dev->data->dev_private;
 184         struct mlx5_compress_qp *qp;
 185         struct mlx5_devx_cq_attr cq_attr = {
 186                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
 187         };
 188         struct mlx5_devx_qp_attr qp_attr = {
 189                 .pd = priv->cdev->pdn,
 190                 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar),
 191                 .user_index = qp_id,
 192         };
 193         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 194         uint32_t alloc_size = sizeof(*qp);
 195         void *opaq_buf;
 196         int ret;
 197
 198         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 199         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 200         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 201                                 socket_id);
 202         if (qp == NULL) {
 203                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 204                 rte_errno = ENOMEM;
 205                 return -rte_errno;
 206         }
 207         dev->data->queue_pairs[qp_id] = qp;
 208         if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen,
 209                               priv->dev_config.socket_id)) {
 210                 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
 211                         (uint32_t)qp_id);
 212                 rte_errno = ENOMEM;
 213                 goto err;
 214         }
 215         opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,
 216                               sizeof(struct mlx5_gga_compress_opaque),
 217                               sizeof(struct mlx5_gga_compress_opaque));
 218         if (opaq_buf == NULL) {
 219                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 220                 rte_errno = ENOMEM;
 221                 goto err;
 222         }
 223         qp->entries_n = 1 << log_ops_n;
 224         qp->socket_id = socket_id;
 225         qp->qp_id = qp_id;
 226         qp->priv = priv;
 227         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 228                                                    RTE_CACHE_LINE_SIZE);
 229         if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n *
 230                                         sizeof(struct mlx5_gga_compress_opaque),
 231                                                          &qp->opaque_mr) != 0) {
 232                 rte_free(opaq_buf);
 233                 DRV_LOG(ERR, "Failed to register opaque MR.");
 234                 rte_errno = ENOMEM;
 235                 goto err;
 236         }
 237         ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr,
 238                                   socket_id);
 239         if (ret != 0) {
 240                 DRV_LOG(ERR, "Failed to create CQ.");
 241                 goto err;
 242         }
 243         qp_attr.cqn = qp->cq.cq->id;
 244         qp_attr.ts_format =
 245                 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
 246         qp_attr.rq_size = 0;
 247         qp_attr.sq_size = RTE_BIT32(log_ops_n);
 248         qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
 249                         && priv->mmo_dma_qp;
 250         ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr,
 251                                   socket_id);
 252         if (ret != 0) {
 253                 DRV_LOG(ERR, "Failed to create QP.");
 254                 goto err;
 255         }
 256         mlx5_compress_init_qp(qp);
 257         ret = mlx5_devx_qp2rts(&qp->qp, 0);
 258         if (ret)
 259                 goto err;
 260         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
 261                 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n);
 262         return 0;
 263 err:
 264         mlx5_compress_qp_release(dev, qp_id);
 265         return -1;
 266 }
 267
 268 static int
 269 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 270 {
 271         struct mlx5_compress_priv *priv = dev->data->dev_private;
 272
 273         rte_spinlock_lock(&priv->xform_sl);
 274         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 275         rte_spinlock_unlock(&priv->xform_sl);
 276         rte_free(xform);
 277         return 0;
 278 }
 279
 280 static int
 281 mlx5_compress_xform_create(struct rte_compressdev *dev,
 282                            const struct rte_comp_xform *xform,
 283                            void **private_xform)
 284 {
 285         struct mlx5_compress_priv *priv = dev->data->dev_private;
 286         struct mlx5_compress_xform *xfrm;
 287         uint32_t size;
 288
 289         switch (xform->type) {
 290         case RTE_COMP_COMPRESS:
 291                 if (xform->compress.algo == RTE_COMP_ALGO_NULL &&
 292                                 !priv->mmo_dma_qp && !priv->mmo_dma_sq) {
 293                         DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?");
 294                         return -ENOTSUP;
 295                 } else if (!priv->mmo_comp_qp && !priv->mmo_comp_sq) {
 296                         DRV_LOG(ERR, "Not enough capabilities to support compress operation, maybe old FW/OFED version?");
 297                         return -ENOTSUP;
 298                 }
 299                 if (xform->compress.level == RTE_COMP_LEVEL_NONE) {
 300                         DRV_LOG(ERR, "Non-compressed block is not supported.");
 301                         return -ENOTSUP;
 302                 }
 303                 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
 304                         DRV_LOG(ERR, "SHA is not supported.");
 305                         return -ENOTSUP;
 306                 }
 307                 break;
 308         case RTE_COMP_DECOMPRESS:
 309                 if (xform->decompress.algo == RTE_COMP_ALGO_NULL &&
 310                                 !priv->mmo_dma_qp && !priv->mmo_dma_sq) {
 311                         DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?");
 312                         return -ENOTSUP;
 313                 } else if (!priv->mmo_decomp_qp && !priv->mmo_decomp_sq) {
 314                         DRV_LOG(ERR, "Not enough capabilities to support decompress operation, maybe old FW/OFED version?");
 315                         return -ENOTSUP;
 316                 }
 317                 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
 318                         DRV_LOG(ERR, "SHA is not supported.");
 319                         return -ENOTSUP;
 320                 }
 321                 break;
 322         default:
 323                 DRV_LOG(ERR, "Xform type should be compress/decompress");
 324                 return -ENOTSUP;
 325         }
 326
 327         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 328                                                     priv->dev_config.socket_id);
 329         if (xfrm == NULL)
 330                 return -ENOMEM;
 331         xfrm->opcode = MLX5_OPCODE_MMO;
 332         xfrm->type = xform->type;
 333         switch (xform->type) {
 334         case RTE_COMP_COMPRESS:
 335                 switch (xform->compress.algo) {
 336                 case RTE_COMP_ALGO_NULL:
 337                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 338                                                         WQE_CSEG_OPC_MOD_OFFSET;
 339                         break;
 340                 case RTE_COMP_ALGO_DEFLATE:
 341                         size = 1 << xform->compress.window_size;
 342                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 343                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 344                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 345                                                 WQE_GGA_COMP_WIN_SIZE_OFFSET;
 346                         size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 347                         xfrm->gga_ctrl1 += size <<
 348                                                 WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 349                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 350                                                         WQE_CSEG_OPC_MOD_OFFSET;
 351                         size = xform->compress.deflate.huffman ==
 352                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 353                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 354                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 355                         xfrm->gga_ctrl1 += size <<
 356                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 357                         break;
 358                 default:
 359                         goto err;
 360                 }
 361                 xfrm->csum_type = xform->compress.chksum;
 362                 break;
 363         case RTE_COMP_DECOMPRESS:
 364                 switch (xform->decompress.algo) {
 365                 case RTE_COMP_ALGO_NULL:
 366                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 367                                                         WQE_CSEG_OPC_MOD_OFFSET;
 368                         break;
 369                 case RTE_COMP_ALGO_DEFLATE:
 370                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 371                                                         WQE_CSEG_OPC_MOD_OFFSET;
 372                         break;
 373                 default:
 374                         goto err;
 375                 }
 376                 xfrm->csum_type = xform->decompress.chksum;
 377                 break;
 378         default:
 379                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 380                 goto err;
 381         }
 382         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 383                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 384         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 385         rte_spinlock_lock(&priv->xform_sl);
 386         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 387         rte_spinlock_unlock(&priv->xform_sl);
 388         *private_xform = xfrm;
 389         return 0;
 390 err:
 391         rte_free(xfrm);
 392         return -ENOTSUP;
 393 }
 394
 395 static void
 396 mlx5_compress_dev_stop(struct rte_compressdev *dev)
 397 {
 398         RTE_SET_USED(dev);
 399 }
 400
 401 static int
 402 mlx5_compress_dev_start(struct rte_compressdev *dev)
 403 {
 404         struct mlx5_compress_priv *priv = dev->data->dev_private;
 405
 406         return mlx5_dev_mempool_subscribe(priv->cdev);
 407 }
 408
 409 static void
 410 mlx5_compress_stats_get(struct rte_compressdev *dev,
 411                 struct rte_compressdev_stats *stats)
 412 {
 413         int qp_id;
 414
 415         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 416                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 417
 418                 stats->enqueued_count += qp->stats.enqueued_count;
 419                 stats->dequeued_count += qp->stats.dequeued_count;
 420                 stats->enqueue_err_count += qp->stats.enqueue_err_count;
 421                 stats->dequeue_err_count += qp->stats.dequeue_err_count;
 422         }
 423 }
 424
 425 static void
 426 mlx5_compress_stats_reset(struct rte_compressdev *dev)
 427 {
 428         int qp_id;
 429
 430         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 431                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 432
 433                 memset(&qp->stats, 0, sizeof(qp->stats));
 434         }
 435 }
 436
 437 static struct rte_compressdev_ops mlx5_compress_ops = {
 438         .dev_configure          = mlx5_compress_dev_configure,
 439         .dev_start              = mlx5_compress_dev_start,
 440         .dev_stop               = mlx5_compress_dev_stop,
 441         .dev_close              = mlx5_compress_dev_close,
 442         .dev_infos_get          = mlx5_compress_dev_info_get,
 443         .stats_get              = mlx5_compress_stats_get,
 444         .stats_reset            = mlx5_compress_stats_reset,
 445         .queue_pair_setup       = mlx5_compress_qp_setup,
 446         .queue_pair_release     = mlx5_compress_qp_release,
 447         .private_xform_create   = mlx5_compress_xform_create,
 448         .private_xform_free     = mlx5_compress_xform_free,
 449         .stream_create          = NULL,
 450         .stream_free            = NULL,
 451 };
 452
 453 static __rte_always_inline uint32_t
 454 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
 455                        volatile struct mlx5_wqe_dseg *restrict dseg,
 456                        struct rte_mbuf *restrict mbuf,
 457                        uint32_t offset, uint32_t len)
 458 {
 459         uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
 460
 461         dseg->bcount = rte_cpu_to_be_32(len);
 462         dseg->lkey = mlx5_mr_mb2mr(qp->priv->cdev, 0, &qp->mr_ctrl, mbuf);
 463         dseg->pbuf = rte_cpu_to_be_64(addr);
 464         return dseg->lkey;
 465 }
 466
 467 /*
 468  * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
 469  * 64bit architectures.
 470  */
 471 static __rte_always_inline void
 472 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv)
 473 {
 474 #ifdef RTE_ARCH_64
 475         *priv->uar_addr = val;
 476 #else /* !RTE_ARCH_64 */
 477         rte_spinlock_lock(&priv->uar32_sl);
 478         *(volatile uint32_t *)priv->uar_addr = val;
 479         rte_io_wmb();
 480         *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;
 481         rte_spinlock_unlock(&priv->uar32_sl);
 482 #endif
 483 }
 484
 485 static uint16_t
 486 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
 487                             uint16_t nb_ops)
 488 {
 489         struct mlx5_compress_qp *qp = queue_pair;
 490         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 491                                                               qp->qp.wqes, *wqe;
 492         struct mlx5_compress_xform *xform;
 493         struct rte_comp_op *op;
 494         uint16_t mask = qp->entries_n - 1;
 495         uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
 496         uint16_t idx;
 497         bool invalid;
 498
 499         if (remain < nb_ops)
 500                 nb_ops = remain;
 501         else
 502                 remain = nb_ops;
 503         if (unlikely(remain == 0))
 504                 return 0;
 505         do {
 506                 idx = qp->pi & mask;
 507                 wqe = &wqes[idx];
 508                 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
 509                 op = *ops++;
 510                 xform = op->private_xform;
 511                 /*
 512                  * Check operation arguments and error cases:
 513                  *   - Operation type must be state-less.
 514                  *   - Compress operation flush flag must be FULL or FINAL.
 515                  *   - Source and destination buffers must be mapped internally.
 516                  */
 517                 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
 518                                             (xform->type == RTE_COMP_COMPRESS &&
 519                                           op->flush_flag < RTE_COMP_FLUSH_FULL);
 520                 if (unlikely(invalid ||
 521                              (mlx5_compress_dseg_set(qp, &wqe->gather,
 522                                                      op->m_src,
 523                                                      op->src.offset,
 524                                                      op->src.length) ==
 525                                                                   UINT32_MAX) ||
 526                              (mlx5_compress_dseg_set(qp, &wqe->scatter,
 527                                                 op->m_dst,
 528                                                 op->dst.offset,
 529                                                 rte_pktmbuf_pkt_len(op->m_dst) -
 530                                                               op->dst.offset) ==
 531                                                                  UINT32_MAX))) {
 532                         op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
 533                                                        RTE_COMP_OP_STATUS_ERROR;
 534                         nb_ops -= remain;
 535                         if (unlikely(nb_ops == 0))
 536                                 return 0;
 537                         break;
 538                 }
 539                 wqe->gga_ctrl1 = xform->gga_ctrl1;
 540                 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
 541                 qp->ops[idx] = op;
 542                 qp->pi++;
 543         } while (--remain);
 544         qp->stats.enqueued_count += nb_ops;
 545         rte_io_wmb();
 546         qp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
 547         rte_wmb();
 548         mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);
 549         rte_wmb();
 550         return nb_ops;
 551 }
 552
 553 static void
 554 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
 555                              volatile uint32_t *opaq)
 556 {
 557         size_t i;
 558
 559         DRV_LOG(ERR, "Error cqe:");
 560         for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
 561                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 562                         cqe[i + 2], cqe[i + 3]);
 563         DRV_LOG(ERR, "\nError wqe:");
 564         for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
 565                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 566                         wqe[i + 2], wqe[i + 3]);
 567         DRV_LOG(ERR, "\nError opaq:");
 568         for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
 569                 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
 570                         opaq[i + 2], opaq[i + 3]);
 571 }
 572
 573 static void
 574 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
 575                              struct rte_comp_op *op)
 576 {
 577         const uint32_t idx = qp->ci & (qp->entries_n - 1);
 578         volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
 579                                                               &qp->cq.cqes[idx];
 580         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 581                                                                     qp->qp.wqes;
 582         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 583
 584         op->status = RTE_COMP_OP_STATUS_ERROR;
 585         op->consumed = 0;
 586         op->produced = 0;
 587         op->output_chksum = 0;
 588         op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
 589                               ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
 590         mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
 591                                  (volatile uint32_t *)&wqes[idx],
 592                                  (volatile uint32_t *)&opaq[idx]);
 593         qp->stats.dequeue_err_count++;
 594 }
 595
 596 static uint16_t
 597 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 598                             uint16_t nb_ops)
 599 {
 600         struct mlx5_compress_qp *qp = queue_pair;
 601         volatile struct mlx5_compress_xform *restrict xform;
 602         volatile struct mlx5_cqe *restrict cqe;
 603         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 604         struct rte_comp_op *restrict op;
 605         const unsigned int cq_size = qp->entries_n;
 606         const unsigned int mask = cq_size - 1;
 607         uint32_t idx;
 608         uint32_t next_idx = qp->ci & mask;
 609         const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
 610         uint16_t i = 0;
 611         int ret;
 612
 613         if (unlikely(max == 0))
 614                 return 0;
 615         do {
 616                 idx = next_idx;
 617                 next_idx = (qp->ci + 1) & mask;
 618                 rte_prefetch0(&qp->cq.cqes[next_idx]);
 619                 rte_prefetch0(qp->ops[next_idx]);
 620                 op = qp->ops[idx];
 621                 cqe = &qp->cq.cqes[idx];
 622                 ret = check_cqe(cqe, cq_size, qp->ci);
 623                 /*
 624                  * Be sure owner read is done before any other cookie field or
 625                  * opaque field.
 626                  */
 627                 rte_io_rmb();
 628                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 629                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 630                                 break;
 631                         mlx5_compress_cqe_err_handle(qp, op);
 632                 } else {
 633                         xform = op->private_xform;
 634                         op->status = RTE_COMP_OP_STATUS_SUCCESS;
 635                         op->consumed = op->src.length;
 636                         op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
 637                         MLX5_ASSERT(cqe->byte_cnt ==
 638                                     opaq[idx].scattered_length);
 639                         switch (xform->csum_type) {
 640                         case RTE_COMP_CHECKSUM_CRC32:
 641                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 642                                                     (opaq[idx].crc32);
 643                                 break;
 644                         case RTE_COMP_CHECKSUM_ADLER32:
 645                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 646                                             (opaq[idx].adler32) << 32;
 647                                 break;
 648                         case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 649                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 650                                                              (opaq[idx].crc32) |
 651                                                      ((uint64_t)rte_be_to_cpu_32
 652                                                      (opaq[idx].adler32) << 32);
 653                                 break;
 654                         default:
 655                                 break;
 656                         }
 657                 }
 658                 ops[i++] = op;
 659                 qp->ci++;
 660         } while (i < max);
 661         if (likely(i != 0)) {
 662                 rte_io_wmb();
 663                 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
 664                 qp->stats.dequeued_count += i;
 665         }
 666         return i;
 667 }
 668
 669 static void
 670 mlx5_compress_uar_release(struct mlx5_compress_priv *priv)
 671 {
 672         if (priv->uar != NULL) {
 673                 mlx5_glue->devx_free_uar(priv->uar);
 674                 priv->uar = NULL;
 675         }
 676 }
 677
 678 static int
 679 mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv)
 680 {
 681         priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);
 682         if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
 683             NULL) {
 684                 rte_errno = errno;
 685                 DRV_LOG(ERR, "Failed to allocate UAR.");
 686                 return -1;
 687         }
 688         priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
 689         MLX5_ASSERT(priv->uar_addr);
 690 #ifndef RTE_ARCH_64
 691         rte_spinlock_init(&priv->uar32_sl);
 692 #endif /* RTE_ARCH_64 */
 693         return 0;
 694 }
 695
 696 static int
 697 mlx5_compress_dev_probe(struct mlx5_common_device *cdev)
 698 {
 699         struct rte_compressdev *compressdev;
 700         struct mlx5_compress_priv *priv;
 701         struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
 702         struct rte_compressdev_pmd_init_params init_params = {
 703                 .name = "",
 704                 .socket_id = cdev->dev->numa_node,
 705         };
 706         const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
 707
 708         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 709                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 710                 rte_errno = ENOTSUP;
 711                 return -rte_errno;
 712         }
 713         if (!attr->mmo_decompress_qp_en && !attr->mmo_decompress_sq_en
 714                 && !attr->mmo_compress_qp_en && !attr->mmo_compress_sq_en
 715                 && !attr->mmo_dma_qp_en && !attr->mmo_dma_sq_en) {
 716                 DRV_LOG(ERR, "Not enough capabilities to support compress operations, maybe old FW/OFED version?");
 717                 claim_zero(mlx5_glue->close_device(cdev->ctx));
 718                 rte_errno = ENOTSUP;
 719                 return -ENOTSUP;
 720         }
 721         compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev,
 722                                                  sizeof(*priv), &init_params);
 723         if (compressdev == NULL) {
 724                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name);
 725                 return -ENODEV;
 726         }
 727         DRV_LOG(INFO,
 728                 "Compress device %s was created successfully.", ibdev_name);
 729         compressdev->dev_ops = &mlx5_compress_ops;
 730         compressdev->dequeue_burst = mlx5_compress_dequeue_burst;
 731         compressdev->enqueue_burst = mlx5_compress_enqueue_burst;
 732         compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 733         priv = compressdev->data->dev_private;
 734         priv->mmo_decomp_sq = attr->mmo_decompress_sq_en;
 735         priv->mmo_decomp_qp = attr->mmo_decompress_qp_en;
 736         priv->mmo_comp_sq = attr->mmo_compress_sq_en;
 737         priv->mmo_comp_qp = attr->mmo_compress_qp_en;
 738         priv->mmo_dma_sq = attr->mmo_dma_sq_en;
 739         priv->mmo_dma_qp = attr->mmo_dma_qp_en;
 740         priv->cdev = cdev;
 741         priv->compressdev = compressdev;
 742         priv->min_block_size = attr->compress_min_block_size;
 743         if (mlx5_compress_uar_prepare(priv) != 0) {
 744                 rte_compressdev_pmd_destroy(priv->compressdev);
 745                 return -1;
 746         }
 747         pthread_mutex_lock(&priv_list_lock);
 748         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 749         pthread_mutex_unlock(&priv_list_lock);
 750         return 0;
 751 }
 752
 753 static int
 754 mlx5_compress_dev_remove(struct mlx5_common_device *cdev)
 755 {
 756         struct mlx5_compress_priv *priv = NULL;
 757
 758         pthread_mutex_lock(&priv_list_lock);
 759         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 760                 if (priv->compressdev->device == cdev->dev)
 761                         break;
 762         if (priv)
 763                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 764         pthread_mutex_unlock(&priv_list_lock);
 765         if (priv) {
 766                 mlx5_compress_uar_release(priv);
 767                 rte_compressdev_pmd_destroy(priv->compressdev);
 768         }
 769         return 0;
 770 }
 771
 772 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 773         {
 774                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 775                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 776         },
 777         {
 778                 .vendor_id = 0
 779         }
 780 };
 781
 782 static struct mlx5_class_driver mlx5_compress_driver = {
 783         .drv_class = MLX5_CLASS_COMPRESS,
 784         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 785         .id_table = mlx5_compress_pci_id_map,
 786         .probe = mlx5_compress_dev_probe,
 787         .remove = mlx5_compress_dev_remove,
 788 };
 789
 790 RTE_INIT(rte_mlx5_compress_init)
 791 {
 792         mlx5_common_init();
 793         if (mlx5_glue != NULL)
 794                 mlx5_class_driver_register(&mlx5_compress_driver);
 795 }
 796
 797 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE)
 798 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 799 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 800 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");