drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_bus_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_devx_cmds.h>
  17 #include <mlx5_common_os.h>
  18 #include <mlx5_common_devx.h>
  19 #include <mlx5_common_mr.h>
  20 #include <mlx5_prm.h>
  21
  22 #include "mlx5_compress_utils.h"
  23
  24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  25 #define MLX5_COMPRESS_MAX_QPS 1024
  26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  27
  28 struct mlx5_compress_xform {
  29         LIST_ENTRY(mlx5_compress_xform) next;
  30         enum rte_comp_xform_type type;
  31         enum rte_comp_checksum_type csum_type;
  32         uint32_t opcode;
  33         uint32_t gga_ctrl1; /* BE. */
  34 };
  35
  36 struct mlx5_compress_priv {
  37         TAILQ_ENTRY(mlx5_compress_priv) next;
  38         struct rte_compressdev *compressdev;
  39         struct mlx5_common_device *cdev; /* Backend mlx5 device. */
  40         void *uar;
  41         uint8_t min_block_size;
  42         /* Minimum huffman block size supported by the device. */
  43         struct rte_compressdev_config dev_config;
  44         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  45         rte_spinlock_t xform_sl;
  46         struct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */
  47         volatile uint64_t *uar_addr;
  48         /* HCA caps*/
  49         uint32_t mmo_decomp_sq:1;
  50         uint32_t mmo_decomp_qp:1;
  51         uint32_t mmo_comp_sq:1;
  52         uint32_t mmo_comp_qp:1;
  53         uint32_t mmo_dma_sq:1;
  54         uint32_t mmo_dma_qp:1;
  55 #ifndef RTE_ARCH_64
  56         rte_spinlock_t uar32_sl;
  57 #endif /* RTE_ARCH_64 */
  58 };
  59
  60 struct mlx5_compress_qp {
  61         uint16_t qp_id;
  62         uint16_t entries_n;
  63         uint16_t pi;
  64         uint16_t ci;
  65         struct mlx5_mr_ctrl mr_ctrl;
  66         int socket_id;
  67         struct mlx5_devx_cq cq;
  68         struct mlx5_devx_qp qp;
  69         struct mlx5_pmd_mr opaque_mr;
  70         struct rte_comp_op **ops;
  71         struct mlx5_compress_priv *priv;
  72         struct rte_compressdev_stats stats;
  73 };
  74
  75 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  76                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  77 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  78
  79 int mlx5_compress_logtype;
  80
  81 static const struct rte_compressdev_capabilities mlx5_caps[] = {
  82         {
  83                 .algo = RTE_COMP_ALGO_NULL,
  84                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  85                                       RTE_COMP_FF_CRC32_CHECKSUM |
  86                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  87                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
  88         },
  89         {
  90                 .algo = RTE_COMP_ALGO_DEFLATE,
  91                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  92                                       RTE_COMP_FF_CRC32_CHECKSUM |
  93                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  94                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
  95                                       RTE_COMP_FF_HUFFMAN_FIXED |
  96                                       RTE_COMP_FF_HUFFMAN_DYNAMIC,
  97                 .window_size = {.min = 10, .max = 15, .increment = 1},
  98         },
  99         {
 100                 .algo = RTE_COMP_ALGO_LIST_END,
 101         }
 102 };
 103
 104 static void
 105 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
 106                            struct rte_compressdev_info *info)
 107 {
 108         RTE_SET_USED(dev);
 109         if (info != NULL) {
 110                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
 111                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 112                 info->capabilities = mlx5_caps;
 113         }
 114 }
 115
 116 static int
 117 mlx5_compress_dev_configure(struct rte_compressdev *dev,
 118                             struct rte_compressdev_config *config)
 119 {
 120         struct mlx5_compress_priv *priv;
 121
 122         if (dev == NULL || config == NULL)
 123                 return -EINVAL;
 124         priv = dev->data->dev_private;
 125         priv->dev_config = *config;
 126         return 0;
 127 }
 128
 129 static int
 130 mlx5_compress_dev_close(struct rte_compressdev *dev)
 131 {
 132         RTE_SET_USED(dev);
 133         return 0;
 134 }
 135
 136 static int
 137 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 138 {
 139         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 140
 141         if (qp->qp.qp != NULL)
 142                 mlx5_devx_qp_destroy(&qp->qp);
 143         if (qp->cq.cq != NULL)
 144                 mlx5_devx_cq_destroy(&qp->cq);
 145         if (qp->opaque_mr.obj != NULL) {
 146                 void *opaq = qp->opaque_mr.addr;
 147
 148                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 149                 if (opaq != NULL)
 150                         rte_free(opaq);
 151         }
 152         mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 153         rte_free(qp);
 154         dev->data->queue_pairs[qp_id] = NULL;
 155         return 0;
 156 }
 157
 158 static void
 159 mlx5_compress_init_qp(struct mlx5_compress_qp *qp)
 160 {
 161         volatile struct mlx5_gga_wqe *restrict wqe =
 162                                     (volatile struct mlx5_gga_wqe *)qp->qp.wqes;
 163         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 164         const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);
 165         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 166                                         MLX5_COMP_MODE_OFFSET);
 167         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 168         int i;
 169
 170         /* All the next fields state should stay constant. */
 171         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 172                 wqe->sq_ds = sq_ds;
 173                 wqe->flags = flags;
 174                 wqe->opaque_lkey = opaq_lkey;
 175                 wqe->opaque_vaddr = rte_cpu_to_be_64
 176                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 177         }
 178 }
 179
 180 static int
 181 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 182                        uint32_t max_inflight_ops, int socket_id)
 183 {
 184         struct mlx5_compress_priv *priv = dev->data->dev_private;
 185         struct mlx5_compress_qp *qp;
 186         struct mlx5_devx_cq_attr cq_attr = {
 187                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),
 188         };
 189         struct mlx5_devx_qp_attr qp_attr = {
 190                 .pd = priv->cdev->pdn,
 191                 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar),
 192                 .user_index = qp_id,
 193         };
 194         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 195         uint32_t alloc_size = sizeof(*qp);
 196         void *opaq_buf;
 197         int ret;
 198
 199         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 200         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 201         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 202                                 socket_id);
 203         if (qp == NULL) {
 204                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 205                 rte_errno = ENOMEM;
 206                 return -rte_errno;
 207         }
 208         dev->data->queue_pairs[qp_id] = qp;
 209         if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->mr_scache.dev_gen,
 210                               priv->dev_config.socket_id)) {
 211                 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
 212                         (uint32_t)qp_id);
 213                 rte_errno = ENOMEM;
 214                 goto err;
 215         }
 216         opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,
 217                               sizeof(struct mlx5_gga_compress_opaque),
 218                               sizeof(struct mlx5_gga_compress_opaque));
 219         if (opaq_buf == NULL) {
 220                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 221                 rte_errno = ENOMEM;
 222                 goto err;
 223         }
 224         qp->entries_n = 1 << log_ops_n;
 225         qp->socket_id = socket_id;
 226         qp->qp_id = qp_id;
 227         qp->priv = priv;
 228         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 229                                                    RTE_CACHE_LINE_SIZE);
 230         if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n *
 231                                         sizeof(struct mlx5_gga_compress_opaque),
 232                                                          &qp->opaque_mr) != 0) {
 233                 rte_free(opaq_buf);
 234                 DRV_LOG(ERR, "Failed to register opaque MR.");
 235                 rte_errno = ENOMEM;
 236                 goto err;
 237         }
 238         ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr,
 239                                   socket_id);
 240         if (ret != 0) {
 241                 DRV_LOG(ERR, "Failed to create CQ.");
 242                 goto err;
 243         }
 244         qp_attr.cqn = qp->cq.cq->id;
 245         qp_attr.ts_format =
 246                 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
 247         qp_attr.rq_size = 0;
 248         qp_attr.sq_size = RTE_BIT32(log_ops_n);
 249         qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
 250                         && priv->mmo_dma_qp;
 251         ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp, log_ops_n, &qp_attr,
 252                                   socket_id);
 253         if (ret != 0) {
 254                 DRV_LOG(ERR, "Failed to create QP.");
 255                 goto err;
 256         }
 257         mlx5_compress_init_qp(qp);
 258         ret = mlx5_devx_qp2rts(&qp->qp, 0);
 259         if (ret)
 260                 goto err;
 261         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
 262                 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n);
 263         return 0;
 264 err:
 265         mlx5_compress_qp_release(dev, qp_id);
 266         return -1;
 267 }
 268
 269 static int
 270 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 271 {
 272         struct mlx5_compress_priv *priv = dev->data->dev_private;
 273
 274         rte_spinlock_lock(&priv->xform_sl);
 275         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 276         rte_spinlock_unlock(&priv->xform_sl);
 277         rte_free(xform);
 278         return 0;
 279 }
 280
 281 static int
 282 mlx5_compress_xform_create(struct rte_compressdev *dev,
 283                            const struct rte_comp_xform *xform,
 284                            void **private_xform)
 285 {
 286         struct mlx5_compress_priv *priv = dev->data->dev_private;
 287         struct mlx5_compress_xform *xfrm;
 288         uint32_t size;
 289
 290         if (xform->type == RTE_COMP_COMPRESS && xform->compress.level ==
 291                                                           RTE_COMP_LEVEL_NONE) {
 292                 DRV_LOG(ERR, "Non-compressed block is not supported.");
 293                 return -ENOTSUP;
 294         }
 295         if ((xform->type == RTE_COMP_COMPRESS && xform->compress.hash_algo !=
 296              RTE_COMP_HASH_ALGO_NONE) || (xform->type == RTE_COMP_DECOMPRESS &&
 297                       xform->decompress.hash_algo != RTE_COMP_HASH_ALGO_NONE)) {
 298                 DRV_LOG(ERR, "SHA is not supported.");
 299                 return -ENOTSUP;
 300         }
 301         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 302                                                     priv->dev_config.socket_id);
 303         if (xfrm == NULL)
 304                 return -ENOMEM;
 305         xfrm->opcode = MLX5_OPCODE_MMO;
 306         xfrm->type = xform->type;
 307         switch (xform->type) {
 308         case RTE_COMP_COMPRESS:
 309                 switch (xform->compress.algo) {
 310                 case RTE_COMP_ALGO_NULL:
 311                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 312                                                         WQE_CSEG_OPC_MOD_OFFSET;
 313                         break;
 314                 case RTE_COMP_ALGO_DEFLATE:
 315                         size = 1 << xform->compress.window_size;
 316                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 317                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 318                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 319                                                 WQE_GGA_COMP_WIN_SIZE_OFFSET;
 320                         switch (xform->compress.level) {
 321                         case RTE_COMP_LEVEL_PMD_DEFAULT:
 322                                 size = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 323                                 break;
 324                         case RTE_COMP_LEVEL_MAX:
 325                                 size = priv->min_block_size;
 326                                 break;
 327                         default:
 328                                 size = RTE_MAX(MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX
 329                                         + 1 - xform->compress.level,
 330                                         priv->min_block_size);
 331                         }
 332                         xfrm->gga_ctrl1 += RTE_MIN(size,
 333                                             MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX) <<
 334                                                  WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 335                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 336                                                         WQE_CSEG_OPC_MOD_OFFSET;
 337                         size = xform->compress.deflate.huffman ==
 338                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 339                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 340                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 341                         xfrm->gga_ctrl1 += size <<
 342                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 343                         break;
 344                 default:
 345                         goto err;
 346                 }
 347                 xfrm->csum_type = xform->compress.chksum;
 348                 break;
 349         case RTE_COMP_DECOMPRESS:
 350                 switch (xform->decompress.algo) {
 351                 case RTE_COMP_ALGO_NULL:
 352                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 353                                                         WQE_CSEG_OPC_MOD_OFFSET;
 354                         break;
 355                 case RTE_COMP_ALGO_DEFLATE:
 356                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 357                                                         WQE_CSEG_OPC_MOD_OFFSET;
 358                         break;
 359                 default:
 360                         goto err;
 361                 }
 362                 xfrm->csum_type = xform->decompress.chksum;
 363                 break;
 364         default:
 365                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 366                 goto err;
 367         }
 368         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 369                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 370         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 371         rte_spinlock_lock(&priv->xform_sl);
 372         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 373         rte_spinlock_unlock(&priv->xform_sl);
 374         *private_xform = xfrm;
 375         return 0;
 376 err:
 377         rte_free(xfrm);
 378         return -ENOTSUP;
 379 }
 380
 381 static void
 382 mlx5_compress_dev_stop(struct rte_compressdev *dev)
 383 {
 384         RTE_SET_USED(dev);
 385 }
 386
 387 static int
 388 mlx5_compress_dev_start(struct rte_compressdev *dev)
 389 {
 390         RTE_SET_USED(dev);
 391         return 0;
 392 }
 393
 394 static void
 395 mlx5_compress_stats_get(struct rte_compressdev *dev,
 396                 struct rte_compressdev_stats *stats)
 397 {
 398         int qp_id;
 399
 400         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 401                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 402
 403                 stats->enqueued_count += qp->stats.enqueued_count;
 404                 stats->dequeued_count += qp->stats.dequeued_count;
 405                 stats->enqueue_err_count += qp->stats.enqueue_err_count;
 406                 stats->dequeue_err_count += qp->stats.dequeue_err_count;
 407         }
 408 }
 409
 410 static void
 411 mlx5_compress_stats_reset(struct rte_compressdev *dev)
 412 {
 413         int qp_id;
 414
 415         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 416                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 417
 418                 memset(&qp->stats, 0, sizeof(qp->stats));
 419         }
 420 }
 421
 422 static struct rte_compressdev_ops mlx5_compress_ops = {
 423         .dev_configure          = mlx5_compress_dev_configure,
 424         .dev_start              = mlx5_compress_dev_start,
 425         .dev_stop               = mlx5_compress_dev_stop,
 426         .dev_close              = mlx5_compress_dev_close,
 427         .dev_infos_get          = mlx5_compress_dev_info_get,
 428         .stats_get              = mlx5_compress_stats_get,
 429         .stats_reset            = mlx5_compress_stats_reset,
 430         .queue_pair_setup       = mlx5_compress_qp_setup,
 431         .queue_pair_release     = mlx5_compress_qp_release,
 432         .private_xform_create   = mlx5_compress_xform_create,
 433         .private_xform_free     = mlx5_compress_xform_free,
 434         .stream_create          = NULL,
 435         .stream_free            = NULL,
 436 };
 437
 438 static __rte_always_inline uint32_t
 439 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
 440                        volatile struct mlx5_wqe_dseg *restrict dseg,
 441                        struct rte_mbuf *restrict mbuf,
 442                        uint32_t offset, uint32_t len)
 443 {
 444         uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
 445
 446         dseg->bcount = rte_cpu_to_be_32(len);
 447         dseg->lkey = mlx5_mr_mb2mr(qp->priv->cdev, 0, &qp->mr_ctrl, mbuf,
 448                                    &qp->priv->mr_scache);
 449         dseg->pbuf = rte_cpu_to_be_64(addr);
 450         return dseg->lkey;
 451 }
 452
 453 /*
 454  * Provide safe 64bit store operation to mlx5 UAR region for both 32bit and
 455  * 64bit architectures.
 456  */
 457 static __rte_always_inline void
 458 mlx5_compress_uar_write(uint64_t val, struct mlx5_compress_priv *priv)
 459 {
 460 #ifdef RTE_ARCH_64
 461         *priv->uar_addr = val;
 462 #else /* !RTE_ARCH_64 */
 463         rte_spinlock_lock(&priv->uar32_sl);
 464         *(volatile uint32_t *)priv->uar_addr = val;
 465         rte_io_wmb();
 466         *((volatile uint32_t *)priv->uar_addr + 1) = val >> 32;
 467         rte_spinlock_unlock(&priv->uar32_sl);
 468 #endif
 469 }
 470
 471 static uint16_t
 472 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
 473                             uint16_t nb_ops)
 474 {
 475         struct mlx5_compress_qp *qp = queue_pair;
 476         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 477                                                               qp->qp.wqes, *wqe;
 478         struct mlx5_compress_xform *xform;
 479         struct rte_comp_op *op;
 480         uint16_t mask = qp->entries_n - 1;
 481         uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
 482         uint16_t idx;
 483         bool invalid;
 484
 485         if (remain < nb_ops)
 486                 nb_ops = remain;
 487         else
 488                 remain = nb_ops;
 489         if (unlikely(remain == 0))
 490                 return 0;
 491         do {
 492                 idx = qp->pi & mask;
 493                 wqe = &wqes[idx];
 494                 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
 495                 op = *ops++;
 496                 xform = op->private_xform;
 497                 /*
 498                  * Check operation arguments and error cases:
 499                  *   - Operation type must be state-less.
 500                  *   - Compress operation flush flag must be FULL or FINAL.
 501                  *   - Source and destination buffers must be mapped internally.
 502                  */
 503                 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
 504                                             (xform->type == RTE_COMP_COMPRESS &&
 505                                           op->flush_flag < RTE_COMP_FLUSH_FULL);
 506                 if (unlikely(invalid ||
 507                              (mlx5_compress_dseg_set(qp, &wqe->gather,
 508                                                      op->m_src,
 509                                                      op->src.offset,
 510                                                      op->src.length) ==
 511                                                                   UINT32_MAX) ||
 512                              (mlx5_compress_dseg_set(qp, &wqe->scatter,
 513                                                 op->m_dst,
 514                                                 op->dst.offset,
 515                                                 rte_pktmbuf_pkt_len(op->m_dst) -
 516                                                               op->dst.offset) ==
 517                                                                  UINT32_MAX))) {
 518                         op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
 519                                                        RTE_COMP_OP_STATUS_ERROR;
 520                         nb_ops -= remain;
 521                         if (unlikely(nb_ops == 0))
 522                                 return 0;
 523                         break;
 524                 }
 525                 wqe->gga_ctrl1 = xform->gga_ctrl1;
 526                 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
 527                 qp->ops[idx] = op;
 528                 qp->pi++;
 529         } while (--remain);
 530         qp->stats.enqueued_count += nb_ops;
 531         rte_io_wmb();
 532         qp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);
 533         rte_wmb();
 534         mlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);
 535         rte_wmb();
 536         return nb_ops;
 537 }
 538
 539 static void
 540 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
 541                              volatile uint32_t *opaq)
 542 {
 543         size_t i;
 544
 545         DRV_LOG(ERR, "Error cqe:");
 546         for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
 547                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 548                         cqe[i + 2], cqe[i + 3]);
 549         DRV_LOG(ERR, "\nError wqe:");
 550         for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
 551                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 552                         wqe[i + 2], wqe[i + 3]);
 553         DRV_LOG(ERR, "\nError opaq:");
 554         for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
 555                 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
 556                         opaq[i + 2], opaq[i + 3]);
 557 }
 558
 559 static void
 560 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
 561                              struct rte_comp_op *op)
 562 {
 563         const uint32_t idx = qp->ci & (qp->entries_n - 1);
 564         volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
 565                                                               &qp->cq.cqes[idx];
 566         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 567                                                                     qp->qp.wqes;
 568         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 569
 570         op->status = RTE_COMP_OP_STATUS_ERROR;
 571         op->consumed = 0;
 572         op->produced = 0;
 573         op->output_chksum = 0;
 574         op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
 575                               ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
 576         mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
 577                                  (volatile uint32_t *)&wqes[idx],
 578                                  (volatile uint32_t *)&opaq[idx]);
 579         qp->stats.dequeue_err_count++;
 580 }
 581
 582 static uint16_t
 583 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 584                             uint16_t nb_ops)
 585 {
 586         struct mlx5_compress_qp *qp = queue_pair;
 587         volatile struct mlx5_compress_xform *restrict xform;
 588         volatile struct mlx5_cqe *restrict cqe;
 589         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 590         struct rte_comp_op *restrict op;
 591         const unsigned int cq_size = qp->entries_n;
 592         const unsigned int mask = cq_size - 1;
 593         uint32_t idx;
 594         uint32_t next_idx = qp->ci & mask;
 595         const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
 596         uint16_t i = 0;
 597         int ret;
 598
 599         if (unlikely(max == 0))
 600                 return 0;
 601         do {
 602                 idx = next_idx;
 603                 next_idx = (qp->ci + 1) & mask;
 604                 rte_prefetch0(&qp->cq.cqes[next_idx]);
 605                 rte_prefetch0(qp->ops[next_idx]);
 606                 op = qp->ops[idx];
 607                 cqe = &qp->cq.cqes[idx];
 608                 ret = check_cqe(cqe, cq_size, qp->ci);
 609                 /*
 610                  * Be sure owner read is done before any other cookie field or
 611                  * opaque field.
 612                  */
 613                 rte_io_rmb();
 614                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 615                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 616                                 break;
 617                         mlx5_compress_cqe_err_handle(qp, op);
 618                 } else {
 619                         xform = op->private_xform;
 620                         op->status = RTE_COMP_OP_STATUS_SUCCESS;
 621                         op->consumed = op->src.length;
 622                         op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
 623                         MLX5_ASSERT(cqe->byte_cnt ==
 624                                     opaq[idx].scattered_length);
 625                         switch (xform->csum_type) {
 626                         case RTE_COMP_CHECKSUM_CRC32:
 627                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 628                                                     (opaq[idx].crc32);
 629                                 break;
 630                         case RTE_COMP_CHECKSUM_ADLER32:
 631                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 632                                             (opaq[idx].adler32) << 32;
 633                                 break;
 634                         case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 635                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 636                                                              (opaq[idx].crc32) |
 637                                                      ((uint64_t)rte_be_to_cpu_32
 638                                                      (opaq[idx].adler32) << 32);
 639                                 break;
 640                         default:
 641                                 break;
 642                         }
 643                 }
 644                 ops[i++] = op;
 645                 qp->ci++;
 646         } while (i < max);
 647         if (likely(i != 0)) {
 648                 rte_io_wmb();
 649                 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
 650                 qp->stats.dequeued_count += i;
 651         }
 652         return i;
 653 }
 654
 655 static void
 656 mlx5_compress_uar_release(struct mlx5_compress_priv *priv)
 657 {
 658         if (priv->uar != NULL) {
 659                 mlx5_glue->devx_free_uar(priv->uar);
 660                 priv->uar = NULL;
 661         }
 662 }
 663
 664 static int
 665 mlx5_compress_uar_prepare(struct mlx5_compress_priv *priv)
 666 {
 667         priv->uar = mlx5_devx_alloc_uar(priv->cdev->ctx, -1);
 668         if (priv->uar == NULL || mlx5_os_get_devx_uar_reg_addr(priv->uar) ==
 669             NULL) {
 670                 rte_errno = errno;
 671                 DRV_LOG(ERR, "Failed to allocate UAR.");
 672                 return -1;
 673         }
 674         priv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);
 675         MLX5_ASSERT(priv->uar_addr);
 676 #ifndef RTE_ARCH_64
 677         rte_spinlock_init(&priv->uar32_sl);
 678 #endif /* RTE_ARCH_64 */
 679         return 0;
 680 }
 681
 682 /**
 683  * Callback for memory event.
 684  *
 685  * @param event_type
 686  *   Memory event type.
 687  * @param addr
 688  *   Address of memory.
 689  * @param len
 690  *   Size of memory.
 691  */
 692 static void
 693 mlx5_compress_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,
 694                               size_t len, void *arg __rte_unused)
 695 {
 696         struct mlx5_compress_priv *priv;
 697
 698         /* Must be called from the primary process. */
 699         MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);
 700         switch (event_type) {
 701         case RTE_MEM_EVENT_FREE:
 702                 pthread_mutex_lock(&priv_list_lock);
 703                 /* Iterate all the existing mlx5 devices. */
 704                 TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 705                         mlx5_free_mr_by_addr(&priv->mr_scache,
 706                                              mlx5_os_get_ctx_device_name
 707                                                               (priv->cdev->ctx),
 708                                              addr, len);
 709                 pthread_mutex_unlock(&priv_list_lock);
 710                 break;
 711         case RTE_MEM_EVENT_ALLOC:
 712         default:
 713                 break;
 714         }
 715 }
 716
 717 static int
 718 mlx5_compress_dev_probe(struct mlx5_common_device *cdev)
 719 {
 720         struct rte_compressdev *compressdev;
 721         struct mlx5_compress_priv *priv;
 722         struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
 723         struct rte_compressdev_pmd_init_params init_params = {
 724                 .name = "",
 725                 .socket_id = cdev->dev->numa_node,
 726         };
 727         const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
 728
 729         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 730                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 731                 rte_errno = ENOTSUP;
 732                 return -rte_errno;
 733         }
 734         if ((attr->mmo_compress_sq_en == 0 || attr->mmo_decompress_sq_en == 0 ||
 735             attr->mmo_dma_sq_en == 0) && (attr->mmo_compress_qp_en == 0 ||
 736             attr->mmo_decompress_qp_en == 0 || attr->mmo_dma_qp_en == 0)) {
 737                 DRV_LOG(ERR, "Not enough capabilities to support compress "
 738                         "operations, maybe old FW/OFED version?");
 739                 rte_errno = ENOTSUP;
 740                 return -ENOTSUP;
 741         }
 742         compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev,
 743                                                  sizeof(*priv), &init_params);
 744         if (compressdev == NULL) {
 745                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name);
 746                 return -ENODEV;
 747         }
 748         DRV_LOG(INFO,
 749                 "Compress device %s was created successfully.", ibdev_name);
 750         compressdev->dev_ops = &mlx5_compress_ops;
 751         compressdev->dequeue_burst = mlx5_compress_dequeue_burst;
 752         compressdev->enqueue_burst = mlx5_compress_enqueue_burst;
 753         compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 754         priv = compressdev->data->dev_private;
 755         priv->mmo_decomp_sq = attr->mmo_decompress_sq_en;
 756         priv->mmo_decomp_qp = attr->mmo_decompress_qp_en;
 757         priv->mmo_comp_sq = attr->mmo_compress_sq_en;
 758         priv->mmo_comp_qp = attr->mmo_compress_qp_en;
 759         priv->mmo_dma_sq = attr->mmo_dma_sq_en;
 760         priv->mmo_dma_qp = attr->mmo_dma_qp_en;
 761         priv->cdev = cdev;
 762         priv->compressdev = compressdev;
 763         priv->min_block_size = attr->compress_min_block_size;
 764         if (mlx5_compress_uar_prepare(priv) != 0) {
 765                 rte_compressdev_pmd_destroy(priv->compressdev);
 766                 return -1;
 767         }
 768         if (mlx5_mr_create_cache(&priv->mr_scache, rte_socket_id()) != 0) {
 769                 DRV_LOG(ERR, "Failed to allocate shared cache MR memory.");
 770                 mlx5_compress_uar_release(priv);
 771                 rte_compressdev_pmd_destroy(priv->compressdev);
 772                 rte_errno = ENOMEM;
 773                 return -rte_errno;
 774         }
 775         /* Register callback function for global shared MR cache management. */
 776         if (TAILQ_EMPTY(&mlx5_compress_priv_list))
 777                 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
 778                                                 mlx5_compress_mr_mem_event_cb,
 779                                                 NULL);
 780         pthread_mutex_lock(&priv_list_lock);
 781         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 782         pthread_mutex_unlock(&priv_list_lock);
 783         return 0;
 784 }
 785
 786 static int
 787 mlx5_compress_dev_remove(struct mlx5_common_device *cdev)
 788 {
 789         struct mlx5_compress_priv *priv = NULL;
 790
 791         pthread_mutex_lock(&priv_list_lock);
 792         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 793                 if (priv->compressdev->device == cdev->dev)
 794                         break;
 795         if (priv)
 796                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 797         pthread_mutex_unlock(&priv_list_lock);
 798         if (priv) {
 799                 if (TAILQ_EMPTY(&mlx5_compress_priv_list))
 800                         rte_mem_event_callback_unregister("MLX5_MEM_EVENT_CB",
 801                                                           NULL);
 802                 mlx5_mr_release_cache(&priv->mr_scache);
 803                 mlx5_compress_uar_release(priv);
 804                 rte_compressdev_pmd_destroy(priv->compressdev);
 805         }
 806         return 0;
 807 }
 808
 809 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 810         {
 811                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 812                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 813         },
 814         {
 815                 .vendor_id = 0
 816         }
 817 };
 818
 819 static struct mlx5_class_driver mlx5_compress_driver = {
 820         .drv_class = MLX5_CLASS_COMPRESS,
 821         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 822         .id_table = mlx5_compress_pci_id_map,
 823         .probe = mlx5_compress_dev_probe,
 824         .remove = mlx5_compress_dev_remove,
 825 };
 826
 827 RTE_INIT(rte_mlx5_compress_init)
 828 {
 829         mlx5_common_init();
 830         if (mlx5_glue != NULL)
 831                 mlx5_class_driver_register(&mlx5_compress_driver);
 832 }
 833
 834 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE)
 835 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 836 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 837 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");