drivers/compress/mlx5/mlx5_compress.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright 2021 Mellanox Technologies, Ltd
   3  */
   4
   5 #include <rte_malloc.h>
   6 #include <rte_log.h>
   7 #include <rte_errno.h>
   8 #include <rte_bus_pci.h>
   9 #include <rte_spinlock.h>
  10 #include <rte_comp.h>
  11 #include <rte_compressdev.h>
  12 #include <rte_compressdev_pmd.h>
  13
  14 #include <mlx5_glue.h>
  15 #include <mlx5_common.h>
  16 #include <mlx5_devx_cmds.h>
  17 #include <mlx5_common_os.h>
  18 #include <mlx5_common_devx.h>
  19 #include <mlx5_common_mr.h>
  20 #include <mlx5_prm.h>
  21
  22 #include "mlx5_compress_utils.h"
  23
  24 #define MLX5_COMPRESS_DRIVER_NAME mlx5_compress
  25 #define MLX5_COMPRESS_MAX_QPS 1024
  26 #define MLX5_COMP_MAX_WIN_SIZE_CONF 6u
  27
  28 struct mlx5_compress_devarg_params {
  29         uint32_t log_block_sz;
  30 };
  31
  32 struct mlx5_compress_xform {
  33         LIST_ENTRY(mlx5_compress_xform) next;
  34         enum rte_comp_xform_type type;
  35         enum rte_comp_checksum_type csum_type;
  36         uint32_t opcode;
  37         uint32_t gga_ctrl1; /* BE. */
  38 };
  39
  40 struct mlx5_compress_priv {
  41         TAILQ_ENTRY(mlx5_compress_priv) next;
  42         struct rte_compressdev *compressdev;
  43         struct mlx5_common_device *cdev; /* Backend mlx5 device. */
  44         struct mlx5_uar uar;
  45         uint8_t min_block_size;
  46         /* Minimum huffman block size supported by the device. */
  47         struct rte_compressdev_config dev_config;
  48         LIST_HEAD(xform_list, mlx5_compress_xform) xform_list;
  49         rte_spinlock_t xform_sl;
  50         /* HCA caps */
  51         uint32_t mmo_decomp_sq:1;
  52         uint32_t mmo_decomp_qp:1;
  53         uint32_t mmo_comp_sq:1;
  54         uint32_t mmo_comp_qp:1;
  55         uint32_t mmo_dma_sq:1;
  56         uint32_t mmo_dma_qp:1;
  57         uint32_t log_block_sz;
  58 };
  59
  60 struct mlx5_compress_qp {
  61         uint16_t qp_id;
  62         uint16_t entries_n;
  63         uint16_t pi;
  64         uint16_t ci;
  65         struct mlx5_mr_ctrl mr_ctrl;
  66         int socket_id;
  67         struct mlx5_devx_cq cq;
  68         struct mlx5_devx_qp qp;
  69         struct mlx5_pmd_mr opaque_mr;
  70         struct rte_comp_op **ops;
  71         struct mlx5_compress_priv *priv;
  72         struct rte_compressdev_stats stats;
  73 };
  74
  75 TAILQ_HEAD(mlx5_compress_privs, mlx5_compress_priv) mlx5_compress_priv_list =
  76                                 TAILQ_HEAD_INITIALIZER(mlx5_compress_priv_list);
  77 static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;
  78
  79 int mlx5_compress_logtype;
  80
  81 static const struct rte_compressdev_capabilities mlx5_caps[] = {
  82         {
  83                 .algo = RTE_COMP_ALGO_NULL,
  84                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  85                                       RTE_COMP_FF_CRC32_CHECKSUM |
  86                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  87                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM,
  88         },
  89         {
  90                 .algo = RTE_COMP_ALGO_DEFLATE,
  91                 .comp_feature_flags = RTE_COMP_FF_ADLER32_CHECKSUM |
  92                                       RTE_COMP_FF_CRC32_CHECKSUM |
  93                                       RTE_COMP_FF_CRC32_ADLER32_CHECKSUM |
  94                                       RTE_COMP_FF_SHAREABLE_PRIV_XFORM |
  95                                       RTE_COMP_FF_HUFFMAN_FIXED |
  96                                       RTE_COMP_FF_HUFFMAN_DYNAMIC,
  97                 .window_size = {.min = 10, .max = 15, .increment = 1},
  98         },
  99         {
 100                 .algo = RTE_COMP_ALGO_LIST_END,
 101         }
 102 };
 103
 104 static void
 105 mlx5_compress_dev_info_get(struct rte_compressdev *dev,
 106                            struct rte_compressdev_info *info)
 107 {
 108         RTE_SET_USED(dev);
 109         if (info != NULL) {
 110                 info->max_nb_queue_pairs = MLX5_COMPRESS_MAX_QPS;
 111                 info->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 112                 info->capabilities = mlx5_caps;
 113         }
 114 }
 115
 116 static int
 117 mlx5_compress_dev_configure(struct rte_compressdev *dev,
 118                             struct rte_compressdev_config *config)
 119 {
 120         struct mlx5_compress_priv *priv;
 121
 122         if (dev == NULL || config == NULL)
 123                 return -EINVAL;
 124         priv = dev->data->dev_private;
 125         priv->dev_config = *config;
 126         return 0;
 127 }
 128
 129 static int
 130 mlx5_compress_dev_close(struct rte_compressdev *dev)
 131 {
 132         RTE_SET_USED(dev);
 133         return 0;
 134 }
 135
 136 static int
 137 mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)
 138 {
 139         struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 140
 141         if (qp->qp.qp != NULL)
 142                 mlx5_devx_qp_destroy(&qp->qp);
 143         if (qp->cq.cq != NULL)
 144                 mlx5_devx_cq_destroy(&qp->cq);
 145         if (qp->opaque_mr.obj != NULL) {
 146                 void *opaq = qp->opaque_mr.addr;
 147
 148                 mlx5_common_verbs_dereg_mr(&qp->opaque_mr);
 149                 if (opaq != NULL)
 150                         rte_free(opaq);
 151         }
 152         mlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);
 153         rte_free(qp);
 154         dev->data->queue_pairs[qp_id] = NULL;
 155         return 0;
 156 }
 157
 158 static void
 159 mlx5_compress_init_qp(struct mlx5_compress_qp *qp)
 160 {
 161         volatile struct mlx5_gga_wqe *restrict wqe =
 162                                     (volatile struct mlx5_gga_wqe *)qp->qp.wqes;
 163         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 164         const uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);
 165         const uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<
 166                                         MLX5_COMP_MODE_OFFSET);
 167         const uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);
 168         int i;
 169
 170         /* All the next fields state should stay constant. */
 171         for (i = 0; i < qp->entries_n; ++i, ++wqe) {
 172                 wqe->sq_ds = sq_ds;
 173                 wqe->flags = flags;
 174                 wqe->opaque_lkey = opaq_lkey;
 175                 wqe->opaque_vaddr = rte_cpu_to_be_64
 176                                                 ((uint64_t)(uintptr_t)&opaq[i]);
 177         }
 178 }
 179
 180 static int
 181 mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,
 182                        uint32_t max_inflight_ops, int socket_id)
 183 {
 184         struct mlx5_compress_priv *priv = dev->data->dev_private;
 185         struct mlx5_compress_qp *qp;
 186         struct mlx5_devx_cq_attr cq_attr = {
 187                 .uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar.obj),
 188         };
 189         struct mlx5_devx_qp_attr qp_attr = {
 190                 .pd = priv->cdev->pdn,
 191                 .uar_index = mlx5_os_get_devx_uar_page_id(priv->uar.obj),
 192                 .user_index = qp_id,
 193         };
 194         uint32_t log_ops_n = rte_log2_u32(max_inflight_ops);
 195         uint32_t alloc_size = sizeof(*qp);
 196         void *opaq_buf;
 197         int ret;
 198
 199         alloc_size = RTE_ALIGN(alloc_size, RTE_CACHE_LINE_SIZE);
 200         alloc_size += sizeof(struct rte_comp_op *) * (1u << log_ops_n);
 201         qp = rte_zmalloc_socket(__func__, alloc_size, RTE_CACHE_LINE_SIZE,
 202                                 socket_id);
 203         if (qp == NULL) {
 204                 DRV_LOG(ERR, "Failed to allocate qp memory.");
 205                 rte_errno = ENOMEM;
 206                 return -rte_errno;
 207         }
 208         dev->data->queue_pairs[qp_id] = qp;
 209         if (mlx5_mr_ctrl_init(&qp->mr_ctrl, &priv->cdev->mr_scache.dev_gen,
 210                               priv->dev_config.socket_id)) {
 211                 DRV_LOG(ERR, "Cannot allocate MR Btree for qp %u.",
 212                         (uint32_t)qp_id);
 213                 rte_errno = ENOMEM;
 214                 goto err;
 215         }
 216         opaq_buf = rte_calloc(__func__, (size_t)1 << log_ops_n,
 217                               sizeof(struct mlx5_gga_compress_opaque),
 218                               sizeof(struct mlx5_gga_compress_opaque));
 219         if (opaq_buf == NULL) {
 220                 DRV_LOG(ERR, "Failed to allocate opaque memory.");
 221                 rte_errno = ENOMEM;
 222                 goto err;
 223         }
 224         qp->entries_n = 1 << log_ops_n;
 225         qp->socket_id = socket_id;
 226         qp->qp_id = qp_id;
 227         qp->priv = priv;
 228         qp->ops = (struct rte_comp_op **)RTE_ALIGN((uintptr_t)(qp + 1),
 229                                                    RTE_CACHE_LINE_SIZE);
 230         if (mlx5_common_verbs_reg_mr(priv->cdev->pd, opaq_buf, qp->entries_n *
 231                                         sizeof(struct mlx5_gga_compress_opaque),
 232                                                          &qp->opaque_mr) != 0) {
 233                 rte_free(opaq_buf);
 234                 DRV_LOG(ERR, "Failed to register opaque MR.");
 235                 rte_errno = ENOMEM;
 236                 goto err;
 237         }
 238         ret = mlx5_devx_cq_create(priv->cdev->ctx, &qp->cq, log_ops_n, &cq_attr,
 239                                   socket_id);
 240         if (ret != 0) {
 241                 DRV_LOG(ERR, "Failed to create CQ.");
 242                 goto err;
 243         }
 244         qp_attr.cqn = qp->cq.cq->id;
 245         qp_attr.ts_format =
 246                 mlx5_ts_format_conv(priv->cdev->config.hca_attr.qp_ts_format);
 247         qp_attr.num_of_receive_wqes = 0;
 248         qp_attr.num_of_send_wqbbs = RTE_BIT32(log_ops_n);
 249         qp_attr.mmo = priv->mmo_decomp_qp && priv->mmo_comp_qp
 250                         && priv->mmo_dma_qp;
 251         ret = mlx5_devx_qp_create(priv->cdev->ctx, &qp->qp,
 252                                         qp_attr.num_of_send_wqbbs *
 253                                         MLX5_WQE_SIZE, &qp_attr, socket_id);
 254         if (ret != 0) {
 255                 DRV_LOG(ERR, "Failed to create QP.");
 256                 goto err;
 257         }
 258         mlx5_compress_init_qp(qp);
 259         ret = mlx5_devx_qp2rts(&qp->qp, 0);
 260         if (ret)
 261                 goto err;
 262         DRV_LOG(INFO, "QP %u: SQN=0x%X CQN=0x%X entries num = %u",
 263                 (uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n);
 264         return 0;
 265 err:
 266         mlx5_compress_qp_release(dev, qp_id);
 267         return -1;
 268 }
 269
 270 static int
 271 mlx5_compress_xform_free(struct rte_compressdev *dev, void *xform)
 272 {
 273         struct mlx5_compress_priv *priv = dev->data->dev_private;
 274
 275         rte_spinlock_lock(&priv->xform_sl);
 276         LIST_REMOVE((struct mlx5_compress_xform *)xform, next);
 277         rte_spinlock_unlock(&priv->xform_sl);
 278         rte_free(xform);
 279         return 0;
 280 }
 281
 282 static int
 283 mlx5_compress_xform_create(struct rte_compressdev *dev,
 284                            const struct rte_comp_xform *xform,
 285                            void **private_xform)
 286 {
 287         struct mlx5_compress_priv *priv = dev->data->dev_private;
 288         struct mlx5_compress_xform *xfrm;
 289         uint32_t size;
 290
 291         switch (xform->type) {
 292         case RTE_COMP_COMPRESS:
 293                 if (xform->compress.algo == RTE_COMP_ALGO_NULL &&
 294                                 !priv->mmo_dma_qp && !priv->mmo_dma_sq) {
 295                         DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?");
 296                         return -ENOTSUP;
 297                 } else if (!priv->mmo_comp_qp && !priv->mmo_comp_sq) {
 298                         DRV_LOG(ERR, "Not enough capabilities to support compress operation, maybe old FW/OFED version?");
 299                         return -ENOTSUP;
 300                 }
 301                 if (xform->compress.level == RTE_COMP_LEVEL_NONE) {
 302                         DRV_LOG(ERR, "Non-compressed block is not supported.");
 303                         return -ENOTSUP;
 304                 }
 305                 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
 306                         DRV_LOG(ERR, "SHA is not supported.");
 307                         return -ENOTSUP;
 308                 }
 309                 break;
 310         case RTE_COMP_DECOMPRESS:
 311                 if (xform->decompress.algo == RTE_COMP_ALGO_NULL &&
 312                                 !priv->mmo_dma_qp && !priv->mmo_dma_sq) {
 313                         DRV_LOG(ERR, "Not enough capabilities to support DMA operation, maybe old FW/OFED version?");
 314                         return -ENOTSUP;
 315                 } else if (!priv->mmo_decomp_qp && !priv->mmo_decomp_sq) {
 316                         DRV_LOG(ERR, "Not enough capabilities to support decompress operation, maybe old FW/OFED version?");
 317                         return -ENOTSUP;
 318                 }
 319                 if (xform->compress.hash_algo != RTE_COMP_HASH_ALGO_NONE) {
 320                         DRV_LOG(ERR, "SHA is not supported.");
 321                         return -ENOTSUP;
 322                 }
 323                 break;
 324         default:
 325                 DRV_LOG(ERR, "Xform type should be compress/decompress");
 326                 return -ENOTSUP;
 327         }
 328
 329         xfrm = rte_zmalloc_socket(__func__, sizeof(*xfrm), 0,
 330                                                     priv->dev_config.socket_id);
 331         if (xfrm == NULL)
 332                 return -ENOMEM;
 333         xfrm->opcode = MLX5_OPCODE_MMO;
 334         xfrm->type = xform->type;
 335         switch (xform->type) {
 336         case RTE_COMP_COMPRESS:
 337                 switch (xform->compress.algo) {
 338                 case RTE_COMP_ALGO_NULL:
 339                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 340                                                         WQE_CSEG_OPC_MOD_OFFSET;
 341                         break;
 342                 case RTE_COMP_ALGO_DEFLATE:
 343                         size = 1 << xform->compress.window_size;
 344                         size /= MLX5_GGA_COMP_WIN_SIZE_UNITS;
 345                         xfrm->gga_ctrl1 += RTE_MIN(rte_log2_u32(size),
 346                                          MLX5_COMP_MAX_WIN_SIZE_CONF) <<
 347                                                 WQE_GGA_COMP_WIN_SIZE_OFFSET;
 348                         size = priv->log_block_sz;
 349                         xfrm->gga_ctrl1 += size <<
 350                                                 WQE_GGA_COMP_BLOCK_SIZE_OFFSET;
 351                         xfrm->opcode += MLX5_OPC_MOD_MMO_COMP <<
 352                                                         WQE_CSEG_OPC_MOD_OFFSET;
 353                         size = xform->compress.deflate.huffman ==
 354                                                       RTE_COMP_HUFFMAN_DYNAMIC ?
 355                                             MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MAX :
 356                                              MLX5_GGA_COMP_LOG_DYNAMIC_SIZE_MIN;
 357                         xfrm->gga_ctrl1 += size <<
 358                                                WQE_GGA_COMP_DYNAMIC_SIZE_OFFSET;
 359                         break;
 360                 default:
 361                         goto err;
 362                 }
 363                 xfrm->csum_type = xform->compress.chksum;
 364                 break;
 365         case RTE_COMP_DECOMPRESS:
 366                 switch (xform->decompress.algo) {
 367                 case RTE_COMP_ALGO_NULL:
 368                         xfrm->opcode += MLX5_OPC_MOD_MMO_DMA <<
 369                                                         WQE_CSEG_OPC_MOD_OFFSET;
 370                         break;
 371                 case RTE_COMP_ALGO_DEFLATE:
 372                         xfrm->opcode += MLX5_OPC_MOD_MMO_DECOMP <<
 373                                                         WQE_CSEG_OPC_MOD_OFFSET;
 374                         break;
 375                 default:
 376                         goto err;
 377                 }
 378                 xfrm->csum_type = xform->decompress.chksum;
 379                 break;
 380         default:
 381                 DRV_LOG(ERR, "Algorithm %u is not supported.", xform->type);
 382                 goto err;
 383         }
 384         DRV_LOG(DEBUG, "New xform: gga ctrl1 = 0x%08X opcode = 0x%08X csum "
 385                 "type = %d.", xfrm->gga_ctrl1, xfrm->opcode, xfrm->csum_type);
 386         xfrm->gga_ctrl1 = rte_cpu_to_be_32(xfrm->gga_ctrl1);
 387         rte_spinlock_lock(&priv->xform_sl);
 388         LIST_INSERT_HEAD(&priv->xform_list, xfrm, next);
 389         rte_spinlock_unlock(&priv->xform_sl);
 390         *private_xform = xfrm;
 391         return 0;
 392 err:
 393         rte_free(xfrm);
 394         return -ENOTSUP;
 395 }
 396
 397 static void
 398 mlx5_compress_dev_stop(struct rte_compressdev *dev)
 399 {
 400         RTE_SET_USED(dev);
 401 }
 402
 403 static int
 404 mlx5_compress_dev_start(struct rte_compressdev *dev)
 405 {
 406         struct mlx5_compress_priv *priv = dev->data->dev_private;
 407
 408         return mlx5_dev_mempool_subscribe(priv->cdev);
 409 }
 410
 411 static void
 412 mlx5_compress_stats_get(struct rte_compressdev *dev,
 413                 struct rte_compressdev_stats *stats)
 414 {
 415         int qp_id;
 416
 417         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 418                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 419
 420                 stats->enqueued_count += qp->stats.enqueued_count;
 421                 stats->dequeued_count += qp->stats.dequeued_count;
 422                 stats->enqueue_err_count += qp->stats.enqueue_err_count;
 423                 stats->dequeue_err_count += qp->stats.dequeue_err_count;
 424         }
 425 }
 426
 427 static void
 428 mlx5_compress_stats_reset(struct rte_compressdev *dev)
 429 {
 430         int qp_id;
 431
 432         for (qp_id = 0; qp_id < dev->data->nb_queue_pairs; qp_id++) {
 433                 struct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];
 434
 435                 memset(&qp->stats, 0, sizeof(qp->stats));
 436         }
 437 }
 438
 439 static struct rte_compressdev_ops mlx5_compress_ops = {
 440         .dev_configure          = mlx5_compress_dev_configure,
 441         .dev_start              = mlx5_compress_dev_start,
 442         .dev_stop               = mlx5_compress_dev_stop,
 443         .dev_close              = mlx5_compress_dev_close,
 444         .dev_infos_get          = mlx5_compress_dev_info_get,
 445         .stats_get              = mlx5_compress_stats_get,
 446         .stats_reset            = mlx5_compress_stats_reset,
 447         .queue_pair_setup       = mlx5_compress_qp_setup,
 448         .queue_pair_release     = mlx5_compress_qp_release,
 449         .private_xform_create   = mlx5_compress_xform_create,
 450         .private_xform_free     = mlx5_compress_xform_free,
 451         .stream_create          = NULL,
 452         .stream_free            = NULL,
 453 };
 454
 455 static __rte_always_inline uint32_t
 456 mlx5_compress_dseg_set(struct mlx5_compress_qp *qp,
 457                        volatile struct mlx5_wqe_dseg *restrict dseg,
 458                        struct rte_mbuf *restrict mbuf,
 459                        uint32_t offset, uint32_t len)
 460 {
 461         uintptr_t addr = rte_pktmbuf_mtod_offset(mbuf, uintptr_t, offset);
 462
 463         dseg->bcount = rte_cpu_to_be_32(len);
 464         dseg->lkey = mlx5_mr_mb2mr(&qp->mr_ctrl, mbuf);
 465         dseg->pbuf = rte_cpu_to_be_64(addr);
 466         return dseg->lkey;
 467 }
 468
 469 static uint16_t
 470 mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,
 471                             uint16_t nb_ops)
 472 {
 473         struct mlx5_compress_qp *qp = queue_pair;
 474         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 475                                                               qp->qp.wqes, *wqe;
 476         struct mlx5_compress_xform *xform;
 477         struct rte_comp_op *op;
 478         uint16_t mask = qp->entries_n - 1;
 479         uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
 480         uint16_t idx;
 481         bool invalid;
 482
 483         if (remain < nb_ops)
 484                 nb_ops = remain;
 485         else
 486                 remain = nb_ops;
 487         if (unlikely(remain == 0))
 488                 return 0;
 489         do {
 490                 idx = qp->pi & mask;
 491                 wqe = &wqes[idx];
 492                 rte_prefetch0(&wqes[(qp->pi + 1) & mask]);
 493                 op = *ops++;
 494                 xform = op->private_xform;
 495                 /*
 496                  * Check operation arguments and error cases:
 497                  *   - Operation type must be state-less.
 498                  *   - Compress operation flush flag must be FULL or FINAL.
 499                  *   - Source and destination buffers must be mapped internally.
 500                  */
 501                 invalid = op->op_type != RTE_COMP_OP_STATELESS ||
 502                                             (xform->type == RTE_COMP_COMPRESS &&
 503                                           op->flush_flag < RTE_COMP_FLUSH_FULL);
 504                 if (unlikely(invalid ||
 505                              (mlx5_compress_dseg_set(qp, &wqe->gather,
 506                                                      op->m_src,
 507                                                      op->src.offset,
 508                                                      op->src.length) ==
 509                                                                   UINT32_MAX) ||
 510                              (mlx5_compress_dseg_set(qp, &wqe->scatter,
 511                                                 op->m_dst,
 512                                                 op->dst.offset,
 513                                                 rte_pktmbuf_pkt_len(op->m_dst) -
 514                                                               op->dst.offset) ==
 515                                                                  UINT32_MAX))) {
 516                         op->status = invalid ? RTE_COMP_OP_STATUS_INVALID_ARGS :
 517                                                        RTE_COMP_OP_STATUS_ERROR;
 518                         nb_ops -= remain;
 519                         if (unlikely(nb_ops == 0))
 520                                 return 0;
 521                         break;
 522                 }
 523                 wqe->gga_ctrl1 = xform->gga_ctrl1;
 524                 wqe->opcode = rte_cpu_to_be_32(xform->opcode + (qp->pi << 8));
 525                 qp->ops[idx] = op;
 526                 qp->pi++;
 527         } while (--remain);
 528         qp->stats.enqueued_count += nb_ops;
 529         mlx5_doorbell_ring(&qp->priv->uar.bf_db, *(volatile uint64_t *)wqe,
 530                            qp->pi, &qp->qp.db_rec[MLX5_SND_DBR],
 531                            !qp->priv->uar.dbnc);
 532         return nb_ops;
 533 }
 534
 535 static void
 536 mlx5_compress_dump_err_objs(volatile uint32_t *cqe, volatile uint32_t *wqe,
 537                              volatile uint32_t *opaq)
 538 {
 539         size_t i;
 540
 541         DRV_LOG(ERR, "Error cqe:");
 542         for (i = 0; i < sizeof(struct mlx5_err_cqe) >> 2; i += 4)
 543                 DRV_LOG(ERR, "%08X %08X %08X %08X", cqe[i], cqe[i + 1],
 544                         cqe[i + 2], cqe[i + 3]);
 545         DRV_LOG(ERR, "\nError wqe:");
 546         for (i = 0; i < sizeof(struct mlx5_gga_wqe) >> 2; i += 4)
 547                 DRV_LOG(ERR, "%08X %08X %08X %08X", wqe[i], wqe[i + 1],
 548                         wqe[i + 2], wqe[i + 3]);
 549         DRV_LOG(ERR, "\nError opaq:");
 550         for (i = 0; i < sizeof(struct mlx5_gga_compress_opaque) >> 2; i += 4)
 551                 DRV_LOG(ERR, "%08X %08X %08X %08X", opaq[i], opaq[i + 1],
 552                         opaq[i + 2], opaq[i + 3]);
 553 }
 554
 555 static void
 556 mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,
 557                              struct rte_comp_op *op)
 558 {
 559         const uint32_t idx = qp->ci & (qp->entries_n - 1);
 560         volatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)
 561                                                               &qp->cq.cqes[idx];
 562         volatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)
 563                                                                     qp->qp.wqes;
 564         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 565
 566         op->status = RTE_COMP_OP_STATUS_ERROR;
 567         op->consumed = 0;
 568         op->produced = 0;
 569         op->output_chksum = 0;
 570         op->debug_status = rte_be_to_cpu_32(opaq[idx].syndrom) |
 571                               ((uint64_t)rte_be_to_cpu_32(cqe->syndrome) << 32);
 572         mlx5_compress_dump_err_objs((volatile uint32_t *)cqe,
 573                                  (volatile uint32_t *)&wqes[idx],
 574                                  (volatile uint32_t *)&opaq[idx]);
 575         qp->stats.dequeue_err_count++;
 576 }
 577
 578 static uint16_t
 579 mlx5_compress_dequeue_burst(void *queue_pair, struct rte_comp_op **ops,
 580                             uint16_t nb_ops)
 581 {
 582         struct mlx5_compress_qp *qp = queue_pair;
 583         volatile struct mlx5_compress_xform *restrict xform;
 584         volatile struct mlx5_cqe *restrict cqe;
 585         volatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;
 586         struct rte_comp_op *restrict op;
 587         const unsigned int cq_size = qp->entries_n;
 588         const unsigned int mask = cq_size - 1;
 589         uint32_t idx;
 590         uint32_t next_idx = qp->ci & mask;
 591         const uint16_t max = RTE_MIN((uint16_t)(qp->pi - qp->ci), nb_ops);
 592         uint16_t i = 0;
 593         int ret;
 594
 595         if (unlikely(max == 0))
 596                 return 0;
 597         do {
 598                 idx = next_idx;
 599                 next_idx = (qp->ci + 1) & mask;
 600                 rte_prefetch0(&qp->cq.cqes[next_idx]);
 601                 rte_prefetch0(qp->ops[next_idx]);
 602                 op = qp->ops[idx];
 603                 cqe = &qp->cq.cqes[idx];
 604                 ret = check_cqe(cqe, cq_size, qp->ci);
 605                 /*
 606                  * Be sure owner read is done before any other cookie field or
 607                  * opaque field.
 608                  */
 609                 rte_io_rmb();
 610                 if (unlikely(ret != MLX5_CQE_STATUS_SW_OWN)) {
 611                         if (likely(ret == MLX5_CQE_STATUS_HW_OWN))
 612                                 break;
 613                         mlx5_compress_cqe_err_handle(qp, op);
 614                 } else {
 615                         xform = op->private_xform;
 616                         op->status = RTE_COMP_OP_STATUS_SUCCESS;
 617                         op->consumed = op->src.length;
 618                         op->produced = rte_be_to_cpu_32(cqe->byte_cnt);
 619                         MLX5_ASSERT(cqe->byte_cnt ==
 620                                     opaq[idx].scattered_length);
 621                         switch (xform->csum_type) {
 622                         case RTE_COMP_CHECKSUM_CRC32:
 623                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 624                                                     (opaq[idx].crc32);
 625                                 break;
 626                         case RTE_COMP_CHECKSUM_ADLER32:
 627                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 628                                             (opaq[idx].adler32) << 32;
 629                                 break;
 630                         case RTE_COMP_CHECKSUM_CRC32_ADLER32:
 631                                 op->output_chksum = (uint64_t)rte_be_to_cpu_32
 632                                                              (opaq[idx].crc32) |
 633                                                      ((uint64_t)rte_be_to_cpu_32
 634                                                      (opaq[idx].adler32) << 32);
 635                                 break;
 636                         default:
 637                                 break;
 638                         }
 639                 }
 640                 ops[i++] = op;
 641                 qp->ci++;
 642         } while (i < max);
 643         if (likely(i != 0)) {
 644                 rte_io_wmb();
 645                 qp->cq.db_rec[0] = rte_cpu_to_be_32(qp->ci);
 646                 qp->stats.dequeued_count += i;
 647         }
 648         return i;
 649 }
 650
 651 static int
 652 mlx5_compress_args_check_handler(const char *key, const char *val, void *opaque)
 653 {
 654         struct mlx5_compress_devarg_params *devarg_prms = opaque;
 655
 656         if (strcmp(key, "log-block-size") == 0) {
 657                 errno = 0;
 658                 devarg_prms->log_block_sz = (uint32_t)strtoul(val, NULL, 10);
 659                 if (errno) {
 660                         DRV_LOG(WARNING, "%s: \"%s\" is an invalid integer."
 661                                 , key, val);
 662                         return -errno;
 663                 }
 664                 return 0;
 665         }
 666         return 0;
 667 }
 668
 669 static int
 670 mlx5_compress_handle_devargs(struct rte_devargs *devargs,
 671                           struct mlx5_compress_devarg_params *devarg_prms,
 672                           struct mlx5_hca_attr *att)
 673 {
 674         struct rte_kvargs *kvlist;
 675
 676         devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 677         if (devargs == NULL)
 678                 return 0;
 679         kvlist = rte_kvargs_parse(devargs->args, NULL);
 680         if (kvlist == NULL) {
 681                 DRV_LOG(ERR, "Failed to parse devargs.");
 682                 rte_errno = EINVAL;
 683                 return -1;
 684         }
 685         if (rte_kvargs_process(kvlist, NULL, mlx5_compress_args_check_handler,
 686                            devarg_prms) != 0) {
 687                 DRV_LOG(ERR, "Devargs handler function Failed.");
 688                 rte_kvargs_free(kvlist);
 689                 rte_errno = EINVAL;
 690                 return -1;
 691         }
 692         rte_kvargs_free(kvlist);
 693         if (devarg_prms->log_block_sz > MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX ||
 694                 devarg_prms->log_block_sz < att->compress_min_block_size) {
 695                 DRV_LOG(WARNING, "Log block size provided is out of range("
 696                         "%u); default it to %u.",
 697                         devarg_prms->log_block_sz,
 698                         MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX);
 699                 devarg_prms->log_block_sz = MLX5_GGA_COMP_LOG_BLOCK_SIZE_MAX;
 700         }
 701         return 0;
 702 }
 703
 704 static int
 705 mlx5_compress_dev_probe(struct mlx5_common_device *cdev)
 706 {
 707         struct rte_compressdev *compressdev;
 708         struct mlx5_compress_priv *priv;
 709         struct mlx5_hca_attr *attr = &cdev->config.hca_attr;
 710         struct mlx5_compress_devarg_params devarg_prms = {0};
 711         struct rte_compressdev_pmd_init_params init_params = {
 712                 .name = "",
 713                 .socket_id = cdev->dev->numa_node,
 714         };
 715         const char *ibdev_name = mlx5_os_get_ctx_device_name(cdev->ctx);
 716
 717         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
 718                 DRV_LOG(ERR, "Non-primary process type is not supported.");
 719                 rte_errno = ENOTSUP;
 720                 return -rte_errno;
 721         }
 722         if (!attr->mmo_decompress_qp_en && !attr->mmo_decompress_sq_en
 723                 && !attr->mmo_compress_qp_en && !attr->mmo_compress_sq_en
 724                 && !attr->mmo_dma_qp_en && !attr->mmo_dma_sq_en) {
 725                 DRV_LOG(ERR, "Not enough capabilities to support compress operations, maybe old FW/OFED version?");
 726                 claim_zero(mlx5_glue->close_device(cdev->ctx));
 727                 rte_errno = ENOTSUP;
 728                 return -ENOTSUP;
 729         }
 730         mlx5_compress_handle_devargs(cdev->dev->devargs, &devarg_prms, attr);
 731         compressdev = rte_compressdev_pmd_create(ibdev_name, cdev->dev,
 732                                                  sizeof(*priv), &init_params);
 733         if (compressdev == NULL) {
 734                 DRV_LOG(ERR, "Failed to create device \"%s\".", ibdev_name);
 735                 return -ENODEV;
 736         }
 737         DRV_LOG(INFO,
 738                 "Compress device %s was created successfully.", ibdev_name);
 739         compressdev->dev_ops = &mlx5_compress_ops;
 740         compressdev->dequeue_burst = mlx5_compress_dequeue_burst;
 741         compressdev->enqueue_burst = mlx5_compress_enqueue_burst;
 742         compressdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;
 743         priv = compressdev->data->dev_private;
 744         priv->log_block_sz = devarg_prms.log_block_sz;
 745         priv->mmo_decomp_sq = attr->mmo_decompress_sq_en;
 746         priv->mmo_decomp_qp = attr->mmo_decompress_qp_en;
 747         priv->mmo_comp_sq = attr->mmo_compress_sq_en;
 748         priv->mmo_comp_qp = attr->mmo_compress_qp_en;
 749         priv->mmo_dma_sq = attr->mmo_dma_sq_en;
 750         priv->mmo_dma_qp = attr->mmo_dma_qp_en;
 751         priv->cdev = cdev;
 752         priv->compressdev = compressdev;
 753         priv->min_block_size = attr->compress_min_block_size;
 754         if (mlx5_devx_uar_prepare(cdev, &priv->uar) != 0) {
 755                 rte_compressdev_pmd_destroy(priv->compressdev);
 756                 return -1;
 757         }
 758         pthread_mutex_lock(&priv_list_lock);
 759         TAILQ_INSERT_TAIL(&mlx5_compress_priv_list, priv, next);
 760         pthread_mutex_unlock(&priv_list_lock);
 761         return 0;
 762 }
 763
 764 static int
 765 mlx5_compress_dev_remove(struct mlx5_common_device *cdev)
 766 {
 767         struct mlx5_compress_priv *priv = NULL;
 768
 769         pthread_mutex_lock(&priv_list_lock);
 770         TAILQ_FOREACH(priv, &mlx5_compress_priv_list, next)
 771                 if (priv->compressdev->device == cdev->dev)
 772                         break;
 773         if (priv)
 774                 TAILQ_REMOVE(&mlx5_compress_priv_list, priv, next);
 775         pthread_mutex_unlock(&priv_list_lock);
 776         if (priv) {
 777                 mlx5_devx_uar_release(&priv->uar);
 778                 rte_compressdev_pmd_destroy(priv->compressdev);
 779         }
 780         return 0;
 781 }
 782
 783 static const struct rte_pci_id mlx5_compress_pci_id_map[] = {
 784         {
 785                 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
 786                                 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF)
 787         },
 788         {
 789                 .vendor_id = 0
 790         }
 791 };
 792
 793 static struct mlx5_class_driver mlx5_compress_driver = {
 794         .drv_class = MLX5_CLASS_COMPRESS,
 795         .name = RTE_STR(MLX5_COMPRESS_DRIVER_NAME),
 796         .id_table = mlx5_compress_pci_id_map,
 797         .probe = mlx5_compress_dev_probe,
 798         .remove = mlx5_compress_dev_remove,
 799 };
 800
 801 RTE_INIT(rte_mlx5_compress_init)
 802 {
 803         mlx5_common_init();
 804         if (mlx5_glue != NULL)
 805                 mlx5_class_driver_register(&mlx5_compress_driver);
 806 }
 807
 808 RTE_LOG_REGISTER_DEFAULT(mlx5_compress_logtype, NOTICE)
 809 RTE_PMD_EXPORT_NAME(MLX5_COMPRESS_DRIVER_NAME, __COUNTER__);
 810 RTE_PMD_REGISTER_PCI_TABLE(MLX5_COMPRESS_DRIVER_NAME, mlx5_compress_pci_id_map);
 811 RTE_PMD_REGISTER_KMOD_DEP(MLX5_COMPRESS_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib");