1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved.
13 #include <rte_bus_pci.h>
14 #include <rte_atomic.h>
15 #include <rte_byteorder.h>
18 #include <rte_spinlock.h>
19 #include <rte_crypto_sym.h>
20 #include <rte_cryptodev.h>
23 #define MAX_HW_QUEUES 5
25 /**< CCP Register Mappings */
26 #define Q_MASK_REG 0x000
27 #define TRNG_OUT_REG 0x00c
29 /* CCP Version 5 Specifics */
30 #define CMD_QUEUE_MASK_OFFSET 0x00
31 #define CMD_QUEUE_PRIO_OFFSET 0x04
32 #define CMD_REQID_CONFIG_OFFSET 0x08
33 #define CMD_CMD_TIMEOUT_OFFSET 0x10
34 #define LSB_PUBLIC_MASK_LO_OFFSET 0x18
35 #define LSB_PUBLIC_MASK_HI_OFFSET 0x1C
36 #define LSB_PRIVATE_MASK_LO_OFFSET 0x20
37 #define LSB_PRIVATE_MASK_HI_OFFSET 0x24
39 #define CMD_Q_CONTROL_BASE 0x0000
40 #define CMD_Q_TAIL_LO_BASE 0x0004
41 #define CMD_Q_HEAD_LO_BASE 0x0008
42 #define CMD_Q_INT_ENABLE_BASE 0x000C
43 #define CMD_Q_INTERRUPT_STATUS_BASE 0x0010
45 #define CMD_Q_STATUS_BASE 0x0100
46 #define CMD_Q_INT_STATUS_BASE 0x0104
48 #define CMD_CONFIG_0_OFFSET 0x6000
49 #define CMD_TRNG_CTL_OFFSET 0x6008
50 #define CMD_AES_MASK_OFFSET 0x6010
51 #define CMD_CLK_GATE_CTL_OFFSET 0x603C
53 /* Address offset between two virtual queue registers */
54 #define CMD_Q_STATUS_INCR 0x1000
58 #define CMD_Q_SIZE 0x1F
60 #define COMMANDS_PER_QUEUE 2048
62 #define QUEUE_SIZE_VAL ((ffs(COMMANDS_PER_QUEUE) - 2) & \
64 #define Q_DESC_SIZE sizeof(struct ccp_desc)
65 #define Q_SIZE(n) (COMMANDS_PER_QUEUE*(n))
67 #define INT_COMPLETION 0x1
69 #define INT_QUEUE_STOPPED 0x4
70 #define ALL_INTERRUPTS (INT_COMPLETION| \
74 #define LSB_REGION_WIDTH 5
78 #define LSB_ITEM_SIZE 32
79 #define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE)
83 BITS_PER_WORD = sizeof(unsigned long) * CHAR_BIT
86 #define WORD_OFFSET(b) ((b) / BITS_PER_WORD)
87 #define BIT_OFFSET(b) ((b) % BITS_PER_WORD)
89 #define CCP_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
90 #define CCP_BITMAP_SIZE(nr) \
91 CCP_DIV_ROUND_UP(nr, CHAR_BIT * sizeof(unsigned long))
93 #define CCP_BITMAP_FIRST_WORD_MASK(start) \
94 (~0UL << ((start) & (BITS_PER_WORD - 1)))
95 #define CCP_BITMAP_LAST_WORD_MASK(nbits) \
96 (~0UL >> (-(nbits) & (BITS_PER_WORD - 1)))
98 #define __ccp_round_mask(x, y) ((typeof(x))((y)-1))
99 #define ccp_round_down(x, y) ((x) & ~__ccp_round_mask(x, y))
101 /** CCP registers Write/Read */
103 static inline void ccp_pci_reg_write(void *base, int offset,
106 volatile void *reg_addr = ((uint8_t *)base + offset);
108 rte_write32((rte_cpu_to_le_32(value)), reg_addr);
111 static inline uint32_t ccp_pci_reg_read(void *base, int offset)
113 volatile void *reg_addr = ((uint8_t *)base + offset);
115 return rte_le_to_cpu_32(rte_read32(reg_addr));
118 #define CCP_READ_REG(hw_addr, reg_offset) \
119 ccp_pci_reg_read(hw_addr, reg_offset)
121 #define CCP_WRITE_REG(hw_addr, reg_offset, value) \
122 ccp_pci_reg_write(hw_addr, reg_offset, value)
124 TAILQ_HEAD(ccp_list, ccp_device);
126 extern struct ccp_list ccp_list;
131 enum ccp_device_version {
137 * A structure describing a CCP command queue.
140 struct ccp_device *dev;
141 char memz_name[RTE_MEMZONE_NAMESIZE];
143 rte_atomic64_t free_slots;
144 /**< available free slots updated from enq/deq calls */
146 /* Queue identifier */
147 uint64_t id; /**< queue id */
148 uint64_t qidx; /**< queue index */
149 uint64_t qsize; /**< queue size */
152 struct ccp_desc *qbase_desc;
154 phys_addr_t qbase_phys_addr;
155 /**< queue-page registers addr */
159 /**< queue ctrl reg */
162 /**< lsb region assigned to queue */
163 unsigned long lsbmask;
164 /**< lsb regions queue can access */
165 unsigned long lsbmap[CCP_BITMAP_SIZE(LSB_SIZE)];
166 /**< all lsb resources which queue is using */
168 /**< lsb assigned for queue */
170 /**< lsb assigned for iv */
172 /**< lsb assigned for sha ctx */
174 /**< lsb assigned for hmac ctx */
175 } ____cacheline_aligned;
178 * A structure describing a CCP device.
181 TAILQ_ENTRY(ccp_device) next;
183 /**< ccp dev id on platform */
184 struct ccp_queue cmd_q[MAX_HW_QUEUES];
187 /**< no. of ccp Queues */
188 struct rte_pci_device pci;
189 /**< ccp pci identifier */
190 unsigned long lsbmap[CCP_BITMAP_SIZE(SLSB_MAP_SIZE)];
191 /**< shared lsb mask of ccp */
192 rte_spinlock_t lsb_lock;
193 /**< protection for shared lsb region allocation */
195 /**< current queue index */
196 } __rte_cache_aligned;
199 * descriptor for version 5 CPP commands
201 * word 0: function; engine; control bits
202 * word 1: length of source data
203 * word 2: low 32 bits of source pointer
204 * word 3: upper 16 bits of source pointer; source memory type
205 * word 4: low 32 bits of destination pointer
206 * word 5: upper 16 bits of destination pointer; destination memory
208 * word 6: low 32 bits of key pointer
209 * word 7: upper 16 bits of key pointer; key memory type
217 uint32_t function:15;
226 uint32_t lsb_cxt_id:8;
232 uint32_t dst_lo; /* NON-SHA */
233 uint32_t sha_len_lo; /* SHA */
264 static inline uint32_t
265 low32_value(unsigned long addr)
267 return ((uint64_t)addr) & 0x0ffffffff;
270 static inline uint32_t
271 high32_value(unsigned long addr)
273 return ((uint64_t)addr >> 32) & 0x00000ffff;
277 * Detect ccp platform and initialize all ccp devices
279 * @param ccp_id rte_pci_id list for supported CCP devices
280 * @return no. of successfully initialized CCP devices
282 int ccp_probe_devices(const struct rte_pci_id *ccp_id);
284 #endif /* _CCP_DEV_H_ */