drivers/crypto/octeontx2/otx2_cryptodev_ops.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (C) 2019 Marvell International Ltd.
   3  */
   4
   5 #include <unistd.h>
   6
   7 #include <rte_cryptodev_pmd.h>
   8 #include <rte_errno.h>
   9 #include <rte_ethdev.h>
  10
  11 #include "otx2_cryptodev.h"
  12 #include "otx2_cryptodev_capabilities.h"
  13 #include "otx2_cryptodev_hw_access.h"
  14 #include "otx2_cryptodev_mbox.h"
  15 #include "otx2_cryptodev_ops.h"
  16 #include "otx2_cryptodev_ops_helper.h"
  17 #include "otx2_ipsec_anti_replay.h"
  18 #include "otx2_ipsec_po_ops.h"
  19 #include "otx2_mbox.h"
  20 #include "otx2_sec_idev.h"
  21 #include "otx2_security.h"
  22
  23 #include "cpt_hw_types.h"
  24 #include "cpt_pmd_logs.h"
  25 #include "cpt_pmd_ops_helper.h"
  26 #include "cpt_ucode.h"
  27 #include "cpt_ucode_asym.h"
  28
  29 #define METABUF_POOL_CACHE_SIZE 512
  30
  31 static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];
  32
  33 /* Forward declarations */
  34
  35 static int
  36 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
  37
  38 static void
  39 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
  40 {
  41         snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
  42 }
  43
  44 static int
  45 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
  46                                 struct otx2_cpt_qp *qp, uint8_t qp_id,
  47                                 int nb_elements)
  48 {
  49         char mempool_name[RTE_MEMPOOL_NAMESIZE];
  50         struct cpt_qp_meta_info *meta_info;
  51         struct rte_mempool *pool;
  52         int ret, max_mlen;
  53         int asym_mlen = 0;
  54         int lb_mlen = 0;
  55         int sg_mlen = 0;
  56
  57         if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
  58
  59                 /* Get meta len for scatter gather mode */
  60                 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
  61
  62                 /* Extra 32B saved for future considerations */
  63                 sg_mlen += 4 * sizeof(uint64_t);
  64
  65                 /* Get meta len for linear buffer (direct) mode */
  66                 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
  67
  68                 /* Extra 32B saved for future considerations */
  69                 lb_mlen += 4 * sizeof(uint64_t);
  70         }
  71
  72         if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
  73
  74                 /* Get meta len required for asymmetric operations */
  75                 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
  76         }
  77
  78         /*
  79          * Check max requirement for meta buffer to
  80          * support crypto op of any type (sym/asym).
  81          */
  82         max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
  83
  84         /* Allocate mempool */
  85
  86         snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
  87                  dev->data->dev_id, qp_id);
  88
  89         pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
  90                                         METABUF_POOL_CACHE_SIZE, 0,
  91                                         rte_socket_id(), 0);
  92
  93         if (pool == NULL) {
  94                 CPT_LOG_ERR("Could not create mempool for metabuf");
  95                 return rte_errno;
  96         }
  97
  98         ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
  99                                          NULL);
 100         if (ret) {
 101                 CPT_LOG_ERR("Could not set mempool ops");
 102                 goto mempool_free;
 103         }
 104
 105         ret = rte_mempool_populate_default(pool);
 106         if (ret <= 0) {
 107                 CPT_LOG_ERR("Could not populate metabuf pool");
 108                 goto mempool_free;
 109         }
 110
 111         meta_info = &qp->meta_info;
 112
 113         meta_info->pool = pool;
 114         meta_info->lb_mlen = lb_mlen;
 115         meta_info->sg_mlen = sg_mlen;
 116
 117         return 0;
 118
 119 mempool_free:
 120         rte_mempool_free(pool);
 121         return ret;
 122 }
 123
 124 static void
 125 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
 126 {
 127         struct cpt_qp_meta_info *meta_info = &qp->meta_info;
 128
 129         rte_mempool_free(meta_info->pool);
 130
 131         meta_info->pool = NULL;
 132         meta_info->lb_mlen = 0;
 133         meta_info->sg_mlen = 0;
 134 }
 135
 136 static int
 137 otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
 138 {
 139         static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
 140         uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
 141         int i, ret;
 142
 143         for (i = 0; i < nb_ethport; i++) {
 144                 port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
 145                 if (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
 146                         break;
 147         }
 148
 149         if (i >= nb_ethport)
 150                 return 0;
 151
 152         ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
 153         if (ret)
 154                 return ret;
 155
 156         /* Publish inline Tx QP to eth dev security */
 157         ret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);
 158         if (ret)
 159                 return ret;
 160
 161         return 0;
 162 }
 163
 164 static struct otx2_cpt_qp *
 165 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
 166                    uint8_t group)
 167 {
 168         struct otx2_cpt_vf *vf = dev->data->dev_private;
 169         uint64_t pg_sz = sysconf(_SC_PAGESIZE);
 170         const struct rte_memzone *lf_mem;
 171         uint32_t len, iq_len, size_div40;
 172         char name[RTE_MEMZONE_NAMESIZE];
 173         uint64_t used_len, iova;
 174         struct otx2_cpt_qp *qp;
 175         uint64_t lmtline;
 176         uint8_t *va;
 177         int ret;
 178
 179         /* Allocate queue pair */
 180         qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
 181                                 OTX2_ALIGN, 0);
 182         if (qp == NULL) {
 183                 CPT_LOG_ERR("Could not allocate queue pair");
 184                 return NULL;
 185         }
 186
 187         iq_len = OTX2_CPT_IQ_LEN;
 188
 189         /*
 190          * Queue size must be a multiple of 40 and effective queue size to
 191          * software is (size_div40 - 1) * 40
 192          */
 193         size_div40 = (iq_len + 40 - 1) / 40 + 1;
 194
 195         /* For pending queue */
 196         len = iq_len * sizeof(uintptr_t);
 197
 198         /* Space for instruction group memory */
 199         len += size_div40 * 16;
 200
 201         /* So that instruction queues start as pg size aligned */
 202         len = RTE_ALIGN(len, pg_sz);
 203
 204         /* For instruction queues */
 205         len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
 206
 207         /* Wastage after instruction queues */
 208         len = RTE_ALIGN(len, pg_sz);
 209
 210         qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 211                             qp_id);
 212
 213         lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
 214                         RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
 215                         RTE_CACHE_LINE_SIZE);
 216         if (lf_mem == NULL) {
 217                 CPT_LOG_ERR("Could not allocate reserved memzone");
 218                 goto qp_free;
 219         }
 220
 221         va = lf_mem->addr;
 222         iova = lf_mem->iova;
 223
 224         memset(va, 0, len);
 225
 226         ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
 227         if (ret) {
 228                 CPT_LOG_ERR("Could not create mempool for metabuf");
 229                 goto lf_mem_free;
 230         }
 231
 232         /* Initialize pending queue */
 233         qp->pend_q.req_queue = (uintptr_t *)va;
 234         qp->pend_q.enq_tail = 0;
 235         qp->pend_q.deq_head = 0;
 236         qp->pend_q.pending_count = 0;
 237
 238         used_len = iq_len * sizeof(uintptr_t);
 239         used_len += size_div40 * 16;
 240         used_len = RTE_ALIGN(used_len, pg_sz);
 241         iova += used_len;
 242
 243         qp->iq_dma_addr = iova;
 244         qp->id = qp_id;
 245         qp->blkaddr = vf->lf_blkaddr[qp_id];
 246         qp->base = OTX2_CPT_LF_BAR2(vf, qp->blkaddr, qp_id);
 247
 248         lmtline = vf->otx2_dev.bar2 +
 249                   (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
 250                   OTX2_LMT_LF_LMTLINE(0);
 251
 252         qp->lmtline = (void *)lmtline;
 253
 254         qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
 255
 256         ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
 257         if (ret && (ret != -ENOENT)) {
 258                 CPT_LOG_ERR("Could not delete inline configuration");
 259                 goto mempool_destroy;
 260         }
 261
 262         otx2_cpt_iq_disable(qp);
 263
 264         ret = otx2_cpt_qp_inline_cfg(dev, qp);
 265         if (ret) {
 266                 CPT_LOG_ERR("Could not configure queue for inline IPsec");
 267                 goto mempool_destroy;
 268         }
 269
 270         ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
 271                                  size_div40);
 272         if (ret) {
 273                 CPT_LOG_ERR("Could not enable instruction queue");
 274                 goto mempool_destroy;
 275         }
 276
 277         return qp;
 278
 279 mempool_destroy:
 280         otx2_cpt_metabuf_mempool_destroy(qp);
 281 lf_mem_free:
 282         rte_memzone_free(lf_mem);
 283 qp_free:
 284         rte_free(qp);
 285         return NULL;
 286 }
 287
 288 static int
 289 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
 290 {
 291         const struct rte_memzone *lf_mem;
 292         char name[RTE_MEMZONE_NAMESIZE];
 293         int ret;
 294
 295         ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
 296         if (ret && (ret != -ENOENT)) {
 297                 CPT_LOG_ERR("Could not delete inline configuration");
 298                 return ret;
 299         }
 300
 301         otx2_cpt_iq_disable(qp);
 302
 303         otx2_cpt_metabuf_mempool_destroy(qp);
 304
 305         qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
 306                             qp->id);
 307
 308         lf_mem = rte_memzone_lookup(name);
 309
 310         ret = rte_memzone_free(lf_mem);
 311         if (ret)
 312                 return ret;
 313
 314         rte_free(qp);
 315
 316         return 0;
 317 }
 318
 319 static int
 320 sym_xform_verify(struct rte_crypto_sym_xform *xform)
 321 {
 322         if (xform->next) {
 323                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 324                     xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 325                     xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT &&
 326                     (xform->auth.algo != RTE_CRYPTO_AUTH_SHA1_HMAC ||
 327                      xform->next->cipher.algo != RTE_CRYPTO_CIPHER_AES_CBC))
 328                         return -ENOTSUP;
 329
 330                 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 331                     xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&
 332                     xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 333                     (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_CBC ||
 334                      xform->next->auth.algo != RTE_CRYPTO_AUTH_SHA1_HMAC))
 335                         return -ENOTSUP;
 336
 337                 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 338                     xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
 339                     xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 340                     xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)
 341                         return -ENOTSUP;
 342
 343                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 344                     xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&
 345                     xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
 346                     xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)
 347                         return -ENOTSUP;
 348
 349         } else {
 350                 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
 351                     xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&
 352                     xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)
 353                         return -ENOTSUP;
 354         }
 355         return 0;
 356 }
 357
 358 static int
 359 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
 360                       struct rte_cryptodev_sym_session *sess,
 361                       struct rte_mempool *pool)
 362 {
 363         struct rte_crypto_sym_xform *temp_xform = xform;
 364         struct cpt_sess_misc *misc;
 365         vq_cmd_word3_t vq_cmd_w3;
 366         void *priv;
 367         int ret;
 368
 369         ret = sym_xform_verify(xform);
 370         if (unlikely(ret))
 371                 return ret;
 372
 373         if (unlikely(rte_mempool_get(pool, &priv))) {
 374                 CPT_LOG_ERR("Could not allocate session private data");
 375                 return -ENOMEM;
 376         }
 377
 378         memset(priv, 0, sizeof(struct cpt_sess_misc) +
 379                         offsetof(struct cpt_ctx, mc_ctx));
 380
 381         misc = priv;
 382
 383         for ( ; xform != NULL; xform = xform->next) {
 384                 switch (xform->type) {
 385                 case RTE_CRYPTO_SYM_XFORM_AEAD:
 386                         ret = fill_sess_aead(xform, misc);
 387                         break;
 388                 case RTE_CRYPTO_SYM_XFORM_CIPHER:
 389                         ret = fill_sess_cipher(xform, misc);
 390                         break;
 391                 case RTE_CRYPTO_SYM_XFORM_AUTH:
 392                         if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
 393                                 ret = fill_sess_gmac(xform, misc);
 394                         else
 395                                 ret = fill_sess_auth(xform, misc);
 396                         break;
 397                 default:
 398                         ret = -1;
 399                 }
 400
 401                 if (ret)
 402                         goto priv_put;
 403         }
 404
 405         if ((GET_SESS_FC_TYPE(misc) == HASH_HMAC) &&
 406                         cpt_mac_len_verify(&temp_xform->auth)) {
 407                 CPT_LOG_ERR("MAC length is not supported");
 408                 ret = -ENOTSUP;
 409                 goto priv_put;
 410         }
 411
 412         set_sym_session_private_data(sess, driver_id, misc);
 413
 414         misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
 415                              sizeof(struct cpt_sess_misc);
 416
 417         vq_cmd_w3.u64 = 0;
 418         vq_cmd_w3.s.cptr = misc->ctx_dma_addr + offsetof(struct cpt_ctx,
 419                                                          mc_ctx);
 420
 421         /*
 422          * IE engines support IPsec operations
 423          * SE engines support IPsec operations, Chacha-Poly and
 424          * Air-Crypto operations
 425          */
 426         if (misc->zsk_flag || misc->chacha_poly)
 427                 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE;
 428         else
 429                 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE_IE;
 430
 431         misc->cpt_inst_w7 = vq_cmd_w3.u64;
 432
 433         return 0;
 434
 435 priv_put:
 436         rte_mempool_put(pool, priv);
 437
 438         return -ENOTSUP;
 439 }
 440
 441 static __rte_always_inline void __rte_hot
 442 otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,
 443                     struct cpt_request_info *req,
 444                     void *lmtline,
 445                     uint64_t cpt_inst_w7)
 446 {
 447         union cpt_inst_s inst;
 448         uint64_t lmt_status;
 449
 450         inst.u[0] = 0;
 451         inst.s9x.res_addr = req->comp_baddr;
 452         inst.u[2] = 0;
 453         inst.u[3] = 0;
 454
 455         inst.s9x.ei0 = req->ist.ei0;
 456         inst.s9x.ei1 = req->ist.ei1;
 457         inst.s9x.ei2 = req->ist.ei2;
 458         inst.s9x.ei3 = cpt_inst_w7;
 459
 460         inst.s9x.qord = 1;
 461         inst.s9x.grp = qp->ev.queue_id;
 462         inst.s9x.tt = qp->ev.sched_type;
 463         inst.s9x.tag = (RTE_EVENT_TYPE_CRYPTODEV << 28) |
 464                         qp->ev.flow_id;
 465         inst.s9x.wq_ptr = (uint64_t)req >> 3;
 466         req->qp = qp;
 467
 468         do {
 469                 /* Copy CPT command to LMTLINE */
 470                 memcpy(lmtline, &inst, sizeof(inst));
 471
 472                 /*
 473                  * Make sure compiler does not reorder memcpy and ldeor.
 474                  * LMTST transactions are always flushed from the write
 475                  * buffer immediately, a DMB is not required to push out
 476                  * LMTSTs.
 477                  */
 478                 rte_io_wmb();
 479                 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
 480         } while (lmt_status == 0);
 481
 482 }
 483
 484 static __rte_always_inline int32_t __rte_hot
 485 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
 486                      struct pending_queue *pend_q,
 487                      struct cpt_request_info *req,
 488                      uint64_t cpt_inst_w7)
 489 {
 490         void *lmtline = qp->lmtline;
 491         union cpt_inst_s inst;
 492         uint64_t lmt_status;
 493
 494         if (qp->ca_enable) {
 495                 otx2_ca_enqueue_req(qp, req, lmtline, cpt_inst_w7);
 496                 return 0;
 497         }
 498
 499         if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
 500                 return -EAGAIN;
 501
 502         inst.u[0] = 0;
 503         inst.s9x.res_addr = req->comp_baddr;
 504         inst.u[2] = 0;
 505         inst.u[3] = 0;
 506
 507         inst.s9x.ei0 = req->ist.ei0;
 508         inst.s9x.ei1 = req->ist.ei1;
 509         inst.s9x.ei2 = req->ist.ei2;
 510         inst.s9x.ei3 = cpt_inst_w7;
 511
 512         req->time_out = rte_get_timer_cycles() +
 513                         DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
 514
 515         do {
 516                 /* Copy CPT command to LMTLINE */
 517                 memcpy(lmtline, &inst, sizeof(inst));
 518
 519                 /*
 520                  * Make sure compiler does not reorder memcpy and ldeor.
 521                  * LMTST transactions are always flushed from the write
 522                  * buffer immediately, a DMB is not required to push out
 523                  * LMTSTs.
 524                  */
 525                 rte_io_wmb();
 526                 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
 527         } while (lmt_status == 0);
 528
 529         pend_q->req_queue[pend_q->enq_tail] = (uintptr_t)req;
 530
 531         /* We will use soft queue length here to limit requests */
 532         MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
 533         pend_q->pending_count += 1;
 534
 535         return 0;
 536 }
 537
 538 static __rte_always_inline int32_t __rte_hot
 539 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
 540                       struct rte_crypto_op *op,
 541                       struct pending_queue *pend_q)
 542 {
 543         struct cpt_qp_meta_info *minfo = &qp->meta_info;
 544         struct rte_crypto_asym_op *asym_op = op->asym;
 545         struct asym_op_params params = {0};
 546         struct cpt_asym_sess_misc *sess;
 547         uintptr_t *cop;
 548         void *mdata;
 549         int ret;
 550
 551         if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
 552                 CPT_LOG_ERR("Could not allocate meta buffer for request");
 553                 return -ENOMEM;
 554         }
 555
 556         sess = get_asym_session_private_data(asym_op->session,
 557                                              otx2_cryptodev_driver_id);
 558
 559         /* Store IO address of the mdata to meta_buf */
 560         params.meta_buf = rte_mempool_virt2iova(mdata);
 561
 562         cop = mdata;
 563         cop[0] = (uintptr_t)mdata;
 564         cop[1] = (uintptr_t)op;
 565         cop[2] = cop[3] = 0ULL;
 566
 567         params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
 568         params.req->op = cop;
 569
 570         /* Adjust meta_buf to point to end of cpt_request_info structure */
 571         params.meta_buf += (4 * sizeof(uintptr_t)) +
 572                             sizeof(struct cpt_request_info);
 573         switch (sess->xfrm_type) {
 574         case RTE_CRYPTO_ASYM_XFORM_MODEX:
 575                 ret = cpt_modex_prep(&params, &sess->mod_ctx);
 576                 if (unlikely(ret))
 577                         goto req_fail;
 578                 break;
 579         case RTE_CRYPTO_ASYM_XFORM_RSA:
 580                 ret = cpt_enqueue_rsa_op(op, &params, sess);
 581                 if (unlikely(ret))
 582                         goto req_fail;
 583                 break;
 584         case RTE_CRYPTO_ASYM_XFORM_ECDSA:
 585                 ret = cpt_enqueue_ecdsa_op(op, &params, sess, otx2_fpm_iova);
 586                 if (unlikely(ret))
 587                         goto req_fail;
 588                 break;
 589         case RTE_CRYPTO_ASYM_XFORM_ECPM:
 590                 ret = cpt_ecpm_prep(&asym_op->ecpm, &params,
 591                                     sess->ec_ctx.curveid);
 592                 if (unlikely(ret))
 593                         goto req_fail;
 594                 break;
 595         default:
 596                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 597                 ret = -EINVAL;
 598                 goto req_fail;
 599         }
 600
 601         ret = otx2_cpt_enqueue_req(qp, pend_q, params.req, sess->cpt_inst_w7);
 602
 603         if (unlikely(ret)) {
 604                 CPT_LOG_DP_ERR("Could not enqueue crypto req");
 605                 goto req_fail;
 606         }
 607
 608         return 0;
 609
 610 req_fail:
 611         free_op_meta(mdata, minfo->pool);
 612
 613         return ret;
 614 }
 615
 616 static __rte_always_inline int __rte_hot
 617 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
 618                      struct pending_queue *pend_q)
 619 {
 620         struct rte_crypto_sym_op *sym_op = op->sym;
 621         struct cpt_request_info *req;
 622         struct cpt_sess_misc *sess;
 623         uint64_t cpt_op;
 624         void *mdata;
 625         int ret;
 626
 627         sess = get_sym_session_private_data(sym_op->session,
 628                                             otx2_cryptodev_driver_id);
 629
 630         cpt_op = sess->cpt_op;
 631
 632         if (cpt_op & CPT_OP_CIPHER_MASK)
 633                 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
 634                                      (void **)&req);
 635         else
 636                 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
 637                                          (void **)&req);
 638
 639         if (unlikely(ret)) {
 640                 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
 641                                 op, (unsigned int)cpt_op, ret);
 642                 return ret;
 643         }
 644
 645         ret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);
 646
 647         if (unlikely(ret)) {
 648                 /* Free buffer allocated by fill params routines */
 649                 free_op_meta(mdata, qp->meta_info.pool);
 650         }
 651
 652         return ret;
 653 }
 654
 655 static __rte_always_inline int __rte_hot
 656 otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
 657                      struct pending_queue *pend_q)
 658 {
 659         uint32_t winsz, esn_low = 0, esn_hi = 0, seql = 0, seqh = 0;
 660         struct rte_mbuf *m_src = op->sym->m_src;
 661         struct otx2_sec_session_ipsec_lp *sess;
 662         struct otx2_ipsec_po_sa_ctl *ctl_wrd;
 663         struct otx2_ipsec_po_in_sa *sa;
 664         struct otx2_sec_session *priv;
 665         struct cpt_request_info *req;
 666         uint64_t seq_in_sa, seq = 0;
 667         uint8_t esn;
 668         int ret;
 669
 670         priv = get_sec_session_private_data(op->sym->sec_session);
 671         sess = &priv->ipsec.lp;
 672         sa = &sess->in_sa;
 673
 674         ctl_wrd = &sa->ctl;
 675         esn = ctl_wrd->esn_en;
 676         winsz = sa->replay_win_sz;
 677
 678         if (ctl_wrd->direction == OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND)
 679                 ret = process_outb_sa(op, sess, &qp->meta_info, (void **)&req);
 680         else {
 681                 if (winsz) {
 682                         esn_low = rte_be_to_cpu_32(sa->esn_low);
 683                         esn_hi = rte_be_to_cpu_32(sa->esn_hi);
 684                         seql = *rte_pktmbuf_mtod_offset(m_src, uint32_t *,
 685                                 sizeof(struct rte_ipv4_hdr) + 4);
 686                         seql = rte_be_to_cpu_32(seql);
 687
 688                         if (!esn)
 689                                 seq = (uint64_t)seql;
 690                         else {
 691                                 seqh = anti_replay_get_seqh(winsz, seql, esn_hi,
 692                                                 esn_low);
 693                                 seq = ((uint64_t)seqh << 32) | seql;
 694                         }
 695
 696                         if (unlikely(seq == 0))
 697                                 return IPSEC_ANTI_REPLAY_FAILED;
 698
 699                         ret = anti_replay_check(sa->replay, seq, winsz);
 700                         if (unlikely(ret)) {
 701                                 otx2_err("Anti replay check failed");
 702                                 return IPSEC_ANTI_REPLAY_FAILED;
 703                         }
 704                 }
 705
 706                 ret = process_inb_sa(op, sess, &qp->meta_info, (void **)&req);
 707         }
 708
 709         if (unlikely(ret)) {
 710                 otx2_err("Crypto req : op %p, ret 0x%x", op, ret);
 711                 return ret;
 712         }
 713
 714         ret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);
 715
 716         if (winsz && esn) {
 717                 seq_in_sa = ((uint64_t)esn_hi << 32) | esn_low;
 718                 if (seq > seq_in_sa) {
 719                         sa->esn_low = rte_cpu_to_be_32(seql);
 720                         sa->esn_hi = rte_cpu_to_be_32(seqh);
 721                 }
 722         }
 723
 724         return ret;
 725 }
 726
 727 static __rte_always_inline int __rte_hot
 728 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
 729                               struct pending_queue *pend_q)
 730 {
 731         const int driver_id = otx2_cryptodev_driver_id;
 732         struct rte_crypto_sym_op *sym_op = op->sym;
 733         struct rte_cryptodev_sym_session *sess;
 734         int ret;
 735
 736         /* Create temporary session */
 737         sess = rte_cryptodev_sym_session_create(qp->sess_mp);
 738         if (sess == NULL)
 739                 return -ENOMEM;
 740
 741         ret = sym_session_configure(driver_id, sym_op->xform, sess,
 742                                     qp->sess_mp_priv);
 743         if (ret)
 744                 goto sess_put;
 745
 746         sym_op->session = sess;
 747
 748         ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
 749
 750         if (unlikely(ret))
 751                 goto priv_put;
 752
 753         return 0;
 754
 755 priv_put:
 756         sym_session_clear(driver_id, sess);
 757 sess_put:
 758         rte_mempool_put(qp->sess_mp, sess);
 759         return ret;
 760 }
 761
 762 static uint16_t
 763 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
 764 {
 765         uint16_t nb_allowed, count = 0;
 766         struct otx2_cpt_qp *qp = qptr;
 767         struct pending_queue *pend_q;
 768         struct rte_crypto_op *op;
 769         int ret;
 770
 771         pend_q = &qp->pend_q;
 772
 773         nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
 774         if (nb_ops > nb_allowed)
 775                 nb_ops = nb_allowed;
 776
 777         for (count = 0; count < nb_ops; count++) {
 778                 op = ops[count];
 779                 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
 780                         if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)
 781                                 ret = otx2_cpt_enqueue_sec(qp, op, pend_q);
 782                         else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
 783                                 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
 784                         else
 785                                 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
 786                                                                     pend_q);
 787                 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
 788                         if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
 789                                 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
 790                         else
 791                                 break;
 792                 } else
 793                         break;
 794
 795                 if (unlikely(ret))
 796                         break;
 797         }
 798
 799         return count;
 800 }
 801
 802 static __rte_always_inline void
 803 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
 804                      struct rte_crypto_rsa_xform *rsa_ctx)
 805 {
 806         struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
 807
 808         switch (rsa->op_type) {
 809         case RTE_CRYPTO_ASYM_OP_ENCRYPT:
 810                 rsa->cipher.length = rsa_ctx->n.length;
 811                 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
 812                 break;
 813         case RTE_CRYPTO_ASYM_OP_DECRYPT:
 814                 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
 815                         rsa->message.length = rsa_ctx->n.length;
 816                         memcpy(rsa->message.data, req->rptr,
 817                                rsa->message.length);
 818                 } else {
 819                         /* Get length of decrypted output */
 820                         rsa->message.length = rte_cpu_to_be_16
 821                                              (*((uint16_t *)req->rptr));
 822                         /*
 823                          * Offset output data pointer by length field
 824                          * (2 bytes) and copy decrypted data.
 825                          */
 826                         memcpy(rsa->message.data, req->rptr + 2,
 827                                rsa->message.length);
 828                 }
 829                 break;
 830         case RTE_CRYPTO_ASYM_OP_SIGN:
 831                 rsa->sign.length = rsa_ctx->n.length;
 832                 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
 833                 break;
 834         case RTE_CRYPTO_ASYM_OP_VERIFY:
 835                 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
 836                         rsa->sign.length = rsa_ctx->n.length;
 837                         memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
 838                 } else {
 839                         /* Get length of signed output */
 840                         rsa->sign.length = rte_cpu_to_be_16
 841                                           (*((uint16_t *)req->rptr));
 842                         /*
 843                          * Offset output data pointer by length field
 844                          * (2 bytes) and copy signed data.
 845                          */
 846                         memcpy(rsa->sign.data, req->rptr + 2,
 847                                rsa->sign.length);
 848                 }
 849                 if (memcmp(rsa->sign.data, rsa->message.data,
 850                            rsa->message.length)) {
 851                         CPT_LOG_DP_ERR("RSA verification failed");
 852                         cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
 853                 }
 854                 break;
 855         default:
 856                 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
 857                 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 858                 break;
 859         }
 860 }
 861
 862 static __rte_always_inline void
 863 otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,
 864                                struct cpt_request_info *req,
 865                                struct cpt_asym_ec_ctx *ec)
 866 {
 867         int prime_len = ec_grp[ec->curveid].prime.length;
 868
 869         if (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)
 870                 return;
 871
 872         /* Separate out sign r and s components */
 873         memcpy(ecdsa->r.data, req->rptr, prime_len);
 874         memcpy(ecdsa->s.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
 875                prime_len);
 876         ecdsa->r.length = prime_len;
 877         ecdsa->s.length = prime_len;
 878 }
 879
 880 static __rte_always_inline void
 881 otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,
 882                              struct cpt_request_info *req,
 883                              struct cpt_asym_ec_ctx *ec)
 884 {
 885         int prime_len = ec_grp[ec->curveid].prime.length;
 886
 887         memcpy(ecpm->r.x.data, req->rptr, prime_len);
 888         memcpy(ecpm->r.y.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
 889                prime_len);
 890         ecpm->r.x.length = prime_len;
 891         ecpm->r.y.length = prime_len;
 892 }
 893
 894 static void
 895 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
 896                            struct cpt_request_info *req)
 897 {
 898         struct rte_crypto_asym_op *op = cop->asym;
 899         struct cpt_asym_sess_misc *sess;
 900
 901         sess = get_asym_session_private_data(op->session,
 902                                              otx2_cryptodev_driver_id);
 903
 904         switch (sess->xfrm_type) {
 905         case RTE_CRYPTO_ASYM_XFORM_RSA:
 906                 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
 907                 break;
 908         case RTE_CRYPTO_ASYM_XFORM_MODEX:
 909                 op->modex.result.length = sess->mod_ctx.modulus.length;
 910                 memcpy(op->modex.result.data, req->rptr,
 911                        op->modex.result.length);
 912                 break;
 913         case RTE_CRYPTO_ASYM_XFORM_ECDSA:
 914                 otx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);
 915                 break;
 916         case RTE_CRYPTO_ASYM_XFORM_ECPM:
 917                 otx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);
 918                 break;
 919         default:
 920                 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
 921                 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 922                 break;
 923         }
 924 }
 925
 926 static void
 927 otx2_cpt_sec_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
 928 {
 929         struct cpt_request_info *req = (struct cpt_request_info *)rsp[2];
 930         vq_cmd_word0_t *word0 = (vq_cmd_word0_t *)&req->ist.ei0;
 931         struct rte_crypto_sym_op *sym_op = cop->sym;
 932         struct rte_mbuf *m = sym_op->m_src;
 933         struct rte_ipv6_hdr *ip6;
 934         struct rte_ipv4_hdr *ip;
 935         uint16_t m_len = 0;
 936         int mdata_len;
 937         char *data;
 938
 939         mdata_len = (int)rsp[3];
 940         rte_pktmbuf_trim(m, mdata_len);
 941
 942         if (word0->s.opcode.major == OTX2_IPSEC_PO_PROCESS_IPSEC_INB) {
 943                 data = rte_pktmbuf_mtod(m, char *);
 944
 945                 if (rsp[4] == OTX2_IPSEC_PO_TRANSPORT ||
 946                     rsp[4] == OTX2_IPSEC_PO_TUNNEL_IPV4) {
 947                         ip = (struct rte_ipv4_hdr *)(data +
 948                                 OTX2_IPSEC_PO_INB_RPTR_HDR);
 949                         m_len = rte_be_to_cpu_16(ip->total_length);
 950                 } else if (rsp[4] == OTX2_IPSEC_PO_TUNNEL_IPV6) {
 951                         ip6 = (struct rte_ipv6_hdr *)(data +
 952                                 OTX2_IPSEC_PO_INB_RPTR_HDR);
 953                         m_len = rte_be_to_cpu_16(ip6->payload_len) +
 954                                 sizeof(struct rte_ipv6_hdr);
 955                 }
 956
 957                 m->data_len = m_len;
 958                 m->pkt_len = m_len;
 959                 m->data_off += OTX2_IPSEC_PO_INB_RPTR_HDR;
 960         }
 961 }
 962
 963 static inline void
 964 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
 965                               uintptr_t *rsp, uint8_t cc)
 966 {
 967         unsigned int sz;
 968
 969         if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
 970                 if (cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
 971                         if (likely(cc == OTX2_IPSEC_PO_CC_SUCCESS)) {
 972                                 otx2_cpt_sec_post_process(cop, rsp);
 973                                 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 974                         } else
 975                                 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
 976
 977                         return;
 978                 }
 979
 980                 if (likely(cc == NO_ERR)) {
 981                         /* Verify authentication data if required */
 982                         if (unlikely(rsp[2]))
 983                                 compl_auth_verify(cop, (uint8_t *)rsp[2],
 984                                                  rsp[3]);
 985                         else
 986                                 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 987                 } else {
 988                         if (cc == ERR_GC_ICV_MISCOMPARE)
 989                                 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 990                         else
 991                                 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
 992                 }
 993
 994                 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 995                         sym_session_clear(otx2_cryptodev_driver_id,
 996                                           cop->sym->session);
 997                         sz = rte_cryptodev_sym_get_existing_header_session_size(
 998                                         cop->sym->session);
 999                         memset(cop->sym->session, 0, sz);
1000                         rte_mempool_put(qp->sess_mp, cop->sym->session);
1001                         cop->sym->session = NULL;
1002                 }
1003         }
1004
1005         if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
1006                 if (likely(cc == NO_ERR)) {
1007                         cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1008                         /*
1009                          * Pass cpt_req_info stored in metabuf during
1010                          * enqueue.
1011                          */
1012                         rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
1013                         otx2_cpt_asym_post_process(cop,
1014                                         (struct cpt_request_info *)rsp);
1015                 } else
1016                         cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
1017         }
1018 }
1019
1020 static uint16_t
1021 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
1022 {
1023         int i, nb_pending, nb_completed;
1024         struct otx2_cpt_qp *qp = qptr;
1025         struct pending_queue *pend_q;
1026         struct cpt_request_info *req;
1027         struct rte_crypto_op *cop;
1028         uint8_t cc[nb_ops];
1029         uintptr_t *rsp;
1030         void *metabuf;
1031
1032         pend_q = &qp->pend_q;
1033
1034         nb_pending = pend_q->pending_count;
1035
1036         if (nb_ops > nb_pending)
1037                 nb_ops = nb_pending;
1038
1039         for (i = 0; i < nb_ops; i++) {
1040                 req = (struct cpt_request_info *)
1041                                 pend_q->req_queue[pend_q->deq_head];
1042
1043                 cc[i] = otx2_cpt_compcode_get(req);
1044
1045                 if (unlikely(cc[i] == ERR_REQ_PENDING))
1046                         break;
1047
1048                 ops[i] = req->op;
1049
1050                 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
1051                 pend_q->pending_count -= 1;
1052         }
1053
1054         nb_completed = i;
1055
1056         for (i = 0; i < nb_completed; i++) {
1057                 rsp = (void *)ops[i];
1058
1059                 metabuf = (void *)rsp[0];
1060                 cop = (void *)rsp[1];
1061
1062                 ops[i] = cop;
1063
1064                 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
1065
1066                 free_op_meta(metabuf, qp->meta_info.pool);
1067         }
1068
1069         return nb_completed;
1070 }
1071
1072 void
1073 otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)
1074 {
1075         dev->enqueue_burst = otx2_cpt_enqueue_burst;
1076         dev->dequeue_burst = otx2_cpt_dequeue_burst;
1077
1078         rte_mb();
1079 }
1080
1081 /* PMD ops */
1082
1083 static int
1084 otx2_cpt_dev_config(struct rte_cryptodev *dev,
1085                     struct rte_cryptodev_config *conf)
1086 {
1087         struct otx2_cpt_vf *vf = dev->data->dev_private;
1088         int ret;
1089
1090         if (conf->nb_queue_pairs > vf->max_queues) {
1091                 CPT_LOG_ERR("Invalid number of queue pairs requested");
1092                 return -EINVAL;
1093         }
1094
1095         dev->feature_flags &= ~conf->ff_disable;
1096
1097         if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
1098                 /* Initialize shared FPM table */
1099                 ret = cpt_fpm_init(otx2_fpm_iova);
1100                 if (ret)
1101                         return ret;
1102         }
1103
1104         /* Unregister error interrupts */
1105         if (vf->err_intr_registered)
1106                 otx2_cpt_err_intr_unregister(dev);
1107
1108         /* Detach queues */
1109         if (vf->nb_queues) {
1110                 ret = otx2_cpt_queues_detach(dev);
1111                 if (ret) {
1112                         CPT_LOG_ERR("Could not detach CPT queues");
1113                         return ret;
1114                 }
1115         }
1116
1117         /* Attach queues */
1118         ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
1119         if (ret) {
1120                 CPT_LOG_ERR("Could not attach CPT queues");
1121                 return -ENODEV;
1122         }
1123
1124         ret = otx2_cpt_msix_offsets_get(dev);
1125         if (ret) {
1126                 CPT_LOG_ERR("Could not get MSI-X offsets");
1127                 goto queues_detach;
1128         }
1129
1130         /* Register error interrupts */
1131         ret = otx2_cpt_err_intr_register(dev);
1132         if (ret) {
1133                 CPT_LOG_ERR("Could not register error interrupts");
1134                 goto queues_detach;
1135         }
1136
1137         ret = otx2_cpt_inline_init(dev);
1138         if (ret) {
1139                 CPT_LOG_ERR("Could not enable inline IPsec");
1140                 goto intr_unregister;
1141         }
1142
1143         otx2_cpt_set_enqdeq_fns(dev);
1144
1145         return 0;
1146
1147 intr_unregister:
1148         otx2_cpt_err_intr_unregister(dev);
1149 queues_detach:
1150         otx2_cpt_queues_detach(dev);
1151         return ret;
1152 }
1153
1154 static int
1155 otx2_cpt_dev_start(struct rte_cryptodev *dev)
1156 {
1157         RTE_SET_USED(dev);
1158
1159         CPT_PMD_INIT_FUNC_TRACE();
1160
1161         return 0;
1162 }
1163
1164 static void
1165 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
1166 {
1167         CPT_PMD_INIT_FUNC_TRACE();
1168
1169         if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
1170                 cpt_fpm_clear();
1171 }
1172
1173 static int
1174 otx2_cpt_dev_close(struct rte_cryptodev *dev)
1175 {
1176         struct otx2_cpt_vf *vf = dev->data->dev_private;
1177         int i, ret = 0;
1178
1179         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1180                 ret = otx2_cpt_queue_pair_release(dev, i);
1181                 if (ret)
1182                         return ret;
1183         }
1184
1185         /* Unregister error interrupts */
1186         if (vf->err_intr_registered)
1187                 otx2_cpt_err_intr_unregister(dev);
1188
1189         /* Detach queues */
1190         if (vf->nb_queues) {
1191                 ret = otx2_cpt_queues_detach(dev);
1192                 if (ret)
1193                         CPT_LOG_ERR("Could not detach CPT queues");
1194         }
1195
1196         return ret;
1197 }
1198
1199 static void
1200 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
1201                       struct rte_cryptodev_info *info)
1202 {
1203         struct otx2_cpt_vf *vf = dev->data->dev_private;
1204
1205         if (info != NULL) {
1206                 info->max_nb_queue_pairs = vf->max_queues;
1207                 info->feature_flags = dev->feature_flags;
1208                 info->capabilities = otx2_cpt_capabilities_get();
1209                 info->sym.max_nb_sessions = 0;
1210                 info->driver_id = otx2_cryptodev_driver_id;
1211                 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
1212                 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
1213         }
1214 }
1215
1216 static int
1217 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
1218                           const struct rte_cryptodev_qp_conf *conf,
1219                           int socket_id __rte_unused)
1220 {
1221         uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
1222         struct rte_pci_device *pci_dev;
1223         struct otx2_cpt_qp *qp;
1224
1225         CPT_PMD_INIT_FUNC_TRACE();
1226
1227         if (dev->data->queue_pairs[qp_id] != NULL)
1228                 otx2_cpt_queue_pair_release(dev, qp_id);
1229
1230         if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
1231                 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
1232                             conf->nb_descriptors);
1233                 return -EINVAL;
1234         }
1235
1236         pci_dev = RTE_DEV_TO_PCI(dev->device);
1237
1238         if (pci_dev->mem_resource[2].addr == NULL) {
1239                 CPT_LOG_ERR("Invalid PCI mem address");
1240                 return -EIO;
1241         }
1242
1243         qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
1244         if (qp == NULL) {
1245                 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
1246                 return -ENOMEM;
1247         }
1248
1249         qp->sess_mp = conf->mp_session;
1250         qp->sess_mp_priv = conf->mp_session_private;
1251         dev->data->queue_pairs[qp_id] = qp;
1252
1253         return 0;
1254 }
1255
1256 static int
1257 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
1258 {
1259         struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
1260         int ret;
1261
1262         CPT_PMD_INIT_FUNC_TRACE();
1263
1264         if (qp == NULL)
1265                 return -EINVAL;
1266
1267         CPT_LOG_INFO("Releasing queue pair %d", qp_id);
1268
1269         ret = otx2_cpt_qp_destroy(dev, qp);
1270         if (ret) {
1271                 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
1272                 return ret;
1273         }
1274
1275         dev->data->queue_pairs[qp_id] = NULL;
1276
1277         return 0;
1278 }
1279
1280 static unsigned int
1281 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1282 {
1283         return cpt_get_session_size();
1284 }
1285
1286 static int
1287 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1288                                struct rte_crypto_sym_xform *xform,
1289                                struct rte_cryptodev_sym_session *sess,
1290                                struct rte_mempool *pool)
1291 {
1292         CPT_PMD_INIT_FUNC_TRACE();
1293
1294         return sym_session_configure(dev->driver_id, xform, sess, pool);
1295 }
1296
1297 static void
1298 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1299                            struct rte_cryptodev_sym_session *sess)
1300 {
1301         CPT_PMD_INIT_FUNC_TRACE();
1302
1303         return sym_session_clear(dev->driver_id, sess);
1304 }
1305
1306 static unsigned int
1307 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1308 {
1309         return sizeof(struct cpt_asym_sess_misc);
1310 }
1311
1312 static int
1313 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1314                           struct rte_crypto_asym_xform *xform,
1315                           struct rte_cryptodev_asym_session *sess,
1316                           struct rte_mempool *pool)
1317 {
1318         struct cpt_asym_sess_misc *priv;
1319         vq_cmd_word3_t vq_cmd_w3;
1320         int ret;
1321
1322         CPT_PMD_INIT_FUNC_TRACE();
1323
1324         if (rte_mempool_get(pool, (void **)&priv)) {
1325                 CPT_LOG_ERR("Could not allocate session_private_data");
1326                 return -ENOMEM;
1327         }
1328
1329         memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1330
1331         ret = cpt_fill_asym_session_parameters(priv, xform);
1332         if (ret) {
1333                 CPT_LOG_ERR("Could not configure session parameters");
1334
1335                 /* Return session to mempool */
1336                 rte_mempool_put(pool, priv);
1337                 return ret;
1338         }
1339
1340         vq_cmd_w3.u64 = 0;
1341         vq_cmd_w3.s.grp = OTX2_CPT_EGRP_AE;
1342         priv->cpt_inst_w7 = vq_cmd_w3.u64;
1343
1344         set_asym_session_private_data(sess, dev->driver_id, priv);
1345
1346         return 0;
1347 }
1348
1349 static void
1350 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1351                             struct rte_cryptodev_asym_session *sess)
1352 {
1353         struct cpt_asym_sess_misc *priv;
1354         struct rte_mempool *sess_mp;
1355
1356         CPT_PMD_INIT_FUNC_TRACE();
1357
1358         priv = get_asym_session_private_data(sess, dev->driver_id);
1359         if (priv == NULL)
1360                 return;
1361
1362         /* Free resources allocated in session_cfg */
1363         cpt_free_asym_session_parameters(priv);
1364
1365         /* Reset and free object back to pool */
1366         memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1367         sess_mp = rte_mempool_from_obj(priv);
1368         set_asym_session_private_data(sess, dev->driver_id, NULL);
1369         rte_mempool_put(sess_mp, priv);
1370 }
1371
1372 struct rte_cryptodev_ops otx2_cpt_ops = {
1373         /* Device control ops */
1374         .dev_configure = otx2_cpt_dev_config,
1375         .dev_start = otx2_cpt_dev_start,
1376         .dev_stop = otx2_cpt_dev_stop,
1377         .dev_close = otx2_cpt_dev_close,
1378         .dev_infos_get = otx2_cpt_dev_info_get,
1379
1380         .stats_get = NULL,
1381         .stats_reset = NULL,
1382         .queue_pair_setup = otx2_cpt_queue_pair_setup,
1383         .queue_pair_release = otx2_cpt_queue_pair_release,
1384
1385         /* Symmetric crypto ops */
1386         .sym_session_get_size = otx2_cpt_sym_session_get_size,
1387         .sym_session_configure = otx2_cpt_sym_session_configure,
1388         .sym_session_clear = otx2_cpt_sym_session_clear,
1389
1390         /* Asymmetric crypto ops */
1391         .asym_session_get_size = otx2_cpt_asym_session_size_get,
1392         .asym_session_configure = otx2_cpt_asym_session_cfg,
1393         .asym_session_clear = otx2_cpt_asym_session_clear,
1394
1395 };