1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright (C) 2019 Marvell International Ltd.
7 #include <rte_cryptodev_pmd.h>
9 #include <rte_ethdev.h>
11 #include "otx2_cryptodev.h"
12 #include "otx2_cryptodev_capabilities.h"
13 #include "otx2_cryptodev_hw_access.h"
14 #include "otx2_cryptodev_mbox.h"
15 #include "otx2_cryptodev_ops.h"
16 #include "otx2_cryptodev_ops_helper.h"
17 #include "otx2_ipsec_po_ops.h"
18 #include "otx2_mbox.h"
19 #include "otx2_sec_idev.h"
20 #include "otx2_security.h"
22 #include "cpt_hw_types.h"
23 #include "cpt_pmd_logs.h"
24 #include "cpt_pmd_ops_helper.h"
25 #include "cpt_ucode.h"
26 #include "cpt_ucode_asym.h"
28 #define METABUF_POOL_CACHE_SIZE 512
30 static uint64_t otx2_fpm_iova[CPT_EC_ID_PMAX];
32 /* Forward declarations */
35 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);
38 qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)
40 snprintf(name, size, "otx2_cpt_lf_mem_%u:%u", dev_id, qp_id);
44 otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,
45 struct otx2_cpt_qp *qp, uint8_t qp_id,
48 char mempool_name[RTE_MEMPOOL_NAMESIZE];
49 struct cpt_qp_meta_info *meta_info;
50 struct rte_mempool *pool;
56 if (dev->feature_flags & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {
58 /* Get meta len for scatter gather mode */
59 sg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();
61 /* Extra 32B saved for future considerations */
62 sg_mlen += 4 * sizeof(uint64_t);
64 /* Get meta len for linear buffer (direct) mode */
65 lb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();
67 /* Extra 32B saved for future considerations */
68 lb_mlen += 4 * sizeof(uint64_t);
71 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
73 /* Get meta len required for asymmetric operations */
74 asym_mlen = cpt_pmd_ops_helper_asym_get_mlen();
78 * Check max requirement for meta buffer to
79 * support crypto op of any type (sym/asym).
81 max_mlen = RTE_MAX(RTE_MAX(lb_mlen, sg_mlen), asym_mlen);
83 /* Allocate mempool */
85 snprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, "otx2_cpt_mb_%u:%u",
86 dev->data->dev_id, qp_id);
88 pool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,
89 METABUF_POOL_CACHE_SIZE, 0,
93 CPT_LOG_ERR("Could not create mempool for metabuf");
97 ret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,
100 CPT_LOG_ERR("Could not set mempool ops");
104 ret = rte_mempool_populate_default(pool);
106 CPT_LOG_ERR("Could not populate metabuf pool");
110 meta_info = &qp->meta_info;
112 meta_info->pool = pool;
113 meta_info->lb_mlen = lb_mlen;
114 meta_info->sg_mlen = sg_mlen;
119 rte_mempool_free(pool);
124 otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)
126 struct cpt_qp_meta_info *meta_info = &qp->meta_info;
128 rte_mempool_free(meta_info->pool);
130 meta_info->pool = NULL;
131 meta_info->lb_mlen = 0;
132 meta_info->sg_mlen = 0;
136 otx2_cpt_qp_inline_cfg(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
138 static rte_atomic16_t port_offset = RTE_ATOMIC16_INIT(-1);
139 uint16_t port_id, nb_ethport = rte_eth_dev_count_avail();
142 for (i = 0; i < nb_ethport; i++) {
143 port_id = rte_atomic16_add_return(&port_offset, 1) % nb_ethport;
144 if (otx2_eth_dev_is_sec_capable(&rte_eth_devices[port_id]))
151 ret = otx2_cpt_qp_ethdev_bind(dev, qp, port_id);
155 /* Publish inline Tx QP to eth dev security */
156 ret = otx2_sec_idev_tx_cpt_qp_add(port_id, qp);
163 static struct otx2_cpt_qp *
164 otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,
167 struct otx2_cpt_vf *vf = dev->data->dev_private;
168 uint64_t pg_sz = sysconf(_SC_PAGESIZE);
169 const struct rte_memzone *lf_mem;
170 uint32_t len, iq_len, size_div40;
171 char name[RTE_MEMZONE_NAMESIZE];
172 uint64_t used_len, iova;
173 struct otx2_cpt_qp *qp;
178 /* Allocate queue pair */
179 qp = rte_zmalloc_socket("OCTEON TX2 Crypto PMD Queue Pair", sizeof(*qp),
182 CPT_LOG_ERR("Could not allocate queue pair");
186 iq_len = OTX2_CPT_IQ_LEN;
189 * Queue size must be a multiple of 40 and effective queue size to
190 * software is (size_div40 - 1) * 40
192 size_div40 = (iq_len + 40 - 1) / 40 + 1;
194 /* For pending queue */
195 len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
197 /* Space for instruction group memory */
198 len += size_div40 * 16;
200 /* So that instruction queues start as pg size aligned */
201 len = RTE_ALIGN(len, pg_sz);
203 /* For instruction queues */
204 len += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);
206 /* Wastage after instruction queues */
207 len = RTE_ALIGN(len, pg_sz);
209 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
212 lf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,
213 RTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,
214 RTE_CACHE_LINE_SIZE);
215 if (lf_mem == NULL) {
216 CPT_LOG_ERR("Could not allocate reserved memzone");
225 ret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);
227 CPT_LOG_ERR("Could not create mempool for metabuf");
231 /* Initialize pending queue */
232 qp->pend_q.rid_queue = (struct rid *)va;
233 qp->pend_q.enq_tail = 0;
234 qp->pend_q.deq_head = 0;
235 qp->pend_q.pending_count = 0;
237 used_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);
238 used_len += size_div40 * 16;
239 used_len = RTE_ALIGN(used_len, pg_sz);
242 qp->iq_dma_addr = iova;
244 qp->base = OTX2_CPT_LF_BAR2(vf, qp_id);
246 lmtline = vf->otx2_dev.bar2 +
247 (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +
248 OTX2_LMT_LF_LMTLINE(0);
250 qp->lmtline = (void *)lmtline;
252 qp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);
254 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
255 if (ret && (ret != -ENOENT)) {
256 CPT_LOG_ERR("Could not delete inline configuration");
257 goto mempool_destroy;
260 otx2_cpt_iq_disable(qp);
262 ret = otx2_cpt_qp_inline_cfg(dev, qp);
264 CPT_LOG_ERR("Could not configure queue for inline IPsec");
265 goto mempool_destroy;
268 ret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,
271 CPT_LOG_ERR("Could not enable instruction queue");
272 goto mempool_destroy;
278 otx2_cpt_metabuf_mempool_destroy(qp);
280 rte_memzone_free(lf_mem);
287 otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)
289 const struct rte_memzone *lf_mem;
290 char name[RTE_MEMZONE_NAMESIZE];
293 ret = otx2_sec_idev_tx_cpt_qp_remove(qp);
294 if (ret && (ret != -ENOENT)) {
295 CPT_LOG_ERR("Could not delete inline configuration");
299 otx2_cpt_iq_disable(qp);
301 otx2_cpt_metabuf_mempool_destroy(qp);
303 qp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,
306 lf_mem = rte_memzone_lookup(name);
308 ret = rte_memzone_free(lf_mem);
318 sym_xform_verify(struct rte_crypto_sym_xform *xform)
321 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
322 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
323 xform->next->cipher.op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
326 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
327 xform->cipher.op == RTE_CRYPTO_CIPHER_OP_DECRYPT &&
328 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
331 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
332 xform->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC &&
333 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
334 xform->next->auth.algo == RTE_CRYPTO_AUTH_SHA1)
337 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
338 xform->auth.algo == RTE_CRYPTO_AUTH_SHA1 &&
339 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
340 xform->next->cipher.algo == RTE_CRYPTO_CIPHER_3DES_CBC)
344 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
345 xform->auth.algo == RTE_CRYPTO_AUTH_NULL &&
346 xform->auth.op == RTE_CRYPTO_AUTH_OP_VERIFY)
353 sym_session_configure(int driver_id, struct rte_crypto_sym_xform *xform,
354 struct rte_cryptodev_sym_session *sess,
355 struct rte_mempool *pool)
357 struct rte_crypto_sym_xform *temp_xform = xform;
358 struct cpt_sess_misc *misc;
359 vq_cmd_word3_t vq_cmd_w3;
363 ret = sym_xform_verify(xform);
367 if (unlikely(rte_mempool_get(pool, &priv))) {
368 CPT_LOG_ERR("Could not allocate session private data");
372 memset(priv, 0, sizeof(struct cpt_sess_misc) +
373 offsetof(struct cpt_ctx, mc_ctx));
377 for ( ; xform != NULL; xform = xform->next) {
378 switch (xform->type) {
379 case RTE_CRYPTO_SYM_XFORM_AEAD:
380 ret = fill_sess_aead(xform, misc);
382 case RTE_CRYPTO_SYM_XFORM_CIPHER:
383 ret = fill_sess_cipher(xform, misc);
385 case RTE_CRYPTO_SYM_XFORM_AUTH:
386 if (xform->auth.algo == RTE_CRYPTO_AUTH_AES_GMAC)
387 ret = fill_sess_gmac(xform, misc);
389 ret = fill_sess_auth(xform, misc);
399 if ((GET_SESS_FC_TYPE(misc) == HASH_HMAC) &&
400 cpt_mac_len_verify(&temp_xform->auth)) {
401 CPT_LOG_ERR("MAC length is not supported");
406 set_sym_session_private_data(sess, driver_id, misc);
408 misc->ctx_dma_addr = rte_mempool_virt2iova(misc) +
409 sizeof(struct cpt_sess_misc);
412 vq_cmd_w3.s.cptr = misc->ctx_dma_addr + offsetof(struct cpt_ctx,
416 * IE engines support IPsec operations
417 * SE engines support IPsec operations, Chacha-Poly and
418 * Air-Crypto operations
420 if (misc->zsk_flag || misc->chacha_poly)
421 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE;
423 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_SE_IE;
425 misc->cpt_inst_w7 = vq_cmd_w3.u64;
430 rte_mempool_put(pool, priv);
435 static __rte_always_inline void __rte_hot
436 otx2_ca_enqueue_req(const struct otx2_cpt_qp *qp,
437 struct cpt_request_info *req,
439 uint64_t cpt_inst_w7)
441 union cpt_inst_s inst;
445 inst.s9x.res_addr = req->comp_baddr;
449 inst.s9x.ei0 = req->ist.ei0;
450 inst.s9x.ei1 = req->ist.ei1;
451 inst.s9x.ei2 = req->ist.ei2;
452 inst.s9x.ei3 = cpt_inst_w7;
455 inst.s9x.grp = qp->ev.queue_id;
456 inst.s9x.tt = qp->ev.sched_type;
457 inst.s9x.tag = (RTE_EVENT_TYPE_CRYPTODEV << 28) |
459 inst.s9x.wq_ptr = (uint64_t)req >> 3;
463 /* Copy CPT command to LMTLINE */
464 memcpy(lmtline, &inst, sizeof(inst));
467 * Make sure compiler does not reorder memcpy and ldeor.
468 * LMTST transactions are always flushed from the write
469 * buffer immediately, a DMB is not required to push out
473 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
474 } while (lmt_status == 0);
478 static __rte_always_inline int32_t __rte_hot
479 otx2_cpt_enqueue_req(const struct otx2_cpt_qp *qp,
480 struct pending_queue *pend_q,
481 struct cpt_request_info *req,
482 uint64_t cpt_inst_w7)
484 void *lmtline = qp->lmtline;
485 union cpt_inst_s inst;
489 otx2_ca_enqueue_req(qp, req, lmtline, cpt_inst_w7);
493 if (unlikely(pend_q->pending_count >= OTX2_CPT_DEFAULT_CMD_QLEN))
497 inst.s9x.res_addr = req->comp_baddr;
501 inst.s9x.ei0 = req->ist.ei0;
502 inst.s9x.ei1 = req->ist.ei1;
503 inst.s9x.ei2 = req->ist.ei2;
504 inst.s9x.ei3 = cpt_inst_w7;
506 req->time_out = rte_get_timer_cycles() +
507 DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();
510 /* Copy CPT command to LMTLINE */
511 memcpy(lmtline, &inst, sizeof(inst));
514 * Make sure compiler does not reorder memcpy and ldeor.
515 * LMTST transactions are always flushed from the write
516 * buffer immediately, a DMB is not required to push out
520 lmt_status = otx2_lmt_submit(qp->lf_nq_reg);
521 } while (lmt_status == 0);
523 pend_q->rid_queue[pend_q->enq_tail].rid = (uintptr_t)req;
525 /* We will use soft queue length here to limit requests */
526 MOD_INC(pend_q->enq_tail, OTX2_CPT_DEFAULT_CMD_QLEN);
527 pend_q->pending_count += 1;
532 static __rte_always_inline int32_t __rte_hot
533 otx2_cpt_enqueue_asym(struct otx2_cpt_qp *qp,
534 struct rte_crypto_op *op,
535 struct pending_queue *pend_q)
537 struct cpt_qp_meta_info *minfo = &qp->meta_info;
538 struct rte_crypto_asym_op *asym_op = op->asym;
539 struct asym_op_params params = {0};
540 struct cpt_asym_sess_misc *sess;
545 if (unlikely(rte_mempool_get(minfo->pool, &mdata) < 0)) {
546 CPT_LOG_ERR("Could not allocate meta buffer for request");
550 sess = get_asym_session_private_data(asym_op->session,
551 otx2_cryptodev_driver_id);
553 /* Store IO address of the mdata to meta_buf */
554 params.meta_buf = rte_mempool_virt2iova(mdata);
557 cop[0] = (uintptr_t)mdata;
558 cop[1] = (uintptr_t)op;
559 cop[2] = cop[3] = 0ULL;
561 params.req = RTE_PTR_ADD(cop, 4 * sizeof(uintptr_t));
562 params.req->op = cop;
564 /* Adjust meta_buf to point to end of cpt_request_info structure */
565 params.meta_buf += (4 * sizeof(uintptr_t)) +
566 sizeof(struct cpt_request_info);
567 switch (sess->xfrm_type) {
568 case RTE_CRYPTO_ASYM_XFORM_MODEX:
569 ret = cpt_modex_prep(¶ms, &sess->mod_ctx);
573 case RTE_CRYPTO_ASYM_XFORM_RSA:
574 ret = cpt_enqueue_rsa_op(op, ¶ms, sess);
578 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
579 ret = cpt_enqueue_ecdsa_op(op, ¶ms, sess, otx2_fpm_iova);
583 case RTE_CRYPTO_ASYM_XFORM_ECPM:
584 ret = cpt_ecpm_prep(&asym_op->ecpm, ¶ms,
585 sess->ec_ctx.curveid);
590 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
595 ret = otx2_cpt_enqueue_req(qp, pend_q, params.req, sess->cpt_inst_w7);
598 CPT_LOG_DP_ERR("Could not enqueue crypto req");
605 free_op_meta(mdata, minfo->pool);
610 static __rte_always_inline int __rte_hot
611 otx2_cpt_enqueue_sym(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
612 struct pending_queue *pend_q)
614 struct rte_crypto_sym_op *sym_op = op->sym;
615 struct cpt_request_info *req;
616 struct cpt_sess_misc *sess;
621 sess = get_sym_session_private_data(sym_op->session,
622 otx2_cryptodev_driver_id);
624 cpt_op = sess->cpt_op;
626 if (cpt_op & CPT_OP_CIPHER_MASK)
627 ret = fill_fc_params(op, sess, &qp->meta_info, &mdata,
630 ret = fill_digest_params(op, sess, &qp->meta_info, &mdata,
634 CPT_LOG_DP_ERR("Crypto req : op %p, cpt_op 0x%x ret 0x%x",
635 op, (unsigned int)cpt_op, ret);
639 ret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);
642 /* Free buffer allocated by fill params routines */
643 free_op_meta(mdata, qp->meta_info.pool);
649 static __rte_always_inline int __rte_hot
650 otx2_cpt_enqueue_sec(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
651 struct pending_queue *pend_q)
653 struct otx2_sec_session_ipsec_lp *sess;
654 struct otx2_ipsec_po_sa_ctl *ctl_wrd;
655 struct otx2_sec_session *priv;
656 struct cpt_request_info *req;
659 priv = get_sec_session_private_data(op->sym->sec_session);
660 sess = &priv->ipsec.lp;
662 ctl_wrd = &sess->in_sa.ctl;
664 if (ctl_wrd->direction == OTX2_IPSEC_PO_SA_DIRECTION_OUTBOUND)
665 ret = process_outb_sa(op, sess, &qp->meta_info, (void **)&req);
667 ret = process_inb_sa(op, sess, &qp->meta_info, (void **)&req);
670 otx2_err("Crypto req : op %p, ret 0x%x", op, ret);
674 ret = otx2_cpt_enqueue_req(qp, pend_q, req, sess->cpt_inst_w7);
679 static __rte_always_inline int __rte_hot
680 otx2_cpt_enqueue_sym_sessless(struct otx2_cpt_qp *qp, struct rte_crypto_op *op,
681 struct pending_queue *pend_q)
683 const int driver_id = otx2_cryptodev_driver_id;
684 struct rte_crypto_sym_op *sym_op = op->sym;
685 struct rte_cryptodev_sym_session *sess;
688 /* Create temporary session */
689 sess = rte_cryptodev_sym_session_create(qp->sess_mp);
693 ret = sym_session_configure(driver_id, sym_op->xform, sess,
698 sym_op->session = sess;
700 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
708 sym_session_clear(driver_id, sess);
710 rte_mempool_put(qp->sess_mp, sess);
715 otx2_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
717 uint16_t nb_allowed, count = 0;
718 struct otx2_cpt_qp *qp = qptr;
719 struct pending_queue *pend_q;
720 struct rte_crypto_op *op;
723 pend_q = &qp->pend_q;
725 nb_allowed = OTX2_CPT_DEFAULT_CMD_QLEN - pend_q->pending_count;
726 if (nb_ops > nb_allowed)
729 for (count = 0; count < nb_ops; count++) {
731 if (op->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
732 if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION)
733 ret = otx2_cpt_enqueue_sec(qp, op, pend_q);
734 else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
735 ret = otx2_cpt_enqueue_sym(qp, op, pend_q);
737 ret = otx2_cpt_enqueue_sym_sessless(qp, op,
739 } else if (op->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
740 if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION)
741 ret = otx2_cpt_enqueue_asym(qp, op, pend_q);
754 static __rte_always_inline void
755 otx2_cpt_asym_rsa_op(struct rte_crypto_op *cop, struct cpt_request_info *req,
756 struct rte_crypto_rsa_xform *rsa_ctx)
758 struct rte_crypto_rsa_op_param *rsa = &cop->asym->rsa;
760 switch (rsa->op_type) {
761 case RTE_CRYPTO_ASYM_OP_ENCRYPT:
762 rsa->cipher.length = rsa_ctx->n.length;
763 memcpy(rsa->cipher.data, req->rptr, rsa->cipher.length);
765 case RTE_CRYPTO_ASYM_OP_DECRYPT:
766 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
767 rsa->message.length = rsa_ctx->n.length;
768 memcpy(rsa->message.data, req->rptr,
769 rsa->message.length);
771 /* Get length of decrypted output */
772 rsa->message.length = rte_cpu_to_be_16
773 (*((uint16_t *)req->rptr));
775 * Offset output data pointer by length field
776 * (2 bytes) and copy decrypted data.
778 memcpy(rsa->message.data, req->rptr + 2,
779 rsa->message.length);
782 case RTE_CRYPTO_ASYM_OP_SIGN:
783 rsa->sign.length = rsa_ctx->n.length;
784 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
786 case RTE_CRYPTO_ASYM_OP_VERIFY:
787 if (rsa->pad == RTE_CRYPTO_RSA_PADDING_NONE) {
788 rsa->sign.length = rsa_ctx->n.length;
789 memcpy(rsa->sign.data, req->rptr, rsa->sign.length);
791 /* Get length of signed output */
792 rsa->sign.length = rte_cpu_to_be_16
793 (*((uint16_t *)req->rptr));
795 * Offset output data pointer by length field
796 * (2 bytes) and copy signed data.
798 memcpy(rsa->sign.data, req->rptr + 2,
801 if (memcmp(rsa->sign.data, rsa->message.data,
802 rsa->message.length)) {
803 CPT_LOG_DP_ERR("RSA verification failed");
804 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
808 CPT_LOG_DP_DEBUG("Invalid RSA operation type");
809 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
814 static __rte_always_inline void
815 otx2_cpt_asym_dequeue_ecdsa_op(struct rte_crypto_ecdsa_op_param *ecdsa,
816 struct cpt_request_info *req,
817 struct cpt_asym_ec_ctx *ec)
819 int prime_len = ec_grp[ec->curveid].prime.length;
821 if (ecdsa->op_type == RTE_CRYPTO_ASYM_OP_VERIFY)
824 /* Separate out sign r and s components */
825 memcpy(ecdsa->r.data, req->rptr, prime_len);
826 memcpy(ecdsa->s.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
828 ecdsa->r.length = prime_len;
829 ecdsa->s.length = prime_len;
832 static __rte_always_inline void
833 otx2_cpt_asym_dequeue_ecpm_op(struct rte_crypto_ecpm_op_param *ecpm,
834 struct cpt_request_info *req,
835 struct cpt_asym_ec_ctx *ec)
837 int prime_len = ec_grp[ec->curveid].prime.length;
839 memcpy(ecpm->r.x.data, req->rptr, prime_len);
840 memcpy(ecpm->r.y.data, req->rptr + RTE_ALIGN_CEIL(prime_len, 8),
842 ecpm->r.x.length = prime_len;
843 ecpm->r.y.length = prime_len;
847 otx2_cpt_asym_post_process(struct rte_crypto_op *cop,
848 struct cpt_request_info *req)
850 struct rte_crypto_asym_op *op = cop->asym;
851 struct cpt_asym_sess_misc *sess;
853 sess = get_asym_session_private_data(op->session,
854 otx2_cryptodev_driver_id);
856 switch (sess->xfrm_type) {
857 case RTE_CRYPTO_ASYM_XFORM_RSA:
858 otx2_cpt_asym_rsa_op(cop, req, &sess->rsa_ctx);
860 case RTE_CRYPTO_ASYM_XFORM_MODEX:
861 op->modex.result.length = sess->mod_ctx.modulus.length;
862 memcpy(op->modex.result.data, req->rptr,
863 op->modex.result.length);
865 case RTE_CRYPTO_ASYM_XFORM_ECDSA:
866 otx2_cpt_asym_dequeue_ecdsa_op(&op->ecdsa, req, &sess->ec_ctx);
868 case RTE_CRYPTO_ASYM_XFORM_ECPM:
869 otx2_cpt_asym_dequeue_ecpm_op(&op->ecpm, req, &sess->ec_ctx);
872 CPT_LOG_DP_DEBUG("Invalid crypto xform type");
873 cop->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
879 otx2_cpt_sec_post_process(struct rte_crypto_op *cop, uintptr_t *rsp)
881 struct cpt_request_info *req = (struct cpt_request_info *)rsp[2];
882 vq_cmd_word0_t *word0 = (vq_cmd_word0_t *)&req->ist.ei0;
883 struct rte_crypto_sym_op *sym_op = cop->sym;
884 struct rte_mbuf *m = sym_op->m_src;
885 struct rte_ipv6_hdr *ip6;
886 struct rte_ipv4_hdr *ip;
891 mdata_len = (int)rsp[3];
892 rte_pktmbuf_trim(m, mdata_len);
894 if (word0->s.opcode.major == OTX2_IPSEC_PO_PROCESS_IPSEC_INB) {
895 data = rte_pktmbuf_mtod(m, char *);
897 if (rsp[4] == RTE_SECURITY_IPSEC_TUNNEL_IPV4) {
898 ip = (struct rte_ipv4_hdr *)(data +
899 OTX2_IPSEC_PO_INB_RPTR_HDR);
900 m_len = rte_be_to_cpu_16(ip->total_length);
902 ip6 = (struct rte_ipv6_hdr *)(data +
903 OTX2_IPSEC_PO_INB_RPTR_HDR);
904 m_len = rte_be_to_cpu_16(ip6->payload_len) +
905 sizeof(struct rte_ipv6_hdr);
910 m->data_off += OTX2_IPSEC_PO_INB_RPTR_HDR;
915 otx2_cpt_dequeue_post_process(struct otx2_cpt_qp *qp, struct rte_crypto_op *cop,
916 uintptr_t *rsp, uint8_t cc)
920 if (cop->type == RTE_CRYPTO_OP_TYPE_SYMMETRIC) {
921 if (cop->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {
922 if (likely(cc == OTX2_IPSEC_PO_CC_SUCCESS)) {
923 otx2_cpt_sec_post_process(cop, rsp);
924 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
926 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
931 if (likely(cc == NO_ERR)) {
932 /* Verify authentication data if required */
933 if (unlikely(rsp[2]))
934 compl_auth_verify(cop, (uint8_t *)rsp[2],
937 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
939 if (cc == ERR_GC_ICV_MISCOMPARE)
940 cop->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
942 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
945 if (unlikely(cop->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
946 sym_session_clear(otx2_cryptodev_driver_id,
948 sz = rte_cryptodev_sym_get_existing_header_session_size(
950 memset(cop->sym->session, 0, sz);
951 rte_mempool_put(qp->sess_mp, cop->sym->session);
952 cop->sym->session = NULL;
956 if (cop->type == RTE_CRYPTO_OP_TYPE_ASYMMETRIC) {
957 if (likely(cc == NO_ERR)) {
958 cop->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
960 * Pass cpt_req_info stored in metabuf during
963 rsp = RTE_PTR_ADD(rsp, 4 * sizeof(uintptr_t));
964 otx2_cpt_asym_post_process(cop,
965 (struct cpt_request_info *)rsp);
967 cop->status = RTE_CRYPTO_OP_STATUS_ERROR;
972 otx2_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)
974 int i, nb_pending, nb_completed;
975 struct otx2_cpt_qp *qp = qptr;
976 struct pending_queue *pend_q;
977 struct cpt_request_info *req;
978 struct rte_crypto_op *cop;
984 pend_q = &qp->pend_q;
986 nb_pending = pend_q->pending_count;
988 if (nb_ops > nb_pending)
991 for (i = 0; i < nb_ops; i++) {
992 rid = &pend_q->rid_queue[pend_q->deq_head];
993 req = (struct cpt_request_info *)(rid->rid);
995 cc[i] = otx2_cpt_compcode_get(req);
997 if (unlikely(cc[i] == ERR_REQ_PENDING))
1002 MOD_INC(pend_q->deq_head, OTX2_CPT_DEFAULT_CMD_QLEN);
1003 pend_q->pending_count -= 1;
1008 for (i = 0; i < nb_completed; i++) {
1009 rsp = (void *)ops[i];
1011 metabuf = (void *)rsp[0];
1012 cop = (void *)rsp[1];
1016 otx2_cpt_dequeue_post_process(qp, cop, rsp, cc[i]);
1018 free_op_meta(metabuf, qp->meta_info.pool);
1021 return nb_completed;
1025 otx2_cpt_set_enqdeq_fns(struct rte_cryptodev *dev)
1027 dev->enqueue_burst = otx2_cpt_enqueue_burst;
1028 dev->dequeue_burst = otx2_cpt_dequeue_burst;
1036 otx2_cpt_dev_config(struct rte_cryptodev *dev,
1037 struct rte_cryptodev_config *conf)
1039 struct otx2_cpt_vf *vf = dev->data->dev_private;
1042 if (conf->nb_queue_pairs > vf->max_queues) {
1043 CPT_LOG_ERR("Invalid number of queue pairs requested");
1047 dev->feature_flags &= ~conf->ff_disable;
1049 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO) {
1050 /* Initialize shared FPM table */
1051 ret = cpt_fpm_init(otx2_fpm_iova);
1056 /* Unregister error interrupts */
1057 if (vf->err_intr_registered)
1058 otx2_cpt_err_intr_unregister(dev);
1061 if (vf->nb_queues) {
1062 ret = otx2_cpt_queues_detach(dev);
1064 CPT_LOG_ERR("Could not detach CPT queues");
1070 ret = otx2_cpt_queues_attach(dev, conf->nb_queue_pairs);
1072 CPT_LOG_ERR("Could not attach CPT queues");
1076 ret = otx2_cpt_msix_offsets_get(dev);
1078 CPT_LOG_ERR("Could not get MSI-X offsets");
1082 /* Register error interrupts */
1083 ret = otx2_cpt_err_intr_register(dev);
1085 CPT_LOG_ERR("Could not register error interrupts");
1089 ret = otx2_cpt_inline_init(dev);
1091 CPT_LOG_ERR("Could not enable inline IPsec");
1092 goto intr_unregister;
1095 otx2_cpt_set_enqdeq_fns(dev);
1100 otx2_cpt_err_intr_unregister(dev);
1102 otx2_cpt_queues_detach(dev);
1107 otx2_cpt_dev_start(struct rte_cryptodev *dev)
1111 CPT_PMD_INIT_FUNC_TRACE();
1117 otx2_cpt_dev_stop(struct rte_cryptodev *dev)
1119 CPT_PMD_INIT_FUNC_TRACE();
1121 if (dev->feature_flags & RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO)
1126 otx2_cpt_dev_close(struct rte_cryptodev *dev)
1128 struct otx2_cpt_vf *vf = dev->data->dev_private;
1131 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1132 ret = otx2_cpt_queue_pair_release(dev, i);
1137 /* Unregister error interrupts */
1138 if (vf->err_intr_registered)
1139 otx2_cpt_err_intr_unregister(dev);
1142 if (vf->nb_queues) {
1143 ret = otx2_cpt_queues_detach(dev);
1145 CPT_LOG_ERR("Could not detach CPT queues");
1152 otx2_cpt_dev_info_get(struct rte_cryptodev *dev,
1153 struct rte_cryptodev_info *info)
1155 struct otx2_cpt_vf *vf = dev->data->dev_private;
1158 info->max_nb_queue_pairs = vf->max_queues;
1159 info->feature_flags = dev->feature_flags;
1160 info->capabilities = otx2_cpt_capabilities_get();
1161 info->sym.max_nb_sessions = 0;
1162 info->driver_id = otx2_cryptodev_driver_id;
1163 info->min_mbuf_headroom_req = OTX2_CPT_MIN_HEADROOM_REQ;
1164 info->min_mbuf_tailroom_req = OTX2_CPT_MIN_TAILROOM_REQ;
1169 otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,
1170 const struct rte_cryptodev_qp_conf *conf,
1171 int socket_id __rte_unused)
1173 uint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;
1174 struct rte_pci_device *pci_dev;
1175 struct otx2_cpt_qp *qp;
1177 CPT_PMD_INIT_FUNC_TRACE();
1179 if (dev->data->queue_pairs[qp_id] != NULL)
1180 otx2_cpt_queue_pair_release(dev, qp_id);
1182 if (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {
1183 CPT_LOG_ERR("Could not setup queue pair for %u descriptors",
1184 conf->nb_descriptors);
1188 pci_dev = RTE_DEV_TO_PCI(dev->device);
1190 if (pci_dev->mem_resource[2].addr == NULL) {
1191 CPT_LOG_ERR("Invalid PCI mem address");
1195 qp = otx2_cpt_qp_create(dev, qp_id, grp_mask);
1197 CPT_LOG_ERR("Could not create queue pair %d", qp_id);
1201 qp->sess_mp = conf->mp_session;
1202 qp->sess_mp_priv = conf->mp_session_private;
1203 dev->data->queue_pairs[qp_id] = qp;
1209 otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)
1211 struct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];
1214 CPT_PMD_INIT_FUNC_TRACE();
1219 CPT_LOG_INFO("Releasing queue pair %d", qp_id);
1221 ret = otx2_cpt_qp_destroy(dev, qp);
1223 CPT_LOG_ERR("Could not destroy queue pair %d", qp_id);
1227 dev->data->queue_pairs[qp_id] = NULL;
1233 otx2_cpt_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)
1235 return cpt_get_session_size();
1239 otx2_cpt_sym_session_configure(struct rte_cryptodev *dev,
1240 struct rte_crypto_sym_xform *xform,
1241 struct rte_cryptodev_sym_session *sess,
1242 struct rte_mempool *pool)
1244 CPT_PMD_INIT_FUNC_TRACE();
1246 return sym_session_configure(dev->driver_id, xform, sess, pool);
1250 otx2_cpt_sym_session_clear(struct rte_cryptodev *dev,
1251 struct rte_cryptodev_sym_session *sess)
1253 CPT_PMD_INIT_FUNC_TRACE();
1255 return sym_session_clear(dev->driver_id, sess);
1259 otx2_cpt_asym_session_size_get(struct rte_cryptodev *dev __rte_unused)
1261 return sizeof(struct cpt_asym_sess_misc);
1265 otx2_cpt_asym_session_cfg(struct rte_cryptodev *dev,
1266 struct rte_crypto_asym_xform *xform,
1267 struct rte_cryptodev_asym_session *sess,
1268 struct rte_mempool *pool)
1270 struct cpt_asym_sess_misc *priv;
1271 vq_cmd_word3_t vq_cmd_w3;
1274 CPT_PMD_INIT_FUNC_TRACE();
1276 if (rte_mempool_get(pool, (void **)&priv)) {
1277 CPT_LOG_ERR("Could not allocate session_private_data");
1281 memset(priv, 0, sizeof(struct cpt_asym_sess_misc));
1283 ret = cpt_fill_asym_session_parameters(priv, xform);
1285 CPT_LOG_ERR("Could not configure session parameters");
1287 /* Return session to mempool */
1288 rte_mempool_put(pool, priv);
1293 vq_cmd_w3.s.grp = OTX2_CPT_EGRP_AE;
1294 priv->cpt_inst_w7 = vq_cmd_w3.u64;
1296 set_asym_session_private_data(sess, dev->driver_id, priv);
1302 otx2_cpt_asym_session_clear(struct rte_cryptodev *dev,
1303 struct rte_cryptodev_asym_session *sess)
1305 struct cpt_asym_sess_misc *priv;
1306 struct rte_mempool *sess_mp;
1308 CPT_PMD_INIT_FUNC_TRACE();
1310 priv = get_asym_session_private_data(sess, dev->driver_id);
1314 /* Free resources allocated in session_cfg */
1315 cpt_free_asym_session_parameters(priv);
1317 /* Reset and free object back to pool */
1318 memset(priv, 0, otx2_cpt_asym_session_size_get(dev));
1319 sess_mp = rte_mempool_from_obj(priv);
1320 set_asym_session_private_data(sess, dev->driver_id, NULL);
1321 rte_mempool_put(sess_mp, priv);
1324 struct rte_cryptodev_ops otx2_cpt_ops = {
1325 /* Device control ops */
1326 .dev_configure = otx2_cpt_dev_config,
1327 .dev_start = otx2_cpt_dev_start,
1328 .dev_stop = otx2_cpt_dev_stop,
1329 .dev_close = otx2_cpt_dev_close,
1330 .dev_infos_get = otx2_cpt_dev_info_get,
1333 .stats_reset = NULL,
1334 .queue_pair_setup = otx2_cpt_queue_pair_setup,
1335 .queue_pair_release = otx2_cpt_queue_pair_release,
1337 /* Symmetric crypto ops */
1338 .sym_session_get_size = otx2_cpt_sym_session_get_size,
1339 .sym_session_configure = otx2_cpt_sym_session_configure,
1340 .sym_session_clear = otx2_cpt_sym_session_clear,
1342 /* Asymmetric crypto ops */
1343 .asym_session_get_size = otx2_cpt_asym_session_size_get,
1344 .asym_session_configure = otx2_cpt_asym_session_cfg,
1345 .asym_session_clear = otx2_cpt_asym_session_clear,