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47 #ifndef _ICP_QAT_HW_H_
48 #define _ICP_QAT_HW_H_
50 enum icp_qat_hw_ae_id {
61 ICP_QAT_HW_AE_10 = 10,
62 ICP_QAT_HW_AE_11 = 11,
63 ICP_QAT_HW_AE_DELIMITER = 12
66 enum icp_qat_hw_qat_id {
73 ICP_QAT_HW_QAT_DELIMITER = 6
76 enum icp_qat_hw_auth_algo {
77 ICP_QAT_HW_AUTH_ALGO_NULL = 0,
78 ICP_QAT_HW_AUTH_ALGO_SHA1 = 1,
79 ICP_QAT_HW_AUTH_ALGO_MD5 = 2,
80 ICP_QAT_HW_AUTH_ALGO_SHA224 = 3,
81 ICP_QAT_HW_AUTH_ALGO_SHA256 = 4,
82 ICP_QAT_HW_AUTH_ALGO_SHA384 = 5,
83 ICP_QAT_HW_AUTH_ALGO_SHA512 = 6,
84 ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC = 7,
85 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC = 8,
86 ICP_QAT_HW_AUTH_ALGO_AES_F9 = 9,
87 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 = 10,
88 ICP_QAT_HW_AUTH_ALGO_GALOIS_64 = 11,
89 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 = 12,
90 ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 = 13,
91 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3 = 14,
92 ICP_QAT_HW_AUTH_RESERVED_1 = 15,
93 ICP_QAT_HW_AUTH_RESERVED_2 = 16,
94 ICP_QAT_HW_AUTH_ALGO_SHA3_256 = 17,
95 ICP_QAT_HW_AUTH_RESERVED_3 = 18,
96 ICP_QAT_HW_AUTH_ALGO_SHA3_512 = 19,
97 ICP_QAT_HW_AUTH_ALGO_DELIMITER = 20
100 enum icp_qat_hw_auth_mode {
101 ICP_QAT_HW_AUTH_MODE0 = 0,
102 ICP_QAT_HW_AUTH_MODE1 = 1,
103 ICP_QAT_HW_AUTH_MODE2 = 2,
104 ICP_QAT_HW_AUTH_MODE_DELIMITER = 3
107 struct icp_qat_hw_auth_config {
112 #define QAT_AUTH_MODE_BITPOS 4
113 #define QAT_AUTH_MODE_MASK 0xF
114 #define QAT_AUTH_ALGO_BITPOS 0
115 #define QAT_AUTH_ALGO_MASK 0xF
116 #define QAT_AUTH_CMP_BITPOS 8
117 #define QAT_AUTH_CMP_MASK 0x7F
118 #define QAT_AUTH_SHA3_PADDING_BITPOS 16
119 #define QAT_AUTH_SHA3_PADDING_MASK 0x1
120 #define QAT_AUTH_ALGO_SHA3_BITPOS 22
121 #define QAT_AUTH_ALGO_SHA3_MASK 0x3
122 #define ICP_QAT_HW_AUTH_CONFIG_BUILD(mode, algo, cmp_len) \
123 (((mode & QAT_AUTH_MODE_MASK) << QAT_AUTH_MODE_BITPOS) | \
124 ((algo & QAT_AUTH_ALGO_MASK) << QAT_AUTH_ALGO_BITPOS) | \
125 (((algo >> 4) & QAT_AUTH_ALGO_SHA3_MASK) << \
126 QAT_AUTH_ALGO_SHA3_BITPOS) | \
127 (((((algo == ICP_QAT_HW_AUTH_ALGO_SHA3_256) || \
128 (algo == ICP_QAT_HW_AUTH_ALGO_SHA3_512)) ? 1 : 0) \
129 & QAT_AUTH_SHA3_PADDING_MASK) << QAT_AUTH_SHA3_PADDING_BITPOS) | \
130 ((cmp_len & QAT_AUTH_CMP_MASK) << QAT_AUTH_CMP_BITPOS))
132 struct icp_qat_hw_auth_counter {
137 #define QAT_AUTH_COUNT_MASK 0xFFFFFFFF
138 #define QAT_AUTH_COUNT_BITPOS 0
139 #define ICP_QAT_HW_AUTH_COUNT_BUILD(val) \
140 (((val) & QAT_AUTH_COUNT_MASK) << QAT_AUTH_COUNT_BITPOS)
142 struct icp_qat_hw_auth_setup {
143 struct icp_qat_hw_auth_config auth_config;
144 struct icp_qat_hw_auth_counter auth_counter;
147 #define QAT_HW_DEFAULT_ALIGNMENT 8
148 #define QAT_HW_ROUND_UP(val, n) (((val) + ((n) - 1)) & (~(n - 1)))
149 #define ICP_QAT_HW_NULL_STATE1_SZ 32
150 #define ICP_QAT_HW_MD5_STATE1_SZ 16
151 #define ICP_QAT_HW_SHA1_STATE1_SZ 20
152 #define ICP_QAT_HW_SHA224_STATE1_SZ 32
153 #define ICP_QAT_HW_SHA256_STATE1_SZ 32
154 #define ICP_QAT_HW_SHA3_256_STATE1_SZ 32
155 #define ICP_QAT_HW_SHA384_STATE1_SZ 64
156 #define ICP_QAT_HW_SHA512_STATE1_SZ 64
157 #define ICP_QAT_HW_SHA3_512_STATE1_SZ 64
158 #define ICP_QAT_HW_SHA3_224_STATE1_SZ 28
159 #define ICP_QAT_HW_SHA3_384_STATE1_SZ 48
160 #define ICP_QAT_HW_AES_XCBC_MAC_STATE1_SZ 16
161 #define ICP_QAT_HW_AES_CBC_MAC_STATE1_SZ 16
162 #define ICP_QAT_HW_AES_F9_STATE1_SZ 32
163 #define ICP_QAT_HW_KASUMI_F9_STATE1_SZ 16
164 #define ICP_QAT_HW_GALOIS_128_STATE1_SZ 16
165 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE1_SZ 8
166 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE1_SZ 8
167 #define ICP_QAT_HW_NULL_STATE2_SZ 32
168 #define ICP_QAT_HW_MD5_STATE2_SZ 16
169 #define ICP_QAT_HW_SHA1_STATE2_SZ 20
170 #define ICP_QAT_HW_SHA224_STATE2_SZ 32
171 #define ICP_QAT_HW_SHA256_STATE2_SZ 32
172 #define ICP_QAT_HW_SHA3_256_STATE2_SZ 0
173 #define ICP_QAT_HW_SHA384_STATE2_SZ 64
174 #define ICP_QAT_HW_SHA512_STATE2_SZ 64
175 #define ICP_QAT_HW_SHA3_512_STATE2_SZ 0
176 #define ICP_QAT_HW_SHA3_224_STATE2_SZ 0
177 #define ICP_QAT_HW_SHA3_384_STATE2_SZ 0
178 #define ICP_QAT_HW_AES_XCBC_MAC_STATE2_SZ 48
179 #define ICP_QAT_HW_AES_XCBC_MAC_KEY_SZ 16
180 #define ICP_QAT_HW_AES_CBC_MAC_KEY_SZ 16
181 #define ICP_QAT_HW_AES_CCM_CBC_E_CTR0_SZ 16
182 #define ICP_QAT_HW_F9_IK_SZ 16
183 #define ICP_QAT_HW_F9_FK_SZ 16
184 #define ICP_QAT_HW_KASUMI_F9_STATE2_SZ (ICP_QAT_HW_F9_IK_SZ + \
186 #define ICP_QAT_HW_AES_F9_STATE2_SZ ICP_QAT_HW_KASUMI_F9_STATE2_SZ
187 #define ICP_QAT_HW_SNOW_3G_UIA2_STATE2_SZ 24
188 #define ICP_QAT_HW_ZUC_3G_EIA3_STATE2_SZ 32
189 #define ICP_QAT_HW_GALOIS_H_SZ 16
190 #define ICP_QAT_HW_GALOIS_LEN_A_SZ 8
191 #define ICP_QAT_HW_GALOIS_E_CTR0_SZ 16
193 struct icp_qat_hw_auth_sha512 {
194 struct icp_qat_hw_auth_setup inner_setup;
195 uint8_t state1[ICP_QAT_HW_SHA512_STATE1_SZ];
196 struct icp_qat_hw_auth_setup outer_setup;
197 uint8_t state2[ICP_QAT_HW_SHA512_STATE2_SZ];
200 struct icp_qat_hw_auth_algo_blk {
201 struct icp_qat_hw_auth_sha512 sha;
204 #define ICP_QAT_HW_GALOIS_LEN_A_BITPOS 0
205 #define ICP_QAT_HW_GALOIS_LEN_A_MASK 0xFFFFFFFF
207 enum icp_qat_hw_cipher_algo {
208 ICP_QAT_HW_CIPHER_ALGO_NULL = 0,
209 ICP_QAT_HW_CIPHER_ALGO_DES = 1,
210 ICP_QAT_HW_CIPHER_ALGO_3DES = 2,
211 ICP_QAT_HW_CIPHER_ALGO_AES128 = 3,
212 ICP_QAT_HW_CIPHER_ALGO_AES192 = 4,
213 ICP_QAT_HW_CIPHER_ALGO_AES256 = 5,
214 ICP_QAT_HW_CIPHER_ALGO_ARC4 = 6,
215 ICP_QAT_HW_CIPHER_ALGO_KASUMI = 7,
216 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 = 8,
217 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 = 9,
218 ICP_QAT_HW_CIPHER_DELIMITER = 10
221 enum icp_qat_hw_cipher_mode {
222 ICP_QAT_HW_CIPHER_ECB_MODE = 0,
223 ICP_QAT_HW_CIPHER_CBC_MODE = 1,
224 ICP_QAT_HW_CIPHER_CTR_MODE = 2,
225 ICP_QAT_HW_CIPHER_F8_MODE = 3,
226 ICP_QAT_HW_CIPHER_XTS_MODE = 6,
227 ICP_QAT_HW_CIPHER_MODE_DELIMITER = 7
230 struct icp_qat_hw_cipher_config {
235 enum icp_qat_hw_cipher_dir {
236 ICP_QAT_HW_CIPHER_ENCRYPT = 0,
237 ICP_QAT_HW_CIPHER_DECRYPT = 1,
240 enum icp_qat_hw_auth_op {
241 ICP_QAT_HW_AUTH_VERIFY = 0,
242 ICP_QAT_HW_AUTH_GENERATE = 1,
245 enum icp_qat_hw_cipher_convert {
246 ICP_QAT_HW_CIPHER_NO_CONVERT = 0,
247 ICP_QAT_HW_CIPHER_KEY_CONVERT = 1,
250 #define QAT_CIPHER_MODE_BITPOS 4
251 #define QAT_CIPHER_MODE_MASK 0xF
252 #define QAT_CIPHER_ALGO_BITPOS 0
253 #define QAT_CIPHER_ALGO_MASK 0xF
254 #define QAT_CIPHER_CONVERT_BITPOS 9
255 #define QAT_CIPHER_CONVERT_MASK 0x1
256 #define QAT_CIPHER_DIR_BITPOS 8
257 #define QAT_CIPHER_DIR_MASK 0x1
258 #define QAT_CIPHER_MODE_F8_KEY_SZ_MULT 2
259 #define QAT_CIPHER_MODE_XTS_KEY_SZ_MULT 2
260 #define ICP_QAT_HW_CIPHER_CONFIG_BUILD(mode, algo, convert, dir) \
261 (((mode & QAT_CIPHER_MODE_MASK) << QAT_CIPHER_MODE_BITPOS) | \
262 ((algo & QAT_CIPHER_ALGO_MASK) << QAT_CIPHER_ALGO_BITPOS) | \
263 ((convert & QAT_CIPHER_CONVERT_MASK) << QAT_CIPHER_CONVERT_BITPOS) | \
264 ((dir & QAT_CIPHER_DIR_MASK) << QAT_CIPHER_DIR_BITPOS))
265 #define ICP_QAT_HW_DES_BLK_SZ 8
266 #define ICP_QAT_HW_3DES_BLK_SZ 8
267 #define ICP_QAT_HW_NULL_BLK_SZ 8
268 #define ICP_QAT_HW_AES_BLK_SZ 16
269 #define ICP_QAT_HW_KASUMI_BLK_SZ 8
270 #define ICP_QAT_HW_SNOW_3G_BLK_SZ 8
271 #define ICP_QAT_HW_ZUC_3G_BLK_SZ 8
272 #define ICP_QAT_HW_NULL_KEY_SZ 256
273 #define ICP_QAT_HW_DES_KEY_SZ 8
274 #define ICP_QAT_HW_3DES_KEY_SZ 24
275 #define ICP_QAT_HW_AES_128_KEY_SZ 16
276 #define ICP_QAT_HW_AES_192_KEY_SZ 24
277 #define ICP_QAT_HW_AES_256_KEY_SZ 32
278 #define ICP_QAT_HW_AES_128_F8_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
279 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
280 #define ICP_QAT_HW_AES_192_F8_KEY_SZ (ICP_QAT_HW_AES_192_KEY_SZ * \
281 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
282 #define ICP_QAT_HW_AES_256_F8_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
283 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
284 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
285 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
286 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
287 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
288 #define ICP_QAT_HW_KASUMI_KEY_SZ 16
289 #define ICP_QAT_HW_KASUMI_F8_KEY_SZ (ICP_QAT_HW_KASUMI_KEY_SZ * \
290 QAT_CIPHER_MODE_F8_KEY_SZ_MULT)
291 #define ICP_QAT_HW_AES_128_XTS_KEY_SZ (ICP_QAT_HW_AES_128_KEY_SZ * \
292 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
293 #define ICP_QAT_HW_AES_256_XTS_KEY_SZ (ICP_QAT_HW_AES_256_KEY_SZ * \
294 QAT_CIPHER_MODE_XTS_KEY_SZ_MULT)
295 #define ICP_QAT_HW_ARC4_KEY_SZ 256
296 #define ICP_QAT_HW_SNOW_3G_UEA2_KEY_SZ 16
297 #define ICP_QAT_HW_SNOW_3G_UEA2_IV_SZ 16
298 #define ICP_QAT_HW_ZUC_3G_EEA3_KEY_SZ 16
299 #define ICP_QAT_HW_ZUC_3G_EEA3_IV_SZ 16
300 #define ICP_QAT_HW_MODE_F8_NUM_REG_TO_CLEAR 2
302 #define ICP_QAT_HW_CIPHER_MAX_KEY_SZ ICP_QAT_HW_AES_256_F8_KEY_SZ
304 /* These defines describe position of the bit-fields
305 * in the flags byte in B0
307 #define ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT 6
308 #define ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT 3
310 #define ICP_QAT_HW_CCM_BUILD_B0_FLAGS(Adata, t, q) \
311 ((((Adata) > 0 ? 1 : 0) << ICP_QAT_HW_CCM_B0_FLAGS_ADATA_SHIFT) \
312 | ((((t) - 2) >> 1) << ICP_QAT_HW_CCM_B0_FLAGS_T_SHIFT) \
315 #define ICP_QAT_HW_CCM_NQ_CONST 15
316 #define ICP_QAT_HW_CCM_AAD_B0_LEN 16
317 #define ICP_QAT_HW_CCM_AAD_LEN_INFO 2
318 #define ICP_QAT_HW_CCM_AAD_DATA_OFFSET (ICP_QAT_HW_CCM_AAD_B0_LEN + \
319 ICP_QAT_HW_CCM_AAD_LEN_INFO)
320 #define ICP_QAT_HW_CCM_AAD_ALIGNMENT 16
321 #define ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE 4
322 #define ICP_QAT_HW_CCM_NONCE_OFFSET 1
324 struct icp_qat_hw_cipher_algo_blk {
325 struct icp_qat_hw_cipher_config cipher_config;
326 uint8_t key[ICP_QAT_HW_CIPHER_MAX_KEY_SZ];
327 } __rte_cache_aligned;