4 * Copyright(c) 2015-2017 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
62 #include <rte_crypto_sym.h>
63 #include <rte_cryptodev_pci.h>
64 #include <openssl/evp.h>
68 #include "qat_crypto.h"
69 #include "adf_transport_access_macros.h"
74 qat_is_cipher_alg_supported(enum rte_crypto_cipher_algorithm algo,
75 struct qat_pmd_private *internals) {
77 const struct rte_cryptodev_capabilities *capability;
79 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
80 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
81 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
84 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_CIPHER)
87 if (capability->sym.cipher.algo == algo)
94 qat_is_auth_alg_supported(enum rte_crypto_auth_algorithm algo,
95 struct qat_pmd_private *internals) {
97 const struct rte_cryptodev_capabilities *capability;
99 while ((capability = &(internals->qat_dev_capabilities[i++]))->op !=
100 RTE_CRYPTO_OP_TYPE_UNDEFINED) {
101 if (capability->op != RTE_CRYPTO_OP_TYPE_SYMMETRIC)
104 if (capability->sym.xform_type != RTE_CRYPTO_SYM_XFORM_AUTH)
107 if (capability->sym.auth.algo == algo)
113 /** Encrypt a single partial block
114 * Depends on openssl libcrypto
115 * Uses ECB+XOR to do CFB encryption, same result, more performant
118 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
119 uint8_t *iv, int ivlen, int srclen,
122 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
124 uint8_t encrypted_iv[16];
127 /* ECB method: encrypt the IV, then XOR this with plaintext */
128 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
130 goto cipher_encrypt_err;
132 for (i = 0; i < srclen; i++)
133 *(dst+i) = *(src+i)^(encrypted_iv[i]);
138 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
142 /** Decrypt a single partial block
143 * Depends on openssl libcrypto
144 * Uses ECB+XOR to do CFB encryption, same result, more performant
147 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
148 uint8_t *iv, int ivlen, int srclen,
151 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
153 uint8_t encrypted_iv[16];
156 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
157 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
159 goto cipher_decrypt_err;
161 for (i = 0; i < srclen; i++)
162 *(dst+i) = *(src+i)^(encrypted_iv[i]);
167 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
171 /** Creates a context in either AES or DES in ECB mode
172 * Depends on openssl libcrypto
175 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
176 enum rte_crypto_cipher_operation direction __rte_unused,
179 const EVP_CIPHER *algo = NULL;
180 EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
185 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
186 algo = EVP_des_ecb();
188 algo = EVP_aes_128_ecb();
190 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
191 if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
198 EVP_CIPHER_CTX_free(ctx);
202 /** Frees a context previously created
203 * Depends on openssl libcrypto
206 bpi_cipher_ctx_free(void *bpi_ctx)
209 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
212 static inline uint32_t
213 adf_modulo(uint32_t data, uint32_t shift);
216 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
217 struct qat_crypto_op_cookie *qat_op_cookie);
219 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
222 struct qat_session *sess = session;
223 phys_addr_t cd_paddr;
225 PMD_INIT_FUNC_TRACE();
228 bpi_cipher_ctx_free(sess->bpi_ctx);
229 sess->bpi_ctx = NULL;
231 cd_paddr = sess->cd_paddr;
232 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
233 sess->cd_paddr = cd_paddr;
235 PMD_DRV_LOG(ERR, "NULL session");
239 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
242 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
243 return ICP_QAT_FW_LA_CMD_CIPHER;
245 /* Authentication Only */
246 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
247 return ICP_QAT_FW_LA_CMD_AUTH;
249 if (xform->next == NULL)
252 /* Cipher then Authenticate */
253 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
254 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
255 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
257 /* Authenticate then Cipher */
258 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
259 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
260 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
265 static struct rte_crypto_auth_xform *
266 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
269 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
278 static struct rte_crypto_cipher_xform *
279 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
282 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
283 return &xform->cipher;
291 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
292 struct rte_crypto_sym_xform *xform, void *session_private)
294 struct qat_session *session = session_private;
295 struct qat_pmd_private *internals = dev->data->dev_private;
296 struct rte_crypto_cipher_xform *cipher_xform = NULL;
298 /* Get cipher xform from crypto xform chain */
299 cipher_xform = qat_get_cipher_xform(xform);
301 switch (cipher_xform->algo) {
302 case RTE_CRYPTO_CIPHER_AES_CBC:
303 if (qat_alg_validate_aes_key(cipher_xform->key.length,
304 &session->qat_cipher_alg) != 0) {
305 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
308 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
310 case RTE_CRYPTO_CIPHER_AES_GCM:
311 if (qat_alg_validate_aes_key(cipher_xform->key.length,
312 &session->qat_cipher_alg) != 0) {
313 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
316 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
318 case RTE_CRYPTO_CIPHER_AES_CTR:
319 if (qat_alg_validate_aes_key(cipher_xform->key.length,
320 &session->qat_cipher_alg) != 0) {
321 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
324 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
326 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
327 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
328 &session->qat_cipher_alg) != 0) {
329 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
332 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
334 case RTE_CRYPTO_CIPHER_NULL:
335 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
337 case RTE_CRYPTO_CIPHER_KASUMI_F8:
338 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
339 &session->qat_cipher_alg) != 0) {
340 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
343 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
345 case RTE_CRYPTO_CIPHER_3DES_CBC:
346 if (qat_alg_validate_3des_key(cipher_xform->key.length,
347 &session->qat_cipher_alg) != 0) {
348 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
351 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
353 case RTE_CRYPTO_CIPHER_DES_CBC:
354 if (qat_alg_validate_des_key(cipher_xform->key.length,
355 &session->qat_cipher_alg) != 0) {
356 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
359 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
361 case RTE_CRYPTO_CIPHER_3DES_CTR:
362 if (qat_alg_validate_3des_key(cipher_xform->key.length,
363 &session->qat_cipher_alg) != 0) {
364 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
367 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
369 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
370 session->bpi_ctx = bpi_cipher_ctx_init(
373 cipher_xform->key.data);
374 if (session->bpi_ctx == NULL) {
375 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
378 if (qat_alg_validate_des_key(cipher_xform->key.length,
379 &session->qat_cipher_alg) != 0) {
380 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
383 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
385 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
386 session->bpi_ctx = bpi_cipher_ctx_init(
389 cipher_xform->key.data);
390 if (session->bpi_ctx == NULL) {
391 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
394 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
395 &session->qat_cipher_alg) != 0) {
396 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
399 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
401 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
402 if (!qat_is_cipher_alg_supported(
403 cipher_xform->algo, internals)) {
404 PMD_DRV_LOG(ERR, "%s not supported on this device",
405 rte_crypto_cipher_algorithm_strings
406 [cipher_xform->algo]);
409 if (qat_alg_validate_zuc_key(cipher_xform->key.length,
410 &session->qat_cipher_alg) != 0) {
411 PMD_DRV_LOG(ERR, "Invalid ZUC cipher key size");
414 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
416 case RTE_CRYPTO_CIPHER_3DES_ECB:
417 case RTE_CRYPTO_CIPHER_AES_ECB:
418 case RTE_CRYPTO_CIPHER_AES_CCM:
419 case RTE_CRYPTO_CIPHER_AES_F8:
420 case RTE_CRYPTO_CIPHER_AES_XTS:
421 case RTE_CRYPTO_CIPHER_ARC4:
422 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
426 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
431 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
432 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
434 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
436 if (qat_alg_aead_session_create_content_desc_cipher(session,
437 cipher_xform->key.data,
438 cipher_xform->key.length))
444 if (session->bpi_ctx) {
445 bpi_cipher_ctx_free(session->bpi_ctx);
446 session->bpi_ctx = NULL;
453 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
454 struct rte_crypto_sym_xform *xform, void *session_private)
456 struct qat_session *session = session_private;
459 PMD_INIT_FUNC_TRACE();
461 /* Get requested QAT command id */
462 qat_cmd_id = qat_get_cmd_id(xform);
463 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
464 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
467 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
468 switch (session->qat_cmd) {
469 case ICP_QAT_FW_LA_CMD_CIPHER:
470 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
472 case ICP_QAT_FW_LA_CMD_AUTH:
473 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
475 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
476 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
477 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
479 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
480 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
481 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
483 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
484 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
485 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
486 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
487 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
488 case ICP_QAT_FW_LA_CMD_MGF1:
489 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
490 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
491 case ICP_QAT_FW_LA_CMD_DELIMITER:
492 PMD_DRV_LOG(ERR, "Unsupported Service %u",
496 PMD_DRV_LOG(ERR, "Unsupported Service %u",
508 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
509 struct rte_crypto_sym_xform *xform,
510 struct qat_session *session_private)
513 struct qat_session *session = session_private;
514 struct rte_crypto_auth_xform *auth_xform = NULL;
515 struct rte_crypto_cipher_xform *cipher_xform = NULL;
516 struct qat_pmd_private *internals = dev->data->dev_private;
517 auth_xform = qat_get_auth_xform(xform);
519 switch (auth_xform->algo) {
520 case RTE_CRYPTO_AUTH_SHA1_HMAC:
521 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
523 case RTE_CRYPTO_AUTH_SHA224_HMAC:
524 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
526 case RTE_CRYPTO_AUTH_SHA256_HMAC:
527 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
529 case RTE_CRYPTO_AUTH_SHA384_HMAC:
530 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
532 case RTE_CRYPTO_AUTH_SHA512_HMAC:
533 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
535 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
536 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
538 case RTE_CRYPTO_AUTH_AES_GCM:
539 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
541 case RTE_CRYPTO_AUTH_AES_GMAC:
542 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
544 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
545 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
547 case RTE_CRYPTO_AUTH_MD5_HMAC:
548 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
550 case RTE_CRYPTO_AUTH_NULL:
551 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
553 case RTE_CRYPTO_AUTH_KASUMI_F9:
554 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
556 case RTE_CRYPTO_AUTH_ZUC_EIA3:
557 if (!qat_is_auth_alg_supported(auth_xform->algo, internals)) {
558 PMD_DRV_LOG(ERR, "%s not supported on this device",
559 rte_crypto_auth_algorithm_strings
563 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3;
565 case RTE_CRYPTO_AUTH_SHA1:
566 case RTE_CRYPTO_AUTH_SHA256:
567 case RTE_CRYPTO_AUTH_SHA512:
568 case RTE_CRYPTO_AUTH_SHA224:
569 case RTE_CRYPTO_AUTH_SHA384:
570 case RTE_CRYPTO_AUTH_MD5:
571 case RTE_CRYPTO_AUTH_AES_CCM:
572 case RTE_CRYPTO_AUTH_AES_CMAC:
573 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
574 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
578 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
582 cipher_xform = qat_get_cipher_xform(xform);
584 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
585 (session->qat_hash_alg ==
586 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
587 if (qat_alg_aead_session_create_content_desc_auth(session,
588 cipher_xform->key.data,
589 cipher_xform->key.length,
590 auth_xform->add_auth_data_length,
591 auth_xform->digest_length,
595 if (qat_alg_aead_session_create_content_desc_auth(session,
596 auth_xform->key.data,
597 auth_xform->key.length,
598 auth_xform->add_auth_data_length,
599 auth_xform->digest_length,
609 unsigned qat_crypto_sym_get_session_private_size(
610 struct rte_cryptodev *dev __rte_unused)
612 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
615 static inline uint32_t
616 qat_bpicipher_preprocess(struct qat_session *ctx,
617 struct rte_crypto_op *op)
619 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
620 struct rte_crypto_sym_op *sym_op = op->sym;
621 uint8_t last_block_len = sym_op->cipher.data.length % block_len;
623 if (last_block_len &&
624 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
626 /* Decrypt last block */
627 uint8_t *last_block, *dst, *iv;
628 uint32_t last_block_offset = sym_op->cipher.data.offset +
629 sym_op->cipher.data.length - last_block_len;
630 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
631 uint8_t *, last_block_offset);
633 if (unlikely(sym_op->m_dst != NULL))
634 /* out-of-place operation (OOP) */
635 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
636 uint8_t *, last_block_offset);
640 if (last_block_len < sym_op->cipher.data.length)
641 /* use previous block ciphertext as IV */
642 iv = last_block - block_len;
644 /* runt block, i.e. less than one full block */
645 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
646 sym_op->cipher.iv.offset);
648 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
649 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
651 if (sym_op->m_dst != NULL)
652 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
655 bpi_cipher_decrypt(last_block, dst, iv, block_len,
656 last_block_len, ctx->bpi_ctx);
657 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
658 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
660 if (sym_op->m_dst != NULL)
661 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
666 return sym_op->cipher.data.length - last_block_len;
669 static inline uint32_t
670 qat_bpicipher_postprocess(struct qat_session *ctx,
671 struct rte_crypto_op *op)
673 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
674 struct rte_crypto_sym_op *sym_op = op->sym;
675 uint8_t last_block_len = sym_op->cipher.data.length % block_len;
677 if (last_block_len > 0 &&
678 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
680 /* Encrypt last block */
681 uint8_t *last_block, *dst, *iv;
682 uint32_t last_block_offset;
684 last_block_offset = sym_op->cipher.data.offset +
685 sym_op->cipher.data.length - last_block_len;
686 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
687 uint8_t *, last_block_offset);
689 if (unlikely(sym_op->m_dst != NULL))
690 /* out-of-place operation (OOP) */
691 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
692 uint8_t *, last_block_offset);
696 if (last_block_len < sym_op->cipher.data.length)
697 /* use previous block ciphertext as IV */
698 iv = dst - block_len;
700 /* runt block, i.e. less than one full block */
701 iv = rte_crypto_op_ctod_offset(op, uint8_t *,
702 sym_op->cipher.iv.offset);
704 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
705 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
707 if (sym_op->m_dst != NULL)
708 rte_hexdump(stdout, "BPI: dst before post-process:",
709 dst, last_block_len);
711 bpi_cipher_encrypt(last_block, dst, iv, block_len,
712 last_block_len, ctx->bpi_ctx);
713 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
714 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
716 if (sym_op->m_dst != NULL)
717 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
721 return sym_op->cipher.data.length - last_block_len;
725 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
728 register struct qat_queue *queue;
729 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
730 register uint32_t nb_ops_sent = 0;
731 register struct rte_crypto_op **cur_op = ops;
733 uint16_t nb_ops_possible = nb_ops;
734 register uint8_t *base_addr;
735 register uint32_t tail;
738 if (unlikely(nb_ops == 0))
741 /* read params used a lot in main loop into registers */
742 queue = &(tmp_qp->tx_q);
743 base_addr = (uint8_t *)queue->base_addr;
746 /* Find how many can actually fit on the ring */
747 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
748 - queue->max_inflights;
750 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
751 nb_ops_possible = nb_ops - overflow;
752 if (nb_ops_possible == 0)
756 while (nb_ops_sent != nb_ops_possible) {
757 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
758 tmp_qp->op_cookies[tail / queue->msg_size]);
760 tmp_qp->stats.enqueue_err_count++;
762 * This message cannot be enqueued,
763 * decrease number of ops that wasn't sent
765 rte_atomic16_sub(&tmp_qp->inflights16,
766 nb_ops_possible - nb_ops_sent);
767 if (nb_ops_sent == 0)
772 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
777 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
778 queue->hw_queue_number, tail);
780 tmp_qp->stats.enqueued_count += nb_ops_sent;
785 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
788 struct qat_queue *queue;
789 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
790 uint32_t msg_counter = 0;
791 struct rte_crypto_op *rx_op;
792 struct icp_qat_fw_comn_resp *resp_msg;
794 queue = &(tmp_qp->rx_q);
795 resp_msg = (struct icp_qat_fw_comn_resp *)
796 ((uint8_t *)queue->base_addr + queue->head);
798 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
799 msg_counter != nb_ops) {
800 rx_op = (struct rte_crypto_op *)(uintptr_t)
801 (resp_msg->opaque_data);
803 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
804 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
805 sizeof(struct icp_qat_fw_comn_resp));
808 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
809 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
810 resp_msg->comn_hdr.comn_status)) {
811 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
813 struct qat_session *sess = (struct qat_session *)
814 (rx_op->sym->session->_private);
816 qat_bpicipher_postprocess(sess, rx_op);
817 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
820 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
821 queue->head = adf_modulo(queue->head +
823 ADF_RING_SIZE_MODULO(queue->queue_size));
824 resp_msg = (struct icp_qat_fw_comn_resp *)
825 ((uint8_t *)queue->base_addr +
831 if (msg_counter > 0) {
832 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
833 queue->hw_bundle_number,
834 queue->hw_queue_number, queue->head);
835 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
836 tmp_qp->stats.dequeued_count += msg_counter;
842 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
843 struct qat_alg_buf_list *list, uint32_t data_len)
847 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
848 buff_start + rte_pktmbuf_data_len(buf);
850 list->bufers[0].addr = buff_start;
851 list->bufers[0].resrvd = 0;
852 list->bufers[0].len = buf_len;
854 if (data_len <= buf_len) {
856 list->bufers[0].len = data_len;
862 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
863 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
869 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
870 list->bufers[nr].resrvd = 0;
871 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
873 buf_len += list->bufers[nr].len;
876 if (buf_len > data_len) {
877 list->bufers[nr].len -=
889 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
890 struct qat_crypto_op_cookie *qat_op_cookie)
893 struct qat_session *ctx;
894 struct icp_qat_fw_la_cipher_req_params *cipher_param;
895 struct icp_qat_fw_la_auth_req_params *auth_param;
896 register struct icp_qat_fw_la_bulk_req *qat_req;
897 uint8_t do_auth = 0, do_cipher = 0;
898 uint32_t cipher_len = 0, cipher_ofs = 0;
899 uint32_t auth_len = 0, auth_ofs = 0;
900 uint32_t min_ofs = 0;
901 uint64_t src_buf_start = 0, dst_buf_start = 0;
906 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
907 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
908 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
909 "operation requests, op (%p) is not a "
910 "symmetric operation.", op);
914 if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
915 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
916 " requests, op (%p) is sessionless.", op);
920 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
921 PMD_DRV_LOG(ERR, "Session was not created for this device");
925 ctx = (struct qat_session *)op->sym->session->_private;
926 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
927 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
928 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
929 cipher_param = (void *)&qat_req->serv_specif_rqpars;
930 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
932 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
933 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
936 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
939 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
946 if (ctx->qat_cipher_alg ==
947 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
948 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
949 ctx->qat_cipher_alg ==
950 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
953 (cipher_param->cipher_length % BYTE_LENGTH != 0)
954 || (cipher_param->cipher_offset
955 % BYTE_LENGTH != 0))) {
957 "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
958 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
961 cipher_len = op->sym->cipher.data.length >> 3;
962 cipher_ofs = op->sym->cipher.data.offset >> 3;
964 } else if (ctx->bpi_ctx) {
965 /* DOCSIS - only send complete blocks to device
966 * Process any partial block using CFB mode.
967 * Even if 0 complete blocks, still send this to device
968 * to get into rx queue for post-process and dequeuing
970 cipher_len = qat_bpicipher_preprocess(ctx, op);
971 cipher_ofs = op->sym->cipher.data.offset;
973 cipher_len = op->sym->cipher.data.length;
974 cipher_ofs = op->sym->cipher.data.offset;
977 iv_ptr = rte_crypto_op_ctod_offset(op, uint8_t *,
978 op->sym->cipher.iv.offset);
979 /* copy IV into request if it fits */
981 * If IV length is zero do not copy anything but still
982 * use request descriptor embedded IV
985 if (op->sym->cipher.iv.length) {
986 if (op->sym->cipher.iv.length <=
987 sizeof(cipher_param->u.cipher_IV_array)) {
988 rte_memcpy(cipher_param->u.cipher_IV_array,
990 op->sym->cipher.iv.length);
992 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
993 qat_req->comn_hdr.serv_specif_flags,
994 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
995 cipher_param->u.s.cipher_IV_ptr =
996 rte_crypto_op_ctophys_offset(op,
997 op->sym->cipher.iv.offset);
1000 min_ofs = cipher_ofs;
1005 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1006 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
1007 ctx->qat_hash_alg ==
1008 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
1009 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1010 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1012 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
1013 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1016 auth_ofs = op->sym->auth.data.offset >> 3;
1017 auth_len = op->sym->auth.data.length >> 3;
1019 if (ctx->qat_hash_alg ==
1020 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1022 auth_len = auth_len + auth_ofs + 1 -
1023 ICP_QAT_HW_KASUMI_BLK_SZ;
1024 auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1026 auth_len = auth_len + auth_ofs + 1;
1031 } else if (ctx->qat_hash_alg ==
1032 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1033 ctx->qat_hash_alg ==
1034 ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1035 auth_ofs = op->sym->cipher.data.offset;
1036 auth_len = op->sym->cipher.data.length;
1038 auth_ofs = op->sym->auth.data.offset;
1039 auth_len = op->sym->auth.data.length;
1043 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1045 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1049 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1052 /* adjust for chain case */
1053 if (do_cipher && do_auth)
1054 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1056 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1059 if (unlikely(op->sym->m_dst != NULL)) {
1060 /* Out-of-place operation (OOP)
1061 * Don't align DMA start. DMA the minimum data-set
1062 * so as not to overwrite data in dest buffer
1065 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1067 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1070 /* In-place operation
1071 * Start DMA at nearest aligned address below min_ofs
1074 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1075 & QAT_64_BTYE_ALIGN_MASK;
1077 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1078 rte_pktmbuf_headroom(op->sym->m_src))
1080 /* alignment has pushed addr ahead of start of mbuf
1081 * so revert and take the performance hit
1084 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1087 dst_buf_start = src_buf_start;
1091 cipher_param->cipher_offset =
1092 (uint32_t)rte_pktmbuf_mtophys_offset(
1093 op->sym->m_src, cipher_ofs) - src_buf_start;
1094 cipher_param->cipher_length = cipher_len;
1096 cipher_param->cipher_offset = 0;
1097 cipher_param->cipher_length = 0;
1100 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1101 op->sym->m_src, auth_ofs) - src_buf_start;
1102 auth_param->auth_len = auth_len;
1104 auth_param->auth_off = 0;
1105 auth_param->auth_len = 0;
1107 qat_req->comn_mid.dst_length =
1108 qat_req->comn_mid.src_length =
1109 (cipher_param->cipher_offset + cipher_param->cipher_length)
1110 > (auth_param->auth_off + auth_param->auth_len) ?
1111 (cipher_param->cipher_offset + cipher_param->cipher_length)
1112 : (auth_param->auth_off + auth_param->auth_len);
1116 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1117 QAT_COMN_PTR_TYPE_SGL);
1118 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1119 &qat_op_cookie->qat_sgl_list_src,
1120 qat_req->comn_mid.src_length);
1122 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1126 if (likely(op->sym->m_dst == NULL))
1127 qat_req->comn_mid.dest_data_addr =
1128 qat_req->comn_mid.src_data_addr =
1129 qat_op_cookie->qat_sgl_src_phys_addr;
1131 ret = qat_sgl_fill_array(op->sym->m_dst,
1133 &qat_op_cookie->qat_sgl_list_dst,
1134 qat_req->comn_mid.dst_length);
1137 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1142 qat_req->comn_mid.src_data_addr =
1143 qat_op_cookie->qat_sgl_src_phys_addr;
1144 qat_req->comn_mid.dest_data_addr =
1145 qat_op_cookie->qat_sgl_dst_phys_addr;
1148 qat_req->comn_mid.src_data_addr = src_buf_start;
1149 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1152 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1153 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1154 if (op->sym->cipher.iv.length == 12) {
1156 * For GCM a 12 byte IV is allowed,
1157 * but we need to inform the f/w
1159 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1160 qat_req->comn_hdr.serv_specif_flags,
1161 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1163 if (op->sym->cipher.data.length == 0) {
1167 qat_req->comn_mid.dest_data_addr =
1168 qat_req->comn_mid.src_data_addr =
1169 op->sym->auth.aad.phys_addr;
1170 qat_req->comn_mid.dst_length =
1171 qat_req->comn_mid.src_length =
1172 rte_pktmbuf_data_len(op->sym->m_src);
1173 cipher_param->cipher_length = 0;
1174 cipher_param->cipher_offset = 0;
1175 auth_param->u1.aad_adr = 0;
1176 auth_param->auth_len = op->sym->auth.aad.length;
1177 auth_param->auth_off = op->sym->auth.data.offset;
1178 auth_param->u2.aad_sz = 0;
1182 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1183 rte_hexdump(stdout, "qat_req:", qat_req,
1184 sizeof(struct icp_qat_fw_la_bulk_req));
1185 rte_hexdump(stdout, "src_data:",
1186 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1187 rte_pktmbuf_data_len(op->sym->m_src));
1189 rte_hexdump(stdout, "iv:", iv_ptr,
1190 op->sym->cipher.iv.length);
1193 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1194 op->sym->auth.digest.length);
1195 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1196 op->sym->auth.aad.length);
1202 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1204 uint32_t div = data >> shift;
1205 uint32_t mult = div << shift;
1210 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1212 struct rte_cryptodev_sym_session *sess = sym_sess;
1213 struct qat_session *s = (void *)sess->_private;
1215 PMD_INIT_FUNC_TRACE();
1216 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1217 offsetof(struct qat_session, cd) +
1218 offsetof(struct rte_cryptodev_sym_session, _private);
1221 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1222 __rte_unused struct rte_cryptodev_config *config)
1224 PMD_INIT_FUNC_TRACE();
1228 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1230 PMD_INIT_FUNC_TRACE();
1234 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1236 PMD_INIT_FUNC_TRACE();
1239 int qat_dev_close(struct rte_cryptodev *dev)
1243 PMD_INIT_FUNC_TRACE();
1245 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1246 ret = qat_crypto_sym_qp_release(dev, i);
1254 void qat_dev_info_get(struct rte_cryptodev *dev,
1255 struct rte_cryptodev_info *info)
1257 struct qat_pmd_private *internals = dev->data->dev_private;
1259 PMD_INIT_FUNC_TRACE();
1261 info->max_nb_queue_pairs =
1262 ADF_NUM_SYM_QPS_PER_BUNDLE *
1263 ADF_NUM_BUNDLES_PER_DEV;
1264 info->feature_flags = dev->feature_flags;
1265 info->capabilities = internals->qat_dev_capabilities;
1266 info->sym.max_nb_sessions = internals->max_nb_sessions;
1267 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1268 info->pci_dev = RTE_DEV_TO_PCI(dev->device);
1272 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1273 struct rte_cryptodev_stats *stats)
1276 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1278 PMD_INIT_FUNC_TRACE();
1279 if (stats == NULL) {
1280 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1283 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1284 if (qp[i] == NULL) {
1285 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1289 stats->enqueued_count += qp[i]->stats.enqueued_count;
1290 stats->dequeued_count += qp[i]->stats.dequeued_count;
1291 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1292 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
1296 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1299 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1301 PMD_INIT_FUNC_TRACE();
1302 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1303 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1304 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");