4 * Copyright(c) 2015-2016 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include <sys/queue.h>
43 #include <rte_common.h>
45 #include <rte_debug.h>
46 #include <rte_memory.h>
47 #include <rte_memzone.h>
48 #include <rte_tailq.h>
49 #include <rte_ether.h>
50 #include <rte_malloc.h>
51 #include <rte_launch.h>
53 #include <rte_per_lcore.h>
54 #include <rte_lcore.h>
55 #include <rte_atomic.h>
56 #include <rte_branch_prediction.h>
57 #include <rte_mempool.h>
59 #include <rte_string_fns.h>
60 #include <rte_spinlock.h>
61 #include <rte_hexdump.h>
62 #include <rte_crypto_sym.h>
63 #include <openssl/evp.h>
67 #include "qat_crypto.h"
68 #include "adf_transport_access_macros.h"
72 static const struct rte_cryptodev_capabilities qat_pmd_capabilities[] = {
74 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
76 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
78 .algo = RTE_CRYPTO_AUTH_SHA1_HMAC,
95 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
97 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
99 .algo = RTE_CRYPTO_AUTH_SHA224_HMAC,
116 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
118 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
120 .algo = RTE_CRYPTO_AUTH_SHA256_HMAC,
137 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
139 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
141 .algo = RTE_CRYPTO_AUTH_SHA384_HMAC,
158 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
160 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
162 .algo = RTE_CRYPTO_AUTH_SHA512_HMAC,
179 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
181 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
183 .algo = RTE_CRYPTO_AUTH_MD5_HMAC,
200 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
202 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
204 .algo = RTE_CRYPTO_AUTH_AES_XCBC_MAC,
220 { /* AES GCM (AUTH) */
221 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
223 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
225 .algo = RTE_CRYPTO_AUTH_AES_GCM,
245 { /* AES GMAC (AUTH) */
246 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
248 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
250 .algo = RTE_CRYPTO_AUTH_AES_GMAC,
270 { /* SNOW 3G (UIA2) */
271 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
273 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
275 .algo = RTE_CRYPTO_AUTH_SNOW3G_UIA2,
295 { /* AES GCM (CIPHER) */
296 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
298 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
300 .algo = RTE_CRYPTO_CIPHER_AES_GCM,
316 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
318 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
320 .algo = RTE_CRYPTO_CIPHER_AES_CBC,
335 { /* AES DOCSISBPI */
336 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
338 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
340 .algo = RTE_CRYPTO_CIPHER_AES_DOCSISBPI,
355 { /* SNOW 3G (UEA2) */
356 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
358 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
360 .algo = RTE_CRYPTO_CIPHER_SNOW3G_UEA2,
376 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
378 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
380 .algo = RTE_CRYPTO_CIPHER_AES_CTR,
396 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
398 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
400 .algo = RTE_CRYPTO_AUTH_NULL,
416 { /* NULL (CIPHER) */
417 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
419 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
421 .algo = RTE_CRYPTO_CIPHER_NULL,
437 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
439 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
441 .algo = RTE_CRYPTO_CIPHER_KASUMI_F8,
457 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
459 .xform_type = RTE_CRYPTO_SYM_XFORM_AUTH,
461 .algo = RTE_CRYPTO_AUTH_KASUMI_F9,
482 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
484 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
486 .algo = RTE_CRYPTO_CIPHER_3DES_CBC,
502 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
504 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
506 .algo = RTE_CRYPTO_CIPHER_3DES_CTR,
522 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
524 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
526 .algo = RTE_CRYPTO_CIPHER_DES_CBC,
541 { /* DES DOCSISBPI */
542 .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,
544 .xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,
546 .algo = RTE_CRYPTO_CIPHER_DES_DOCSISBPI,
561 RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()
564 /** Encrypt a single partial block
565 * Depends on openssl libcrypto
566 * Uses ECB+XOR to do CFB encryption, same result, more performant
569 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
570 uint8_t *iv, int ivlen, int srclen,
573 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
575 uint8_t encrypted_iv[16];
578 /* ECB method: encrypt the IV, then XOR this with plaintext */
579 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
581 goto cipher_encrypt_err;
583 for (i = 0; i < srclen; i++)
584 *(dst+i) = *(src+i)^(encrypted_iv[i]);
589 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
593 /** Decrypt a single partial block
594 * Depends on openssl libcrypto
595 * Uses ECB+XOR to do CFB encryption, same result, more performant
598 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
599 uint8_t *iv, int ivlen, int srclen,
602 EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
604 uint8_t encrypted_iv[16];
607 /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
608 if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
610 goto cipher_decrypt_err;
612 for (i = 0; i < srclen; i++)
613 *(dst+i) = *(src+i)^(encrypted_iv[i]);
618 PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt for BPI IV failed");
622 /** Creates a context in either AES or DES in ECB mode
623 * Depends on openssl libcrypto
626 bpi_cipher_ctx_init(enum rte_crypto_cipher_algorithm cryptodev_algo,
627 enum rte_crypto_cipher_operation direction __rte_unused,
630 const EVP_CIPHER *algo = NULL;
631 EVP_CIPHER_CTX *ctx = EVP_CIPHER_CTX_new();
636 if (cryptodev_algo == RTE_CRYPTO_CIPHER_DES_DOCSISBPI)
637 algo = EVP_des_ecb();
639 algo = EVP_aes_128_ecb();
641 /* IV will be ECB encrypted whether direction is encrypt or decrypt*/
642 if (EVP_EncryptInit_ex(ctx, algo, NULL, key, 0) != 1)
649 EVP_CIPHER_CTX_free(ctx);
653 /** Frees a context previously created
654 * Depends on openssl libcrypto
657 bpi_cipher_ctx_free(void *bpi_ctx)
660 EVP_CIPHER_CTX_free((EVP_CIPHER_CTX *)bpi_ctx);
663 static inline uint32_t
664 adf_modulo(uint32_t data, uint32_t shift);
667 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
668 struct qat_crypto_op_cookie *qat_op_cookie);
670 void qat_crypto_sym_clear_session(struct rte_cryptodev *dev,
673 struct qat_session *sess = session;
674 phys_addr_t cd_paddr;
676 PMD_INIT_FUNC_TRACE();
679 bpi_cipher_ctx_free(sess->bpi_ctx);
680 sess->bpi_ctx = NULL;
682 cd_paddr = sess->cd_paddr;
683 memset(sess, 0, qat_crypto_sym_get_session_private_size(dev));
684 sess->cd_paddr = cd_paddr;
686 PMD_DRV_LOG(ERR, "NULL session");
690 qat_get_cmd_id(const struct rte_crypto_sym_xform *xform)
693 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER && xform->next == NULL)
694 return ICP_QAT_FW_LA_CMD_CIPHER;
696 /* Authentication Only */
697 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH && xform->next == NULL)
698 return ICP_QAT_FW_LA_CMD_AUTH;
700 if (xform->next == NULL)
703 /* Cipher then Authenticate */
704 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER &&
705 xform->next->type == RTE_CRYPTO_SYM_XFORM_AUTH)
706 return ICP_QAT_FW_LA_CMD_CIPHER_HASH;
708 /* Authenticate then Cipher */
709 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH &&
710 xform->next->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
711 return ICP_QAT_FW_LA_CMD_HASH_CIPHER;
716 static struct rte_crypto_auth_xform *
717 qat_get_auth_xform(struct rte_crypto_sym_xform *xform)
720 if (xform->type == RTE_CRYPTO_SYM_XFORM_AUTH)
729 static struct rte_crypto_cipher_xform *
730 qat_get_cipher_xform(struct rte_crypto_sym_xform *xform)
733 if (xform->type == RTE_CRYPTO_SYM_XFORM_CIPHER)
734 return &xform->cipher;
742 qat_crypto_sym_configure_session_cipher(struct rte_cryptodev *dev,
743 struct rte_crypto_sym_xform *xform, void *session_private)
745 struct qat_pmd_private *internals = dev->data->dev_private;
747 struct qat_session *session = session_private;
749 struct rte_crypto_cipher_xform *cipher_xform = NULL;
751 /* Get cipher xform from crypto xform chain */
752 cipher_xform = qat_get_cipher_xform(xform);
754 switch (cipher_xform->algo) {
755 case RTE_CRYPTO_CIPHER_AES_CBC:
756 if (qat_alg_validate_aes_key(cipher_xform->key.length,
757 &session->qat_cipher_alg) != 0) {
758 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
761 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
763 case RTE_CRYPTO_CIPHER_AES_GCM:
764 if (qat_alg_validate_aes_key(cipher_xform->key.length,
765 &session->qat_cipher_alg) != 0) {
766 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
769 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
771 case RTE_CRYPTO_CIPHER_AES_CTR:
772 if (qat_alg_validate_aes_key(cipher_xform->key.length,
773 &session->qat_cipher_alg) != 0) {
774 PMD_DRV_LOG(ERR, "Invalid AES cipher key size");
777 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
779 case RTE_CRYPTO_CIPHER_SNOW3G_UEA2:
780 if (qat_alg_validate_snow3g_key(cipher_xform->key.length,
781 &session->qat_cipher_alg) != 0) {
782 PMD_DRV_LOG(ERR, "Invalid SNOW 3G cipher key size");
785 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
787 case RTE_CRYPTO_CIPHER_NULL:
788 session->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;
790 case RTE_CRYPTO_CIPHER_KASUMI_F8:
791 if (qat_alg_validate_kasumi_key(cipher_xform->key.length,
792 &session->qat_cipher_alg) != 0) {
793 PMD_DRV_LOG(ERR, "Invalid KASUMI cipher key size");
796 session->qat_mode = ICP_QAT_HW_CIPHER_F8_MODE;
798 case RTE_CRYPTO_CIPHER_3DES_CBC:
799 if (qat_alg_validate_3des_key(cipher_xform->key.length,
800 &session->qat_cipher_alg) != 0) {
801 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
804 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
806 case RTE_CRYPTO_CIPHER_DES_CBC:
807 if (qat_alg_validate_des_key(cipher_xform->key.length,
808 &session->qat_cipher_alg) != 0) {
809 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
812 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
814 case RTE_CRYPTO_CIPHER_3DES_CTR:
815 if (qat_alg_validate_3des_key(cipher_xform->key.length,
816 &session->qat_cipher_alg) != 0) {
817 PMD_DRV_LOG(ERR, "Invalid 3DES cipher key size");
820 session->qat_mode = ICP_QAT_HW_CIPHER_CTR_MODE;
822 case RTE_CRYPTO_CIPHER_DES_DOCSISBPI:
823 session->bpi_ctx = bpi_cipher_ctx_init(
826 cipher_xform->key.data);
827 if (session->bpi_ctx == NULL) {
828 PMD_DRV_LOG(ERR, "failed to create DES BPI ctx");
831 if (qat_alg_validate_des_key(cipher_xform->key.length,
832 &session->qat_cipher_alg) != 0) {
833 PMD_DRV_LOG(ERR, "Invalid DES cipher key size");
836 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
838 case RTE_CRYPTO_CIPHER_AES_DOCSISBPI:
839 session->bpi_ctx = bpi_cipher_ctx_init(
842 cipher_xform->key.data);
843 if (session->bpi_ctx == NULL) {
844 PMD_DRV_LOG(ERR, "failed to create AES BPI ctx");
847 if (qat_alg_validate_aes_docsisbpi_key(cipher_xform->key.length,
848 &session->qat_cipher_alg) != 0) {
849 PMD_DRV_LOG(ERR, "Invalid AES DOCSISBPI key size");
852 session->qat_mode = ICP_QAT_HW_CIPHER_CBC_MODE;
854 case RTE_CRYPTO_CIPHER_3DES_ECB:
855 case RTE_CRYPTO_CIPHER_AES_ECB:
856 case RTE_CRYPTO_CIPHER_AES_CCM:
857 case RTE_CRYPTO_CIPHER_AES_F8:
858 case RTE_CRYPTO_CIPHER_AES_XTS:
859 case RTE_CRYPTO_CIPHER_ARC4:
860 case RTE_CRYPTO_CIPHER_ZUC_EEA3:
861 PMD_DRV_LOG(ERR, "Crypto QAT PMD: Unsupported Cipher alg %u",
865 PMD_DRV_LOG(ERR, "Crypto: Undefined Cipher specified %u\n",
870 if (cipher_xform->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)
871 session->qat_dir = ICP_QAT_HW_CIPHER_ENCRYPT;
873 session->qat_dir = ICP_QAT_HW_CIPHER_DECRYPT;
875 if (qat_alg_aead_session_create_content_desc_cipher(session,
876 cipher_xform->key.data,
877 cipher_xform->key.length))
883 if (session->bpi_ctx) {
884 bpi_cipher_ctx_free(session->bpi_ctx);
885 session->bpi_ctx = NULL;
887 rte_mempool_put(internals->sess_mp, session);
893 qat_crypto_sym_configure_session(struct rte_cryptodev *dev,
894 struct rte_crypto_sym_xform *xform, void *session_private)
896 struct qat_pmd_private *internals = dev->data->dev_private;
898 struct qat_session *session = session_private;
901 PMD_INIT_FUNC_TRACE();
903 /* Get requested QAT command id */
904 qat_cmd_id = qat_get_cmd_id(xform);
905 if (qat_cmd_id < 0 || qat_cmd_id >= ICP_QAT_FW_LA_CMD_DELIMITER) {
906 PMD_DRV_LOG(ERR, "Unsupported xform chain requested");
909 session->qat_cmd = (enum icp_qat_fw_la_cmd_id)qat_cmd_id;
910 switch (session->qat_cmd) {
911 case ICP_QAT_FW_LA_CMD_CIPHER:
912 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
914 case ICP_QAT_FW_LA_CMD_AUTH:
915 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
917 case ICP_QAT_FW_LA_CMD_CIPHER_HASH:
918 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
919 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
921 case ICP_QAT_FW_LA_CMD_HASH_CIPHER:
922 session = qat_crypto_sym_configure_session_auth(dev, xform, session);
923 session = qat_crypto_sym_configure_session_cipher(dev, xform, session);
925 case ICP_QAT_FW_LA_CMD_TRNG_GET_RANDOM:
926 case ICP_QAT_FW_LA_CMD_TRNG_TEST:
927 case ICP_QAT_FW_LA_CMD_SSL3_KEY_DERIVE:
928 case ICP_QAT_FW_LA_CMD_TLS_V1_1_KEY_DERIVE:
929 case ICP_QAT_FW_LA_CMD_TLS_V1_2_KEY_DERIVE:
930 case ICP_QAT_FW_LA_CMD_MGF1:
931 case ICP_QAT_FW_LA_CMD_AUTH_PRE_COMP:
932 case ICP_QAT_FW_LA_CMD_CIPHER_PRE_COMP:
933 case ICP_QAT_FW_LA_CMD_DELIMITER:
934 PMD_DRV_LOG(ERR, "Unsupported Service %u",
938 PMD_DRV_LOG(ERR, "Unsupported Service %u",
946 rte_mempool_put(internals->sess_mp, session);
951 qat_crypto_sym_configure_session_auth(struct rte_cryptodev *dev,
952 struct rte_crypto_sym_xform *xform,
953 struct qat_session *session_private)
956 struct qat_pmd_private *internals = dev->data->dev_private;
957 struct qat_session *session = session_private;
958 struct rte_crypto_auth_xform *auth_xform = NULL;
959 struct rte_crypto_cipher_xform *cipher_xform = NULL;
960 auth_xform = qat_get_auth_xform(xform);
962 switch (auth_xform->algo) {
963 case RTE_CRYPTO_AUTH_SHA1_HMAC:
964 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA1;
966 case RTE_CRYPTO_AUTH_SHA224_HMAC:
967 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA224;
969 case RTE_CRYPTO_AUTH_SHA256_HMAC:
970 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA256;
972 case RTE_CRYPTO_AUTH_SHA384_HMAC:
973 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA384;
975 case RTE_CRYPTO_AUTH_SHA512_HMAC:
976 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SHA512;
978 case RTE_CRYPTO_AUTH_AES_XCBC_MAC:
979 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;
981 case RTE_CRYPTO_AUTH_AES_GCM:
982 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
984 case RTE_CRYPTO_AUTH_AES_GMAC:
985 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_GALOIS_128;
987 case RTE_CRYPTO_AUTH_SNOW3G_UIA2:
988 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;
990 case RTE_CRYPTO_AUTH_MD5_HMAC:
991 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_MD5;
993 case RTE_CRYPTO_AUTH_NULL:
994 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;
996 case RTE_CRYPTO_AUTH_KASUMI_F9:
997 session->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_KASUMI_F9;
999 case RTE_CRYPTO_AUTH_SHA1:
1000 case RTE_CRYPTO_AUTH_SHA256:
1001 case RTE_CRYPTO_AUTH_SHA512:
1002 case RTE_CRYPTO_AUTH_SHA224:
1003 case RTE_CRYPTO_AUTH_SHA384:
1004 case RTE_CRYPTO_AUTH_MD5:
1005 case RTE_CRYPTO_AUTH_AES_CCM:
1006 case RTE_CRYPTO_AUTH_AES_CMAC:
1007 case RTE_CRYPTO_AUTH_AES_CBC_MAC:
1008 case RTE_CRYPTO_AUTH_ZUC_EIA3:
1009 PMD_DRV_LOG(ERR, "Crypto: Unsupported hash alg %u",
1013 PMD_DRV_LOG(ERR, "Crypto: Undefined Hash algo %u specified",
1017 cipher_xform = qat_get_cipher_xform(xform);
1019 if ((session->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) ||
1020 (session->qat_hash_alg ==
1021 ICP_QAT_HW_AUTH_ALGO_GALOIS_64)) {
1022 if (qat_alg_aead_session_create_content_desc_auth(session,
1023 cipher_xform->key.data,
1024 cipher_xform->key.length,
1025 auth_xform->add_auth_data_length,
1026 auth_xform->digest_length,
1030 if (qat_alg_aead_session_create_content_desc_auth(session,
1031 auth_xform->key.data,
1032 auth_xform->key.length,
1033 auth_xform->add_auth_data_length,
1034 auth_xform->digest_length,
1041 if (internals->sess_mp != NULL)
1042 rte_mempool_put(internals->sess_mp, session);
1046 unsigned qat_crypto_sym_get_session_private_size(
1047 struct rte_cryptodev *dev __rte_unused)
1049 return RTE_ALIGN_CEIL(sizeof(struct qat_session), 8);
1052 static inline uint32_t
1053 qat_bpicipher_preprocess(struct qat_session *ctx,
1054 struct rte_crypto_op *op)
1056 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
1057 struct rte_crypto_sym_op *sym_op = op->sym;
1058 uint8_t last_block_len = sym_op->cipher.data.length % block_len;
1060 if (last_block_len &&
1061 ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
1063 /* Decrypt last block */
1064 uint8_t *last_block, *dst, *iv;
1065 uint32_t last_block_offset = sym_op->cipher.data.offset +
1066 sym_op->cipher.data.length - last_block_len;
1067 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
1068 uint8_t *, last_block_offset);
1070 if (unlikely(sym_op->m_dst != NULL))
1071 /* out-of-place operation (OOP) */
1072 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
1073 uint8_t *, last_block_offset);
1077 if (last_block_len < sym_op->cipher.data.length)
1078 /* use previous block ciphertext as IV */
1079 iv = last_block - block_len;
1081 /* runt block, i.e. less than one full block */
1082 iv = sym_op->cipher.iv.data;
1084 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1085 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
1087 if (sym_op->m_dst != NULL)
1088 rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
1091 bpi_cipher_decrypt(last_block, dst, iv, block_len,
1092 last_block_len, ctx->bpi_ctx);
1093 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1094 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
1096 if (sym_op->m_dst != NULL)
1097 rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
1102 return sym_op->cipher.data.length - last_block_len;
1105 static inline uint32_t
1106 qat_bpicipher_postprocess(struct qat_session *ctx,
1107 struct rte_crypto_op *op)
1109 uint8_t block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
1110 struct rte_crypto_sym_op *sym_op = op->sym;
1111 uint8_t last_block_len = sym_op->cipher.data.length % block_len;
1113 if (last_block_len > 0 &&
1114 ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
1116 /* Encrypt last block */
1117 uint8_t *last_block, *dst, *iv;
1118 uint32_t last_block_offset;
1120 last_block_offset = sym_op->cipher.data.offset +
1121 sym_op->cipher.data.length - last_block_len;
1122 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
1123 uint8_t *, last_block_offset);
1125 if (unlikely(sym_op->m_dst != NULL))
1126 /* out-of-place operation (OOP) */
1127 dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
1128 uint8_t *, last_block_offset);
1132 if (last_block_len < sym_op->cipher.data.length)
1133 /* use previous block ciphertext as IV */
1134 iv = dst - block_len;
1136 /* runt block, i.e. less than one full block */
1137 iv = sym_op->cipher.iv.data;
1139 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
1140 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
1142 if (sym_op->m_dst != NULL)
1143 rte_hexdump(stdout, "BPI: dst before post-process:",
1144 dst, last_block_len);
1146 bpi_cipher_encrypt(last_block, dst, iv, block_len,
1147 last_block_len, ctx->bpi_ctx);
1148 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
1149 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
1151 if (sym_op->m_dst != NULL)
1152 rte_hexdump(stdout, "BPI: dst after post-process:", dst,
1156 return sym_op->cipher.data.length - last_block_len;
1160 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
1163 register struct qat_queue *queue;
1164 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
1165 register uint32_t nb_ops_sent = 0;
1166 register struct rte_crypto_op **cur_op = ops;
1168 uint16_t nb_ops_possible = nb_ops;
1169 register uint8_t *base_addr;
1170 register uint32_t tail;
1173 if (unlikely(nb_ops == 0))
1176 /* read params used a lot in main loop into registers */
1177 queue = &(tmp_qp->tx_q);
1178 base_addr = (uint8_t *)queue->base_addr;
1181 /* Find how many can actually fit on the ring */
1182 overflow = rte_atomic16_add_return(&tmp_qp->inflights16, nb_ops)
1183 - queue->max_inflights;
1185 rte_atomic16_sub(&tmp_qp->inflights16, overflow);
1186 nb_ops_possible = nb_ops - overflow;
1187 if (nb_ops_possible == 0)
1191 while (nb_ops_sent != nb_ops_possible) {
1192 ret = qat_write_hw_desc_entry(*cur_op, base_addr + tail,
1193 tmp_qp->op_cookies[tail / queue->msg_size]);
1195 tmp_qp->stats.enqueue_err_count++;
1197 * This message cannot be enqueued,
1198 * decrease number of ops that wasnt sent
1200 rte_atomic16_sub(&tmp_qp->inflights16,
1201 nb_ops_possible - nb_ops_sent);
1202 if (nb_ops_sent == 0)
1207 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
1212 WRITE_CSR_RING_TAIL(tmp_qp->mmap_bar_addr, queue->hw_bundle_number,
1213 queue->hw_queue_number, tail);
1215 tmp_qp->stats.enqueued_count += nb_ops_sent;
1220 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
1223 struct qat_queue *queue;
1224 struct qat_qp *tmp_qp = (struct qat_qp *)qp;
1225 uint32_t msg_counter = 0;
1226 struct rte_crypto_op *rx_op;
1227 struct icp_qat_fw_comn_resp *resp_msg;
1229 queue = &(tmp_qp->rx_q);
1230 resp_msg = (struct icp_qat_fw_comn_resp *)
1231 ((uint8_t *)queue->base_addr + queue->head);
1233 while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
1234 msg_counter != nb_ops) {
1235 rx_op = (struct rte_crypto_op *)(uintptr_t)
1236 (resp_msg->opaque_data);
1238 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
1239 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
1240 sizeof(struct icp_qat_fw_comn_resp));
1242 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
1243 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
1244 resp_msg->comn_hdr.comn_status)) {
1245 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
1247 struct qat_session *sess = (struct qat_session *)
1248 (rx_op->sym->session->_private);
1250 qat_bpicipher_postprocess(sess, rx_op);
1251 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
1254 *(uint32_t *)resp_msg = ADF_RING_EMPTY_SIG;
1255 queue->head = adf_modulo(queue->head +
1257 ADF_RING_SIZE_MODULO(queue->queue_size));
1258 resp_msg = (struct icp_qat_fw_comn_resp *)
1259 ((uint8_t *)queue->base_addr +
1265 if (msg_counter > 0) {
1266 WRITE_CSR_RING_HEAD(tmp_qp->mmap_bar_addr,
1267 queue->hw_bundle_number,
1268 queue->hw_queue_number, queue->head);
1269 rte_atomic16_sub(&tmp_qp->inflights16, msg_counter);
1270 tmp_qp->stats.dequeued_count += msg_counter;
1276 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
1277 struct qat_alg_buf_list *list, uint32_t data_len)
1281 uint32_t buf_len = rte_pktmbuf_mtophys(buf) -
1282 buff_start + rte_pktmbuf_data_len(buf);
1284 list->bufers[0].addr = buff_start;
1285 list->bufers[0].resrvd = 0;
1286 list->bufers[0].len = buf_len;
1288 if (data_len <= buf_len) {
1289 list->num_bufs = nr;
1290 list->bufers[0].len = data_len;
1296 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
1297 PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
1299 QAT_SGL_MAX_NUMBER);
1303 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
1304 list->bufers[nr].resrvd = 0;
1305 list->bufers[nr].addr = rte_pktmbuf_mtophys(buf);
1307 buf_len += list->bufers[nr].len;
1310 if (buf_len > data_len) {
1311 list->bufers[nr].len -=
1317 list->num_bufs = nr;
1323 qat_write_hw_desc_entry(struct rte_crypto_op *op, uint8_t *out_msg,
1324 struct qat_crypto_op_cookie *qat_op_cookie)
1327 struct qat_session *ctx;
1328 struct icp_qat_fw_la_cipher_req_params *cipher_param;
1329 struct icp_qat_fw_la_auth_req_params *auth_param;
1330 register struct icp_qat_fw_la_bulk_req *qat_req;
1331 uint8_t do_auth = 0, do_cipher = 0;
1332 uint32_t cipher_len = 0, cipher_ofs = 0;
1333 uint32_t auth_len = 0, auth_ofs = 0;
1334 uint32_t min_ofs = 0;
1335 uint64_t src_buf_start = 0, dst_buf_start = 0;
1339 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1340 if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
1341 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
1342 "operation requests, op (%p) is not a "
1343 "symmetric operation.", op);
1347 if (unlikely(op->sym->sess_type == RTE_CRYPTO_SYM_OP_SESSIONLESS)) {
1348 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
1349 " requests, op (%p) is sessionless.", op);
1353 if (unlikely(op->sym->session->dev_type != RTE_CRYPTODEV_QAT_SYM_PMD)) {
1354 PMD_DRV_LOG(ERR, "Session was not created for this device");
1358 ctx = (struct qat_session *)op->sym->session->_private;
1359 qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
1360 rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
1361 qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
1362 cipher_param = (void *)&qat_req->serv_specif_rqpars;
1363 auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
1365 if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
1366 ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
1369 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
1372 } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
1379 if (ctx->qat_cipher_alg ==
1380 ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
1381 ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI) {
1384 (cipher_param->cipher_length % BYTE_LENGTH != 0)
1385 || (cipher_param->cipher_offset
1386 % BYTE_LENGTH != 0))) {
1388 "SNOW3G/KASUMI in QAT PMD only supports byte aligned values");
1389 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1392 cipher_len = op->sym->cipher.data.length >> 3;
1393 cipher_ofs = op->sym->cipher.data.offset >> 3;
1395 } else if (ctx->bpi_ctx) {
1396 /* DOCSIS - only send complete blocks to device
1397 * Process any partial block using CFB mode.
1398 * Even if 0 complete blocks, still send this to device
1399 * to get into rx queue for post-process and dequeuing
1401 cipher_len = qat_bpicipher_preprocess(ctx, op);
1402 cipher_ofs = op->sym->cipher.data.offset;
1404 cipher_len = op->sym->cipher.data.length;
1405 cipher_ofs = op->sym->cipher.data.offset;
1408 /* copy IV into request if it fits */
1409 if (op->sym->cipher.iv.length && (op->sym->cipher.iv.length <=
1410 sizeof(cipher_param->u.cipher_IV_array))) {
1411 rte_memcpy(cipher_param->u.cipher_IV_array,
1412 op->sym->cipher.iv.data,
1413 op->sym->cipher.iv.length);
1415 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
1416 qat_req->comn_hdr.serv_specif_flags,
1417 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
1418 cipher_param->u.s.cipher_IV_ptr =
1419 op->sym->cipher.iv.phys_addr;
1421 min_ofs = cipher_ofs;
1426 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
1427 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1428 if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
1429 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
1431 "For SNOW3G/KASUMI, QAT PMD only supports byte aligned values");
1432 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
1435 auth_ofs = op->sym->auth.data.offset >> 3;
1436 auth_len = op->sym->auth.data.length >> 3;
1438 if (ctx->qat_hash_alg ==
1439 ICP_QAT_HW_AUTH_ALGO_KASUMI_F9) {
1441 auth_len = auth_len + auth_ofs + 1 -
1442 ICP_QAT_HW_KASUMI_BLK_SZ;
1443 auth_ofs = ICP_QAT_HW_KASUMI_BLK_SZ;
1445 auth_len = auth_len + auth_ofs + 1;
1451 auth_ofs = op->sym->auth.data.offset;
1452 auth_len = op->sym->auth.data.length;
1456 auth_param->auth_res_addr = op->sym->auth.digest.phys_addr;
1458 auth_param->u1.aad_adr = op->sym->auth.aad.phys_addr;
1462 if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
1465 /* adjust for chain case */
1466 if (do_cipher && do_auth)
1467 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
1469 if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
1472 if (unlikely(op->sym->m_dst != NULL)) {
1473 /* Out-of-place operation (OOP)
1474 * Don't align DMA start. DMA the minimum data-set
1475 * so as not to overwrite data in dest buffer
1478 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs);
1480 rte_pktmbuf_mtophys_offset(op->sym->m_dst, min_ofs);
1483 /* In-place operation
1484 * Start DMA at nearest aligned address below min_ofs
1487 rte_pktmbuf_mtophys_offset(op->sym->m_src, min_ofs)
1488 & QAT_64_BTYE_ALIGN_MASK;
1490 if (unlikely((rte_pktmbuf_mtophys(op->sym->m_src) -
1491 rte_pktmbuf_headroom(op->sym->m_src))
1493 /* alignment has pushed addr ahead of start of mbuf
1494 * so revert and take the performance hit
1497 rte_pktmbuf_mtophys_offset(op->sym->m_src,
1500 dst_buf_start = src_buf_start;
1504 cipher_param->cipher_offset =
1505 (uint32_t)rte_pktmbuf_mtophys_offset(
1506 op->sym->m_src, cipher_ofs) - src_buf_start;
1507 cipher_param->cipher_length = cipher_len;
1509 cipher_param->cipher_offset = 0;
1510 cipher_param->cipher_length = 0;
1513 auth_param->auth_off = (uint32_t)rte_pktmbuf_mtophys_offset(
1514 op->sym->m_src, auth_ofs) - src_buf_start;
1515 auth_param->auth_len = auth_len;
1517 auth_param->auth_off = 0;
1518 auth_param->auth_len = 0;
1520 qat_req->comn_mid.dst_length =
1521 qat_req->comn_mid.src_length =
1522 (cipher_param->cipher_offset + cipher_param->cipher_length)
1523 > (auth_param->auth_off + auth_param->auth_len) ?
1524 (cipher_param->cipher_offset + cipher_param->cipher_length)
1525 : (auth_param->auth_off + auth_param->auth_len);
1529 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
1530 QAT_COMN_PTR_TYPE_SGL);
1531 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
1532 &qat_op_cookie->qat_sgl_list_src,
1533 qat_req->comn_mid.src_length);
1535 PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
1539 if (likely(op->sym->m_dst == NULL))
1540 qat_req->comn_mid.dest_data_addr =
1541 qat_req->comn_mid.src_data_addr =
1542 qat_op_cookie->qat_sgl_src_phys_addr;
1544 ret = qat_sgl_fill_array(op->sym->m_dst,
1546 &qat_op_cookie->qat_sgl_list_dst,
1547 qat_req->comn_mid.dst_length);
1550 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
1555 qat_req->comn_mid.src_data_addr =
1556 qat_op_cookie->qat_sgl_src_phys_addr;
1557 qat_req->comn_mid.dest_data_addr =
1558 qat_op_cookie->qat_sgl_dst_phys_addr;
1561 qat_req->comn_mid.src_data_addr = src_buf_start;
1562 qat_req->comn_mid.dest_data_addr = dst_buf_start;
1565 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
1566 ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
1567 if (op->sym->cipher.iv.length == 12) {
1569 * For GCM a 12 bit IV is allowed,
1570 * but we need to inform the f/w
1572 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
1573 qat_req->comn_hdr.serv_specif_flags,
1574 ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
1576 if (op->sym->cipher.data.length == 0) {
1580 qat_req->comn_mid.dest_data_addr =
1581 qat_req->comn_mid.src_data_addr =
1582 op->sym->auth.aad.phys_addr;
1583 qat_req->comn_mid.dst_length =
1584 qat_req->comn_mid.src_length =
1585 rte_pktmbuf_data_len(op->sym->m_src);
1586 cipher_param->cipher_length = 0;
1587 cipher_param->cipher_offset = 0;
1588 auth_param->u1.aad_adr = 0;
1589 auth_param->auth_len = op->sym->auth.aad.length;
1590 auth_param->auth_off = op->sym->auth.data.offset;
1591 auth_param->u2.aad_sz = 0;
1595 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
1596 rte_hexdump(stdout, "qat_req:", qat_req,
1597 sizeof(struct icp_qat_fw_la_bulk_req));
1598 rte_hexdump(stdout, "src_data:",
1599 rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
1600 rte_pktmbuf_data_len(op->sym->m_src));
1601 rte_hexdump(stdout, "iv:", op->sym->cipher.iv.data,
1602 op->sym->cipher.iv.length);
1603 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
1604 op->sym->auth.digest.length);
1605 rte_hexdump(stdout, "aad:", op->sym->auth.aad.data,
1606 op->sym->auth.aad.length);
1611 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
1613 uint32_t div = data >> shift;
1614 uint32_t mult = div << shift;
1619 void qat_crypto_sym_session_init(struct rte_mempool *mp, void *sym_sess)
1621 struct rte_cryptodev_sym_session *sess = sym_sess;
1622 struct qat_session *s = (void *)sess->_private;
1624 PMD_INIT_FUNC_TRACE();
1625 s->cd_paddr = rte_mempool_virt2phy(mp, sess) +
1626 offsetof(struct qat_session, cd) +
1627 offsetof(struct rte_cryptodev_sym_session, _private);
1630 int qat_dev_config(__rte_unused struct rte_cryptodev *dev,
1631 __rte_unused struct rte_cryptodev_config *config)
1633 PMD_INIT_FUNC_TRACE();
1637 int qat_dev_start(__rte_unused struct rte_cryptodev *dev)
1639 PMD_INIT_FUNC_TRACE();
1643 void qat_dev_stop(__rte_unused struct rte_cryptodev *dev)
1645 PMD_INIT_FUNC_TRACE();
1648 int qat_dev_close(struct rte_cryptodev *dev)
1652 PMD_INIT_FUNC_TRACE();
1654 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1655 ret = qat_crypto_sym_qp_release(dev, i);
1663 void qat_dev_info_get(__rte_unused struct rte_cryptodev *dev,
1664 struct rte_cryptodev_info *info)
1666 struct qat_pmd_private *internals = dev->data->dev_private;
1668 PMD_INIT_FUNC_TRACE();
1670 info->max_nb_queue_pairs =
1671 ADF_NUM_SYM_QPS_PER_BUNDLE *
1672 ADF_NUM_BUNDLES_PER_DEV;
1673 info->feature_flags = dev->feature_flags;
1674 info->capabilities = qat_pmd_capabilities;
1675 info->sym.max_nb_sessions = internals->max_nb_sessions;
1676 info->dev_type = RTE_CRYPTODEV_QAT_SYM_PMD;
1680 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
1681 struct rte_cryptodev_stats *stats)
1684 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1686 PMD_INIT_FUNC_TRACE();
1687 if (stats == NULL) {
1688 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
1691 for (i = 0; i < dev->data->nb_queue_pairs; i++) {
1692 if (qp[i] == NULL) {
1693 PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
1697 stats->enqueued_count += qp[i]->stats.enqueued_count;
1698 stats->dequeued_count += qp[i]->stats.enqueued_count;
1699 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
1700 stats->dequeue_err_count += qp[i]->stats.enqueue_err_count;
1704 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev)
1707 struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
1709 PMD_INIT_FUNC_TRACE();
1710 for (i = 0; i < dev->data->nb_queue_pairs; i++)
1711 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
1712 PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");