drivers/crypto/qat/qat_crypto.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4
   5 #ifndef _QAT_CRYPTO_H_
   6 #define _QAT_CRYPTO_H_
   7
   8 #include <rte_cryptodev_pmd.h>
   9 #include <rte_memzone.h>
  10
  11 #include "qat_common.h"
  12 #include "qat_device.h"
  13 #include "qat_crypto_capabilities.h"
  14
  15 /*
  16  * This macro rounds up a number to a be a multiple of
  17  * the alignment when the alignment is a power of 2
  18  */
  19 #define ALIGN_POW2_ROUNDUP(num, align) \
  20         (((num) + (align) - 1) & ~((align) - 1))
  21 #define QAT_64_BTYE_ALIGN_MASK (~0x3f)
  22
  23 #define QAT_CSR_HEAD_WRITE_THRESH 32U
  24 /* number of requests to accumulate before writing head CSR */
  25 #define QAT_CSR_TAIL_WRITE_THRESH 32U
  26 /* number of requests to accumulate before writing tail CSR */
  27 #define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
  28 /* number of inflights below which no tail write coalescing should occur */
  29
  30 struct qat_session;
  31
  32 /**
  33  * Structure associated with each queue.
  34  */
  35 struct qat_queue {
  36         char            memz_name[RTE_MEMZONE_NAMESIZE];
  37         void            *base_addr;             /* Base address */
  38         rte_iova_t      base_phys_addr;         /* Queue physical address */
  39         uint32_t        head;                   /* Shadow copy of the head */
  40         uint32_t        tail;                   /* Shadow copy of the tail */
  41         uint32_t        modulo;
  42         uint32_t        msg_size;
  43         uint16_t        max_inflights;
  44         uint32_t        queue_size;
  45         uint8_t         hw_bundle_number;
  46         uint8_t         hw_queue_number;
  47         /* HW queue aka ring offset on bundle */
  48         uint32_t        csr_head;               /* last written head value */
  49         uint32_t        csr_tail;               /* last written tail value */
  50         uint16_t        nb_processed_responses;
  51         /* number of responses processed since last CSR head write */
  52         uint16_t        nb_pending_requests;
  53         /* number of requests pending since last CSR tail write */
  54 };
  55
  56 struct qat_qp {
  57         void                    *mmap_bar_addr;
  58         uint16_t                inflights16;
  59         struct  qat_queue       tx_q;
  60         struct  qat_queue       rx_q;
  61         struct  rte_cryptodev_stats stats;
  62         struct rte_mempool *op_cookie_pool;
  63         void **op_cookies;
  64         uint32_t nb_descriptors;
  65         enum qat_device_gen qat_dev_gen;
  66 } __rte_cache_aligned;
  67
  68 void qat_crypto_sym_stats_get(struct rte_cryptodev *dev,
  69         struct rte_cryptodev_stats *stats);
  70 void qat_crypto_sym_stats_reset(struct rte_cryptodev *dev);
  71
  72 int qat_crypto_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,
  73         const struct rte_cryptodev_qp_conf *rx_conf, int socket_id,
  74         struct rte_mempool *session_pool);
  75 int qat_crypto_sym_qp_release(struct rte_cryptodev *dev,
  76         uint16_t queue_pair_id);
  77
  78
  79 extern uint16_t
  80 qat_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
  81                 uint16_t nb_ops);
  82
  83 extern uint16_t
  84 qat_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
  85                 uint16_t nb_ops);
  86
  87 #endif /* _QAT_CRYPTO_H_ */