drivers/crypto/qat/qat_sym.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4
   5 #include <rte_mempool.h>
   6 #include <rte_mbuf.h>
   7 #include <rte_hexdump.h>
   8 #include <rte_crypto_sym.h>
   9 #include <rte_bus_pci.h>
  10 #include <rte_byteorder.h>
  11
  12 #include <openssl/evp.h>
  13
  14 #include "qat_logs.h"
  15 #include "qat_sym_session.h"
  16 #include "qat_sym.h"
  17 #include "adf_transport_access_macros.h"
  18
  19 #define BYTE_LENGTH    8
  20 /* bpi is only used for partial blocks of DES and AES
  21  * so AES block len can be assumed as max len for iv, src and dst
  22  */
  23 #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ
  24
  25 /** Encrypt a single partial block
  26  *  Depends on openssl libcrypto
  27  *  Uses ECB+XOR to do CFB encryption, same result, more performant
  28  */
  29 static inline int
  30 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
  31                 uint8_t *iv, int ivlen, int srclen,
  32                 void *bpi_ctx)
  33 {
  34         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
  35         int encrypted_ivlen;
  36         uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
  37         uint8_t *encr = encrypted_iv;
  38
  39         /* ECB method: encrypt the IV, then XOR this with plaintext */
  40         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
  41                                                                 <= 0)
  42                 goto cipher_encrypt_err;
  43
  44         for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
  45                 *dst = *src ^ *encr;
  46
  47         return 0;
  48
  49 cipher_encrypt_err:
  50         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
  51         return -EINVAL;
  52 }
  53
  54 /** Decrypt a single partial block
  55  *  Depends on openssl libcrypto
  56  *  Uses ECB+XOR to do CFB encryption, same result, more performant
  57  */
  58 static inline int
  59 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
  60                 uint8_t *iv, int ivlen, int srclen,
  61                 void *bpi_ctx)
  62 {
  63         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
  64         int encrypted_ivlen;
  65         uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
  66         uint8_t *encr = encrypted_iv;
  67
  68         /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
  69         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
  70                                                                 <= 0)
  71                 goto cipher_decrypt_err;
  72
  73         for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
  74                 *dst = *src ^ *encr;
  75
  76         return 0;
  77
  78 cipher_decrypt_err:
  79         PMD_DRV_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
  80         return -EINVAL;
  81 }
  82
  83 /** Creates a context in either AES or DES in ECB mode
  84  *  Depends on openssl libcrypto
  85  */
  86 static inline uint32_t
  87 adf_modulo(uint32_t data, uint32_t shift);
  88
  89 static inline uint32_t
  90 qat_bpicipher_preprocess(struct qat_sym_session *ctx,
  91                                 struct rte_crypto_op *op)
  92 {
  93         int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
  94         struct rte_crypto_sym_op *sym_op = op->sym;
  95         uint8_t last_block_len = block_len > 0 ?
  96                         sym_op->cipher.data.length % block_len : 0;
  97
  98         if (last_block_len &&
  99                         ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
 100
 101                 /* Decrypt last block */
 102                 uint8_t *last_block, *dst, *iv;
 103                 uint32_t last_block_offset = sym_op->cipher.data.offset +
 104                                 sym_op->cipher.data.length - last_block_len;
 105                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 106                                 uint8_t *, last_block_offset);
 107
 108                 if (unlikely(sym_op->m_dst != NULL))
 109                         /* out-of-place operation (OOP) */
 110                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 111                                                 uint8_t *, last_block_offset);
 112                 else
 113                         dst = last_block;
 114
 115                 if (last_block_len < sym_op->cipher.data.length)
 116                         /* use previous block ciphertext as IV */
 117                         iv = last_block - block_len;
 118                 else
 119                         /* runt block, i.e. less than one full block */
 120                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 121                                         ctx->cipher_iv.offset);
 122
 123 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 124                 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
 125                         last_block_len);
 126                 if (sym_op->m_dst != NULL)
 127                         rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
 128                                 last_block_len);
 129 #endif
 130                 bpi_cipher_decrypt(last_block, dst, iv, block_len,
 131                                 last_block_len, ctx->bpi_ctx);
 132 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 133                 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
 134                         last_block_len);
 135                 if (sym_op->m_dst != NULL)
 136                         rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
 137                                 last_block_len);
 138 #endif
 139         }
 140
 141         return sym_op->cipher.data.length - last_block_len;
 142 }
 143
 144 static inline uint32_t
 145 qat_bpicipher_postprocess(struct qat_sym_session *ctx,
 146                                 struct rte_crypto_op *op)
 147 {
 148         int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 149         struct rte_crypto_sym_op *sym_op = op->sym;
 150         uint8_t last_block_len = block_len > 0 ?
 151                         sym_op->cipher.data.length % block_len : 0;
 152
 153         if (last_block_len > 0 &&
 154                         ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
 155
 156                 /* Encrypt last block */
 157                 uint8_t *last_block, *dst, *iv;
 158                 uint32_t last_block_offset;
 159
 160                 last_block_offset = sym_op->cipher.data.offset +
 161                                 sym_op->cipher.data.length - last_block_len;
 162                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 163                                 uint8_t *, last_block_offset);
 164
 165                 if (unlikely(sym_op->m_dst != NULL))
 166                         /* out-of-place operation (OOP) */
 167                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 168                                                 uint8_t *, last_block_offset);
 169                 else
 170                         dst = last_block;
 171
 172                 if (last_block_len < sym_op->cipher.data.length)
 173                         /* use previous block ciphertext as IV */
 174                         iv = dst - block_len;
 175                 else
 176                         /* runt block, i.e. less than one full block */
 177                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 178                                         ctx->cipher_iv.offset);
 179
 180 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 181                 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
 182                         last_block_len);
 183                 if (sym_op->m_dst != NULL)
 184                         rte_hexdump(stdout, "BPI: dst before post-process:",
 185                                         dst, last_block_len);
 186 #endif
 187                 bpi_cipher_encrypt(last_block, dst, iv, block_len,
 188                                 last_block_len, ctx->bpi_ctx);
 189 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 190                 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
 191                         last_block_len);
 192                 if (sym_op->m_dst != NULL)
 193                         rte_hexdump(stdout, "BPI: dst after post-process:", dst,
 194                                 last_block_len);
 195 #endif
 196         }
 197         return sym_op->cipher.data.length - last_block_len;
 198 }
 199
 200 static inline void
 201 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
 202         WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
 203                         q->hw_queue_number, q->tail);
 204         q->nb_pending_requests = 0;
 205         q->csr_tail = q->tail;
 206 }
 207
 208 static uint16_t
 209 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 210 {
 211         register struct qat_queue *queue;
 212         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 213         register uint32_t nb_ops_sent = 0;
 214         register int ret;
 215         uint16_t nb_ops_possible = nb_ops;
 216         register uint8_t *base_addr;
 217         register uint32_t tail;
 218         int overflow;
 219
 220         if (unlikely(nb_ops == 0))
 221                 return 0;
 222
 223         /* read params used a lot in main loop into registers */
 224         queue = &(tmp_qp->tx_q);
 225         base_addr = (uint8_t *)queue->base_addr;
 226         tail = queue->tail;
 227
 228         /* Find how many can actually fit on the ring */
 229         tmp_qp->inflights16 += nb_ops;
 230         overflow = tmp_qp->inflights16 - queue->max_inflights;
 231         if (overflow > 0) {
 232                 tmp_qp->inflights16 -= overflow;
 233                 nb_ops_possible = nb_ops - overflow;
 234                 if (nb_ops_possible == 0)
 235                         return 0;
 236         }
 237
 238         while (nb_ops_sent != nb_ops_possible) {
 239                 ret = tmp_qp->build_request(*ops, base_addr + tail,
 240                                 tmp_qp->op_cookies[tail / queue->msg_size],
 241                                 tmp_qp->qat_dev_gen);
 242                 if (ret != 0) {
 243                         tmp_qp->stats.enqueue_err_count++;
 244                         /*
 245                          * This message cannot be enqueued,
 246                          * decrease number of ops that wasn't sent
 247                          */
 248                         tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
 249                         if (nb_ops_sent == 0)
 250                                 return 0;
 251                         goto kick_tail;
 252                 }
 253
 254                 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
 255                 ops++;
 256                 nb_ops_sent++;
 257         }
 258 kick_tail:
 259         queue->tail = tail;
 260         tmp_qp->stats.enqueued_count += nb_ops_sent;
 261         queue->nb_pending_requests += nb_ops_sent;
 262         if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
 263                         queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
 264                 txq_write_tail(tmp_qp, queue);
 265         }
 266         return nb_ops_sent;
 267 }
 268
 269 static inline
 270 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
 271 {
 272         uint32_t old_head, new_head;
 273         uint32_t max_head;
 274
 275         old_head = q->csr_head;
 276         new_head = q->head;
 277         max_head = qp->nb_descriptors * q->msg_size;
 278
 279         /* write out free descriptors */
 280         void *cur_desc = (uint8_t *)q->base_addr + old_head;
 281
 282         if (new_head < old_head) {
 283                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
 284                 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
 285         } else {
 286                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
 287         }
 288         q->nb_processed_responses = 0;
 289         q->csr_head = new_head;
 290
 291         /* write current head to CSR */
 292         WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
 293                             q->hw_queue_number, new_head);
 294 }
 295
 296 uint16_t
 297 qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 298                 uint16_t nb_ops)
 299 {
 300         return qat_enqueue_op_burst(qp, (void **)ops, nb_ops);
 301 }
 302
 303 int
 304 qat_sym_process_response(void **op, uint8_t *resp,
 305                 __rte_unused void *op_cookie,
 306                 __rte_unused enum qat_device_gen qat_dev_gen)
 307 {
 308
 309         struct icp_qat_fw_comn_resp *resp_msg =
 310                         (struct icp_qat_fw_comn_resp *)resp;
 311         struct rte_crypto_op *rx_op = (struct rte_crypto_op *)(uintptr_t)
 312                         (resp_msg->opaque_data);
 313
 314 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 315         rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
 316                         sizeof(struct icp_qat_fw_comn_resp));
 317 #endif
 318
 319         if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
 320                         ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 321                         resp_msg->comn_hdr.comn_status)) {
 322
 323                 rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 324         } else {
 325                 struct qat_sym_session *sess = (struct qat_sym_session *)
 326                                                 get_session_private_data(
 327                                                 rx_op->sym->session,
 328                                                 cryptodev_qat_driver_id);
 329
 330                 if (sess->bpi_ctx)
 331                         qat_bpicipher_postprocess(sess, rx_op);
 332                 rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 333         }
 334         *op = (void *)rx_op;
 335
 336         return 0;
 337 }
 338
 339 static uint16_t
 340 qat_dequeue_op_burst(void *qp, void **ops, uint16_t nb_ops)
 341 {
 342         struct qat_queue *rx_queue, *tx_queue;
 343         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 344         uint32_t head;
 345         uint32_t resp_counter = 0;
 346         uint8_t *resp_msg;
 347
 348         rx_queue = &(tmp_qp->rx_q);
 349         tx_queue = &(tmp_qp->tx_q);
 350         head = rx_queue->head;
 351         resp_msg = (uint8_t *)rx_queue->base_addr + rx_queue->head;
 352
 353         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 354                         resp_counter != nb_ops) {
 355
 356                 tmp_qp->process_response(ops, resp_msg,
 357                         tmp_qp->op_cookies[head / rx_queue->msg_size],
 358                         tmp_qp->qat_dev_gen);
 359
 360                 head = adf_modulo(head + rx_queue->msg_size, rx_queue->modulo);
 361
 362                 resp_msg = (uint8_t *)rx_queue->base_addr + head;
 363                 ops++;
 364                 resp_counter++;
 365         }
 366         if (resp_counter > 0) {
 367                 rx_queue->head = head;
 368                 tmp_qp->stats.dequeued_count += resp_counter;
 369                 rx_queue->nb_processed_responses += resp_counter;
 370                 tmp_qp->inflights16 -= resp_counter;
 371
 372                 if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
 373                         rxq_free_desc(tmp_qp, rx_queue);
 374         }
 375         /* also check if tail needs to be advanced */
 376         if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
 377                 tx_queue->tail != tx_queue->csr_tail) {
 378                 txq_write_tail(tmp_qp, tx_queue);
 379         }
 380         return resp_counter;
 381 }
 382
 383 uint16_t
 384 qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 385                 uint16_t nb_ops)
 386 {
 387         return qat_dequeue_op_burst(qp, (void **)ops, nb_ops);
 388 }
 389
 390 static inline int
 391 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
 392                 struct qat_alg_buf_list *list, uint32_t data_len)
 393 {
 394         int nr = 1;
 395
 396         uint32_t buf_len = rte_pktmbuf_iova(buf) -
 397                         buff_start + rte_pktmbuf_data_len(buf);
 398
 399         list->bufers[0].addr = buff_start;
 400         list->bufers[0].resrvd = 0;
 401         list->bufers[0].len = buf_len;
 402
 403         if (data_len <= buf_len) {
 404                 list->num_bufs = nr;
 405                 list->bufers[0].len = data_len;
 406                 return 0;
 407         }
 408
 409         buf = buf->next;
 410         while (buf) {
 411                 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
 412                         PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
 413                                         " entry(%u)",
 414                                         QAT_SGL_MAX_NUMBER);
 415                         return -EINVAL;
 416                 }
 417
 418                 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
 419                 list->bufers[nr].resrvd = 0;
 420                 list->bufers[nr].addr = rte_pktmbuf_iova(buf);
 421
 422                 buf_len += list->bufers[nr].len;
 423                 buf = buf->next;
 424
 425                 if (buf_len > data_len) {
 426                         list->bufers[nr].len -=
 427                                 buf_len - data_len;
 428                         buf = NULL;
 429                 }
 430                 ++nr;
 431         }
 432         list->num_bufs = nr;
 433
 434         return 0;
 435 }
 436
 437 static inline void
 438 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
 439                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
 440                 struct rte_crypto_op *op,
 441                 struct icp_qat_fw_la_bulk_req *qat_req)
 442 {
 443         /* copy IV into request if it fits */
 444         if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
 445                 rte_memcpy(cipher_param->u.cipher_IV_array,
 446                                 rte_crypto_op_ctod_offset(op, uint8_t *,
 447                                         iv_offset),
 448                                 iv_length);
 449         } else {
 450                 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
 451                                 qat_req->comn_hdr.serv_specif_flags,
 452                                 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
 453                 cipher_param->u.s.cipher_IV_ptr =
 454                                 rte_crypto_op_ctophys_offset(op,
 455                                         iv_offset);
 456         }
 457 }
 458
 459 /** Set IV for CCM is special case, 0th byte is set to q-1
 460  *  where q is padding of nonce in 16 byte block
 461  */
 462 static inline void
 463 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
 464                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
 465                 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
 466 {
 467         rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
 468                         ICP_QAT_HW_CCM_NONCE_OFFSET,
 469                         rte_crypto_op_ctod_offset(op, uint8_t *,
 470                                 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
 471                         iv_length);
 472         *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
 473                         q - ICP_QAT_HW_CCM_NONCE_OFFSET;
 474
 475         if (aad_len_field_sz)
 476                 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
 477                         rte_crypto_op_ctod_offset(op, uint8_t *,
 478                                 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
 479                         iv_length);
 480 }
 481
 482
 483 int
 484 qat_sym_build_request(void *in_op, uint8_t *out_msg,
 485                 void *op_cookie, enum qat_device_gen qat_dev_gen)
 486 {
 487         int ret = 0;
 488         struct qat_sym_session *ctx;
 489         struct icp_qat_fw_la_cipher_req_params *cipher_param;
 490         struct icp_qat_fw_la_auth_req_params *auth_param;
 491         register struct icp_qat_fw_la_bulk_req *qat_req;
 492         uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
 493         uint32_t cipher_len = 0, cipher_ofs = 0;
 494         uint32_t auth_len = 0, auth_ofs = 0;
 495         uint32_t min_ofs = 0;
 496         uint64_t src_buf_start = 0, dst_buf_start = 0;
 497         uint8_t do_sgl = 0;
 498         struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
 499         struct qat_sym_op_cookie *cookie =
 500                                 (struct qat_sym_op_cookie *)op_cookie;
 501
 502 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 503         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
 504                 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
 505                                 "operation requests, op (%p) is not a "
 506                                 "symmetric operation.", op);
 507                 return -EINVAL;
 508         }
 509 #endif
 510         if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 511                 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
 512                                 " requests, op (%p) is sessionless.", op);
 513                 return -EINVAL;
 514         }
 515
 516         ctx = (struct qat_sym_session *)get_session_private_data(
 517                         op->sym->session, cryptodev_qat_driver_id);
 518
 519         if (unlikely(ctx == NULL)) {
 520                 PMD_DRV_LOG(ERR, "Session was not created for this device");
 521                 return -EINVAL;
 522         }
 523
 524         if (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {
 525                 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
 526                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
 527                 return -EINVAL;
 528         }
 529
 530         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
 531         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
 532         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
 533         cipher_param = (void *)&qat_req->serv_specif_rqpars;
 534         auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
 535
 536         if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
 537                         ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
 538                 /* AES-GCM or AES-CCM */
 539                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 540                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
 541                         (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
 542                         && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
 543                         && ctx->qat_hash_alg ==
 544                                         ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
 545                         do_aead = 1;
 546                 } else {
 547                         do_auth = 1;
 548                         do_cipher = 1;
 549                 }
 550         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
 551                 do_auth = 1;
 552                 do_cipher = 0;
 553         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
 554                 do_auth = 0;
 555                 do_cipher = 1;
 556         }
 557
 558         if (do_cipher) {
 559
 560                 if (ctx->qat_cipher_alg ==
 561                                          ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 562                         ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
 563                         ctx->qat_cipher_alg ==
 564                                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
 565
 566                         if (unlikely(
 567                                 (cipher_param->cipher_length % BYTE_LENGTH != 0)
 568                                  || (cipher_param->cipher_offset
 569                                                         % BYTE_LENGTH != 0))) {
 570                                 PMD_DRV_LOG(ERR,
 571                   "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
 572                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 573                                 return -EINVAL;
 574                         }
 575                         cipher_len = op->sym->cipher.data.length >> 3;
 576                         cipher_ofs = op->sym->cipher.data.offset >> 3;
 577
 578                 } else if (ctx->bpi_ctx) {
 579                         /* DOCSIS - only send complete blocks to device
 580                          * Process any partial block using CFB mode.
 581                          * Even if 0 complete blocks, still send this to device
 582                          * to get into rx queue for post-process and dequeuing
 583                          */
 584                         cipher_len = qat_bpicipher_preprocess(ctx, op);
 585                         cipher_ofs = op->sym->cipher.data.offset;
 586                 } else {
 587                         cipher_len = op->sym->cipher.data.length;
 588                         cipher_ofs = op->sym->cipher.data.offset;
 589                 }
 590
 591                 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
 592                                 cipher_param, op, qat_req);
 593                 min_ofs = cipher_ofs;
 594         }
 595
 596         if (do_auth) {
 597
 598                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
 599                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
 600                         ctx->qat_hash_alg ==
 601                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
 602                         if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
 603                                 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
 604                                 PMD_DRV_LOG(ERR,
 605                 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
 606                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 607                                 return -EINVAL;
 608                         }
 609                         auth_ofs = op->sym->auth.data.offset >> 3;
 610                         auth_len = op->sym->auth.data.length >> 3;
 611
 612                         auth_param->u1.aad_adr =
 613                                         rte_crypto_op_ctophys_offset(op,
 614                                                         ctx->auth_iv.offset);
 615
 616                 } else if (ctx->qat_hash_alg ==
 617                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 618                                 ctx->qat_hash_alg ==
 619                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
 620                         /* AES-GMAC */
 621                         set_cipher_iv(ctx->auth_iv.length,
 622                                 ctx->auth_iv.offset,
 623                                 cipher_param, op, qat_req);
 624                         auth_ofs = op->sym->auth.data.offset;
 625                         auth_len = op->sym->auth.data.length;
 626
 627                         auth_param->u1.aad_adr = 0;
 628                         auth_param->u2.aad_sz = 0;
 629
 630                         /*
 631                          * If len(iv)==12B fw computes J0
 632                          */
 633                         if (ctx->auth_iv.length == 12) {
 634                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
 635                                         qat_req->comn_hdr.serv_specif_flags,
 636                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 637
 638                         }
 639                 } else {
 640                         auth_ofs = op->sym->auth.data.offset;
 641                         auth_len = op->sym->auth.data.length;
 642
 643                 }
 644                 min_ofs = auth_ofs;
 645
 646                 if (likely(ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL))
 647                         auth_param->auth_res_addr =
 648                                         op->sym->auth.digest.phys_addr;
 649
 650         }
 651
 652         if (do_aead) {
 653                 /*
 654                  * This address may used for setting AAD physical pointer
 655                  * into IV offset from op
 656                  */
 657                 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
 658                 if (ctx->qat_hash_alg ==
 659                                 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 660                                 ctx->qat_hash_alg ==
 661                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
 662                         /*
 663                          * If len(iv)==12B fw computes J0
 664                          */
 665                         if (ctx->cipher_iv.length == 12) {
 666                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
 667                                         qat_req->comn_hdr.serv_specif_flags,
 668                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 669                         }
 670                         set_cipher_iv(ctx->cipher_iv.length,
 671                                         ctx->cipher_iv.offset,
 672                                         cipher_param, op, qat_req);
 673
 674                 } else if (ctx->qat_hash_alg ==
 675                                 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
 676
 677                         /* In case of AES-CCM this may point to user selected
 678                          * memory or iv offset in cypto_op
 679                          */
 680                         uint8_t *aad_data = op->sym->aead.aad.data;
 681                         /* This is true AAD length, it not includes 18 bytes of
 682                          * preceding data
 683                          */
 684                         uint8_t aad_ccm_real_len = 0;
 685                         uint8_t aad_len_field_sz = 0;
 686                         uint32_t msg_len_be =
 687                                         rte_bswap32(op->sym->aead.data.length);
 688
 689                         if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
 690                                 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
 691                                 aad_ccm_real_len = ctx->aad_len -
 692                                         ICP_QAT_HW_CCM_AAD_B0_LEN -
 693                                         ICP_QAT_HW_CCM_AAD_LEN_INFO;
 694                         } else {
 695                                 /*
 696                                  * aad_len not greater than 18, so no actual aad
 697                                  *  data, then use IV after op for B0 block
 698                                  */
 699                                 aad_data = rte_crypto_op_ctod_offset(op,
 700                                                 uint8_t *,
 701                                                 ctx->cipher_iv.offset);
 702                                 aad_phys_addr_aead =
 703                                                 rte_crypto_op_ctophys_offset(op,
 704                                                         ctx->cipher_iv.offset);
 705                         }
 706
 707                         uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
 708                                                         ctx->cipher_iv.length;
 709
 710                         aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
 711                                                         aad_len_field_sz,
 712                                                         ctx->digest_length, q);
 713
 714                         if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
 715                                 memcpy(aad_data + ctx->cipher_iv.length +
 716                                     ICP_QAT_HW_CCM_NONCE_OFFSET +
 717                                     (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
 718                                     (uint8_t *)&msg_len_be,
 719                                     ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
 720                         } else {
 721                                 memcpy(aad_data + ctx->cipher_iv.length +
 722                                     ICP_QAT_HW_CCM_NONCE_OFFSET,
 723                                     (uint8_t *)&msg_len_be
 724                                     + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
 725                                     - q), q);
 726                         }
 727
 728                         if (aad_len_field_sz > 0) {
 729                                 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
 730                                                 = rte_bswap16(aad_ccm_real_len);
 731
 732                                 if ((aad_ccm_real_len + aad_len_field_sz)
 733                                                 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
 734                                         uint8_t pad_len = 0;
 735                                         uint8_t pad_idx = 0;
 736
 737                                         pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
 738                                         ((aad_ccm_real_len + aad_len_field_sz) %
 739                                                 ICP_QAT_HW_CCM_AAD_B0_LEN);
 740                                         pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
 741                                             aad_ccm_real_len + aad_len_field_sz;
 742                                         memset(&aad_data[pad_idx],
 743                                                         0, pad_len);
 744                                 }
 745
 746                         }
 747
 748                         set_cipher_iv_ccm(ctx->cipher_iv.length,
 749                                         ctx->cipher_iv.offset,
 750                                         cipher_param, op, q,
 751                                         aad_len_field_sz);
 752
 753                 }
 754
 755                 cipher_len = op->sym->aead.data.length;
 756                 cipher_ofs = op->sym->aead.data.offset;
 757                 auth_len = op->sym->aead.data.length;
 758                 auth_ofs = op->sym->aead.data.offset;
 759
 760                 auth_param->u1.aad_adr = aad_phys_addr_aead;
 761                 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
 762                 min_ofs = op->sym->aead.data.offset;
 763         }
 764
 765         if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
 766                 do_sgl = 1;
 767
 768         /* adjust for chain case */
 769         if (do_cipher && do_auth)
 770                 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
 771
 772         if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
 773                 min_ofs = 0;
 774
 775         if (unlikely(op->sym->m_dst != NULL)) {
 776                 /* Out-of-place operation (OOP)
 777                  * Don't align DMA start. DMA the minimum data-set
 778                  * so as not to overwrite data in dest buffer
 779                  */
 780                 src_buf_start =
 781                         rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
 782                 dst_buf_start =
 783                         rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
 784
 785         } else {
 786                 /* In-place operation
 787                  * Start DMA at nearest aligned address below min_ofs
 788                  */
 789                 src_buf_start =
 790                         rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
 791                                                 & QAT_64_BTYE_ALIGN_MASK;
 792
 793                 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
 794                                         rte_pktmbuf_headroom(op->sym->m_src))
 795                                                         > src_buf_start)) {
 796                         /* alignment has pushed addr ahead of start of mbuf
 797                          * so revert and take the performance hit
 798                          */
 799                         src_buf_start =
 800                                 rte_pktmbuf_iova_offset(op->sym->m_src,
 801                                                                 min_ofs);
 802                 }
 803                 dst_buf_start = src_buf_start;
 804         }
 805
 806         if (do_cipher || do_aead) {
 807                 cipher_param->cipher_offset =
 808                                 (uint32_t)rte_pktmbuf_iova_offset(
 809                                 op->sym->m_src, cipher_ofs) - src_buf_start;
 810                 cipher_param->cipher_length = cipher_len;
 811         } else {
 812                 cipher_param->cipher_offset = 0;
 813                 cipher_param->cipher_length = 0;
 814         }
 815
 816         if (do_auth || do_aead) {
 817                 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
 818                                 op->sym->m_src, auth_ofs) - src_buf_start;
 819                 auth_param->auth_len = auth_len;
 820         } else {
 821                 auth_param->auth_off = 0;
 822                 auth_param->auth_len = 0;
 823         }
 824
 825         qat_req->comn_mid.dst_length =
 826                 qat_req->comn_mid.src_length =
 827                 (cipher_param->cipher_offset + cipher_param->cipher_length)
 828                 > (auth_param->auth_off + auth_param->auth_len) ?
 829                 (cipher_param->cipher_offset + cipher_param->cipher_length)
 830                 : (auth_param->auth_off + auth_param->auth_len);
 831
 832         if (do_sgl) {
 833
 834                 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
 835                                 QAT_COMN_PTR_TYPE_SGL);
 836                 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
 837                                 &cookie->qat_sgl_list_src,
 838                                 qat_req->comn_mid.src_length);
 839                 if (ret) {
 840                         PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
 841                         return ret;
 842                 }
 843
 844                 if (likely(op->sym->m_dst == NULL))
 845                         qat_req->comn_mid.dest_data_addr =
 846                                 qat_req->comn_mid.src_data_addr =
 847                                 cookie->qat_sgl_src_phys_addr;
 848                 else {
 849                         ret = qat_sgl_fill_array(op->sym->m_dst,
 850                                         dst_buf_start,
 851                                         &cookie->qat_sgl_list_dst,
 852                                                 qat_req->comn_mid.dst_length);
 853
 854                         if (ret) {
 855                                 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
 856                                                 "fill sgl array");
 857                                 return ret;
 858                         }
 859
 860                         qat_req->comn_mid.src_data_addr =
 861                                 cookie->qat_sgl_src_phys_addr;
 862                         qat_req->comn_mid.dest_data_addr =
 863                                         cookie->qat_sgl_dst_phys_addr;
 864                 }
 865         } else {
 866                 qat_req->comn_mid.src_data_addr = src_buf_start;
 867                 qat_req->comn_mid.dest_data_addr = dst_buf_start;
 868         }
 869
 870 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 871         rte_hexdump(stdout, "qat_req:", qat_req,
 872                         sizeof(struct icp_qat_fw_la_bulk_req));
 873         rte_hexdump(stdout, "src_data:",
 874                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
 875                         rte_pktmbuf_data_len(op->sym->m_src));
 876         if (do_cipher) {
 877                 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
 878                                                 uint8_t *,
 879                                                 ctx->cipher_iv.offset);
 880                 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
 881                                 ctx->cipher_iv.length);
 882         }
 883
 884         if (do_auth) {
 885                 if (ctx->auth_iv.length) {
 886                         uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
 887                                                         uint8_t *,
 888                                                         ctx->auth_iv.offset);
 889                         rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
 890                                                 ctx->auth_iv.length);
 891                 }
 892                 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
 893                                 ctx->digest_length);
 894         }
 895
 896         if (do_aead) {
 897                 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
 898                                 ctx->digest_length);
 899                 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
 900                                 ctx->aad_len);
 901         }
 902 #endif
 903         return 0;
 904 }
 905
 906 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
 907 {
 908         uint32_t div = data >> shift;
 909         uint32_t mult = div << shift;
 910
 911         return data - mult;
 912 }
 913
 914 void qat_sym_stats_get(struct rte_cryptodev *dev,
 915                 struct rte_cryptodev_stats *stats)
 916 {
 917         int i;
 918         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
 919
 920         PMD_INIT_FUNC_TRACE();
 921         if (stats == NULL) {
 922                 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
 923                 return;
 924         }
 925         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
 926                 if (qp[i] == NULL) {
 927                         PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
 928                         continue;
 929                 }
 930
 931                 stats->enqueued_count += qp[i]->stats.enqueued_count;
 932                 stats->dequeued_count += qp[i]->stats.dequeued_count;
 933                 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
 934                 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
 935         }
 936 }
 937
 938 void qat_sym_stats_reset(struct rte_cryptodev *dev)
 939 {
 940         int i;
 941         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
 942
 943         PMD_INIT_FUNC_TRACE();
 944         for (i = 0; i < dev->data->nb_queue_pairs; i++)
 945                 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
 946         PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
 947 }