drivers/crypto/qat/qat_sym.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2019 Intel Corporation
   3  */
   4
   5 #include <openssl/evp.h>
   6
   7 #include <rte_mempool.h>
   8 #include <rte_mbuf.h>
   9 #include <rte_crypto_sym.h>
  10 #include <rte_bus_pci.h>
  11 #include <rte_byteorder.h>
  12 #ifdef RTE_LIBRTE_SECURITY
  13 #include <rte_net_crc.h>
  14 #endif
  15
  16 #include "qat_sym.h"
  17
  18
  19 /** Decrypt a single partial block
  20  *  Depends on openssl libcrypto
  21  *  Uses ECB+XOR to do CFB encryption, same result, more performant
  22  */
  23 static inline int
  24 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
  25                 uint8_t *iv, int ivlen, int srclen,
  26                 void *bpi_ctx)
  27 {
  28         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
  29         int encrypted_ivlen;
  30         uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
  31         uint8_t *encr = encrypted_iv;
  32
  33         /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
  34         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
  35                                                                 <= 0)
  36                 goto cipher_decrypt_err;
  37
  38         for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
  39                 *dst = *src ^ *encr;
  40
  41         return 0;
  42
  43 cipher_decrypt_err:
  44         QAT_DP_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
  45         return -EINVAL;
  46 }
  47
  48
  49 static inline uint32_t
  50 qat_bpicipher_preprocess(struct qat_sym_session *ctx,
  51                                 struct rte_crypto_op *op)
  52 {
  53         int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
  54         struct rte_crypto_sym_op *sym_op = op->sym;
  55         uint8_t last_block_len = block_len > 0 ?
  56                         sym_op->cipher.data.length % block_len : 0;
  57
  58         if (last_block_len &&
  59                         ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
  60
  61                 /* Decrypt last block */
  62                 uint8_t *last_block, *dst, *iv;
  63                 uint32_t last_block_offset = sym_op->cipher.data.offset +
  64                                 sym_op->cipher.data.length - last_block_len;
  65                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
  66                                 uint8_t *, last_block_offset);
  67
  68                 if (unlikely((sym_op->m_dst != NULL)
  69                                 && (sym_op->m_dst != sym_op->m_src)))
  70                         /* out-of-place operation (OOP) */
  71                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
  72                                                 uint8_t *, last_block_offset);
  73                 else
  74                         dst = last_block;
  75
  76                 if (last_block_len < sym_op->cipher.data.length)
  77                         /* use previous block ciphertext as IV */
  78                         iv = last_block - block_len;
  79                 else
  80                         /* runt block, i.e. less than one full block */
  81                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
  82                                         ctx->cipher_iv.offset);
  83
  84 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
  85                 QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: src before pre-process:",
  86                         last_block, last_block_len);
  87                 if (sym_op->m_dst != NULL)
  88                         QAT_DP_HEXDUMP_LOG(DEBUG, "BPI:dst before pre-process:",
  89                         dst, last_block_len);
  90 #endif
  91                 bpi_cipher_decrypt(last_block, dst, iv, block_len,
  92                                 last_block_len, ctx->bpi_ctx);
  93 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
  94                 QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: src after pre-process:",
  95                         last_block, last_block_len);
  96                 if (sym_op->m_dst != NULL)
  97                         QAT_DP_HEXDUMP_LOG(DEBUG, "BPI: dst after pre-process:",
  98                         dst, last_block_len);
  99 #endif
 100         }
 101
 102         return sym_op->cipher.data.length - last_block_len;
 103 }
 104
 105 #ifdef RTE_LIBRTE_SECURITY
 106 static inline void
 107 qat_crc_generate(struct qat_sym_session *ctx,
 108                         struct rte_crypto_op *op)
 109 {
 110         struct rte_crypto_sym_op *sym_op = op->sym;
 111         uint32_t *crc, crc_length;
 112         uint8_t *crc_data;
 113
 114         if (ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT &&
 115                         sym_op->auth.data.length != 0) {
 116
 117                 crc_length = sym_op->auth.data.length;
 118                 crc_data = rte_pktmbuf_mtod_offset(sym_op->m_src, uint8_t *,
 119                                 sym_op->auth.data.offset);
 120                 crc = (uint32_t *)(crc_data + crc_length);
 121
 122                 *crc = rte_net_crc_calc(crc_data, crc_length,
 123                                 RTE_NET_CRC32_ETH);
 124         }
 125 }
 126 #endif
 127
 128 static inline void
 129 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
 130                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
 131                 struct rte_crypto_op *op,
 132                 struct icp_qat_fw_la_bulk_req *qat_req)
 133 {
 134         /* copy IV into request if it fits */
 135         if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
 136                 rte_memcpy(cipher_param->u.cipher_IV_array,
 137                                 rte_crypto_op_ctod_offset(op, uint8_t *,
 138                                         iv_offset),
 139                                 iv_length);
 140         } else {
 141                 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
 142                                 qat_req->comn_hdr.serv_specif_flags,
 143                                 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
 144                 cipher_param->u.s.cipher_IV_ptr =
 145                                 rte_crypto_op_ctophys_offset(op,
 146                                         iv_offset);
 147         }
 148 }
 149
 150 /** Set IV for CCM is special case, 0th byte is set to q-1
 151  *  where q is padding of nonce in 16 byte block
 152  */
 153 static inline void
 154 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
 155                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
 156                 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
 157 {
 158         rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
 159                         ICP_QAT_HW_CCM_NONCE_OFFSET,
 160                         rte_crypto_op_ctod_offset(op, uint8_t *,
 161                                 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
 162                         iv_length);
 163         *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
 164                         q - ICP_QAT_HW_CCM_NONCE_OFFSET;
 165
 166         if (aad_len_field_sz)
 167                 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
 168                         rte_crypto_op_ctod_offset(op, uint8_t *,
 169                                 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
 170                         iv_length);
 171 }
 172
 173 int
 174 qat_sym_build_request(void *in_op, uint8_t *out_msg,
 175                 void *op_cookie, enum qat_device_gen qat_dev_gen)
 176 {
 177         int ret = 0;
 178         struct qat_sym_session *ctx = NULL;
 179         struct icp_qat_fw_la_cipher_req_params *cipher_param;
 180         struct icp_qat_fw_la_auth_req_params *auth_param;
 181         register struct icp_qat_fw_la_bulk_req *qat_req;
 182         uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
 183         uint32_t cipher_len = 0, cipher_ofs = 0;
 184         uint32_t auth_len = 0, auth_ofs = 0;
 185         uint32_t min_ofs = 0;
 186         uint64_t src_buf_start = 0, dst_buf_start = 0;
 187         uint64_t auth_data_end = 0;
 188         uint8_t do_sgl = 0;
 189         uint8_t in_place = 1;
 190         uint8_t is_docsis_sec = 0;
 191         int alignment_adjustment = 0;
 192         struct rte_crypto_op *op = (struct rte_crypto_op *)in_op;
 193         struct qat_sym_op_cookie *cookie =
 194                                 (struct qat_sym_op_cookie *)op_cookie;
 195
 196         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
 197                 QAT_DP_LOG(ERR, "QAT PMD only supports symmetric crypto "
 198                                 "operation requests, op (%p) is not a "
 199                                 "symmetric operation.", op);
 200                 return -EINVAL;
 201         }
 202
 203         if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 204                 QAT_DP_LOG(ERR, "QAT PMD only supports session oriented"
 205                                 " requests, op (%p) is sessionless.", op);
 206                 return -EINVAL;
 207         } else if (op->sess_type == RTE_CRYPTO_OP_WITH_SESSION) {
 208                 ctx = (struct qat_sym_session *)get_sym_session_private_data(
 209                                 op->sym->session, qat_sym_driver_id);
 210 #ifdef RTE_LIBRTE_SECURITY
 211         } else {
 212                 ctx = (struct qat_sym_session *)get_sec_session_private_data(
 213                                 op->sym->sec_session);
 214                 if (ctx && ctx->bpi_ctx == NULL) {
 215                         QAT_DP_LOG(ERR, "QAT PMD only supports security"
 216                                         " operation requests for DOCSIS, op"
 217                                         " (%p) is not for DOCSIS.", op);
 218                         return -EINVAL;
 219                 }
 220                 is_docsis_sec = 1;
 221 #endif
 222         }
 223
 224         if (unlikely(ctx == NULL)) {
 225                 QAT_DP_LOG(ERR, "Session was not created for this device");
 226                 return -EINVAL;
 227         }
 228
 229         if (unlikely(ctx->min_qat_dev_gen > qat_dev_gen)) {
 230                 QAT_DP_LOG(ERR, "Session alg not supported on this device gen");
 231                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
 232                 return -EINVAL;
 233         }
 234
 235         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
 236         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
 237         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
 238         cipher_param = (void *)&qat_req->serv_specif_rqpars;
 239         auth_param = (void *)((uint8_t *)cipher_param +
 240                         ICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);
 241
 242         if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
 243                         ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
 244                 /* AES-GCM or AES-CCM */
 245                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 246                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
 247                         (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
 248                         && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
 249                         && ctx->qat_hash_alg ==
 250                                         ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
 251                         do_aead = 1;
 252                 } else {
 253                         do_auth = 1;
 254                         do_cipher = 1;
 255                 }
 256         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
 257                 do_auth = 1;
 258                 do_cipher = 0;
 259         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
 260                 do_auth = 0;
 261                 do_cipher = 1;
 262         }
 263
 264         if (do_cipher) {
 265
 266                 if (ctx->qat_cipher_alg ==
 267                                          ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 268                         ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
 269                         ctx->qat_cipher_alg ==
 270                                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
 271
 272                         if (unlikely(
 273                             (op->sym->cipher.data.length % BYTE_LENGTH != 0) ||
 274                             (op->sym->cipher.data.offset % BYTE_LENGTH != 0))) {
 275                                 QAT_DP_LOG(ERR,
 276                   "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
 277                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 278                                 return -EINVAL;
 279                         }
 280                         cipher_len = op->sym->cipher.data.length >> 3;
 281                         cipher_ofs = op->sym->cipher.data.offset >> 3;
 282
 283                 } else if (ctx->bpi_ctx) {
 284                         /* DOCSIS processing */
 285 #ifdef RTE_LIBRTE_SECURITY
 286                         if (is_docsis_sec) {
 287                                 /* Check for OOP or multi-segment buffers */
 288                                 if (unlikely(((op->sym->m_dst != NULL) &&
 289                                                 (op->sym->m_dst !=
 290                                                 op->sym->m_src)) ||
 291                                                 op->sym->m_src->nb_segs > 1)) {
 292                                         QAT_DP_LOG(ERR,
 293                                                 "OOP and/or multi-segment "
 294                                                 "buffers are not supported for "
 295                                                 "DOCSIS security");
 296                                         op->status =
 297                                         RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 298                                         return -EINVAL;
 299                                 }
 300
 301                                 /* Calculate CRC */
 302                                 qat_crc_generate(ctx, op);
 303                         }
 304 #else
 305                         RTE_SET_USED(is_docsis_sec);
 306 #endif
 307
 308                         /* Only send complete blocks to device.
 309                          * Process any partial block using CFB mode.
 310                          * Even if 0 complete blocks, still send this to device
 311                          * to get into rx queue for post-process and dequeuing
 312                          */
 313                         cipher_len = qat_bpicipher_preprocess(ctx, op);
 314                         cipher_ofs = op->sym->cipher.data.offset;
 315                 } else {
 316                         cipher_len = op->sym->cipher.data.length;
 317                         cipher_ofs = op->sym->cipher.data.offset;
 318                 }
 319
 320                 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
 321                                 cipher_param, op, qat_req);
 322                 min_ofs = cipher_ofs;
 323         }
 324
 325         if (do_auth) {
 326
 327                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
 328                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
 329                         ctx->qat_hash_alg ==
 330                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
 331                         if (unlikely(
 332                             (op->sym->auth.data.offset % BYTE_LENGTH != 0) ||
 333                             (op->sym->auth.data.length % BYTE_LENGTH != 0))) {
 334                                 QAT_DP_LOG(ERR,
 335                 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
 336                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 337                                 return -EINVAL;
 338                         }
 339                         auth_ofs = op->sym->auth.data.offset >> 3;
 340                         auth_len = op->sym->auth.data.length >> 3;
 341
 342                         auth_param->u1.aad_adr =
 343                                         rte_crypto_op_ctophys_offset(op,
 344                                                         ctx->auth_iv.offset);
 345
 346                 } else if (ctx->qat_hash_alg ==
 347                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 348                                 ctx->qat_hash_alg ==
 349                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
 350                         /* AES-GMAC */
 351                         set_cipher_iv(ctx->auth_iv.length,
 352                                 ctx->auth_iv.offset,
 353                                 cipher_param, op, qat_req);
 354                         auth_ofs = op->sym->auth.data.offset;
 355                         auth_len = op->sym->auth.data.length;
 356
 357                         auth_param->u1.aad_adr = 0;
 358                         auth_param->u2.aad_sz = 0;
 359
 360                         /*
 361                          * If len(iv)==12B fw computes J0
 362                          */
 363                         if (ctx->auth_iv.length == 12) {
 364                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
 365                                         qat_req->comn_hdr.serv_specif_flags,
 366                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 367
 368                         }
 369                 } else {
 370                         auth_ofs = op->sym->auth.data.offset;
 371                         auth_len = op->sym->auth.data.length;
 372
 373                 }
 374                 min_ofs = auth_ofs;
 375
 376                 auth_param->auth_res_addr =
 377                         op->sym->auth.digest.phys_addr;
 378
 379         }
 380
 381         if (do_aead) {
 382                 /*
 383                  * This address may used for setting AAD physical pointer
 384                  * into IV offset from op
 385                  */
 386                 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
 387                 if (ctx->qat_hash_alg ==
 388                                 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 389                                 ctx->qat_hash_alg ==
 390                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
 391                         /*
 392                          * If len(iv)==12B fw computes J0
 393                          */
 394                         if (ctx->cipher_iv.length == 12) {
 395                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
 396                                         qat_req->comn_hdr.serv_specif_flags,
 397                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 398                         }
 399                         set_cipher_iv(ctx->cipher_iv.length,
 400                                         ctx->cipher_iv.offset,
 401                                         cipher_param, op, qat_req);
 402
 403                 } else if (ctx->qat_hash_alg ==
 404                                 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
 405
 406                         /* In case of AES-CCM this may point to user selected
 407                          * memory or iv offset in cypto_op
 408                          */
 409                         uint8_t *aad_data = op->sym->aead.aad.data;
 410                         /* This is true AAD length, it not includes 18 bytes of
 411                          * preceding data
 412                          */
 413                         uint8_t aad_ccm_real_len = 0;
 414                         uint8_t aad_len_field_sz = 0;
 415                         uint32_t msg_len_be =
 416                                         rte_bswap32(op->sym->aead.data.length);
 417
 418                         if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
 419                                 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
 420                                 aad_ccm_real_len = ctx->aad_len -
 421                                         ICP_QAT_HW_CCM_AAD_B0_LEN -
 422                                         ICP_QAT_HW_CCM_AAD_LEN_INFO;
 423                         } else {
 424                                 /*
 425                                  * aad_len not greater than 18, so no actual aad
 426                                  *  data, then use IV after op for B0 block
 427                                  */
 428                                 aad_data = rte_crypto_op_ctod_offset(op,
 429                                                 uint8_t *,
 430                                                 ctx->cipher_iv.offset);
 431                                 aad_phys_addr_aead =
 432                                                 rte_crypto_op_ctophys_offset(op,
 433                                                         ctx->cipher_iv.offset);
 434                         }
 435
 436                         uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
 437                                                         ctx->cipher_iv.length;
 438
 439                         aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
 440                                                         aad_len_field_sz,
 441                                                         ctx->digest_length, q);
 442
 443                         if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
 444                                 memcpy(aad_data + ctx->cipher_iv.length +
 445                                     ICP_QAT_HW_CCM_NONCE_OFFSET +
 446                                     (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
 447                                     (uint8_t *)&msg_len_be,
 448                                     ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
 449                         } else {
 450                                 memcpy(aad_data + ctx->cipher_iv.length +
 451                                     ICP_QAT_HW_CCM_NONCE_OFFSET,
 452                                     (uint8_t *)&msg_len_be
 453                                     + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
 454                                     - q), q);
 455                         }
 456
 457                         if (aad_len_field_sz > 0) {
 458                                 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
 459                                                 = rte_bswap16(aad_ccm_real_len);
 460
 461                                 if ((aad_ccm_real_len + aad_len_field_sz)
 462                                                 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
 463                                         uint8_t pad_len = 0;
 464                                         uint8_t pad_idx = 0;
 465
 466                                         pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
 467                                         ((aad_ccm_real_len + aad_len_field_sz) %
 468                                                 ICP_QAT_HW_CCM_AAD_B0_LEN);
 469                                         pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
 470                                             aad_ccm_real_len + aad_len_field_sz;
 471                                         memset(&aad_data[pad_idx],
 472                                                         0, pad_len);
 473                                 }
 474
 475                         }
 476
 477                         set_cipher_iv_ccm(ctx->cipher_iv.length,
 478                                         ctx->cipher_iv.offset,
 479                                         cipher_param, op, q,
 480                                         aad_len_field_sz);
 481
 482                 }
 483
 484                 cipher_len = op->sym->aead.data.length;
 485                 cipher_ofs = op->sym->aead.data.offset;
 486                 auth_len = op->sym->aead.data.length;
 487                 auth_ofs = op->sym->aead.data.offset;
 488
 489                 auth_param->u1.aad_adr = aad_phys_addr_aead;
 490                 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
 491                 min_ofs = op->sym->aead.data.offset;
 492         }
 493
 494         if (op->sym->m_src->nb_segs > 1 ||
 495                         (op->sym->m_dst && op->sym->m_dst->nb_segs > 1))
 496                 do_sgl = 1;
 497
 498         /* adjust for chain case */
 499         if (do_cipher && do_auth)
 500                 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
 501
 502         if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
 503                 min_ofs = 0;
 504
 505         if (unlikely((op->sym->m_dst != NULL) &&
 506                         (op->sym->m_dst != op->sym->m_src))) {
 507                 /* Out-of-place operation (OOP)
 508                  * Don't align DMA start. DMA the minimum data-set
 509                  * so as not to overwrite data in dest buffer
 510                  */
 511                 in_place = 0;
 512                 src_buf_start =
 513                         rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
 514                 dst_buf_start =
 515                         rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
 516
 517         } else {
 518                 /* In-place operation
 519                  * Start DMA at nearest aligned address below min_ofs
 520                  */
 521                 src_buf_start =
 522                         rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
 523                                                 & QAT_64_BTYE_ALIGN_MASK;
 524
 525                 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
 526                                         rte_pktmbuf_headroom(op->sym->m_src))
 527                                                         > src_buf_start)) {
 528                         /* alignment has pushed addr ahead of start of mbuf
 529                          * so revert and take the performance hit
 530                          */
 531                         src_buf_start =
 532                                 rte_pktmbuf_iova_offset(op->sym->m_src,
 533                                                                 min_ofs);
 534                 }
 535                 dst_buf_start = src_buf_start;
 536
 537                 /* remember any adjustment for later, note, can be +/- */
 538                 alignment_adjustment = src_buf_start -
 539                         rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
 540         }
 541
 542         if (do_cipher || do_aead) {
 543                 cipher_param->cipher_offset =
 544                                 (uint32_t)rte_pktmbuf_iova_offset(
 545                                 op->sym->m_src, cipher_ofs) - src_buf_start;
 546                 cipher_param->cipher_length = cipher_len;
 547         } else {
 548                 cipher_param->cipher_offset = 0;
 549                 cipher_param->cipher_length = 0;
 550         }
 551
 552         if (do_auth || do_aead) {
 553                 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
 554                                 op->sym->m_src, auth_ofs) - src_buf_start;
 555                 auth_param->auth_len = auth_len;
 556         } else {
 557                 auth_param->auth_off = 0;
 558                 auth_param->auth_len = 0;
 559         }
 560
 561         qat_req->comn_mid.dst_length =
 562                 qat_req->comn_mid.src_length =
 563                 (cipher_param->cipher_offset + cipher_param->cipher_length)
 564                 > (auth_param->auth_off + auth_param->auth_len) ?
 565                 (cipher_param->cipher_offset + cipher_param->cipher_length)
 566                 : (auth_param->auth_off + auth_param->auth_len);
 567
 568         if (do_auth && do_cipher) {
 569                 /* Handle digest-encrypted cases, i.e.
 570                  * auth-gen-then-cipher-encrypt and
 571                  * cipher-decrypt-then-auth-verify
 572                  */
 573                  /* First find the end of the data */
 574                 if (do_sgl) {
 575                         uint32_t remaining_off = auth_param->auth_off +
 576                                 auth_param->auth_len + alignment_adjustment;
 577                         struct rte_mbuf *sgl_buf =
 578                                 (in_place ?
 579                                         op->sym->m_src : op->sym->m_dst);
 580
 581                         while (remaining_off >= rte_pktmbuf_data_len(sgl_buf)
 582                                         && sgl_buf->next != NULL) {
 583                                 remaining_off -= rte_pktmbuf_data_len(sgl_buf);
 584                                 sgl_buf = sgl_buf->next;
 585                         }
 586
 587                         auth_data_end = (uint64_t)rte_pktmbuf_iova_offset(
 588                                 sgl_buf, remaining_off);
 589                 } else {
 590                         auth_data_end = (in_place ?
 591                                 src_buf_start : dst_buf_start) +
 592                                 auth_param->auth_off + auth_param->auth_len;
 593                 }
 594                 /* Then check if digest-encrypted conditions are met */
 595                 if ((auth_param->auth_off + auth_param->auth_len <
 596                                         cipher_param->cipher_offset +
 597                                         cipher_param->cipher_length) &&
 598                                 (op->sym->auth.digest.phys_addr ==
 599                                         auth_data_end)) {
 600                         /* Handle partial digest encryption */
 601                         if (cipher_param->cipher_offset +
 602                                         cipher_param->cipher_length <
 603                                         auth_param->auth_off +
 604                                         auth_param->auth_len +
 605                                         ctx->digest_length)
 606                                 qat_req->comn_mid.dst_length =
 607                                         qat_req->comn_mid.src_length =
 608                                         auth_param->auth_off +
 609                                         auth_param->auth_len +
 610                                         ctx->digest_length;
 611                         struct icp_qat_fw_comn_req_hdr *header =
 612                                 &qat_req->comn_hdr;
 613                         ICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(
 614                                 header->serv_specif_flags,
 615                                 ICP_QAT_FW_LA_DIGEST_IN_BUFFER);
 616                 }
 617         }
 618
 619         if (do_sgl) {
 620
 621                 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
 622                                 QAT_COMN_PTR_TYPE_SGL);
 623                 ret = qat_sgl_fill_array(op->sym->m_src,
 624                    (int64_t)(src_buf_start - rte_pktmbuf_iova(op->sym->m_src)),
 625                    &cookie->qat_sgl_src,
 626                    qat_req->comn_mid.src_length,
 627                    QAT_SYM_SGL_MAX_NUMBER);
 628
 629                 if (unlikely(ret)) {
 630                         QAT_DP_LOG(ERR, "QAT PMD Cannot fill sgl array");
 631                         return ret;
 632                 }
 633
 634                 if (in_place)
 635                         qat_req->comn_mid.dest_data_addr =
 636                                 qat_req->comn_mid.src_data_addr =
 637                                 cookie->qat_sgl_src_phys_addr;
 638                 else {
 639                         ret = qat_sgl_fill_array(op->sym->m_dst,
 640                                 (int64_t)(dst_buf_start -
 641                                           rte_pktmbuf_iova(op->sym->m_dst)),
 642                                  &cookie->qat_sgl_dst,
 643                                  qat_req->comn_mid.dst_length,
 644                                  QAT_SYM_SGL_MAX_NUMBER);
 645
 646                         if (unlikely(ret)) {
 647                                 QAT_DP_LOG(ERR, "QAT PMD can't fill sgl array");
 648                                 return ret;
 649                         }
 650
 651                         qat_req->comn_mid.src_data_addr =
 652                                 cookie->qat_sgl_src_phys_addr;
 653                         qat_req->comn_mid.dest_data_addr =
 654                                         cookie->qat_sgl_dst_phys_addr;
 655                 }
 656                 qat_req->comn_mid.src_length = 0;
 657                 qat_req->comn_mid.dst_length = 0;
 658         } else {
 659                 qat_req->comn_mid.src_data_addr = src_buf_start;
 660                 qat_req->comn_mid.dest_data_addr = dst_buf_start;
 661         }
 662
 663         /* Handle Single-Pass GCM */
 664         if (ctx->is_single_pass) {
 665                 cipher_param->spc_aad_addr = op->sym->aead.aad.phys_addr;
 666                 cipher_param->spc_auth_res_addr =
 667                                 op->sym->aead.digest.phys_addr;
 668         }
 669
 670 #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG
 671         QAT_DP_HEXDUMP_LOG(DEBUG, "qat_req:", qat_req,
 672                         sizeof(struct icp_qat_fw_la_bulk_req));
 673         QAT_DP_HEXDUMP_LOG(DEBUG, "src_data:",
 674                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
 675                         rte_pktmbuf_data_len(op->sym->m_src));
 676         if (do_cipher) {
 677                 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
 678                                                 uint8_t *,
 679                                                 ctx->cipher_iv.offset);
 680                 QAT_DP_HEXDUMP_LOG(DEBUG, "cipher iv:", cipher_iv_ptr,
 681                                 ctx->cipher_iv.length);
 682         }
 683
 684         if (do_auth) {
 685                 if (ctx->auth_iv.length) {
 686                         uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
 687                                                         uint8_t *,
 688                                                         ctx->auth_iv.offset);
 689                         QAT_DP_HEXDUMP_LOG(DEBUG, "auth iv:", auth_iv_ptr,
 690                                                 ctx->auth_iv.length);
 691                 }
 692                 QAT_DP_HEXDUMP_LOG(DEBUG, "digest:", op->sym->auth.digest.data,
 693                                 ctx->digest_length);
 694         }
 695
 696         if (do_aead) {
 697                 QAT_DP_HEXDUMP_LOG(DEBUG, "digest:", op->sym->aead.digest.data,
 698                                 ctx->digest_length);
 699                 QAT_DP_HEXDUMP_LOG(DEBUG, "aad:", op->sym->aead.aad.data,
 700                                 ctx->aad_len);
 701         }
 702 #endif
 703         return 0;
 704 }