drivers/crypto/qat/qat_sym.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4
   5 #include <rte_mempool.h>
   6 #include <rte_mbuf.h>
   7 #include <rte_hexdump.h>
   8 #include <rte_crypto_sym.h>
   9 #include <rte_bus_pci.h>
  10 #include <rte_byteorder.h>
  11
  12 #include <openssl/evp.h>
  13
  14 #include "qat_logs.h"
  15 #include "qat_sym_session.h"
  16 #include "qat_sym.h"
  17 #include "adf_transport_access_macros.h"
  18
  19 #define BYTE_LENGTH    8
  20 /* bpi is only used for partial blocks of DES and AES
  21  * so AES block len can be assumed as max len for iv, src and dst
  22  */
  23 #define BPI_MAX_ENCR_IV_LEN ICP_QAT_HW_AES_BLK_SZ
  24
  25 /** Encrypt a single partial block
  26  *  Depends on openssl libcrypto
  27  *  Uses ECB+XOR to do CFB encryption, same result, more performant
  28  */
  29 static inline int
  30 bpi_cipher_encrypt(uint8_t *src, uint8_t *dst,
  31                 uint8_t *iv, int ivlen, int srclen,
  32                 void *bpi_ctx)
  33 {
  34         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
  35         int encrypted_ivlen;
  36         uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
  37         uint8_t *encr = encrypted_iv;
  38
  39         /* ECB method: encrypt the IV, then XOR this with plaintext */
  40         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
  41                                                                 <= 0)
  42                 goto cipher_encrypt_err;
  43
  44         for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
  45                 *dst = *src ^ *encr;
  46
  47         return 0;
  48
  49 cipher_encrypt_err:
  50         PMD_DRV_LOG(ERR, "libcrypto ECB cipher encrypt failed");
  51         return -EINVAL;
  52 }
  53
  54 /** Decrypt a single partial block
  55  *  Depends on openssl libcrypto
  56  *  Uses ECB+XOR to do CFB encryption, same result, more performant
  57  */
  58 static inline int
  59 bpi_cipher_decrypt(uint8_t *src, uint8_t *dst,
  60                 uint8_t *iv, int ivlen, int srclen,
  61                 void *bpi_ctx)
  62 {
  63         EVP_CIPHER_CTX *ctx = (EVP_CIPHER_CTX *)bpi_ctx;
  64         int encrypted_ivlen;
  65         uint8_t encrypted_iv[BPI_MAX_ENCR_IV_LEN];
  66         uint8_t *encr = encrypted_iv;
  67
  68         /* ECB method: encrypt (not decrypt!) the IV, then XOR with plaintext */
  69         if (EVP_EncryptUpdate(ctx, encrypted_iv, &encrypted_ivlen, iv, ivlen)
  70                                                                 <= 0)
  71                 goto cipher_decrypt_err;
  72
  73         for (; srclen != 0; --srclen, ++dst, ++src, ++encr)
  74                 *dst = *src ^ *encr;
  75
  76         return 0;
  77
  78 cipher_decrypt_err:
  79         PMD_DRV_LOG(ERR, "libcrypto ECB cipher decrypt for BPI IV failed");
  80         return -EINVAL;
  81 }
  82
  83 /** Creates a context in either AES or DES in ECB mode
  84  *  Depends on openssl libcrypto
  85  */
  86 static inline uint32_t
  87 adf_modulo(uint32_t data, uint32_t shift);
  88
  89 static inline int
  90 qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,
  91                 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp);
  92
  93 static inline uint32_t
  94 qat_bpicipher_preprocess(struct qat_session *ctx,
  95                                 struct rte_crypto_op *op)
  96 {
  97         int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
  98         struct rte_crypto_sym_op *sym_op = op->sym;
  99         uint8_t last_block_len = block_len > 0 ?
 100                         sym_op->cipher.data.length % block_len : 0;
 101
 102         if (last_block_len &&
 103                         ctx->qat_dir == ICP_QAT_HW_CIPHER_DECRYPT) {
 104
 105                 /* Decrypt last block */
 106                 uint8_t *last_block, *dst, *iv;
 107                 uint32_t last_block_offset = sym_op->cipher.data.offset +
 108                                 sym_op->cipher.data.length - last_block_len;
 109                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 110                                 uint8_t *, last_block_offset);
 111
 112                 if (unlikely(sym_op->m_dst != NULL))
 113                         /* out-of-place operation (OOP) */
 114                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 115                                                 uint8_t *, last_block_offset);
 116                 else
 117                         dst = last_block;
 118
 119                 if (last_block_len < sym_op->cipher.data.length)
 120                         /* use previous block ciphertext as IV */
 121                         iv = last_block - block_len;
 122                 else
 123                         /* runt block, i.e. less than one full block */
 124                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 125                                         ctx->cipher_iv.offset);
 126
 127 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 128                 rte_hexdump(stdout, "BPI: src before pre-process:", last_block,
 129                         last_block_len);
 130                 if (sym_op->m_dst != NULL)
 131                         rte_hexdump(stdout, "BPI: dst before pre-process:", dst,
 132                                 last_block_len);
 133 #endif
 134                 bpi_cipher_decrypt(last_block, dst, iv, block_len,
 135                                 last_block_len, ctx->bpi_ctx);
 136 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 137                 rte_hexdump(stdout, "BPI: src after pre-process:", last_block,
 138                         last_block_len);
 139                 if (sym_op->m_dst != NULL)
 140                         rte_hexdump(stdout, "BPI: dst after pre-process:", dst,
 141                                 last_block_len);
 142 #endif
 143         }
 144
 145         return sym_op->cipher.data.length - last_block_len;
 146 }
 147
 148 static inline uint32_t
 149 qat_bpicipher_postprocess(struct qat_session *ctx,
 150                                 struct rte_crypto_op *op)
 151 {
 152         int block_len = qat_cipher_get_block_size(ctx->qat_cipher_alg);
 153         struct rte_crypto_sym_op *sym_op = op->sym;
 154         uint8_t last_block_len = block_len > 0 ?
 155                         sym_op->cipher.data.length % block_len : 0;
 156
 157         if (last_block_len > 0 &&
 158                         ctx->qat_dir == ICP_QAT_HW_CIPHER_ENCRYPT) {
 159
 160                 /* Encrypt last block */
 161                 uint8_t *last_block, *dst, *iv;
 162                 uint32_t last_block_offset;
 163
 164                 last_block_offset = sym_op->cipher.data.offset +
 165                                 sym_op->cipher.data.length - last_block_len;
 166                 last_block = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_src,
 167                                 uint8_t *, last_block_offset);
 168
 169                 if (unlikely(sym_op->m_dst != NULL))
 170                         /* out-of-place operation (OOP) */
 171                         dst = (uint8_t *) rte_pktmbuf_mtod_offset(sym_op->m_dst,
 172                                                 uint8_t *, last_block_offset);
 173                 else
 174                         dst = last_block;
 175
 176                 if (last_block_len < sym_op->cipher.data.length)
 177                         /* use previous block ciphertext as IV */
 178                         iv = dst - block_len;
 179                 else
 180                         /* runt block, i.e. less than one full block */
 181                         iv = rte_crypto_op_ctod_offset(op, uint8_t *,
 182                                         ctx->cipher_iv.offset);
 183
 184 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 185                 rte_hexdump(stdout, "BPI: src before post-process:", last_block,
 186                         last_block_len);
 187                 if (sym_op->m_dst != NULL)
 188                         rte_hexdump(stdout, "BPI: dst before post-process:",
 189                                         dst, last_block_len);
 190 #endif
 191                 bpi_cipher_encrypt(last_block, dst, iv, block_len,
 192                                 last_block_len, ctx->bpi_ctx);
 193 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 194                 rte_hexdump(stdout, "BPI: src after post-process:", last_block,
 195                         last_block_len);
 196                 if (sym_op->m_dst != NULL)
 197                         rte_hexdump(stdout, "BPI: dst after post-process:", dst,
 198                                 last_block_len);
 199 #endif
 200         }
 201         return sym_op->cipher.data.length - last_block_len;
 202 }
 203
 204 static inline void
 205 txq_write_tail(struct qat_qp *qp, struct qat_queue *q) {
 206         WRITE_CSR_RING_TAIL(qp->mmap_bar_addr, q->hw_bundle_number,
 207                         q->hw_queue_number, q->tail);
 208         q->nb_pending_requests = 0;
 209         q->csr_tail = q->tail;
 210 }
 211
 212 uint16_t
 213 qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
 214                 uint16_t nb_ops)
 215 {
 216         register struct qat_queue *queue;
 217         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 218         register uint32_t nb_ops_sent = 0;
 219         register struct rte_crypto_op **cur_op = ops;
 220         register int ret;
 221         uint16_t nb_ops_possible = nb_ops;
 222         register uint8_t *base_addr;
 223         register uint32_t tail;
 224         int overflow;
 225
 226         if (unlikely(nb_ops == 0))
 227                 return 0;
 228
 229         /* read params used a lot in main loop into registers */
 230         queue = &(tmp_qp->tx_q);
 231         base_addr = (uint8_t *)queue->base_addr;
 232         tail = queue->tail;
 233
 234         /* Find how many can actually fit on the ring */
 235         tmp_qp->inflights16 += nb_ops;
 236         overflow = tmp_qp->inflights16 - queue->max_inflights;
 237         if (overflow > 0) {
 238                 tmp_qp->inflights16 -= overflow;
 239                 nb_ops_possible = nb_ops - overflow;
 240                 if (nb_ops_possible == 0)
 241                         return 0;
 242         }
 243
 244         while (nb_ops_sent != nb_ops_possible) {
 245                 ret = qat_sym_build_request(*cur_op, base_addr + tail,
 246                         tmp_qp->op_cookies[tail / queue->msg_size], tmp_qp);
 247                 if (ret != 0) {
 248                         tmp_qp->stats.enqueue_err_count++;
 249                         /*
 250                          * This message cannot be enqueued,
 251                          * decrease number of ops that wasn't sent
 252                          */
 253                         tmp_qp->inflights16 -= nb_ops_possible - nb_ops_sent;
 254                         if (nb_ops_sent == 0)
 255                                 return 0;
 256                         goto kick_tail;
 257                 }
 258
 259                 tail = adf_modulo(tail + queue->msg_size, queue->modulo);
 260                 nb_ops_sent++;
 261                 cur_op++;
 262         }
 263 kick_tail:
 264         queue->tail = tail;
 265         tmp_qp->stats.enqueued_count += nb_ops_sent;
 266         queue->nb_pending_requests += nb_ops_sent;
 267         if (tmp_qp->inflights16 < QAT_CSR_TAIL_FORCE_WRITE_THRESH ||
 268                         queue->nb_pending_requests > QAT_CSR_TAIL_WRITE_THRESH) {
 269                 txq_write_tail(tmp_qp, queue);
 270         }
 271         return nb_ops_sent;
 272 }
 273
 274 static inline
 275 void rxq_free_desc(struct qat_qp *qp, struct qat_queue *q)
 276 {
 277         uint32_t old_head, new_head;
 278         uint32_t max_head;
 279
 280         old_head = q->csr_head;
 281         new_head = q->head;
 282         max_head = qp->nb_descriptors * q->msg_size;
 283
 284         /* write out free descriptors */
 285         void *cur_desc = (uint8_t *)q->base_addr + old_head;
 286
 287         if (new_head < old_head) {
 288                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, max_head - old_head);
 289                 memset(q->base_addr, ADF_RING_EMPTY_SIG_BYTE, new_head);
 290         } else {
 291                 memset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head - old_head);
 292         }
 293         q->nb_processed_responses = 0;
 294         q->csr_head = new_head;
 295
 296         /* write current head to CSR */
 297         WRITE_CSR_RING_HEAD(qp->mmap_bar_addr, q->hw_bundle_number,
 298                             q->hw_queue_number, new_head);
 299 }
 300
 301 uint16_t
 302 qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
 303                 uint16_t nb_ops)
 304 {
 305         struct qat_queue *rx_queue, *tx_queue;
 306         struct qat_qp *tmp_qp = (struct qat_qp *)qp;
 307         uint32_t msg_counter = 0;
 308         struct rte_crypto_op *rx_op;
 309         struct icp_qat_fw_comn_resp *resp_msg;
 310         uint32_t head;
 311
 312         rx_queue = &(tmp_qp->rx_q);
 313         tx_queue = &(tmp_qp->tx_q);
 314         head = rx_queue->head;
 315         resp_msg = (struct icp_qat_fw_comn_resp *)
 316                         ((uint8_t *)rx_queue->base_addr + head);
 317
 318         while (*(uint32_t *)resp_msg != ADF_RING_EMPTY_SIG &&
 319                         msg_counter != nb_ops) {
 320                 rx_op = (struct rte_crypto_op *)(uintptr_t)
 321                                 (resp_msg->opaque_data);
 322
 323 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_RX
 324                 rte_hexdump(stdout, "qat_response:", (uint8_t *)resp_msg,
 325                         sizeof(struct icp_qat_fw_comn_resp));
 326 #endif
 327                 if (ICP_QAT_FW_COMN_STATUS_FLAG_OK !=
 328                                 ICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(
 329                                         resp_msg->comn_hdr.comn_status)) {
 330                         rx_op->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;
 331                 } else {
 332                         struct qat_session *sess = (struct qat_session *)
 333                                         get_session_private_data(
 334                                         rx_op->sym->session,
 335                                         cryptodev_qat_driver_id);
 336
 337                         if (sess->bpi_ctx)
 338                                 qat_bpicipher_postprocess(sess, rx_op);
 339                         rx_op->status = RTE_CRYPTO_OP_STATUS_SUCCESS;
 340                 }
 341
 342                 head = adf_modulo(head + rx_queue->msg_size, rx_queue->modulo);
 343                 resp_msg = (struct icp_qat_fw_comn_resp *)
 344                                 ((uint8_t *)rx_queue->base_addr + head);
 345                 *ops = rx_op;
 346                 ops++;
 347                 msg_counter++;
 348         }
 349         if (msg_counter > 0) {
 350                 rx_queue->head = head;
 351                 tmp_qp->stats.dequeued_count += msg_counter;
 352                 rx_queue->nb_processed_responses += msg_counter;
 353                 tmp_qp->inflights16 -= msg_counter;
 354
 355                 if (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH)
 356                         rxq_free_desc(tmp_qp, rx_queue);
 357         }
 358         /* also check if tail needs to be advanced */
 359         if (tmp_qp->inflights16 <= QAT_CSR_TAIL_FORCE_WRITE_THRESH &&
 360                         tx_queue->tail != tx_queue->csr_tail) {
 361                 txq_write_tail(tmp_qp, tx_queue);
 362         }
 363         return msg_counter;
 364 }
 365
 366 static inline int
 367 qat_sgl_fill_array(struct rte_mbuf *buf, uint64_t buff_start,
 368                 struct qat_alg_buf_list *list, uint32_t data_len)
 369 {
 370         int nr = 1;
 371
 372         uint32_t buf_len = rte_pktmbuf_iova(buf) -
 373                         buff_start + rte_pktmbuf_data_len(buf);
 374
 375         list->bufers[0].addr = buff_start;
 376         list->bufers[0].resrvd = 0;
 377         list->bufers[0].len = buf_len;
 378
 379         if (data_len <= buf_len) {
 380                 list->num_bufs = nr;
 381                 list->bufers[0].len = data_len;
 382                 return 0;
 383         }
 384
 385         buf = buf->next;
 386         while (buf) {
 387                 if (unlikely(nr == QAT_SGL_MAX_NUMBER)) {
 388                         PMD_DRV_LOG(ERR, "QAT PMD exceeded size of QAT SGL"
 389                                         " entry(%u)",
 390                                         QAT_SGL_MAX_NUMBER);
 391                         return -EINVAL;
 392                 }
 393
 394                 list->bufers[nr].len = rte_pktmbuf_data_len(buf);
 395                 list->bufers[nr].resrvd = 0;
 396                 list->bufers[nr].addr = rte_pktmbuf_iova(buf);
 397
 398                 buf_len += list->bufers[nr].len;
 399                 buf = buf->next;
 400
 401                 if (buf_len > data_len) {
 402                         list->bufers[nr].len -=
 403                                 buf_len - data_len;
 404                         buf = NULL;
 405                 }
 406                 ++nr;
 407         }
 408         list->num_bufs = nr;
 409
 410         return 0;
 411 }
 412
 413 static inline void
 414 set_cipher_iv(uint16_t iv_length, uint16_t iv_offset,
 415                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
 416                 struct rte_crypto_op *op,
 417                 struct icp_qat_fw_la_bulk_req *qat_req)
 418 {
 419         /* copy IV into request if it fits */
 420         if (iv_length <= sizeof(cipher_param->u.cipher_IV_array)) {
 421                 rte_memcpy(cipher_param->u.cipher_IV_array,
 422                                 rte_crypto_op_ctod_offset(op, uint8_t *,
 423                                         iv_offset),
 424                                 iv_length);
 425         } else {
 426                 ICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(
 427                                 qat_req->comn_hdr.serv_specif_flags,
 428                                 ICP_QAT_FW_CIPH_IV_64BIT_PTR);
 429                 cipher_param->u.s.cipher_IV_ptr =
 430                                 rte_crypto_op_ctophys_offset(op,
 431                                         iv_offset);
 432         }
 433 }
 434
 435 /** Set IV for CCM is special case, 0th byte is set to q-1
 436  *  where q is padding of nonce in 16 byte block
 437  */
 438 static inline void
 439 set_cipher_iv_ccm(uint16_t iv_length, uint16_t iv_offset,
 440                 struct icp_qat_fw_la_cipher_req_params *cipher_param,
 441                 struct rte_crypto_op *op, uint8_t q, uint8_t aad_len_field_sz)
 442 {
 443         rte_memcpy(((uint8_t *)cipher_param->u.cipher_IV_array) +
 444                         ICP_QAT_HW_CCM_NONCE_OFFSET,
 445                         rte_crypto_op_ctod_offset(op, uint8_t *,
 446                                 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
 447                         iv_length);
 448         *(uint8_t *)&cipher_param->u.cipher_IV_array[0] =
 449                         q - ICP_QAT_HW_CCM_NONCE_OFFSET;
 450
 451         if (aad_len_field_sz)
 452                 rte_memcpy(&op->sym->aead.aad.data[ICP_QAT_HW_CCM_NONCE_OFFSET],
 453                         rte_crypto_op_ctod_offset(op, uint8_t *,
 454                                 iv_offset) + ICP_QAT_HW_CCM_NONCE_OFFSET,
 455                         iv_length);
 456 }
 457
 458 static inline int
 459 qat_sym_build_request(struct rte_crypto_op *op, uint8_t *out_msg,
 460                 struct qat_crypto_op_cookie *qat_op_cookie, struct qat_qp *qp)
 461 {
 462         int ret = 0;
 463         struct qat_session *ctx;
 464         struct icp_qat_fw_la_cipher_req_params *cipher_param;
 465         struct icp_qat_fw_la_auth_req_params *auth_param;
 466         register struct icp_qat_fw_la_bulk_req *qat_req;
 467         uint8_t do_auth = 0, do_cipher = 0, do_aead = 0;
 468         uint32_t cipher_len = 0, cipher_ofs = 0;
 469         uint32_t auth_len = 0, auth_ofs = 0;
 470         uint32_t min_ofs = 0;
 471         uint64_t src_buf_start = 0, dst_buf_start = 0;
 472         uint8_t do_sgl = 0;
 473
 474 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 475         if (unlikely(op->type != RTE_CRYPTO_OP_TYPE_SYMMETRIC)) {
 476                 PMD_DRV_LOG(ERR, "QAT PMD only supports symmetric crypto "
 477                                 "operation requests, op (%p) is not a "
 478                                 "symmetric operation.", op);
 479                 return -EINVAL;
 480         }
 481 #endif
 482         if (unlikely(op->sess_type == RTE_CRYPTO_OP_SESSIONLESS)) {
 483                 PMD_DRV_LOG(ERR, "QAT PMD only supports session oriented"
 484                                 " requests, op (%p) is sessionless.", op);
 485                 return -EINVAL;
 486         }
 487
 488         ctx = (struct qat_session *)get_session_private_data(
 489                         op->sym->session, cryptodev_qat_driver_id);
 490
 491         if (unlikely(ctx == NULL)) {
 492                 PMD_DRV_LOG(ERR, "Session was not created for this device");
 493                 return -EINVAL;
 494         }
 495
 496         if (unlikely(ctx->min_qat_dev_gen > qp->qat_dev_gen)) {
 497                 PMD_DRV_LOG(ERR, "Session alg not supported on this device gen");
 498                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;
 499                 return -EINVAL;
 500         }
 501
 502         qat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;
 503         rte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));
 504         qat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;
 505         cipher_param = (void *)&qat_req->serv_specif_rqpars;
 506         auth_param = (void *)((uint8_t *)cipher_param + sizeof(*cipher_param));
 507
 508         if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_HASH_CIPHER ||
 509                         ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER_HASH) {
 510                 /* AES-GCM or AES-CCM */
 511                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 512                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_64 ||
 513                         (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES128
 514                         && ctx->qat_mode == ICP_QAT_HW_CIPHER_CTR_MODE
 515                         && ctx->qat_hash_alg ==
 516                                         ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC)) {
 517                         do_aead = 1;
 518                 } else {
 519                         do_auth = 1;
 520                         do_cipher = 1;
 521                 }
 522         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_AUTH) {
 523                 do_auth = 1;
 524                 do_cipher = 0;
 525         } else if (ctx->qat_cmd == ICP_QAT_FW_LA_CMD_CIPHER) {
 526                 do_auth = 0;
 527                 do_cipher = 1;
 528         }
 529
 530         if (do_cipher) {
 531
 532                 if (ctx->qat_cipher_alg ==
 533                                          ICP_QAT_HW_CIPHER_ALGO_SNOW_3G_UEA2 ||
 534                         ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_KASUMI ||
 535                         ctx->qat_cipher_alg ==
 536                                 ICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3) {
 537
 538                         if (unlikely(
 539                                 (cipher_param->cipher_length % BYTE_LENGTH != 0)
 540                                  || (cipher_param->cipher_offset
 541                                                         % BYTE_LENGTH != 0))) {
 542                                 PMD_DRV_LOG(ERR,
 543                   "SNOW3G/KASUMI/ZUC in QAT PMD only supports byte aligned values");
 544                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 545                                 return -EINVAL;
 546                         }
 547                         cipher_len = op->sym->cipher.data.length >> 3;
 548                         cipher_ofs = op->sym->cipher.data.offset >> 3;
 549
 550                 } else if (ctx->bpi_ctx) {
 551                         /* DOCSIS - only send complete blocks to device
 552                          * Process any partial block using CFB mode.
 553                          * Even if 0 complete blocks, still send this to device
 554                          * to get into rx queue for post-process and dequeuing
 555                          */
 556                         cipher_len = qat_bpicipher_preprocess(ctx, op);
 557                         cipher_ofs = op->sym->cipher.data.offset;
 558                 } else {
 559                         cipher_len = op->sym->cipher.data.length;
 560                         cipher_ofs = op->sym->cipher.data.offset;
 561                 }
 562
 563                 set_cipher_iv(ctx->cipher_iv.length, ctx->cipher_iv.offset,
 564                                 cipher_param, op, qat_req);
 565                 min_ofs = cipher_ofs;
 566         }
 567
 568         if (do_auth) {
 569
 570                 if (ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2 ||
 571                         ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_KASUMI_F9 ||
 572                         ctx->qat_hash_alg ==
 573                                 ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3) {
 574                         if (unlikely((auth_param->auth_off % BYTE_LENGTH != 0)
 575                                 || (auth_param->auth_len % BYTE_LENGTH != 0))) {
 576                                 PMD_DRV_LOG(ERR,
 577                 "For SNOW3G/KASUMI/ZUC, QAT PMD only supports byte aligned values");
 578                                 op->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;
 579                                 return -EINVAL;
 580                         }
 581                         auth_ofs = op->sym->auth.data.offset >> 3;
 582                         auth_len = op->sym->auth.data.length >> 3;
 583
 584                         auth_param->u1.aad_adr =
 585                                         rte_crypto_op_ctophys_offset(op,
 586                                                         ctx->auth_iv.offset);
 587
 588                 } else if (ctx->qat_hash_alg ==
 589                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 590                                 ctx->qat_hash_alg ==
 591                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
 592                         /* AES-GMAC */
 593                         set_cipher_iv(ctx->auth_iv.length,
 594                                 ctx->auth_iv.offset,
 595                                 cipher_param, op, qat_req);
 596                         auth_ofs = op->sym->auth.data.offset;
 597                         auth_len = op->sym->auth.data.length;
 598
 599                         auth_param->u1.aad_adr = 0;
 600                         auth_param->u2.aad_sz = 0;
 601
 602                         /*
 603                          * If len(iv)==12B fw computes J0
 604                          */
 605                         if (ctx->auth_iv.length == 12) {
 606                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
 607                                         qat_req->comn_hdr.serv_specif_flags,
 608                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 609
 610                         }
 611                 } else {
 612                         auth_ofs = op->sym->auth.data.offset;
 613                         auth_len = op->sym->auth.data.length;
 614
 615                 }
 616                 min_ofs = auth_ofs;
 617
 618                 if (likely(ctx->qat_hash_alg != ICP_QAT_HW_AUTH_ALGO_NULL))
 619                         auth_param->auth_res_addr =
 620                                         op->sym->auth.digest.phys_addr;
 621
 622         }
 623
 624         if (do_aead) {
 625                 /*
 626                  * This address may used for setting AAD physical pointer
 627                  * into IV offset from op
 628                  */
 629                 rte_iova_t aad_phys_addr_aead = op->sym->aead.aad.phys_addr;
 630                 if (ctx->qat_hash_alg ==
 631                                 ICP_QAT_HW_AUTH_ALGO_GALOIS_128 ||
 632                                 ctx->qat_hash_alg ==
 633                                         ICP_QAT_HW_AUTH_ALGO_GALOIS_64) {
 634                         /*
 635                          * If len(iv)==12B fw computes J0
 636                          */
 637                         if (ctx->cipher_iv.length == 12) {
 638                                 ICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(
 639                                         qat_req->comn_hdr.serv_specif_flags,
 640                                         ICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);
 641                         }
 642                         set_cipher_iv(ctx->cipher_iv.length,
 643                                         ctx->cipher_iv.offset,
 644                                         cipher_param, op, qat_req);
 645
 646                 } else if (ctx->qat_hash_alg ==
 647                                 ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC) {
 648
 649                         /* In case of AES-CCM this may point to user selected
 650                          * memory or iv offset in cypto_op
 651                          */
 652                         uint8_t *aad_data = op->sym->aead.aad.data;
 653                         /* This is true AAD length, it not includes 18 bytes of
 654                          * preceding data
 655                          */
 656                         uint8_t aad_ccm_real_len = 0;
 657                         uint8_t aad_len_field_sz = 0;
 658                         uint32_t msg_len_be =
 659                                         rte_bswap32(op->sym->aead.data.length);
 660
 661                         if (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {
 662                                 aad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;
 663                                 aad_ccm_real_len = ctx->aad_len -
 664                                         ICP_QAT_HW_CCM_AAD_B0_LEN -
 665                                         ICP_QAT_HW_CCM_AAD_LEN_INFO;
 666                         } else {
 667                                 /*
 668                                  * aad_len not greater than 18, so no actual aad
 669                                  *  data, then use IV after op for B0 block
 670                                  */
 671                                 aad_data = rte_crypto_op_ctod_offset(op,
 672                                                 uint8_t *,
 673                                                 ctx->cipher_iv.offset);
 674                                 aad_phys_addr_aead =
 675                                                 rte_crypto_op_ctophys_offset(op,
 676                                                         ctx->cipher_iv.offset);
 677                         }
 678
 679                         uint8_t q = ICP_QAT_HW_CCM_NQ_CONST -
 680                                                         ctx->cipher_iv.length;
 681
 682                         aad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(
 683                                                         aad_len_field_sz,
 684                                                         ctx->digest_length, q);
 685
 686                         if (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {
 687                                 memcpy(aad_data + ctx->cipher_iv.length +
 688                                     ICP_QAT_HW_CCM_NONCE_OFFSET +
 689                                     (q - ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),
 690                                     (uint8_t *)&msg_len_be,
 691                                     ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);
 692                         } else {
 693                                 memcpy(aad_data + ctx->cipher_iv.length +
 694                                     ICP_QAT_HW_CCM_NONCE_OFFSET,
 695                                     (uint8_t *)&msg_len_be
 696                                     + (ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE
 697                                     - q), q);
 698                         }
 699
 700                         if (aad_len_field_sz > 0) {
 701                                 *(uint16_t *)&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN]
 702                                                 = rte_bswap16(aad_ccm_real_len);
 703
 704                                 if ((aad_ccm_real_len + aad_len_field_sz)
 705                                                 % ICP_QAT_HW_CCM_AAD_B0_LEN) {
 706                                         uint8_t pad_len = 0;
 707                                         uint8_t pad_idx = 0;
 708
 709                                         pad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -
 710                                         ((aad_ccm_real_len + aad_len_field_sz) %
 711                                                 ICP_QAT_HW_CCM_AAD_B0_LEN);
 712                                         pad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +
 713                                             aad_ccm_real_len + aad_len_field_sz;
 714                                         memset(&aad_data[pad_idx],
 715                                                         0, pad_len);
 716                                 }
 717
 718                         }
 719
 720                         set_cipher_iv_ccm(ctx->cipher_iv.length,
 721                                         ctx->cipher_iv.offset,
 722                                         cipher_param, op, q,
 723                                         aad_len_field_sz);
 724
 725                 }
 726
 727                 cipher_len = op->sym->aead.data.length;
 728                 cipher_ofs = op->sym->aead.data.offset;
 729                 auth_len = op->sym->aead.data.length;
 730                 auth_ofs = op->sym->aead.data.offset;
 731
 732                 auth_param->u1.aad_adr = aad_phys_addr_aead;
 733                 auth_param->auth_res_addr = op->sym->aead.digest.phys_addr;
 734                 min_ofs = op->sym->aead.data.offset;
 735         }
 736
 737         if (op->sym->m_src->next || (op->sym->m_dst && op->sym->m_dst->next))
 738                 do_sgl = 1;
 739
 740         /* adjust for chain case */
 741         if (do_cipher && do_auth)
 742                 min_ofs = cipher_ofs < auth_ofs ? cipher_ofs : auth_ofs;
 743
 744         if (unlikely(min_ofs >= rte_pktmbuf_data_len(op->sym->m_src) && do_sgl))
 745                 min_ofs = 0;
 746
 747         if (unlikely(op->sym->m_dst != NULL)) {
 748                 /* Out-of-place operation (OOP)
 749                  * Don't align DMA start. DMA the minimum data-set
 750                  * so as not to overwrite data in dest buffer
 751                  */
 752                 src_buf_start =
 753                         rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs);
 754                 dst_buf_start =
 755                         rte_pktmbuf_iova_offset(op->sym->m_dst, min_ofs);
 756
 757         } else {
 758                 /* In-place operation
 759                  * Start DMA at nearest aligned address below min_ofs
 760                  */
 761                 src_buf_start =
 762                         rte_pktmbuf_iova_offset(op->sym->m_src, min_ofs)
 763                                                 & QAT_64_BTYE_ALIGN_MASK;
 764
 765                 if (unlikely((rte_pktmbuf_iova(op->sym->m_src) -
 766                                         rte_pktmbuf_headroom(op->sym->m_src))
 767                                                         > src_buf_start)) {
 768                         /* alignment has pushed addr ahead of start of mbuf
 769                          * so revert and take the performance hit
 770                          */
 771                         src_buf_start =
 772                                 rte_pktmbuf_iova_offset(op->sym->m_src,
 773                                                                 min_ofs);
 774                 }
 775                 dst_buf_start = src_buf_start;
 776         }
 777
 778         if (do_cipher || do_aead) {
 779                 cipher_param->cipher_offset =
 780                                 (uint32_t)rte_pktmbuf_iova_offset(
 781                                 op->sym->m_src, cipher_ofs) - src_buf_start;
 782                 cipher_param->cipher_length = cipher_len;
 783         } else {
 784                 cipher_param->cipher_offset = 0;
 785                 cipher_param->cipher_length = 0;
 786         }
 787
 788         if (do_auth || do_aead) {
 789                 auth_param->auth_off = (uint32_t)rte_pktmbuf_iova_offset(
 790                                 op->sym->m_src, auth_ofs) - src_buf_start;
 791                 auth_param->auth_len = auth_len;
 792         } else {
 793                 auth_param->auth_off = 0;
 794                 auth_param->auth_len = 0;
 795         }
 796
 797         qat_req->comn_mid.dst_length =
 798                 qat_req->comn_mid.src_length =
 799                 (cipher_param->cipher_offset + cipher_param->cipher_length)
 800                 > (auth_param->auth_off + auth_param->auth_len) ?
 801                 (cipher_param->cipher_offset + cipher_param->cipher_length)
 802                 : (auth_param->auth_off + auth_param->auth_len);
 803
 804         if (do_sgl) {
 805
 806                 ICP_QAT_FW_COMN_PTR_TYPE_SET(qat_req->comn_hdr.comn_req_flags,
 807                                 QAT_COMN_PTR_TYPE_SGL);
 808                 ret = qat_sgl_fill_array(op->sym->m_src, src_buf_start,
 809                                 &qat_op_cookie->qat_sgl_list_src,
 810                                 qat_req->comn_mid.src_length);
 811                 if (ret) {
 812                         PMD_DRV_LOG(ERR, "QAT PMD Cannot fill sgl array");
 813                         return ret;
 814                 }
 815
 816                 if (likely(op->sym->m_dst == NULL))
 817                         qat_req->comn_mid.dest_data_addr =
 818                                 qat_req->comn_mid.src_data_addr =
 819                                 qat_op_cookie->qat_sgl_src_phys_addr;
 820                 else {
 821                         ret = qat_sgl_fill_array(op->sym->m_dst,
 822                                         dst_buf_start,
 823                                         &qat_op_cookie->qat_sgl_list_dst,
 824                                                 qat_req->comn_mid.dst_length);
 825
 826                         if (ret) {
 827                                 PMD_DRV_LOG(ERR, "QAT PMD Cannot "
 828                                                 "fill sgl array");
 829                                 return ret;
 830                         }
 831
 832                         qat_req->comn_mid.src_data_addr =
 833                                 qat_op_cookie->qat_sgl_src_phys_addr;
 834                         qat_req->comn_mid.dest_data_addr =
 835                                         qat_op_cookie->qat_sgl_dst_phys_addr;
 836                 }
 837         } else {
 838                 qat_req->comn_mid.src_data_addr = src_buf_start;
 839                 qat_req->comn_mid.dest_data_addr = dst_buf_start;
 840         }
 841
 842 #ifdef RTE_LIBRTE_PMD_QAT_DEBUG_TX
 843         rte_hexdump(stdout, "qat_req:", qat_req,
 844                         sizeof(struct icp_qat_fw_la_bulk_req));
 845         rte_hexdump(stdout, "src_data:",
 846                         rte_pktmbuf_mtod(op->sym->m_src, uint8_t*),
 847                         rte_pktmbuf_data_len(op->sym->m_src));
 848         if (do_cipher) {
 849                 uint8_t *cipher_iv_ptr = rte_crypto_op_ctod_offset(op,
 850                                                 uint8_t *,
 851                                                 ctx->cipher_iv.offset);
 852                 rte_hexdump(stdout, "cipher iv:", cipher_iv_ptr,
 853                                 ctx->cipher_iv.length);
 854         }
 855
 856         if (do_auth) {
 857                 if (ctx->auth_iv.length) {
 858                         uint8_t *auth_iv_ptr = rte_crypto_op_ctod_offset(op,
 859                                                         uint8_t *,
 860                                                         ctx->auth_iv.offset);
 861                         rte_hexdump(stdout, "auth iv:", auth_iv_ptr,
 862                                                 ctx->auth_iv.length);
 863                 }
 864                 rte_hexdump(stdout, "digest:", op->sym->auth.digest.data,
 865                                 ctx->digest_length);
 866         }
 867
 868         if (do_aead) {
 869                 rte_hexdump(stdout, "digest:", op->sym->aead.digest.data,
 870                                 ctx->digest_length);
 871                 rte_hexdump(stdout, "aad:", op->sym->aead.aad.data,
 872                                 ctx->aad_len);
 873         }
 874 #endif
 875         return 0;
 876 }
 877
 878 static inline uint32_t adf_modulo(uint32_t data, uint32_t shift)
 879 {
 880         uint32_t div = data >> shift;
 881         uint32_t mult = div << shift;
 882
 883         return data - mult;
 884 }
 885
 886 void qat_sym_stats_get(struct rte_cryptodev *dev,
 887                 struct rte_cryptodev_stats *stats)
 888 {
 889         int i;
 890         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
 891
 892         PMD_INIT_FUNC_TRACE();
 893         if (stats == NULL) {
 894                 PMD_DRV_LOG(ERR, "invalid stats ptr NULL");
 895                 return;
 896         }
 897         for (i = 0; i < dev->data->nb_queue_pairs; i++) {
 898                 if (qp[i] == NULL) {
 899                         PMD_DRV_LOG(DEBUG, "Uninitialised queue pair");
 900                         continue;
 901                 }
 902
 903                 stats->enqueued_count += qp[i]->stats.enqueued_count;
 904                 stats->dequeued_count += qp[i]->stats.dequeued_count;
 905                 stats->enqueue_err_count += qp[i]->stats.enqueue_err_count;
 906                 stats->dequeue_err_count += qp[i]->stats.dequeue_err_count;
 907         }
 908 }
 909
 910 void qat_sym_stats_reset(struct rte_cryptodev *dev)
 911 {
 912         int i;
 913         struct qat_qp **qp = (struct qat_qp **)(dev->data->queue_pairs);
 914
 915         PMD_INIT_FUNC_TRACE();
 916         for (i = 0; i < dev->data->nb_queue_pairs; i++)
 917                 memset(&(qp[i]->stats), 0, sizeof(qp[i]->stats));
 918         PMD_DRV_LOG(DEBUG, "QAT crypto: stats cleared");
 919 }