drivers/crypto/qat/qat_sym.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015-2018 Intel Corporation
   3  */
   4
   5 #ifndef _QAT_SYM_H_
   6 #define _QAT_SYM_H_
   7
   8 #include <rte_cryptodev_pmd.h>
   9 #include <rte_memzone.h>
  10
  11 #include "qat_common.h"
  12 #include "qat_device.h"
  13 #include "qat_crypto_capabilities.h"
  14
  15 /*
  16  * This macro rounds up a number to a be a multiple of
  17  * the alignment when the alignment is a power of 2
  18  */
  19 #define ALIGN_POW2_ROUNDUP(num, align) \
  20         (((num) + (align) - 1) & ~((align) - 1))
  21 #define QAT_64_BTYE_ALIGN_MASK (~0x3f)
  22
  23 #define QAT_CSR_HEAD_WRITE_THRESH 32U
  24 /* number of requests to accumulate before writing head CSR */
  25 #define QAT_CSR_TAIL_WRITE_THRESH 32U
  26 /* number of requests to accumulate before writing tail CSR */
  27 #define QAT_CSR_TAIL_FORCE_WRITE_THRESH 256U
  28 /* number of inflights below which no tail write coalescing should occur */
  29
  30 typedef int (*build_request_t)(void *op,
  31                 uint8_t *req, void *op_cookie,
  32                 enum qat_device_gen qat_dev_gen);
  33 /**< Build a request from an op. */
  34
  35 struct qat_sym_session;
  36
  37 /**
  38  * Structure associated with each queue.
  39  */
  40 struct qat_queue {
  41         char            memz_name[RTE_MEMZONE_NAMESIZE];
  42         void            *base_addr;             /* Base address */
  43         rte_iova_t      base_phys_addr;         /* Queue physical address */
  44         uint32_t        head;                   /* Shadow copy of the head */
  45         uint32_t        tail;                   /* Shadow copy of the tail */
  46         uint32_t        modulo;
  47         uint32_t        msg_size;
  48         uint16_t        max_inflights;
  49         uint32_t        queue_size;
  50         uint8_t         hw_bundle_number;
  51         uint8_t         hw_queue_number;
  52         /* HW queue aka ring offset on bundle */
  53         uint32_t        csr_head;               /* last written head value */
  54         uint32_t        csr_tail;               /* last written tail value */
  55         uint16_t        nb_processed_responses;
  56         /* number of responses processed since last CSR head write */
  57         uint16_t        nb_pending_requests;
  58         /* number of requests pending since last CSR tail write */
  59 };
  60
  61 struct qat_qp {
  62         void                    *mmap_bar_addr;
  63         uint16_t                inflights16;
  64         struct  qat_queue       tx_q;
  65         struct  qat_queue       rx_q;
  66         struct  rte_cryptodev_stats stats;
  67         struct rte_mempool *op_cookie_pool;
  68         void **op_cookies;
  69         uint32_t nb_descriptors;
  70         enum qat_device_gen qat_dev_gen;
  71         build_request_t build_request;
  72 } __rte_cache_aligned;
  73
  74
  75 int
  76 qat_sym_build_request(void *in_op, uint8_t *out_msg,
  77                 void *op_cookie, enum qat_device_gen qat_dev_gen);
  78
  79 void qat_sym_stats_get(struct rte_cryptodev *dev,
  80         struct rte_cryptodev_stats *stats);
  81 void qat_sym_stats_reset(struct rte_cryptodev *dev);
  82
  83 int qat_sym_qp_setup(struct rte_cryptodev *dev, uint16_t queue_pair_id,
  84         const struct rte_cryptodev_qp_conf *rx_conf, int socket_id,
  85         struct rte_mempool *session_pool);
  86 int qat_sym_qp_release(struct rte_cryptodev *dev,
  87         uint16_t queue_pair_id);
  88
  89
  90 uint16_t
  91 qat_sym_pmd_enqueue_op_burst(void *qp, struct rte_crypto_op **ops,
  92                 uint16_t nb_ops);
  93
  94 uint16_t
  95 qat_sym_pmd_dequeue_op_burst(void *qp, struct rte_crypto_op **ops,
  96                 uint16_t nb_ops);
  97
  98 #endif /* _QAT_SYM_H_ */