1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2021 Marvell.
5 #include "cn10k_worker.h"
6 #include "cnxk_eventdev.h"
7 #include "cnxk_worker.h"
9 #define CN10K_SET_EVDEV_DEQ_OP(dev, deq_op, deq_ops) \
10 (deq_op = deq_ops[!!(dev->rx_offloads & NIX_RX_OFFLOAD_VLAN_STRIP_F)] \
11 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_TSTAMP_F)] \
12 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_MARK_UPDATE_F)] \
13 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_CHECKSUM_F)] \
14 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_PTYPE_F)] \
15 [!!(dev->rx_offloads & NIX_RX_OFFLOAD_RSS_F)])
17 #define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
19 enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)] \
20 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)] \
21 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)] \
22 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)] \
23 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_OL3_OL4_CSUM_F)] \
24 [!!(dev->tx_offloads & NIX_TX_OFFLOAD_L3_L4_CSUM_F)])
27 cn10k_sso_gw_mode_wdata(struct cnxk_sso_evdev *dev)
29 uint32_t wdata = BIT(16) | 1;
31 switch (dev->gw_mode) {
32 case CN10K_GW_MODE_NONE:
35 case CN10K_GW_MODE_PREF:
38 case CN10K_GW_MODE_PREF_WFE:
39 wdata |= BIT(20) | BIT(19);
47 cn10k_sso_init_hws_mem(void *arg, uint8_t port_id)
49 struct cnxk_sso_evdev *dev = arg;
50 struct cn10k_sso_hws *ws;
52 /* Allocate event port memory */
53 ws = rte_zmalloc("cn10k_ws",
54 sizeof(struct cn10k_sso_hws) + RTE_CACHE_LINE_SIZE,
57 plt_err("Failed to alloc memory for port=%d", port_id);
61 /* First cache line is reserved for cookie */
62 ws = (struct cn10k_sso_hws *)((uint8_t *)ws + RTE_CACHE_LINE_SIZE);
63 ws->base = roc_sso_hws_base_get(&dev->sso, port_id);
64 ws->tx_base = ws->base;
67 ws->gw_wdata = cn10k_sso_gw_mode_wdata(dev);
68 ws->lmt_base = dev->sso.lmt_base;
74 cn10k_sso_hws_link(void *arg, void *port, uint16_t *map, uint16_t nb_link)
76 struct cnxk_sso_evdev *dev = arg;
77 struct cn10k_sso_hws *ws = port;
79 return roc_sso_hws_link(&dev->sso, ws->hws_id, map, nb_link);
83 cn10k_sso_hws_unlink(void *arg, void *port, uint16_t *map, uint16_t nb_link)
85 struct cnxk_sso_evdev *dev = arg;
86 struct cn10k_sso_hws *ws = port;
88 return roc_sso_hws_unlink(&dev->sso, ws->hws_id, map, nb_link);
92 cn10k_sso_hws_setup(void *arg, void *hws, uintptr_t *grps_base)
94 struct cnxk_sso_evdev *dev = arg;
95 struct cn10k_sso_hws *ws = hws;
98 rte_memcpy(ws->grps_base, grps_base,
99 sizeof(uintptr_t) * CNXK_SSO_MAX_HWGRP);
100 ws->fc_mem = dev->fc_mem;
101 ws->xaq_lmt = dev->xaq_lmt;
103 /* Set get_work timeout for HWS */
104 val = NSEC2USEC(dev->deq_tmo_ns) - 1;
105 plt_write64(val, ws->base + SSOW_LF_GWS_NW_TIM);
109 cn10k_sso_hws_release(void *arg, void *hws)
111 struct cnxk_sso_evdev *dev = arg;
112 struct cn10k_sso_hws *ws = hws;
115 for (i = 0; i < dev->nb_event_queues; i++)
116 roc_sso_hws_unlink(&dev->sso, ws->hws_id, (uint16_t *)&i, 1);
117 memset(ws, 0, sizeof(*ws));
121 cn10k_sso_hws_flush_events(void *hws, uint8_t queue_id, uintptr_t base,
122 cnxk_handle_event_t fn, void *arg)
124 struct cn10k_sso_hws *ws = hws;
125 uint64_t cq_ds_cnt = 1;
131 plt_write64(0, base + SSO_LF_GGRP_QCTL);
133 req = queue_id; /* GGRP ID */
134 req |= BIT_ULL(18); /* Grouped */
135 req |= BIT_ULL(16); /* WAIT */
137 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
138 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
139 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
140 cq_ds_cnt &= 0x3FFF3FFF0000;
142 while (aq_cnt || cq_ds_cnt || ds_cnt) {
143 plt_write64(req, ws->base + SSOW_LF_GWS_OP_GET_WORK0);
144 cn10k_sso_hws_get_work_empty(ws, &ev);
145 if (fn != NULL && ev.u64 != 0)
147 if (ev.sched_type != SSO_TT_EMPTY)
148 cnxk_sso_hws_swtag_flush(
149 ws->base + SSOW_LF_GWS_WQE0,
150 ws->base + SSOW_LF_GWS_OP_SWTAG_FLUSH);
152 val = plt_read64(ws->base + SSOW_LF_GWS_PENDSTATE);
153 } while (val & BIT_ULL(56));
154 aq_cnt = plt_read64(base + SSO_LF_GGRP_AQ_CNT);
155 ds_cnt = plt_read64(base + SSO_LF_GGRP_MISC_CNT);
156 cq_ds_cnt = plt_read64(base + SSO_LF_GGRP_INT_CNT);
157 /* Extract cq and ds count */
158 cq_ds_cnt &= 0x3FFF3FFF0000;
161 plt_write64(0, ws->base + SSOW_LF_GWS_OP_GWC_INVAL);
166 cn10k_sso_hws_reset(void *arg, void *hws)
168 struct cnxk_sso_evdev *dev = arg;
169 struct cn10k_sso_hws *ws = hws;
170 uintptr_t base = ws->base;
178 /* Wait till getwork/swtp/waitw/desched completes. */
180 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
181 } while (pend_state & (BIT_ULL(63) | BIT_ULL(62) | BIT_ULL(58) |
182 BIT_ULL(56) | BIT_ULL(54)));
183 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
184 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
185 if (pend_tt == SSO_TT_ATOMIC || pend_tt == SSO_TT_ORDERED)
186 cnxk_sso_hws_swtag_untag(base +
187 SSOW_LF_GWS_OP_SWTAG_UNTAG);
188 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
191 /* Wait for desched to complete. */
193 pend_state = plt_read64(base + SSOW_LF_GWS_PENDSTATE);
194 } while (pend_state & BIT_ULL(58));
196 switch (dev->gw_mode) {
197 case CN10K_GW_MODE_PREF:
198 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) & BIT_ULL(63))
201 case CN10K_GW_MODE_PREF_WFE:
202 while (plt_read64(base + SSOW_LF_GWS_PRF_WQE0) &
203 SSOW_LF_GWS_TAG_PEND_GET_WORK_BIT)
205 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
207 case CN10K_GW_MODE_NONE:
212 if (CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_PRF_WQE0)) !=
214 plt_write64(BIT_ULL(16) | 1,
215 ws->base + SSOW_LF_GWS_OP_GET_WORK0);
217 roc_load_pair(gw.u64[0], gw.u64[1],
218 ws->base + SSOW_LF_GWS_WQE0);
219 } while (gw.u64[0] & BIT_ULL(63));
220 pend_tt = CNXK_TT_FROM_TAG(plt_read64(base + SSOW_LF_GWS_WQE0));
221 if (pend_tt != SSO_TT_EMPTY) { /* Work was pending */
222 if (pend_tt == SSO_TT_ATOMIC ||
223 pend_tt == SSO_TT_ORDERED)
224 cnxk_sso_hws_swtag_untag(
225 base + SSOW_LF_GWS_OP_SWTAG_UNTAG);
226 plt_write64(0, base + SSOW_LF_GWS_OP_DESCHED);
230 plt_write64(0, base + SSOW_LF_GWS_OP_GWC_INVAL);
235 cn10k_sso_set_rsrc(void *arg)
237 struct cnxk_sso_evdev *dev = arg;
239 dev->max_event_ports = dev->sso.max_hws;
240 dev->max_event_queues =
241 dev->sso.max_hwgrp > RTE_EVENT_MAX_QUEUES_PER_DEV ?
242 RTE_EVENT_MAX_QUEUES_PER_DEV :
247 cn10k_sso_rsrc_init(void *arg, uint8_t hws, uint8_t hwgrp)
249 struct cnxk_sso_evdev *dev = arg;
251 return roc_sso_rsrc_init(&dev->sso, hws, hwgrp);
255 cn10k_sso_updt_tx_adptr_data(const struct rte_eventdev *event_dev)
257 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
260 if (dev->tx_adptr_data == NULL)
263 for (i = 0; i < dev->nb_event_ports; i++) {
264 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
267 ws_cookie = cnxk_sso_hws_get_cookie(ws);
268 ws_cookie = rte_realloc_socket(
270 sizeof(struct cnxk_sso_hws_cookie) +
271 sizeof(struct cn10k_sso_hws) +
272 (sizeof(uint64_t) * (dev->max_port_id + 1) *
273 RTE_MAX_QUEUES_PER_PORT),
274 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);
275 if (ws_cookie == NULL)
277 ws = RTE_PTR_ADD(ws_cookie, sizeof(struct cnxk_sso_hws_cookie));
278 memcpy(&ws->tx_adptr_data, dev->tx_adptr_data,
279 sizeof(uint64_t) * (dev->max_port_id + 1) *
280 RTE_MAX_QUEUES_PER_PORT);
281 event_dev->data->ports[i] = ws;
288 cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
290 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
291 const event_dequeue_t sso_hws_deq[2][2][2][2][2][2] = {
292 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
293 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_##name,
294 NIX_RX_FASTPATH_MODES
298 const event_dequeue_burst_t sso_hws_deq_burst[2][2][2][2][2][2] = {
299 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
300 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_burst_##name,
301 NIX_RX_FASTPATH_MODES
305 const event_dequeue_t sso_hws_deq_tmo[2][2][2][2][2][2] = {
306 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
307 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_##name,
308 NIX_RX_FASTPATH_MODES
312 const event_dequeue_burst_t sso_hws_deq_tmo_burst[2][2][2][2][2][2] = {
313 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
314 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_burst_##name,
315 NIX_RX_FASTPATH_MODES
319 const event_dequeue_t sso_hws_deq_seg[2][2][2][2][2][2] = {
320 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
321 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_##name,
322 NIX_RX_FASTPATH_MODES
326 const event_dequeue_burst_t sso_hws_deq_seg_burst[2][2][2][2][2][2] = {
327 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
328 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_seg_burst_##name,
329 NIX_RX_FASTPATH_MODES
333 const event_dequeue_t sso_hws_deq_tmo_seg[2][2][2][2][2][2] = {
334 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
335 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_##name,
336 NIX_RX_FASTPATH_MODES
340 const event_dequeue_burst_t
341 sso_hws_deq_tmo_seg_burst[2][2][2][2][2][2] = {
342 #define R(name, f5, f4, f3, f2, f1, f0, flags) \
343 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_deq_tmo_seg_burst_##name,
344 NIX_RX_FASTPATH_MODES
349 const event_tx_adapter_enqueue
350 sso_hws_tx_adptr_enq[2][2][2][2][2][2] = {
351 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
352 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_##name,
353 NIX_TX_FASTPATH_MODES
357 const event_tx_adapter_enqueue
358 sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2] = {
359 #define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
360 [f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
361 NIX_TX_FASTPATH_MODES
365 event_dev->enqueue = cn10k_sso_hws_enq;
366 event_dev->enqueue_burst = cn10k_sso_hws_enq_burst;
367 event_dev->enqueue_new_burst = cn10k_sso_hws_enq_new_burst;
368 event_dev->enqueue_forward_burst = cn10k_sso_hws_enq_fwd_burst;
369 if (dev->rx_offloads & NIX_RX_MULTI_SEG_F) {
370 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
372 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
373 sso_hws_deq_seg_burst);
374 if (dev->is_timeout_deq) {
375 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
376 sso_hws_deq_tmo_seg);
377 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
378 sso_hws_deq_tmo_seg_burst);
381 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue, sso_hws_deq);
382 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
384 if (dev->is_timeout_deq) {
385 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue,
387 CN10K_SET_EVDEV_DEQ_OP(dev, event_dev->dequeue_burst,
388 sso_hws_deq_tmo_burst);
392 if (dev->tx_offloads & NIX_TX_MULTI_SEG_F)
393 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
394 sso_hws_tx_adptr_enq_seg);
396 CN10K_SET_EVDEV_ENQ_OP(dev, event_dev->txa_enqueue,
397 sso_hws_tx_adptr_enq);
399 event_dev->txa_enqueue_same_dest = event_dev->txa_enqueue;
403 cn10k_sso_info_get(struct rte_eventdev *event_dev,
404 struct rte_event_dev_info *dev_info)
406 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
408 dev_info->driver_name = RTE_STR(EVENTDEV_NAME_CN10K_PMD);
409 cnxk_sso_info_get(dev, dev_info);
413 cn10k_sso_dev_configure(const struct rte_eventdev *event_dev)
415 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
418 rc = cnxk_sso_dev_validate(event_dev);
420 plt_err("Invalid event device configuration");
424 roc_sso_rsrc_fini(&dev->sso);
426 rc = cn10k_sso_rsrc_init(dev, dev->nb_event_ports,
427 dev->nb_event_queues);
429 plt_err("Failed to initialize SSO resources");
433 rc = cnxk_sso_xaq_allocate(dev);
437 rc = cnxk_setup_event_ports(event_dev, cn10k_sso_init_hws_mem,
438 cn10k_sso_hws_setup);
442 /* Restore any prior port-queue mapping. */
443 cnxk_sso_restore_links(event_dev, cn10k_sso_hws_link);
450 roc_sso_rsrc_fini(&dev->sso);
451 dev->nb_event_ports = 0;
456 cn10k_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
457 const struct rte_event_port_conf *port_conf)
460 RTE_SET_USED(port_conf);
461 return cnxk_sso_port_setup(event_dev, port_id, cn10k_sso_hws_setup);
465 cn10k_sso_port_release(void *port)
467 struct cnxk_sso_hws_cookie *gws_cookie = cnxk_sso_hws_get_cookie(port);
468 struct cnxk_sso_evdev *dev;
473 dev = cnxk_sso_pmd_priv(gws_cookie->event_dev);
474 if (!gws_cookie->configured)
477 cn10k_sso_hws_release(dev, port);
478 memset(gws_cookie, 0, sizeof(*gws_cookie));
480 rte_free(gws_cookie);
484 cn10k_sso_port_link(struct rte_eventdev *event_dev, void *port,
485 const uint8_t queues[], const uint8_t priorities[],
488 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
489 uint16_t hwgrp_ids[nb_links];
492 RTE_SET_USED(priorities);
493 for (link = 0; link < nb_links; link++)
494 hwgrp_ids[link] = queues[link];
495 nb_links = cn10k_sso_hws_link(dev, port, hwgrp_ids, nb_links);
497 return (int)nb_links;
501 cn10k_sso_port_unlink(struct rte_eventdev *event_dev, void *port,
502 uint8_t queues[], uint16_t nb_unlinks)
504 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
505 uint16_t hwgrp_ids[nb_unlinks];
508 for (unlink = 0; unlink < nb_unlinks; unlink++)
509 hwgrp_ids[unlink] = queues[unlink];
510 nb_unlinks = cn10k_sso_hws_unlink(dev, port, hwgrp_ids, nb_unlinks);
512 return (int)nb_unlinks;
516 cn10k_sso_start(struct rte_eventdev *event_dev)
520 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
524 rc = cnxk_sso_start(event_dev, cn10k_sso_hws_reset,
525 cn10k_sso_hws_flush_events);
528 cn10k_sso_fp_fns_set(event_dev);
534 cn10k_sso_stop(struct rte_eventdev *event_dev)
536 cnxk_sso_stop(event_dev, cn10k_sso_hws_reset,
537 cn10k_sso_hws_flush_events);
541 cn10k_sso_close(struct rte_eventdev *event_dev)
543 return cnxk_sso_close(event_dev, cn10k_sso_hws_unlink);
547 cn10k_sso_selftest(void)
549 return cnxk_sso_selftest(RTE_STR(event_cn10k));
553 cn10k_sso_rx_adapter_caps_get(const struct rte_eventdev *event_dev,
554 const struct rte_eth_dev *eth_dev, uint32_t *caps)
558 RTE_SET_USED(event_dev);
559 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 9);
561 *caps = RTE_EVENT_ETH_RX_ADAPTER_SW_CAP;
563 *caps = RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT |
564 RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ |
565 RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID |
566 RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR;
572 cn10k_sso_set_priv_mem(const struct rte_eventdev *event_dev, void *lookup_mem,
575 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
578 for (i = 0; i < dev->nb_event_ports; i++) {
579 struct cn10k_sso_hws *ws = event_dev->data->ports[i];
580 ws->lookup_mem = lookup_mem;
581 ws->tstamp = tstmp_info;
586 cn10k_sso_rx_adapter_queue_add(
587 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
589 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf)
591 struct cn10k_eth_rxq *rxq;
596 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
600 rc = cnxk_sso_rx_adapter_queue_add(event_dev, eth_dev, rx_queue_id,
604 rxq = eth_dev->data->rx_queues[0];
605 lookup_mem = rxq->lookup_mem;
606 tstmp_info = rxq->tstamp;
607 cn10k_sso_set_priv_mem(event_dev, lookup_mem, tstmp_info);
608 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
614 cn10k_sso_rx_adapter_queue_del(const struct rte_eventdev *event_dev,
615 const struct rte_eth_dev *eth_dev,
620 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
624 return cnxk_sso_rx_adapter_queue_del(event_dev, eth_dev, rx_queue_id);
628 cn10k_sso_rx_adapter_vector_limits(
629 const struct rte_eventdev *dev, const struct rte_eth_dev *eth_dev,
630 struct rte_event_eth_rx_adapter_vector_limits *limits)
632 struct cnxk_eth_dev *cnxk_eth_dev;
636 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
640 cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
641 limits->log2_sz = true;
642 limits->min_sz = 1 << ROC_NIX_VWQE_MIN_SIZE_LOG2;
643 limits->max_sz = 1 << ROC_NIX_VWQE_MAX_SIZE_LOG2;
644 limits->min_timeout_ns =
645 (roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100;
646 limits->max_timeout_ns = BITMASK_ULL(8, 0) * limits->min_timeout_ns;
652 cnxk_sso_rx_adapter_vwqe_enable(struct cnxk_eth_dev *cnxk_eth_dev,
653 uint16_t port_id, uint16_t rq_id, uint16_t sz,
654 uint64_t tmo_ns, struct rte_mempool *vmp)
656 struct roc_nix_rq *rq;
658 rq = &cnxk_eth_dev->rqs[rq_id];
662 if (rq->flow_tag_width == 0)
666 rq->vwqe_first_skip = 0;
667 rq->vwqe_aura_handle = roc_npa_aura_handle_to_aura(vmp->pool_id);
668 rq->vwqe_max_sz_exp = rte_log2_u32(sz);
671 ((roc_nix_get_vwqe_interval(&cnxk_eth_dev->nix) + 1) * 100);
672 rq->tag_mask = (port_id & 0xF) << 20;
674 (((port_id >> 4) & 0xF) | (RTE_EVENT_TYPE_ETHDEV_VECTOR << 4))
677 return roc_nix_rq_modify(&cnxk_eth_dev->nix, rq, 0);
681 cn10k_sso_rx_adapter_vector_config(
682 const struct rte_eventdev *event_dev, const struct rte_eth_dev *eth_dev,
684 const struct rte_event_eth_rx_adapter_event_vector_config *config)
686 struct cnxk_eth_dev *cnxk_eth_dev;
687 struct cnxk_sso_evdev *dev;
690 rc = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
694 dev = cnxk_sso_pmd_priv(event_dev);
695 cnxk_eth_dev = cnxk_eth_pmd_priv(eth_dev);
696 if (rx_queue_id < 0) {
697 for (i = 0; i < eth_dev->data->nb_rx_queues; i++) {
698 cnxk_sso_updt_xae_cnt(dev, config->vector_mp,
699 RTE_EVENT_TYPE_ETHDEV_VECTOR);
700 rc = cnxk_sso_xae_reconfigure(
701 (struct rte_eventdev *)(uintptr_t)event_dev);
702 rc = cnxk_sso_rx_adapter_vwqe_enable(
703 cnxk_eth_dev, eth_dev->data->port_id, i,
704 config->vector_sz, config->vector_timeout_ns,
711 cnxk_sso_updt_xae_cnt(dev, config->vector_mp,
712 RTE_EVENT_TYPE_ETHDEV_VECTOR);
713 rc = cnxk_sso_xae_reconfigure(
714 (struct rte_eventdev *)(uintptr_t)event_dev);
715 rc = cnxk_sso_rx_adapter_vwqe_enable(
716 cnxk_eth_dev, eth_dev->data->port_id, rx_queue_id,
717 config->vector_sz, config->vector_timeout_ns,
727 cn10k_sso_tx_adapter_caps_get(const struct rte_eventdev *dev,
728 const struct rte_eth_dev *eth_dev, uint32_t *caps)
733 ret = strncmp(eth_dev->device->driver->name, "net_cn10k", 8);
737 *caps = RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT |
738 RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR;
744 cn10k_sso_tx_adapter_queue_add(uint8_t id, const struct rte_eventdev *event_dev,
745 const struct rte_eth_dev *eth_dev,
751 rc = cnxk_sso_tx_adapter_queue_add(event_dev, eth_dev, tx_queue_id);
754 rc = cn10k_sso_updt_tx_adptr_data(event_dev);
757 cn10k_sso_fp_fns_set((struct rte_eventdev *)(uintptr_t)event_dev);
763 cn10k_sso_tx_adapter_queue_del(uint8_t id, const struct rte_eventdev *event_dev,
764 const struct rte_eth_dev *eth_dev,
770 rc = cnxk_sso_tx_adapter_queue_del(event_dev, eth_dev, tx_queue_id);
773 return cn10k_sso_updt_tx_adptr_data(event_dev);
776 static struct rte_eventdev_ops cn10k_sso_dev_ops = {
777 .dev_infos_get = cn10k_sso_info_get,
778 .dev_configure = cn10k_sso_dev_configure,
779 .queue_def_conf = cnxk_sso_queue_def_conf,
780 .queue_setup = cnxk_sso_queue_setup,
781 .queue_release = cnxk_sso_queue_release,
782 .port_def_conf = cnxk_sso_port_def_conf,
783 .port_setup = cn10k_sso_port_setup,
784 .port_release = cn10k_sso_port_release,
785 .port_link = cn10k_sso_port_link,
786 .port_unlink = cn10k_sso_port_unlink,
787 .timeout_ticks = cnxk_sso_timeout_ticks,
789 .eth_rx_adapter_caps_get = cn10k_sso_rx_adapter_caps_get,
790 .eth_rx_adapter_queue_add = cn10k_sso_rx_adapter_queue_add,
791 .eth_rx_adapter_queue_del = cn10k_sso_rx_adapter_queue_del,
792 .eth_rx_adapter_start = cnxk_sso_rx_adapter_start,
793 .eth_rx_adapter_stop = cnxk_sso_rx_adapter_stop,
795 .eth_rx_adapter_vector_limits_get = cn10k_sso_rx_adapter_vector_limits,
796 .eth_rx_adapter_event_vector_config =
797 cn10k_sso_rx_adapter_vector_config,
799 .eth_tx_adapter_caps_get = cn10k_sso_tx_adapter_caps_get,
800 .eth_tx_adapter_queue_add = cn10k_sso_tx_adapter_queue_add,
801 .eth_tx_adapter_queue_del = cn10k_sso_tx_adapter_queue_del,
803 .timer_adapter_caps_get = cnxk_tim_caps_get,
805 .dump = cnxk_sso_dump,
806 .dev_start = cn10k_sso_start,
807 .dev_stop = cn10k_sso_stop,
808 .dev_close = cn10k_sso_close,
809 .dev_selftest = cn10k_sso_selftest,
813 cn10k_sso_init(struct rte_eventdev *event_dev)
815 struct cnxk_sso_evdev *dev = cnxk_sso_pmd_priv(event_dev);
818 if (RTE_CACHE_LINE_SIZE != 64) {
819 plt_err("Driver not compiled for CN10K");
825 plt_err("Failed to initialize platform model");
829 event_dev->dev_ops = &cn10k_sso_dev_ops;
830 /* For secondary processes, the primary has done all the work */
831 if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
832 cn10k_sso_fp_fns_set(event_dev);
836 rc = cnxk_sso_init(event_dev);
840 cn10k_sso_set_rsrc(cnxk_sso_pmd_priv(event_dev));
841 if (!dev->max_event_ports || !dev->max_event_queues) {
842 plt_err("Not enough eventdev resource queues=%d ports=%d",
843 dev->max_event_queues, dev->max_event_ports);
844 cnxk_sso_fini(event_dev);
848 plt_sso_dbg("Initializing %s max_queues=%d max_ports=%d",
849 event_dev->data->name, dev->max_event_queues,
850 dev->max_event_ports);
856 cn10k_sso_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
858 return rte_event_pmd_pci_probe(pci_drv, pci_dev,
859 sizeof(struct cnxk_sso_evdev),
863 static const struct rte_pci_id cn10k_pci_sso_map[] = {
864 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
865 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_PF),
866 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KA, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
867 CNXK_PCI_ID(PCI_SUBSYSTEM_DEVID_CN10KAS, PCI_DEVID_CNXK_RVU_SSO_TIM_VF),
873 static struct rte_pci_driver cn10k_pci_sso = {
874 .id_table = cn10k_pci_sso_map,
875 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
876 .probe = cn10k_sso_probe,
877 .remove = cnxk_sso_remove,
880 RTE_PMD_REGISTER_PCI(event_cn10k, cn10k_pci_sso);
881 RTE_PMD_REGISTER_PCI_TABLE(event_cn10k, cn10k_pci_sso_map);
882 RTE_PMD_REGISTER_KMOD_DEP(event_cn10k, "vfio-pci");
883 RTE_PMD_REGISTER_PARAM_STRING(event_cn10k, CNXK_SSO_XAE_CNT "=<int>"
884 CNXK_SSO_GGRP_QOS "=<string>"
885 CNXK_SSO_FORCE_BP "=1"
886 CN10K_SSO_GW_MODE "=<int>"
887 CNXK_TIM_DISABLE_NPA "=1"
888 CNXK_TIM_CHNK_SLOTS "=<int>"
889 CNXK_TIM_RINGS_LMT "=<int>"
890 CNXK_TIM_STATS_ENA "=1");