drivers/event/cnxk/cnxk_eventdev.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #ifndef __CNXK_EVENTDEV_H__
   6 #define __CNXK_EVENTDEV_H__
   7
   8 #include <rte_devargs.h>
   9 #include <rte_kvargs.h>
  10 #include <rte_mbuf_pool_ops.h>
  11 #include <rte_pci.h>
  12
  13 #include <eventdev_pmd_pci.h>
  14
  15 #include "roc_api.h"
  16
  17 #define CNXK_SSO_XAE_CNT   "xae_cnt"
  18 #define CNXK_SSO_GGRP_QOS  "qos"
  19 #define CN9K_SSO_SINGLE_WS "single_ws"
  20 #define CN10K_SSO_GW_MODE  "gw_mode"
  21
  22 #define NSEC2USEC(__ns)         ((__ns) / 1E3)
  23 #define USEC2NSEC(__us)         ((__us)*1E3)
  24 #define NSEC2TICK(__ns, __freq) (((__ns) * (__freq)) / 1E9)
  25
  26 #define CNXK_SSO_MAX_HWGRP     (RTE_EVENT_MAX_QUEUES_PER_DEV + 1)
  27 #define CNXK_SSO_FC_NAME       "cnxk_evdev_xaq_fc"
  28 #define CNXK_SSO_MZ_NAME       "cnxk_evdev_mz"
  29 #define CNXK_SSO_XAQ_CACHE_CNT (0x7)
  30 #define CNXK_SSO_XAQ_SLACK     (8)
  31
  32 #define CN10K_GW_MODE_NONE     0
  33 #define CN10K_GW_MODE_PREF     1
  34 #define CN10K_GW_MODE_PREF_WFE 2
  35
  36 typedef void *(*cnxk_sso_init_hws_mem_t)(void *dev, uint8_t port_id);
  37 typedef void (*cnxk_sso_hws_setup_t)(void *dev, void *ws, uintptr_t *grp_base);
  38 typedef void (*cnxk_sso_hws_release_t)(void *dev, void *ws);
  39 typedef int (*cnxk_sso_link_t)(void *dev, void *ws, uint16_t *map,
  40                                uint16_t nb_link);
  41
  42 struct cnxk_sso_qos {
  43         uint16_t queue;
  44         uint8_t xaq_prcnt;
  45         uint8_t taq_prcnt;
  46         uint8_t iaq_prcnt;
  47 };
  48
  49 struct cnxk_sso_evdev {
  50         struct roc_sso sso;
  51         uint8_t max_event_queues;
  52         uint8_t max_event_ports;
  53         uint8_t is_timeout_deq;
  54         uint8_t nb_event_queues;
  55         uint8_t nb_event_ports;
  56         uint8_t configured;
  57         uint32_t deq_tmo_ns;
  58         uint32_t min_dequeue_timeout_ns;
  59         uint32_t max_dequeue_timeout_ns;
  60         int32_t max_num_events;
  61         uint64_t *fc_mem;
  62         uint64_t xaq_lmt;
  63         uint64_t nb_xaq_cfg;
  64         rte_iova_t fc_iova;
  65         struct rte_mempool *xaq_pool;
  66         /* Dev args */
  67         uint32_t xae_cnt;
  68         uint8_t qos_queue_cnt;
  69         struct cnxk_sso_qos *qos_parse_data;
  70         /* CN9K */
  71         uint8_t dual_ws;
  72         /* CN10K */
  73         uint8_t gw_mode;
  74 } __rte_cache_aligned;
  75
  76 /* CN10K HWS ops */
  77 #define CN10K_SSO_HWS_OPS                                                      \
  78         uintptr_t swtag_desched_op;                                            \
  79         uintptr_t swtag_flush_op;                                              \
  80         uintptr_t swtag_untag_op;                                              \
  81         uintptr_t swtag_norm_op;                                               \
  82         uintptr_t updt_wqe_op;                                                 \
  83         uintptr_t tag_wqe_op;                                                  \
  84         uintptr_t getwrk_op
  85
  86 struct cn10k_sso_hws {
  87         /* Get Work Fastpath data */
  88         CN10K_SSO_HWS_OPS;
  89         uint32_t gw_wdata;
  90         uint8_t swtag_req;
  91         uint8_t hws_id;
  92         /* Add Work Fastpath data */
  93         uint64_t xaq_lmt __rte_cache_aligned;
  94         uint64_t *fc_mem;
  95         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
  96         uint64_t base;
  97         uintptr_t lmt_base;
  98 } __rte_cache_aligned;
  99
 100 /* CN9K HWS ops */
 101 #define CN9K_SSO_HWS_OPS                                                       \
 102         uintptr_t swtag_desched_op;                                            \
 103         uintptr_t swtag_flush_op;                                              \
 104         uintptr_t swtag_norm_op;                                               \
 105         uintptr_t getwrk_op;                                                   \
 106         uintptr_t tag_op;                                                      \
 107         uintptr_t wqp_op
 108
 109 /* Event port a.k.a GWS */
 110 struct cn9k_sso_hws {
 111         /* Get Work Fastpath data */
 112         CN9K_SSO_HWS_OPS;
 113         uint8_t swtag_req;
 114         uint8_t hws_id;
 115         /* Add Work Fastpath data */
 116         uint64_t xaq_lmt __rte_cache_aligned;
 117         uint64_t *fc_mem;
 118         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 119         uint64_t base;
 120 } __rte_cache_aligned;
 121
 122 struct cn9k_sso_hws_state {
 123         CN9K_SSO_HWS_OPS;
 124 };
 125
 126 struct cn9k_sso_hws_dual {
 127         /* Get Work Fastpath data */
 128         struct cn9k_sso_hws_state ws_state[2]; /* Ping and Pong */
 129         uint8_t swtag_req;
 130         uint8_t vws; /* Ping pong bit */
 131         uint8_t hws_id;
 132         /* Add Work Fastpath data */
 133         uint64_t xaq_lmt __rte_cache_aligned;
 134         uint64_t *fc_mem;
 135         uintptr_t grps_base[CNXK_SSO_MAX_HWGRP];
 136         uint64_t base[2];
 137 } __rte_cache_aligned;
 138
 139 struct cnxk_sso_hws_cookie {
 140         const struct rte_eventdev *event_dev;
 141         bool configured;
 142 } __rte_cache_aligned;
 143
 144 static inline int
 145 parse_kvargs_value(const char *key, const char *value, void *opaque)
 146 {
 147         RTE_SET_USED(key);
 148
 149         *(uint32_t *)opaque = (uint32_t)atoi(value);
 150         return 0;
 151 }
 152
 153 static inline struct cnxk_sso_evdev *
 154 cnxk_sso_pmd_priv(const struct rte_eventdev *event_dev)
 155 {
 156         return event_dev->data->dev_private;
 157 }
 158
 159 static inline struct cnxk_sso_hws_cookie *
 160 cnxk_sso_hws_get_cookie(void *ws)
 161 {
 162         return RTE_PTR_SUB(ws, sizeof(struct cnxk_sso_hws_cookie));
 163 }
 164
 165 /* Configuration functions */
 166 int cnxk_sso_xaq_allocate(struct cnxk_sso_evdev *dev);
 167
 168 /* Common ops API. */
 169 int cnxk_sso_init(struct rte_eventdev *event_dev);
 170 int cnxk_sso_fini(struct rte_eventdev *event_dev);
 171 int cnxk_sso_remove(struct rte_pci_device *pci_dev);
 172 void cnxk_sso_info_get(struct cnxk_sso_evdev *dev,
 173                        struct rte_event_dev_info *dev_info);
 174 int cnxk_sso_dev_validate(const struct rte_eventdev *event_dev);
 175 int cnxk_setup_event_ports(const struct rte_eventdev *event_dev,
 176                            cnxk_sso_init_hws_mem_t init_hws_mem,
 177                            cnxk_sso_hws_setup_t hws_setup);
 178 void cnxk_sso_restore_links(const struct rte_eventdev *event_dev,
 179                             cnxk_sso_link_t link_fn);
 180 void cnxk_sso_queue_def_conf(struct rte_eventdev *event_dev, uint8_t queue_id,
 181                              struct rte_event_queue_conf *queue_conf);
 182 int cnxk_sso_queue_setup(struct rte_eventdev *event_dev, uint8_t queue_id,
 183                          const struct rte_event_queue_conf *queue_conf);
 184 void cnxk_sso_queue_release(struct rte_eventdev *event_dev, uint8_t queue_id);
 185 void cnxk_sso_port_def_conf(struct rte_eventdev *event_dev, uint8_t port_id,
 186                             struct rte_event_port_conf *port_conf);
 187 int cnxk_sso_port_setup(struct rte_eventdev *event_dev, uint8_t port_id,
 188                         cnxk_sso_hws_setup_t hws_setup_fn);
 189 int cnxk_sso_timeout_ticks(struct rte_eventdev *event_dev, uint64_t ns,
 190                            uint64_t *tmo_ticks);
 191
 192 #endif /* __CNXK_EVENTDEV_H__ */