drivers/event/cnxk/cnxk_tim_evdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(C) 2021 Marvell.
   3  */
   4
   5 #include "cnxk_eventdev.h"
   6 #include "cnxk_tim_evdev.h"
   7
   8 static struct rte_event_timer_adapter_ops cnxk_tim_ops;
   9
  10 static int
  11 cnxk_tim_chnk_pool_create(struct cnxk_tim_ring *tim_ring,
  12                           struct rte_event_timer_adapter_conf *rcfg)
  13 {
  14         unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
  15         unsigned int mp_flags = 0;
  16         char pool_name[25];
  17         int rc;
  18
  19         cache_sz /= rte_lcore_count();
  20         /* Create chunk pool. */
  21         if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
  22                 mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
  23                 plt_tim_dbg("Using single producer mode");
  24                 tim_ring->prod_type_sp = true;
  25         }
  26
  27         snprintf(pool_name, sizeof(pool_name), "cnxk_tim_chunk_pool%d",
  28                  tim_ring->ring_id);
  29
  30         if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
  31                 cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
  32         cache_sz = cache_sz != 0 ? cache_sz : 2;
  33         tim_ring->nb_chunks += (cache_sz * rte_lcore_count());
  34         if (!tim_ring->disable_npa) {
  35                 tim_ring->chunk_pool = rte_mempool_create_empty(
  36                         pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
  37                         cache_sz, 0, rte_socket_id(), mp_flags);
  38
  39                 if (tim_ring->chunk_pool == NULL) {
  40                         plt_err("Unable to create chunkpool.");
  41                         return -ENOMEM;
  42                 }
  43
  44                 rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
  45                                                 rte_mbuf_platform_mempool_ops(),
  46                                                 NULL);
  47                 if (rc < 0) {
  48                         plt_err("Unable to set chunkpool ops");
  49                         goto free;
  50                 }
  51
  52                 rc = rte_mempool_populate_default(tim_ring->chunk_pool);
  53                 if (rc < 0) {
  54                         plt_err("Unable to set populate chunkpool.");
  55                         goto free;
  56                 }
  57                 tim_ring->aura = roc_npa_aura_handle_to_aura(
  58                         tim_ring->chunk_pool->pool_id);
  59                 tim_ring->ena_dfb = 0;
  60         } else {
  61                 tim_ring->chunk_pool = rte_mempool_create(
  62                         pool_name, tim_ring->nb_chunks, tim_ring->chunk_sz,
  63                         cache_sz, 0, NULL, NULL, NULL, NULL, rte_socket_id(),
  64                         mp_flags);
  65                 if (tim_ring->chunk_pool == NULL) {
  66                         plt_err("Unable to create chunkpool.");
  67                         return -ENOMEM;
  68                 }
  69                 tim_ring->ena_dfb = 1;
  70         }
  71
  72         return 0;
  73
  74 free:
  75         rte_mempool_free(tim_ring->chunk_pool);
  76         return rc;
  77 }
  78
  79 static void
  80 cnxk_tim_set_fp_ops(struct cnxk_tim_ring *tim_ring)
  81 {
  82         uint8_t prod_flag = !tim_ring->prod_type_sp;
  83
  84         /* [DFB/FB] [SP][MP]*/
  85         const rte_event_timer_arm_burst_t arm_burst[2][2] = {
  86 #define FP(_name, _f2, _f1, flags) [_f2][_f1] = cnxk_tim_arm_burst_##_name,
  87                 TIM_ARM_FASTPATH_MODES
  88 #undef FP
  89         };
  90
  91         cnxk_tim_ops.arm_burst = arm_burst[tim_ring->ena_dfb][prod_flag];
  92 }
  93
  94 static void
  95 cnxk_tim_ring_info_get(const struct rte_event_timer_adapter *adptr,
  96                        struct rte_event_timer_adapter_info *adptr_info)
  97 {
  98         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
  99
 100         adptr_info->max_tmo_ns = tim_ring->max_tout;
 101         adptr_info->min_resolution_ns = tim_ring->tck_nsec;
 102         rte_memcpy(&adptr_info->conf, &adptr->data->conf,
 103                    sizeof(struct rte_event_timer_adapter_conf));
 104 }
 105
 106 static int
 107 cnxk_tim_ring_create(struct rte_event_timer_adapter *adptr)
 108 {
 109         struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
 110         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 111         struct cnxk_tim_ring *tim_ring;
 112         int rc;
 113
 114         if (dev == NULL)
 115                 return -ENODEV;
 116
 117         if (adptr->data->id >= dev->nb_rings)
 118                 return -ENODEV;
 119
 120         tim_ring = rte_zmalloc("cnxk_tim_prv", sizeof(struct cnxk_tim_ring), 0);
 121         if (tim_ring == NULL)
 122                 return -ENOMEM;
 123
 124         rc = roc_tim_lf_alloc(&dev->tim, adptr->data->id, NULL);
 125         if (rc < 0) {
 126                 plt_err("Failed to create timer ring");
 127                 goto tim_ring_free;
 128         }
 129
 130         if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(
 131                               rcfg->timer_tick_ns,
 132                               cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq())),
 133                       cnxk_tim_cntfrq()) <
 134             cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq())) {
 135                 if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_ADJUST_RES)
 136                         rcfg->timer_tick_ns = TICK2NSEC(
 137                                 cnxk_tim_min_tmo_ticks(cnxk_tim_cntfrq()),
 138                                 cnxk_tim_cntfrq());
 139                 else {
 140                         rc = -ERANGE;
 141                         goto tim_hw_free;
 142                 }
 143         }
 144         tim_ring->ring_id = adptr->data->id;
 145         tim_ring->clk_src = (int)rcfg->clk_src;
 146         tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(
 147                 rcfg->timer_tick_ns,
 148                 cnxk_tim_min_resolution_ns(cnxk_tim_cntfrq()));
 149         tim_ring->max_tout = rcfg->max_tmo_ns;
 150         tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
 151         tim_ring->nb_timers = rcfg->nb_timers;
 152         tim_ring->chunk_sz = dev->chunk_sz;
 153         tim_ring->disable_npa = dev->disable_npa;
 154
 155         if (tim_ring->disable_npa) {
 156                 tim_ring->nb_chunks =
 157                         tim_ring->nb_timers /
 158                         CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 159                 tim_ring->nb_chunks = tim_ring->nb_chunks * tim_ring->nb_bkts;
 160         } else {
 161                 tim_ring->nb_chunks = tim_ring->nb_timers;
 162         }
 163
 164         tim_ring->nb_chunk_slots = CNXK_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
 165         /* Create buckets. */
 166         tim_ring->bkt =
 167                 rte_zmalloc("cnxk_tim_bucket",
 168                             (tim_ring->nb_bkts) * sizeof(struct cnxk_tim_bkt),
 169                             RTE_CACHE_LINE_SIZE);
 170         if (tim_ring->bkt == NULL)
 171                 goto tim_hw_free;
 172
 173         rc = cnxk_tim_chnk_pool_create(tim_ring, rcfg);
 174         if (rc < 0)
 175                 goto tim_bkt_free;
 176
 177         rc = roc_tim_lf_config(
 178                 &dev->tim, tim_ring->ring_id,
 179                 cnxk_tim_convert_clk_src(tim_ring->clk_src), 0, 0,
 180                 tim_ring->nb_bkts, tim_ring->chunk_sz,
 181                 NSEC2TICK(tim_ring->tck_nsec, cnxk_tim_cntfrq()));
 182         if (rc < 0) {
 183                 plt_err("Failed to configure timer ring");
 184                 goto tim_chnk_free;
 185         }
 186
 187         tim_ring->base = roc_tim_lf_base_get(&dev->tim, tim_ring->ring_id);
 188         plt_write64((uint64_t)tim_ring->bkt, tim_ring->base + TIM_LF_RING_BASE);
 189         plt_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
 190
 191         /* Set fastpath ops. */
 192         cnxk_tim_set_fp_ops(tim_ring);
 193
 194         /* Update SSO xae count. */
 195         cnxk_sso_updt_xae_cnt(cnxk_sso_pmd_priv(dev->event_dev), tim_ring,
 196                               RTE_EVENT_TYPE_TIMER);
 197         cnxk_sso_xae_reconfigure(dev->event_dev);
 198
 199         plt_tim_dbg(
 200                 "Total memory used %" PRIu64 "MB\n",
 201                 (uint64_t)(((tim_ring->nb_chunks * tim_ring->chunk_sz) +
 202                             (tim_ring->nb_bkts * sizeof(struct cnxk_tim_bkt))) /
 203                            BIT_ULL(20)));
 204
 205         adptr->data->adapter_priv = tim_ring;
 206         return rc;
 207
 208 tim_chnk_free:
 209         rte_mempool_free(tim_ring->chunk_pool);
 210 tim_bkt_free:
 211         rte_free(tim_ring->bkt);
 212 tim_hw_free:
 213         roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
 214 tim_ring_free:
 215         rte_free(tim_ring);
 216         return rc;
 217 }
 218
 219 static int
 220 cnxk_tim_ring_free(struct rte_event_timer_adapter *adptr)
 221 {
 222         struct cnxk_tim_ring *tim_ring = adptr->data->adapter_priv;
 223         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 224
 225         if (dev == NULL)
 226                 return -ENODEV;
 227
 228         roc_tim_lf_free(&dev->tim, tim_ring->ring_id);
 229         rte_free(tim_ring->bkt);
 230         rte_mempool_free(tim_ring->chunk_pool);
 231         rte_free(tim_ring);
 232
 233         return 0;
 234 }
 235
 236 int
 237 cnxk_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
 238                   uint32_t *caps,
 239                   const struct rte_event_timer_adapter_ops **ops)
 240 {
 241         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 242
 243         RTE_SET_USED(flags);
 244         RTE_SET_USED(ops);
 245
 246         if (dev == NULL)
 247                 return -ENODEV;
 248
 249         cnxk_tim_ops.init = cnxk_tim_ring_create;
 250         cnxk_tim_ops.uninit = cnxk_tim_ring_free;
 251         cnxk_tim_ops.get_info = cnxk_tim_ring_info_get;
 252
 253         /* Store evdev pointer for later use. */
 254         dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
 255         *caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
 256
 257         return 0;
 258 }
 259
 260 static void
 261 cnxk_tim_parse_devargs(struct rte_devargs *devargs, struct cnxk_tim_evdev *dev)
 262 {
 263         struct rte_kvargs *kvlist;
 264
 265         if (devargs == NULL)
 266                 return;
 267
 268         kvlist = rte_kvargs_parse(devargs->args, NULL);
 269         if (kvlist == NULL)
 270                 return;
 271
 272         rte_kvargs_process(kvlist, CNXK_TIM_DISABLE_NPA, &parse_kvargs_flag,
 273                            &dev->disable_npa);
 274         rte_kvargs_process(kvlist, CNXK_TIM_CHNK_SLOTS, &parse_kvargs_value,
 275                            &dev->chunk_slots);
 276         rte_kvargs_process(kvlist, CNXK_TIM_RINGS_LMT, &parse_kvargs_value,
 277                            &dev->min_ring_cnt);
 278
 279         rte_kvargs_free(kvlist);
 280 }
 281
 282 void
 283 cnxk_tim_init(struct roc_sso *sso)
 284 {
 285         const struct rte_memzone *mz;
 286         struct cnxk_tim_evdev *dev;
 287         int rc;
 288
 289         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 290                 return;
 291
 292         mz = rte_memzone_reserve(RTE_STR(CNXK_TIM_EVDEV_NAME),
 293                                  sizeof(struct cnxk_tim_evdev), 0, 0);
 294         if (mz == NULL) {
 295                 plt_tim_dbg("Unable to allocate memory for TIM Event device");
 296                 return;
 297         }
 298         dev = mz->addr;
 299
 300         cnxk_tim_parse_devargs(sso->pci_dev->device.devargs, dev);
 301
 302         dev->tim.roc_sso = sso;
 303         dev->tim.nb_lfs = dev->min_ring_cnt;
 304         rc = roc_tim_init(&dev->tim);
 305         if (rc < 0) {
 306                 plt_err("Failed to initialize roc tim resources");
 307                 rte_memzone_free(mz);
 308                 return;
 309         }
 310         dev->nb_rings = rc;
 311
 312         if (dev->chunk_slots && dev->chunk_slots <= CNXK_TIM_MAX_CHUNK_SLOTS &&
 313             dev->chunk_slots >= CNXK_TIM_MIN_CHUNK_SLOTS) {
 314                 dev->chunk_sz =
 315                         (dev->chunk_slots + 1) * CNXK_TIM_CHUNK_ALIGNMENT;
 316         } else {
 317                 dev->chunk_sz = CNXK_TIM_RING_DEF_CHUNK_SZ;
 318         }
 319 }
 320
 321 void
 322 cnxk_tim_fini(void)
 323 {
 324         struct cnxk_tim_evdev *dev = cnxk_tim_priv_get();
 325
 326         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 327                 return;
 328
 329         roc_tim_fini(&dev->tim);
 330         rte_memzone_free(rte_memzone_lookup(RTE_STR(CNXK_TIM_EVDEV_NAME)));
 331 }