6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in
14 * the documentation and/or other materials provided with the
16 * * Neither the name of NXP nor the names of its
17 * contributors may be used to endorse or promote products derived
18 * from this software without specific prior written permission.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <sys/epoll.h>
41 #include <rte_atomic.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_debug.h>
47 #include <rte_fslmc.h>
48 #include <rte_lcore.h>
50 #include <rte_malloc.h>
51 #include <rte_memcpy.h>
52 #include <rte_memory.h>
53 #include <rte_memzone.h>
57 #include <fslmc_vfio.h>
58 #include <dpaa2_hw_pvt.h>
59 #include <dpaa2_hw_mempool.h>
60 #include <dpaa2_hw_dpio.h>
61 #include "dpaa2_eventdev.h"
62 #include <portal/dpaa2_hw_pvt.h>
63 #include <mc/fsl_dpci.h>
66 * Evendev = SoC Instance
67 * Eventport = DPIO Instance
68 * Eventqueue = DPCON Instance
69 * 1 Eventdev can have N Eventqueue
70 * Soft Event Flow is DPCI Instance
74 dpaa2_eventdev_enqueue_burst(void *port, const struct rte_event ev[],
77 struct rte_eventdev *ev_dev =
78 ((struct dpaa2_io_portal_t *)port)->eventdev;
79 struct dpaa2_eventdev *priv = ev_dev->data->dev_private;
80 uint32_t queue_id = ev[0].queue_id;
81 struct evq_info_t *evq_info = &priv->evq_info[queue_id];
83 struct qbman_swp *swp;
84 struct qbman_fd fd_arr[MAX_TX_RING_SLOTS];
85 uint32_t loop, frames_to_send;
86 struct qbman_eq_desc eqdesc[MAX_TX_RING_SLOTS];
92 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
93 ret = dpaa2_affine_qbman_swp();
95 PMD_DRV_LOG(ERR, "Failure in affining portal\n");
100 swp = DPAA2_PER_LCORE_PORTAL;
103 frames_to_send = (nb_events >> 3) ?
104 MAX_TX_RING_SLOTS : nb_events;
106 for (loop = 0; loop < frames_to_send; loop++) {
107 const struct rte_event *event = &ev[num_tx + loop];
109 if (event->sched_type != RTE_SCHED_TYPE_ATOMIC)
110 fqid = evq_info->dpci->queue[
111 DPAA2_EVENT_DPCI_PARALLEL_QUEUE].fqid;
113 fqid = evq_info->dpci->queue[
114 DPAA2_EVENT_DPCI_ATOMIC_QUEUE].fqid;
116 /* Prepare enqueue descriptor */
117 qbman_eq_desc_clear(&eqdesc[loop]);
118 qbman_eq_desc_set_fq(&eqdesc[loop], fqid);
119 qbman_eq_desc_set_no_orp(&eqdesc[loop], 0);
120 qbman_eq_desc_set_response(&eqdesc[loop], 0, 0);
122 if (event->impl_opaque) {
123 uint8_t dqrr_index = event->impl_opaque - 1;
125 qbman_eq_desc_set_dca(&eqdesc[loop], 1,
127 DPAA2_PER_LCORE_DPIO->dqrr_size--;
128 DPAA2_PER_LCORE_DPIO->dqrr_held &=
132 memset(&fd_arr[loop], 0, sizeof(struct qbman_fd));
135 * todo - need to align with hw context data
138 struct rte_event *ev_temp = rte_malloc(NULL,
139 sizeof(struct rte_event), 0);
140 rte_memcpy(ev_temp, event, sizeof(struct rte_event));
141 DPAA2_SET_FD_ADDR((&fd_arr[loop]), ev_temp);
142 DPAA2_SET_FD_LEN((&fd_arr[loop]),
143 sizeof(struct rte_event));
146 while (loop < frames_to_send) {
147 loop += qbman_swp_enqueue_multiple_eqdesc(swp,
148 &eqdesc[loop], &fd_arr[loop],
149 frames_to_send - loop);
151 num_tx += frames_to_send;
152 nb_events -= frames_to_send;
159 dpaa2_eventdev_enqueue(void *port, const struct rte_event *ev)
161 return dpaa2_eventdev_enqueue_burst(port, ev, 1);
164 static void dpaa2_eventdev_dequeue_wait(uint64_t timeout_ticks)
166 struct epoll_event epoll_ev;
169 qbman_swp_interrupt_clear_status(DPAA2_PER_LCORE_PORTAL,
170 QBMAN_SWP_INTERRUPT_DQRI);
173 ret = epoll_wait(DPAA2_PER_LCORE_DPIO->epoll_fd,
174 &epoll_ev, 1, timeout_ticks);
176 /* sometimes due to some spurious interrupts epoll_wait fails
177 * with errno EINTR. so here we are retrying epoll_wait in such
178 * case to avoid the problem.
180 if (errno == EINTR) {
181 PMD_DRV_LOG(DEBUG, "epoll_wait fails\n");
183 PMD_DRV_LOG(DEBUG, "Dequeue burst Failed\n");
189 static void dpaa2_eventdev_process_parallel(struct qbman_swp *swp,
190 const struct qbman_fd *fd,
191 const struct qbman_result *dq,
192 struct rte_event *ev)
194 struct rte_event *ev_temp =
195 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
196 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
199 qbman_swp_dqrr_consume(swp, dq);
202 static void dpaa2_eventdev_process_atomic(struct qbman_swp *swp,
203 const struct qbman_fd *fd,
204 const struct qbman_result *dq,
205 struct rte_event *ev)
207 struct rte_event *ev_temp =
208 (struct rte_event *)DPAA2_GET_FD_ADDR(fd);
209 uint8_t dqrr_index = qbman_get_dqrr_idx(dq);
213 rte_memcpy(ev, ev_temp, sizeof(struct rte_event));
215 ev->impl_opaque = dqrr_index + 1;
216 DPAA2_PER_LCORE_DPIO->dqrr_size++;
217 DPAA2_PER_LCORE_DPIO->dqrr_held |= 1 << dqrr_index;
221 dpaa2_eventdev_dequeue_burst(void *port, struct rte_event ev[],
222 uint16_t nb_events, uint64_t timeout_ticks)
224 const struct qbman_result *dq;
225 struct qbman_swp *swp;
226 const struct qbman_fd *fd;
227 struct dpaa2_queue *rxq;
228 int num_pkts = 0, ret, i = 0;
232 if (unlikely(!DPAA2_PER_LCORE_DPIO)) {
233 ret = dpaa2_affine_qbman_swp();
235 PMD_DRV_LOG(ERR, "Failure in affining portal\n");
240 swp = DPAA2_PER_LCORE_PORTAL;
242 /* Check if there are atomic contexts to be released */
243 while (DPAA2_PER_LCORE_DPIO->dqrr_size) {
244 if (DPAA2_PER_LCORE_DPIO->dqrr_held & (1 << i)) {
245 dq = qbman_get_dqrr_from_idx(swp, i);
246 qbman_swp_dqrr_consume(swp, dq);
247 DPAA2_PER_LCORE_DPIO->dqrr_size--;
251 DPAA2_PER_LCORE_DPIO->dqrr_held = 0;
254 dq = qbman_swp_dqrr_next(swp);
256 if (!num_pkts && timeout_ticks) {
257 dpaa2_eventdev_dequeue_wait(timeout_ticks);
264 fd = qbman_result_DQ_fd(dq);
266 rxq = (struct dpaa2_queue *)qbman_result_DQ_fqd_ctx(dq);
268 rxq->cb(swp, fd, dq, &ev[num_pkts]);
270 qbman_swp_dqrr_consume(swp, dq);
271 PMD_DRV_LOG(ERR, "Null Return VQ received\n");
276 } while (num_pkts < nb_events);
282 dpaa2_eventdev_dequeue(void *port, struct rte_event *ev,
283 uint64_t timeout_ticks)
285 return dpaa2_eventdev_dequeue_burst(port, ev, 1, timeout_ticks);
289 dpaa2_eventdev_info_get(struct rte_eventdev *dev,
290 struct rte_event_dev_info *dev_info)
292 struct dpaa2_eventdev *priv = dev->data->dev_private;
294 PMD_DRV_FUNC_TRACE();
298 memset(dev_info, 0, sizeof(struct rte_event_dev_info));
299 dev_info->min_dequeue_timeout_ns =
300 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
301 dev_info->max_dequeue_timeout_ns =
302 DPAA2_EVENT_MAX_DEQUEUE_TIMEOUT;
303 dev_info->dequeue_timeout_ns =
304 DPAA2_EVENT_MIN_DEQUEUE_TIMEOUT;
305 dev_info->max_event_queues = priv->max_event_queues;
306 dev_info->max_event_queue_flows =
307 DPAA2_EVENT_MAX_QUEUE_FLOWS;
308 dev_info->max_event_queue_priority_levels =
309 DPAA2_EVENT_MAX_QUEUE_PRIORITY_LEVELS;
310 dev_info->max_event_priority_levels =
311 DPAA2_EVENT_MAX_EVENT_PRIORITY_LEVELS;
312 dev_info->max_event_ports = RTE_MAX_LCORE;
313 dev_info->max_event_port_dequeue_depth =
314 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
315 dev_info->max_event_port_enqueue_depth =
316 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
317 dev_info->max_num_events = DPAA2_EVENT_MAX_NUM_EVENTS;
318 dev_info->event_dev_cap = RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED;
322 dpaa2_eventdev_configure(const struct rte_eventdev *dev)
324 struct dpaa2_eventdev *priv = dev->data->dev_private;
325 struct rte_event_dev_config *conf = &dev->data->dev_conf;
327 PMD_DRV_FUNC_TRACE();
329 priv->dequeue_timeout_ns = conf->dequeue_timeout_ns;
330 priv->nb_event_queues = conf->nb_event_queues;
331 priv->nb_event_ports = conf->nb_event_ports;
332 priv->nb_event_queue_flows = conf->nb_event_queue_flows;
333 priv->nb_event_port_dequeue_depth = conf->nb_event_port_dequeue_depth;
334 priv->nb_event_port_enqueue_depth = conf->nb_event_port_enqueue_depth;
335 priv->event_dev_cfg = conf->event_dev_cfg;
337 PMD_DRV_LOG(DEBUG, "Configured eventdev devid=%d", dev->data->dev_id);
342 dpaa2_eventdev_start(struct rte_eventdev *dev)
344 PMD_DRV_FUNC_TRACE();
352 dpaa2_eventdev_stop(struct rte_eventdev *dev)
354 PMD_DRV_FUNC_TRACE();
360 dpaa2_eventdev_close(struct rte_eventdev *dev)
362 PMD_DRV_FUNC_TRACE();
370 dpaa2_eventdev_queue_def_conf(struct rte_eventdev *dev, uint8_t queue_id,
371 struct rte_event_queue_conf *queue_conf)
373 PMD_DRV_FUNC_TRACE();
376 RTE_SET_USED(queue_id);
377 RTE_SET_USED(queue_conf);
379 queue_conf->nb_atomic_flows = DPAA2_EVENT_QUEUE_ATOMIC_FLOWS;
380 queue_conf->event_queue_cfg = RTE_EVENT_QUEUE_CFG_ATOMIC_ONLY |
381 RTE_EVENT_QUEUE_CFG_PARALLEL_ONLY;
382 queue_conf->priority = RTE_EVENT_DEV_PRIORITY_NORMAL;
386 dpaa2_eventdev_queue_release(struct rte_eventdev *dev, uint8_t queue_id)
388 PMD_DRV_FUNC_TRACE();
391 RTE_SET_USED(queue_id);
395 dpaa2_eventdev_queue_setup(struct rte_eventdev *dev, uint8_t queue_id,
396 const struct rte_event_queue_conf *queue_conf)
398 struct dpaa2_eventdev *priv = dev->data->dev_private;
399 struct evq_info_t *evq_info =
400 &priv->evq_info[queue_id];
402 PMD_DRV_FUNC_TRACE();
404 evq_info->event_queue_cfg = queue_conf->event_queue_cfg;
410 dpaa2_eventdev_port_def_conf(struct rte_eventdev *dev, uint8_t port_id,
411 struct rte_event_port_conf *port_conf)
413 PMD_DRV_FUNC_TRACE();
416 RTE_SET_USED(port_id);
417 RTE_SET_USED(port_conf);
419 port_conf->new_event_threshold =
420 DPAA2_EVENT_MAX_NUM_EVENTS;
421 port_conf->dequeue_depth =
422 DPAA2_EVENT_MAX_PORT_DEQUEUE_DEPTH;
423 port_conf->enqueue_depth =
424 DPAA2_EVENT_MAX_PORT_ENQUEUE_DEPTH;
428 dpaa2_eventdev_port_release(void *port)
430 PMD_DRV_FUNC_TRACE();
436 dpaa2_eventdev_port_setup(struct rte_eventdev *dev, uint8_t port_id,
437 const struct rte_event_port_conf *port_conf)
439 PMD_DRV_FUNC_TRACE();
441 RTE_SET_USED(port_conf);
443 if (!dpaa2_io_portal[port_id].dpio_dev) {
444 dpaa2_io_portal[port_id].dpio_dev =
445 dpaa2_get_qbman_swp(port_id);
446 rte_atomic16_inc(&dpaa2_io_portal[port_id].dpio_dev->ref_count);
447 if (!dpaa2_io_portal[port_id].dpio_dev)
451 dpaa2_io_portal[port_id].eventdev = dev;
452 dev->data->ports[port_id] = &dpaa2_io_portal[port_id];
457 dpaa2_eventdev_port_unlink(struct rte_eventdev *dev, void *port,
458 uint8_t queues[], uint16_t nb_unlinks)
460 struct dpaa2_eventdev *priv = dev->data->dev_private;
461 struct dpaa2_io_portal_t *dpaa2_portal = port;
462 struct evq_info_t *evq_info;
465 PMD_DRV_FUNC_TRACE();
467 for (i = 0; i < nb_unlinks; i++) {
468 evq_info = &priv->evq_info[queues[i]];
469 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
470 evq_info->dpcon->channel_index, 0);
471 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
472 0, dpaa2_portal->dpio_dev->token,
473 evq_info->dpcon->dpcon_id);
477 return (int)nb_unlinks;
481 dpaa2_eventdev_port_link(struct rte_eventdev *dev, void *port,
482 const uint8_t queues[], const uint8_t priorities[],
485 struct dpaa2_eventdev *priv = dev->data->dev_private;
486 struct dpaa2_io_portal_t *dpaa2_portal = port;
487 struct evq_info_t *evq_info;
488 uint8_t channel_index;
491 PMD_DRV_FUNC_TRACE();
493 for (i = 0; i < nb_links; i++) {
494 evq_info = &priv->evq_info[queues[i]];
498 ret = dpio_add_static_dequeue_channel(
499 dpaa2_portal->dpio_dev->dpio,
500 CMD_PRI_LOW, dpaa2_portal->dpio_dev->token,
501 evq_info->dpcon->dpcon_id, &channel_index);
503 PMD_DRV_ERR("Static dequeue cfg failed with ret: %d\n",
508 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
510 evq_info->dpcon->channel_index = channel_index;
514 RTE_SET_USED(priorities);
516 return (int)nb_links;
518 for (n = 0; n < i; n++) {
519 evq_info = &priv->evq_info[queues[n]];
520 qbman_swp_push_set(dpaa2_portal->dpio_dev->sw_portal,
521 evq_info->dpcon->channel_index, 0);
522 dpio_remove_static_dequeue_channel(dpaa2_portal->dpio_dev->dpio,
523 0, dpaa2_portal->dpio_dev->token,
524 evq_info->dpcon->dpcon_id);
531 dpaa2_eventdev_timeout_ticks(struct rte_eventdev *dev, uint64_t ns,
532 uint64_t *timeout_ticks)
536 PMD_DRV_FUNC_TRACE();
539 *timeout_ticks = ns * scale;
545 dpaa2_eventdev_dump(struct rte_eventdev *dev, FILE *f)
547 PMD_DRV_FUNC_TRACE();
553 static const struct rte_eventdev_ops dpaa2_eventdev_ops = {
554 .dev_infos_get = dpaa2_eventdev_info_get,
555 .dev_configure = dpaa2_eventdev_configure,
556 .dev_start = dpaa2_eventdev_start,
557 .dev_stop = dpaa2_eventdev_stop,
558 .dev_close = dpaa2_eventdev_close,
559 .queue_def_conf = dpaa2_eventdev_queue_def_conf,
560 .queue_setup = dpaa2_eventdev_queue_setup,
561 .queue_release = dpaa2_eventdev_queue_release,
562 .port_def_conf = dpaa2_eventdev_port_def_conf,
563 .port_setup = dpaa2_eventdev_port_setup,
564 .port_release = dpaa2_eventdev_port_release,
565 .port_link = dpaa2_eventdev_port_link,
566 .port_unlink = dpaa2_eventdev_port_unlink,
567 .timeout_ticks = dpaa2_eventdev_timeout_ticks,
568 .dump = dpaa2_eventdev_dump
572 dpaa2_eventdev_setup_dpci(struct dpaa2_dpci_dev *dpci_dev,
573 struct dpaa2_dpcon_dev *dpcon_dev)
575 struct dpci_rx_queue_cfg rx_queue_cfg;
578 /*Do settings to get the frame on a DPCON object*/
579 rx_queue_cfg.options = DPCI_QUEUE_OPT_DEST |
580 DPCI_QUEUE_OPT_USER_CTX;
581 rx_queue_cfg.dest_cfg.dest_type = DPCI_DEST_DPCON;
582 rx_queue_cfg.dest_cfg.dest_id = dpcon_dev->dpcon_id;
583 rx_queue_cfg.dest_cfg.priority = DPAA2_EVENT_DEFAULT_DPCI_PRIO;
585 dpci_dev->queue[DPAA2_EVENT_DPCI_PARALLEL_QUEUE].cb =
586 dpaa2_eventdev_process_parallel;
587 dpci_dev->queue[DPAA2_EVENT_DPCI_ATOMIC_QUEUE].cb =
588 dpaa2_eventdev_process_atomic;
590 for (i = 0 ; i < DPAA2_EVENT_DPCI_MAX_QUEUES; i++) {
591 rx_queue_cfg.user_ctx = (uint64_t)(&dpci_dev->queue[i]);
592 ret = dpci_set_rx_queue(&dpci_dev->dpci,
598 "set_rx_q failed with err code: %d", ret);
606 dpaa2_eventdev_create(const char *name)
608 struct rte_eventdev *eventdev;
609 struct dpaa2_eventdev *priv;
610 struct dpaa2_dpcon_dev *dpcon_dev = NULL;
611 struct dpaa2_dpci_dev *dpci_dev = NULL;
614 eventdev = rte_event_pmd_vdev_init(name,
615 sizeof(struct dpaa2_eventdev),
617 if (eventdev == NULL) {
618 PMD_DRV_ERR("Failed to create eventdev vdev %s", name);
622 eventdev->dev_ops = &dpaa2_eventdev_ops;
623 eventdev->schedule = NULL;
624 eventdev->enqueue = dpaa2_eventdev_enqueue;
625 eventdev->enqueue_burst = dpaa2_eventdev_enqueue_burst;
626 eventdev->enqueue_new_burst = dpaa2_eventdev_enqueue_burst;
627 eventdev->enqueue_forward_burst = dpaa2_eventdev_enqueue_burst;
628 eventdev->dequeue = dpaa2_eventdev_dequeue;
629 eventdev->dequeue_burst = dpaa2_eventdev_dequeue_burst;
631 /* For secondary processes, the primary has done all the work */
632 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
635 priv = eventdev->data->dev_private;
636 priv->max_event_queues = 0;
639 dpcon_dev = rte_dpaa2_alloc_dpcon_dev();
642 priv->evq_info[priv->max_event_queues].dpcon = dpcon_dev;
644 dpci_dev = rte_dpaa2_alloc_dpci_dev();
646 rte_dpaa2_free_dpcon_dev(dpcon_dev);
649 priv->evq_info[priv->max_event_queues].dpci = dpci_dev;
651 ret = dpaa2_eventdev_setup_dpci(dpci_dev, dpcon_dev);
654 "dpci setup failed with err code: %d", ret);
657 priv->max_event_queues++;
658 } while (dpcon_dev && dpci_dev);
666 dpaa2_eventdev_probe(struct rte_vdev_device *vdev)
670 name = rte_vdev_device_name(vdev);
671 PMD_DRV_LOG(INFO, "Initializing %s", name);
672 return dpaa2_eventdev_create(name);
676 dpaa2_eventdev_remove(struct rte_vdev_device *vdev)
680 name = rte_vdev_device_name(vdev);
681 PMD_DRV_LOG(INFO, "Closing %s", name);
683 return rte_event_pmd_vdev_uninit(name);
686 static struct rte_vdev_driver vdev_eventdev_dpaa2_pmd = {
687 .probe = dpaa2_eventdev_probe,
688 .remove = dpaa2_eventdev_remove
691 RTE_PMD_REGISTER_VDEV(EVENTDEV_NAME_DPAA2_PMD, vdev_eventdev_dpaa2_pmd);